mii-bitbang.c 8.0 KB

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  1. /*
  2. * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
  3. *
  4. * Copyright (c) 2003 Intracom S.A.
  5. * by Pantelis Antoniou <panto@intracom.gr>
  6. *
  7. * 2005 (c) MontaVista Software, Inc.
  8. * Vitaly Bordug <vbordug@ru.mvista.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public License
  11. * version 2. This program is licensed "as is" without any warranty of any
  12. * kind, whether express or implied.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/ptrace.h>
  19. #include <linux/errno.h>
  20. #include <linux/ioport.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <linux/skbuff.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/mii.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/bitops.h>
  32. #include <linux/platform_device.h>
  33. #include <asm/pgtable.h>
  34. #include <asm/irq.h>
  35. #include <asm/uaccess.h>
  36. #include "fs_enet.h"
  37. static int bitbang_prep_bit(u8 **datp, u8 *mskp,
  38. struct fs_mii_bit *mii_bit)
  39. {
  40. void *dat;
  41. int adv;
  42. u8 msk;
  43. dat = (void*) mii_bit->offset;
  44. adv = mii_bit->bit >> 3;
  45. dat = (char *)dat + adv;
  46. msk = 1 << (7 - (mii_bit->bit & 7));
  47. *datp = dat;
  48. *mskp = msk;
  49. return 0;
  50. }
  51. static inline void bb_set(u8 *p, u8 m)
  52. {
  53. out_8(p, in_8(p) | m);
  54. }
  55. static inline void bb_clr(u8 *p, u8 m)
  56. {
  57. out_8(p, in_8(p) & ~m);
  58. }
  59. static inline int bb_read(u8 *p, u8 m)
  60. {
  61. return (in_8(p) & m) != 0;
  62. }
  63. static inline void mdio_active(struct bb_info *bitbang)
  64. {
  65. bb_set(bitbang->mdio_dir, bitbang->mdio_dir_msk);
  66. }
  67. static inline void mdio_tristate(struct bb_info *bitbang )
  68. {
  69. bb_clr(bitbang->mdio_dir, bitbang->mdio_dir_msk);
  70. }
  71. static inline int mdio_read(struct bb_info *bitbang )
  72. {
  73. return bb_read(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  74. }
  75. static inline void mdio(struct bb_info *bitbang , int what)
  76. {
  77. if (what)
  78. bb_set(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  79. else
  80. bb_clr(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  81. }
  82. static inline void mdc(struct bb_info *bitbang , int what)
  83. {
  84. if (what)
  85. bb_set(bitbang->mdc_dat, bitbang->mdc_msk);
  86. else
  87. bb_clr(bitbang->mdc_dat, bitbang->mdc_msk);
  88. }
  89. static inline void mii_delay(struct bb_info *bitbang )
  90. {
  91. udelay(bitbang->delay);
  92. }
  93. /* Utility to send the preamble, address, and register (common to read and write). */
  94. static void bitbang_pre(struct bb_info *bitbang , int read, u8 addr, u8 reg)
  95. {
  96. int j;
  97. /*
  98. * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
  99. * The IEEE spec says this is a PHY optional requirement. The AMD
  100. * 79C874 requires one after power up and one after a MII communications
  101. * error. This means that we are doing more preambles than we need,
  102. * but it is safer and will be much more robust.
  103. */
  104. mdio_active(bitbang);
  105. mdio(bitbang, 1);
  106. for (j = 0; j < 32; j++) {
  107. mdc(bitbang, 0);
  108. mii_delay(bitbang);
  109. mdc(bitbang, 1);
  110. mii_delay(bitbang);
  111. }
  112. /* send the start bit (01) and the read opcode (10) or write (10) */
  113. mdc(bitbang, 0);
  114. mdio(bitbang, 0);
  115. mii_delay(bitbang);
  116. mdc(bitbang, 1);
  117. mii_delay(bitbang);
  118. mdc(bitbang, 0);
  119. mdio(bitbang, 1);
  120. mii_delay(bitbang);
  121. mdc(bitbang, 1);
  122. mii_delay(bitbang);
  123. mdc(bitbang, 0);
  124. mdio(bitbang, read);
  125. mii_delay(bitbang);
  126. mdc(bitbang, 1);
  127. mii_delay(bitbang);
  128. mdc(bitbang, 0);
  129. mdio(bitbang, !read);
  130. mii_delay(bitbang);
  131. mdc(bitbang, 1);
  132. mii_delay(bitbang);
  133. /* send the PHY address */
  134. for (j = 0; j < 5; j++) {
  135. mdc(bitbang, 0);
  136. mdio(bitbang, (addr & 0x10) != 0);
  137. mii_delay(bitbang);
  138. mdc(bitbang, 1);
  139. mii_delay(bitbang);
  140. addr <<= 1;
  141. }
  142. /* send the register address */
  143. for (j = 0; j < 5; j++) {
  144. mdc(bitbang, 0);
  145. mdio(bitbang, (reg & 0x10) != 0);
  146. mii_delay(bitbang);
  147. mdc(bitbang, 1);
  148. mii_delay(bitbang);
  149. reg <<= 1;
  150. }
  151. }
  152. static int fs_enet_mii_bb_read(struct mii_bus *bus , int phy_id, int location)
  153. {
  154. u16 rdreg;
  155. int ret, j;
  156. u8 addr = phy_id & 0xff;
  157. u8 reg = location & 0xff;
  158. struct bb_info* bitbang = bus->priv;
  159. bitbang_pre(bitbang, 1, addr, reg);
  160. /* tri-state our MDIO I/O pin so we can read */
  161. mdc(bitbang, 0);
  162. mdio_tristate(bitbang);
  163. mii_delay(bitbang);
  164. mdc(bitbang, 1);
  165. mii_delay(bitbang);
  166. /* check the turnaround bit: the PHY should be driving it to zero */
  167. if (mdio_read(bitbang) != 0) {
  168. /* PHY didn't drive TA low */
  169. for (j = 0; j < 32; j++) {
  170. mdc(bitbang, 0);
  171. mii_delay(bitbang);
  172. mdc(bitbang, 1);
  173. mii_delay(bitbang);
  174. }
  175. ret = -1;
  176. goto out;
  177. }
  178. mdc(bitbang, 0);
  179. mii_delay(bitbang);
  180. /* read 16 bits of register data, MSB first */
  181. rdreg = 0;
  182. for (j = 0; j < 16; j++) {
  183. mdc(bitbang, 1);
  184. mii_delay(bitbang);
  185. rdreg <<= 1;
  186. rdreg |= mdio_read(bitbang);
  187. mdc(bitbang, 0);
  188. mii_delay(bitbang);
  189. }
  190. mdc(bitbang, 1);
  191. mii_delay(bitbang);
  192. mdc(bitbang, 0);
  193. mii_delay(bitbang);
  194. mdc(bitbang, 1);
  195. mii_delay(bitbang);
  196. ret = rdreg;
  197. out:
  198. return ret;
  199. }
  200. static int fs_enet_mii_bb_write(struct mii_bus *bus, int phy_id, int location, u16 val)
  201. {
  202. int j;
  203. struct bb_info* bitbang = bus->priv;
  204. u8 addr = phy_id & 0xff;
  205. u8 reg = location & 0xff;
  206. u16 value = val & 0xffff;
  207. bitbang_pre(bitbang, 0, addr, reg);
  208. /* send the turnaround (10) */
  209. mdc(bitbang, 0);
  210. mdio(bitbang, 1);
  211. mii_delay(bitbang);
  212. mdc(bitbang, 1);
  213. mii_delay(bitbang);
  214. mdc(bitbang, 0);
  215. mdio(bitbang, 0);
  216. mii_delay(bitbang);
  217. mdc(bitbang, 1);
  218. mii_delay(bitbang);
  219. /* write 16 bits of register data, MSB first */
  220. for (j = 0; j < 16; j++) {
  221. mdc(bitbang, 0);
  222. mdio(bitbang, (value & 0x8000) != 0);
  223. mii_delay(bitbang);
  224. mdc(bitbang, 1);
  225. mii_delay(bitbang);
  226. value <<= 1;
  227. }
  228. /*
  229. * Tri-state the MDIO line.
  230. */
  231. mdio_tristate(bitbang);
  232. mdc(bitbang, 0);
  233. mii_delay(bitbang);
  234. mdc(bitbang, 1);
  235. mii_delay(bitbang);
  236. return 0;
  237. }
  238. static int fs_enet_mii_bb_reset(struct mii_bus *bus)
  239. {
  240. /*nothing here - dunno how to reset it*/
  241. return 0;
  242. }
  243. static int fs_mii_bitbang_init(struct bb_info *bitbang, struct fs_mii_bb_platform_info* fmpi)
  244. {
  245. int r;
  246. bitbang->delay = fmpi->delay;
  247. r = bitbang_prep_bit(&bitbang->mdio_dir,
  248. &bitbang->mdio_dir_msk,
  249. &fmpi->mdio_dir);
  250. if (r != 0)
  251. return r;
  252. r = bitbang_prep_bit(&bitbang->mdio_dat,
  253. &bitbang->mdio_dat_msk,
  254. &fmpi->mdio_dat);
  255. if (r != 0)
  256. return r;
  257. r = bitbang_prep_bit(&bitbang->mdc_dat,
  258. &bitbang->mdc_msk,
  259. &fmpi->mdc_dat);
  260. if (r != 0)
  261. return r;
  262. return 0;
  263. }
  264. static int __devinit fs_enet_mdio_probe(struct device *dev)
  265. {
  266. struct platform_device *pdev = to_platform_device(dev);
  267. struct fs_mii_bb_platform_info *pdata;
  268. struct mii_bus *new_bus;
  269. struct bb_info *bitbang;
  270. int err = 0;
  271. if (NULL == dev)
  272. return -EINVAL;
  273. new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
  274. if (NULL == new_bus)
  275. return -ENOMEM;
  276. bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
  277. if (NULL == bitbang)
  278. return -ENOMEM;
  279. new_bus->name = "BB MII Bus",
  280. new_bus->read = &fs_enet_mii_bb_read,
  281. new_bus->write = &fs_enet_mii_bb_write,
  282. new_bus->reset = &fs_enet_mii_bb_reset,
  283. new_bus->id = pdev->id;
  284. new_bus->phy_mask = ~0x9;
  285. pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
  286. if (NULL == pdata) {
  287. printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
  288. return -ENODEV;
  289. }
  290. /*set up workspace*/
  291. fs_mii_bitbang_init(bitbang, pdata);
  292. new_bus->priv = bitbang;
  293. new_bus->irq = pdata->irq;
  294. new_bus->dev = dev;
  295. dev_set_drvdata(dev, new_bus);
  296. err = mdiobus_register(new_bus);
  297. if (0 != err) {
  298. printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
  299. new_bus->name);
  300. goto bus_register_fail;
  301. }
  302. return 0;
  303. bus_register_fail:
  304. kfree(bitbang);
  305. kfree(new_bus);
  306. return err;
  307. }
  308. static int fs_enet_mdio_remove(struct device *dev)
  309. {
  310. struct mii_bus *bus = dev_get_drvdata(dev);
  311. mdiobus_unregister(bus);
  312. dev_set_drvdata(dev, NULL);
  313. iounmap((void *) (&bus->priv));
  314. bus->priv = NULL;
  315. kfree(bus);
  316. return 0;
  317. }
  318. static struct device_driver fs_enet_bb_mdio_driver = {
  319. .name = "fsl-bb-mdio",
  320. .bus = &platform_bus_type,
  321. .probe = fs_enet_mdio_probe,
  322. .remove = fs_enet_mdio_remove,
  323. };
  324. int fs_enet_mdio_bb_init(void)
  325. {
  326. return driver_register(&fs_enet_bb_mdio_driver);
  327. }
  328. void fs_enet_mdio_bb_exit(void)
  329. {
  330. driver_unregister(&fs_enet_bb_mdio_driver);
  331. }