gianfar.c 81 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080
  1. /*
  2. * drivers/net/gianfar.c
  3. *
  4. * Gianfar Ethernet Driver
  5. * This driver is designed for the non-CPM ethernet controllers
  6. * on the 85xx and 83xx family of integrated processors
  7. * Based on 8260_io/fcc_enet.c
  8. *
  9. * Author: Andy Fleming
  10. * Maintainer: Kumar Gala
  11. * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12. *
  13. * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14. * Copyright 2007 MontaVista Software, Inc.
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the
  18. * Free Software Foundation; either version 2 of the License, or (at your
  19. * option) any later version.
  20. *
  21. * Gianfar: AKA Lambda Draconis, "Dragon"
  22. * RA 11 31 24.2
  23. * Dec +69 19 52
  24. * V 3.84
  25. * B-V +1.62
  26. *
  27. * Theory of operation
  28. *
  29. * The driver is initialized through of_device. Configuration information
  30. * is therefore conveyed through an OF-style device tree.
  31. *
  32. * The Gianfar Ethernet Controller uses a ring of buffer
  33. * descriptors. The beginning is indicated by a register
  34. * pointing to the physical address of the start of the ring.
  35. * The end is determined by a "wrap" bit being set in the
  36. * last descriptor of the ring.
  37. *
  38. * When a packet is received, the RXF bit in the
  39. * IEVENT register is set, triggering an interrupt when the
  40. * corresponding bit in the IMASK register is also set (if
  41. * interrupt coalescing is active, then the interrupt may not
  42. * happen immediately, but will wait until either a set number
  43. * of frames or amount of time have passed). In NAPI, the
  44. * interrupt handler will signal there is work to be done, and
  45. * exit. This method will start at the last known empty
  46. * descriptor, and process every subsequent descriptor until there
  47. * are none left with data (NAPI will stop after a set number of
  48. * packets to give time to other tasks, but will eventually
  49. * process all the packets). The data arrives inside a
  50. * pre-allocated skb, and so after the skb is passed up to the
  51. * stack, a new skb must be allocated, and the address field in
  52. * the buffer descriptor must be updated to indicate this new
  53. * skb.
  54. *
  55. * When the kernel requests that a packet be transmitted, the
  56. * driver starts where it left off last time, and points the
  57. * descriptor at the buffer which was passed in. The driver
  58. * then informs the DMA engine that there are packets ready to
  59. * be transmitted. Once the controller is finished transmitting
  60. * the packet, an interrupt may be triggered (under the same
  61. * conditions as for reception, but depending on the TXF bit).
  62. * The driver then cleans up the buffer.
  63. */
  64. #include <linux/kernel.h>
  65. #include <linux/string.h>
  66. #include <linux/errno.h>
  67. #include <linux/unistd.h>
  68. #include <linux/slab.h>
  69. #include <linux/interrupt.h>
  70. #include <linux/init.h>
  71. #include <linux/delay.h>
  72. #include <linux/netdevice.h>
  73. #include <linux/etherdevice.h>
  74. #include <linux/skbuff.h>
  75. #include <linux/if_vlan.h>
  76. #include <linux/spinlock.h>
  77. #include <linux/mm.h>
  78. #include <linux/of_mdio.h>
  79. #include <linux/of_platform.h>
  80. #include <linux/ip.h>
  81. #include <linux/tcp.h>
  82. #include <linux/udp.h>
  83. #include <linux/in.h>
  84. #include <asm/io.h>
  85. #include <asm/irq.h>
  86. #include <asm/uaccess.h>
  87. #include <linux/module.h>
  88. #include <linux/dma-mapping.h>
  89. #include <linux/crc32.h>
  90. #include <linux/mii.h>
  91. #include <linux/phy.h>
  92. #include <linux/phy_fixed.h>
  93. #include <linux/of.h>
  94. #include "gianfar.h"
  95. #include "fsl_pq_mdio.h"
  96. #define TX_TIMEOUT (1*HZ)
  97. #undef BRIEF_GFAR_ERRORS
  98. #undef VERBOSE_GFAR_ERRORS
  99. const char gfar_driver_name[] = "Gianfar Ethernet";
  100. const char gfar_driver_version[] = "1.3";
  101. static int gfar_enet_open(struct net_device *dev);
  102. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
  103. static void gfar_reset_task(struct work_struct *work);
  104. static void gfar_timeout(struct net_device *dev);
  105. static int gfar_close(struct net_device *dev);
  106. struct sk_buff *gfar_new_skb(struct net_device *dev);
  107. static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  108. struct sk_buff *skb);
  109. static int gfar_set_mac_address(struct net_device *dev);
  110. static int gfar_change_mtu(struct net_device *dev, int new_mtu);
  111. static irqreturn_t gfar_error(int irq, void *dev_id);
  112. static irqreturn_t gfar_transmit(int irq, void *dev_id);
  113. static irqreturn_t gfar_interrupt(int irq, void *dev_id);
  114. static void adjust_link(struct net_device *dev);
  115. static void init_registers(struct net_device *dev);
  116. static int init_phy(struct net_device *dev);
  117. static int gfar_probe(struct of_device *ofdev,
  118. const struct of_device_id *match);
  119. static int gfar_remove(struct of_device *ofdev);
  120. static void free_skb_resources(struct gfar_private *priv);
  121. static void gfar_set_multi(struct net_device *dev);
  122. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
  123. static void gfar_configure_serdes(struct net_device *dev);
  124. static int gfar_poll(struct napi_struct *napi, int budget);
  125. #ifdef CONFIG_NET_POLL_CONTROLLER
  126. static void gfar_netpoll(struct net_device *dev);
  127. #endif
  128. int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
  129. static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
  130. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  131. int amount_pull);
  132. static void gfar_vlan_rx_register(struct net_device *netdev,
  133. struct vlan_group *grp);
  134. void gfar_halt(struct net_device *dev);
  135. static void gfar_halt_nodisable(struct net_device *dev);
  136. void gfar_start(struct net_device *dev);
  137. static void gfar_clear_exact_match(struct net_device *dev);
  138. static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
  139. static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  140. u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb);
  141. MODULE_AUTHOR("Freescale Semiconductor, Inc");
  142. MODULE_DESCRIPTION("Gianfar Ethernet Driver");
  143. MODULE_LICENSE("GPL");
  144. static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  145. dma_addr_t buf)
  146. {
  147. u32 lstatus;
  148. bdp->bufPtr = buf;
  149. lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
  150. if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
  151. lstatus |= BD_LFLAG(RXBD_WRAP);
  152. eieio();
  153. bdp->lstatus = lstatus;
  154. }
  155. static int gfar_init_bds(struct net_device *ndev)
  156. {
  157. struct gfar_private *priv = netdev_priv(ndev);
  158. struct gfar_priv_tx_q *tx_queue = NULL;
  159. struct gfar_priv_rx_q *rx_queue = NULL;
  160. struct txbd8 *txbdp;
  161. struct rxbd8 *rxbdp;
  162. int i, j;
  163. for (i = 0; i < priv->num_tx_queues; i++) {
  164. tx_queue = priv->tx_queue[i];
  165. /* Initialize some variables in our dev structure */
  166. tx_queue->num_txbdfree = tx_queue->tx_ring_size;
  167. tx_queue->dirty_tx = tx_queue->tx_bd_base;
  168. tx_queue->cur_tx = tx_queue->tx_bd_base;
  169. tx_queue->skb_curtx = 0;
  170. tx_queue->skb_dirtytx = 0;
  171. /* Initialize Transmit Descriptor Ring */
  172. txbdp = tx_queue->tx_bd_base;
  173. for (j = 0; j < tx_queue->tx_ring_size; j++) {
  174. txbdp->lstatus = 0;
  175. txbdp->bufPtr = 0;
  176. txbdp++;
  177. }
  178. /* Set the last descriptor in the ring to indicate wrap */
  179. txbdp--;
  180. txbdp->status |= TXBD_WRAP;
  181. }
  182. for (i = 0; i < priv->num_rx_queues; i++) {
  183. rx_queue = priv->rx_queue[i];
  184. rx_queue->cur_rx = rx_queue->rx_bd_base;
  185. rx_queue->skb_currx = 0;
  186. rxbdp = rx_queue->rx_bd_base;
  187. for (j = 0; j < rx_queue->rx_ring_size; j++) {
  188. struct sk_buff *skb = rx_queue->rx_skbuff[j];
  189. if (skb) {
  190. gfar_init_rxbdp(rx_queue, rxbdp,
  191. rxbdp->bufPtr);
  192. } else {
  193. skb = gfar_new_skb(ndev);
  194. if (!skb) {
  195. pr_err("%s: Can't allocate RX buffers\n",
  196. ndev->name);
  197. goto err_rxalloc_fail;
  198. }
  199. rx_queue->rx_skbuff[j] = skb;
  200. gfar_new_rxbdp(rx_queue, rxbdp, skb);
  201. }
  202. rxbdp++;
  203. }
  204. }
  205. return 0;
  206. err_rxalloc_fail:
  207. free_skb_resources(priv);
  208. return -ENOMEM;
  209. }
  210. static int gfar_alloc_skb_resources(struct net_device *ndev)
  211. {
  212. void *vaddr;
  213. dma_addr_t addr;
  214. int i, j, k;
  215. struct gfar_private *priv = netdev_priv(ndev);
  216. struct device *dev = &priv->ofdev->dev;
  217. struct gfar_priv_tx_q *tx_queue = NULL;
  218. struct gfar_priv_rx_q *rx_queue = NULL;
  219. priv->total_tx_ring_size = 0;
  220. for (i = 0; i < priv->num_tx_queues; i++)
  221. priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
  222. priv->total_rx_ring_size = 0;
  223. for (i = 0; i < priv->num_rx_queues; i++)
  224. priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
  225. /* Allocate memory for the buffer descriptors */
  226. vaddr = dma_alloc_coherent(dev,
  227. sizeof(struct txbd8) * priv->total_tx_ring_size +
  228. sizeof(struct rxbd8) * priv->total_rx_ring_size,
  229. &addr, GFP_KERNEL);
  230. if (!vaddr) {
  231. if (netif_msg_ifup(priv))
  232. pr_err("%s: Could not allocate buffer descriptors!\n",
  233. ndev->name);
  234. return -ENOMEM;
  235. }
  236. for (i = 0; i < priv->num_tx_queues; i++) {
  237. tx_queue = priv->tx_queue[i];
  238. tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
  239. tx_queue->tx_bd_dma_base = addr;
  240. tx_queue->dev = ndev;
  241. /* enet DMA only understands physical addresses */
  242. addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
  243. vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
  244. }
  245. /* Start the rx descriptor ring where the tx ring leaves off */
  246. for (i = 0; i < priv->num_rx_queues; i++) {
  247. rx_queue = priv->rx_queue[i];
  248. rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
  249. rx_queue->rx_bd_dma_base = addr;
  250. rx_queue->dev = ndev;
  251. addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
  252. vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
  253. }
  254. /* Setup the skbuff rings */
  255. for (i = 0; i < priv->num_tx_queues; i++) {
  256. tx_queue = priv->tx_queue[i];
  257. tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
  258. tx_queue->tx_ring_size, GFP_KERNEL);
  259. if (!tx_queue->tx_skbuff) {
  260. if (netif_msg_ifup(priv))
  261. pr_err("%s: Could not allocate tx_skbuff\n",
  262. ndev->name);
  263. goto cleanup;
  264. }
  265. for (k = 0; k < tx_queue->tx_ring_size; k++)
  266. tx_queue->tx_skbuff[k] = NULL;
  267. }
  268. for (i = 0; i < priv->num_rx_queues; i++) {
  269. rx_queue = priv->rx_queue[i];
  270. rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
  271. rx_queue->rx_ring_size, GFP_KERNEL);
  272. if (!rx_queue->rx_skbuff) {
  273. if (netif_msg_ifup(priv))
  274. pr_err("%s: Could not allocate rx_skbuff\n",
  275. ndev->name);
  276. goto cleanup;
  277. }
  278. for (j = 0; j < rx_queue->rx_ring_size; j++)
  279. rx_queue->rx_skbuff[j] = NULL;
  280. }
  281. if (gfar_init_bds(ndev))
  282. goto cleanup;
  283. return 0;
  284. cleanup:
  285. free_skb_resources(priv);
  286. return -ENOMEM;
  287. }
  288. static void gfar_init_tx_rx_base(struct gfar_private *priv)
  289. {
  290. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  291. u32 __iomem *baddr;
  292. int i;
  293. baddr = &regs->tbase0;
  294. for(i = 0; i < priv->num_tx_queues; i++) {
  295. gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
  296. baddr += 2;
  297. }
  298. baddr = &regs->rbase0;
  299. for(i = 0; i < priv->num_rx_queues; i++) {
  300. gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
  301. baddr += 2;
  302. }
  303. }
  304. static void gfar_init_mac(struct net_device *ndev)
  305. {
  306. struct gfar_private *priv = netdev_priv(ndev);
  307. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  308. u32 rctrl = 0;
  309. u32 tctrl = 0;
  310. u32 attrs = 0;
  311. /* write the tx/rx base registers */
  312. gfar_init_tx_rx_base(priv);
  313. /* Configure the coalescing support */
  314. gfar_configure_coalescing(priv, 0xFF, 0xFF);
  315. if (priv->rx_filer_enable) {
  316. rctrl |= RCTRL_FILREN;
  317. /* Program the RIR0 reg with the required distribution */
  318. gfar_write(&regs->rir0, DEFAULT_RIR0);
  319. }
  320. if (priv->rx_csum_enable)
  321. rctrl |= RCTRL_CHECKSUMMING;
  322. if (priv->extended_hash) {
  323. rctrl |= RCTRL_EXTHASH;
  324. gfar_clear_exact_match(ndev);
  325. rctrl |= RCTRL_EMEN;
  326. }
  327. if (priv->padding) {
  328. rctrl &= ~RCTRL_PAL_MASK;
  329. rctrl |= RCTRL_PADDING(priv->padding);
  330. }
  331. /* keep vlan related bits if it's enabled */
  332. if (priv->vlgrp) {
  333. rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
  334. tctrl |= TCTRL_VLINS;
  335. }
  336. /* Init rctrl based on our settings */
  337. gfar_write(&regs->rctrl, rctrl);
  338. if (ndev->features & NETIF_F_IP_CSUM)
  339. tctrl |= TCTRL_INIT_CSUM;
  340. tctrl |= TCTRL_TXSCHED_PRIO;
  341. gfar_write(&regs->tctrl, tctrl);
  342. /* Set the extraction length and index */
  343. attrs = ATTRELI_EL(priv->rx_stash_size) |
  344. ATTRELI_EI(priv->rx_stash_index);
  345. gfar_write(&regs->attreli, attrs);
  346. /* Start with defaults, and add stashing or locking
  347. * depending on the approprate variables */
  348. attrs = ATTR_INIT_SETTINGS;
  349. if (priv->bd_stash_en)
  350. attrs |= ATTR_BDSTASH;
  351. if (priv->rx_stash_size != 0)
  352. attrs |= ATTR_BUFSTASH;
  353. gfar_write(&regs->attr, attrs);
  354. gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
  355. gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
  356. gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
  357. }
  358. static struct net_device_stats *gfar_get_stats(struct net_device *dev)
  359. {
  360. struct gfar_private *priv = netdev_priv(dev);
  361. struct netdev_queue *txq;
  362. unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
  363. unsigned long tx_packets = 0, tx_bytes = 0;
  364. int i = 0;
  365. for (i = 0; i < priv->num_rx_queues; i++) {
  366. rx_packets += priv->rx_queue[i]->stats.rx_packets;
  367. rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
  368. rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
  369. }
  370. dev->stats.rx_packets = rx_packets;
  371. dev->stats.rx_bytes = rx_bytes;
  372. dev->stats.rx_dropped = rx_dropped;
  373. for (i = 0; i < priv->num_tx_queues; i++) {
  374. txq = netdev_get_tx_queue(dev, i);
  375. tx_bytes += txq->tx_bytes;
  376. tx_packets += txq->tx_packets;
  377. }
  378. dev->stats.tx_bytes = tx_bytes;
  379. dev->stats.tx_packets = tx_packets;
  380. return &dev->stats;
  381. }
  382. static const struct net_device_ops gfar_netdev_ops = {
  383. .ndo_open = gfar_enet_open,
  384. .ndo_start_xmit = gfar_start_xmit,
  385. .ndo_stop = gfar_close,
  386. .ndo_change_mtu = gfar_change_mtu,
  387. .ndo_set_multicast_list = gfar_set_multi,
  388. .ndo_tx_timeout = gfar_timeout,
  389. .ndo_do_ioctl = gfar_ioctl,
  390. .ndo_select_queue = gfar_select_queue,
  391. .ndo_get_stats = gfar_get_stats,
  392. .ndo_vlan_rx_register = gfar_vlan_rx_register,
  393. .ndo_set_mac_address = eth_mac_addr,
  394. .ndo_validate_addr = eth_validate_addr,
  395. #ifdef CONFIG_NET_POLL_CONTROLLER
  396. .ndo_poll_controller = gfar_netpoll,
  397. #endif
  398. };
  399. unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
  400. unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
  401. void lock_rx_qs(struct gfar_private *priv)
  402. {
  403. int i = 0x0;
  404. for (i = 0; i < priv->num_rx_queues; i++)
  405. spin_lock(&priv->rx_queue[i]->rxlock);
  406. }
  407. void lock_tx_qs(struct gfar_private *priv)
  408. {
  409. int i = 0x0;
  410. for (i = 0; i < priv->num_tx_queues; i++)
  411. spin_lock(&priv->tx_queue[i]->txlock);
  412. }
  413. void unlock_rx_qs(struct gfar_private *priv)
  414. {
  415. int i = 0x0;
  416. for (i = 0; i < priv->num_rx_queues; i++)
  417. spin_unlock(&priv->rx_queue[i]->rxlock);
  418. }
  419. void unlock_tx_qs(struct gfar_private *priv)
  420. {
  421. int i = 0x0;
  422. for (i = 0; i < priv->num_tx_queues; i++)
  423. spin_unlock(&priv->tx_queue[i]->txlock);
  424. }
  425. /* Returns 1 if incoming frames use an FCB */
  426. static inline int gfar_uses_fcb(struct gfar_private *priv)
  427. {
  428. return priv->vlgrp || priv->rx_csum_enable;
  429. }
  430. u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb)
  431. {
  432. return skb_get_queue_mapping(skb);
  433. }
  434. static void free_tx_pointers(struct gfar_private *priv)
  435. {
  436. int i = 0;
  437. for (i = 0; i < priv->num_tx_queues; i++)
  438. kfree(priv->tx_queue[i]);
  439. }
  440. static void free_rx_pointers(struct gfar_private *priv)
  441. {
  442. int i = 0;
  443. for (i = 0; i < priv->num_rx_queues; i++)
  444. kfree(priv->rx_queue[i]);
  445. }
  446. static void unmap_group_regs(struct gfar_private *priv)
  447. {
  448. int i = 0;
  449. for (i = 0; i < MAXGROUPS; i++)
  450. if (priv->gfargrp[i].regs)
  451. iounmap(priv->gfargrp[i].regs);
  452. }
  453. static void disable_napi(struct gfar_private *priv)
  454. {
  455. int i = 0;
  456. for (i = 0; i < priv->num_grps; i++)
  457. napi_disable(&priv->gfargrp[i].napi);
  458. }
  459. static void enable_napi(struct gfar_private *priv)
  460. {
  461. int i = 0;
  462. for (i = 0; i < priv->num_grps; i++)
  463. napi_enable(&priv->gfargrp[i].napi);
  464. }
  465. static int gfar_parse_group(struct device_node *np,
  466. struct gfar_private *priv, const char *model)
  467. {
  468. u32 *queue_mask;
  469. u64 addr, size;
  470. addr = of_translate_address(np,
  471. of_get_address(np, 0, &size, NULL));
  472. priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);
  473. if (!priv->gfargrp[priv->num_grps].regs)
  474. return -ENOMEM;
  475. priv->gfargrp[priv->num_grps].interruptTransmit =
  476. irq_of_parse_and_map(np, 0);
  477. /* If we aren't the FEC we have multiple interrupts */
  478. if (model && strcasecmp(model, "FEC")) {
  479. priv->gfargrp[priv->num_grps].interruptReceive =
  480. irq_of_parse_and_map(np, 1);
  481. priv->gfargrp[priv->num_grps].interruptError =
  482. irq_of_parse_and_map(np,2);
  483. if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
  484. priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
  485. priv->gfargrp[priv->num_grps].interruptError < 0) {
  486. return -EINVAL;
  487. }
  488. }
  489. priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
  490. priv->gfargrp[priv->num_grps].priv = priv;
  491. spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
  492. if(priv->mode == MQ_MG_MODE) {
  493. queue_mask = (u32 *)of_get_property(np,
  494. "fsl,rx-bit-map", NULL);
  495. priv->gfargrp[priv->num_grps].rx_bit_map =
  496. queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
  497. queue_mask = (u32 *)of_get_property(np,
  498. "fsl,tx-bit-map", NULL);
  499. priv->gfargrp[priv->num_grps].tx_bit_map =
  500. queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
  501. } else {
  502. priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
  503. priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
  504. }
  505. priv->num_grps++;
  506. return 0;
  507. }
  508. static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
  509. {
  510. const char *model;
  511. const char *ctype;
  512. const void *mac_addr;
  513. int err = 0, i;
  514. struct net_device *dev = NULL;
  515. struct gfar_private *priv = NULL;
  516. struct device_node *np = ofdev->node;
  517. struct device_node *child = NULL;
  518. const u32 *stash;
  519. const u32 *stash_len;
  520. const u32 *stash_idx;
  521. unsigned int num_tx_qs, num_rx_qs;
  522. u32 *tx_queues, *rx_queues;
  523. if (!np || !of_device_is_available(np))
  524. return -ENODEV;
  525. /* parse the num of tx and rx queues */
  526. tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
  527. num_tx_qs = tx_queues ? *tx_queues : 1;
  528. if (num_tx_qs > MAX_TX_QS) {
  529. printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
  530. num_tx_qs, MAX_TX_QS);
  531. printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
  532. return -EINVAL;
  533. }
  534. rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
  535. num_rx_qs = rx_queues ? *rx_queues : 1;
  536. if (num_rx_qs > MAX_RX_QS) {
  537. printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
  538. num_tx_qs, MAX_TX_QS);
  539. printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
  540. return -EINVAL;
  541. }
  542. *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
  543. dev = *pdev;
  544. if (NULL == dev)
  545. return -ENOMEM;
  546. priv = netdev_priv(dev);
  547. priv->node = ofdev->node;
  548. priv->ndev = dev;
  549. dev->num_tx_queues = num_tx_qs;
  550. dev->real_num_tx_queues = num_tx_qs;
  551. priv->num_tx_queues = num_tx_qs;
  552. priv->num_rx_queues = num_rx_qs;
  553. priv->num_grps = 0x0;
  554. model = of_get_property(np, "model", NULL);
  555. for (i = 0; i < MAXGROUPS; i++)
  556. priv->gfargrp[i].regs = NULL;
  557. /* Parse and initialize group specific information */
  558. if (of_device_is_compatible(np, "fsl,etsec2")) {
  559. priv->mode = MQ_MG_MODE;
  560. for_each_child_of_node(np, child) {
  561. err = gfar_parse_group(child, priv, model);
  562. if (err)
  563. goto err_grp_init;
  564. }
  565. } else {
  566. priv->mode = SQ_SG_MODE;
  567. err = gfar_parse_group(np, priv, model);
  568. if(err)
  569. goto err_grp_init;
  570. }
  571. for (i = 0; i < priv->num_tx_queues; i++)
  572. priv->tx_queue[i] = NULL;
  573. for (i = 0; i < priv->num_rx_queues; i++)
  574. priv->rx_queue[i] = NULL;
  575. for (i = 0; i < priv->num_tx_queues; i++) {
  576. priv->tx_queue[i] = (struct gfar_priv_tx_q *)kmalloc(
  577. sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
  578. if (!priv->tx_queue[i]) {
  579. err = -ENOMEM;
  580. goto tx_alloc_failed;
  581. }
  582. priv->tx_queue[i]->tx_skbuff = NULL;
  583. priv->tx_queue[i]->qindex = i;
  584. priv->tx_queue[i]->dev = dev;
  585. spin_lock_init(&(priv->tx_queue[i]->txlock));
  586. }
  587. for (i = 0; i < priv->num_rx_queues; i++) {
  588. priv->rx_queue[i] = (struct gfar_priv_rx_q *)kmalloc(
  589. sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
  590. if (!priv->rx_queue[i]) {
  591. err = -ENOMEM;
  592. goto rx_alloc_failed;
  593. }
  594. priv->rx_queue[i]->rx_skbuff = NULL;
  595. priv->rx_queue[i]->qindex = i;
  596. priv->rx_queue[i]->dev = dev;
  597. spin_lock_init(&(priv->rx_queue[i]->rxlock));
  598. }
  599. stash = of_get_property(np, "bd-stash", NULL);
  600. if (stash) {
  601. priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
  602. priv->bd_stash_en = 1;
  603. }
  604. stash_len = of_get_property(np, "rx-stash-len", NULL);
  605. if (stash_len)
  606. priv->rx_stash_size = *stash_len;
  607. stash_idx = of_get_property(np, "rx-stash-idx", NULL);
  608. if (stash_idx)
  609. priv->rx_stash_index = *stash_idx;
  610. if (stash_len || stash_idx)
  611. priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
  612. mac_addr = of_get_mac_address(np);
  613. if (mac_addr)
  614. memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
  615. if (model && !strcasecmp(model, "TSEC"))
  616. priv->device_flags =
  617. FSL_GIANFAR_DEV_HAS_GIGABIT |
  618. FSL_GIANFAR_DEV_HAS_COALESCE |
  619. FSL_GIANFAR_DEV_HAS_RMON |
  620. FSL_GIANFAR_DEV_HAS_MULTI_INTR;
  621. if (model && !strcasecmp(model, "eTSEC"))
  622. priv->device_flags =
  623. FSL_GIANFAR_DEV_HAS_GIGABIT |
  624. FSL_GIANFAR_DEV_HAS_COALESCE |
  625. FSL_GIANFAR_DEV_HAS_RMON |
  626. FSL_GIANFAR_DEV_HAS_MULTI_INTR |
  627. FSL_GIANFAR_DEV_HAS_PADDING |
  628. FSL_GIANFAR_DEV_HAS_CSUM |
  629. FSL_GIANFAR_DEV_HAS_VLAN |
  630. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
  631. FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
  632. ctype = of_get_property(np, "phy-connection-type", NULL);
  633. /* We only care about rgmii-id. The rest are autodetected */
  634. if (ctype && !strcmp(ctype, "rgmii-id"))
  635. priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
  636. else
  637. priv->interface = PHY_INTERFACE_MODE_MII;
  638. if (of_get_property(np, "fsl,magic-packet", NULL))
  639. priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
  640. priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
  641. /* Find the TBI PHY. If it's not there, we don't support SGMII */
  642. priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
  643. return 0;
  644. rx_alloc_failed:
  645. free_rx_pointers(priv);
  646. tx_alloc_failed:
  647. free_tx_pointers(priv);
  648. err_grp_init:
  649. unmap_group_regs(priv);
  650. free_netdev(dev);
  651. return err;
  652. }
  653. /* Ioctl MII Interface */
  654. static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  655. {
  656. struct gfar_private *priv = netdev_priv(dev);
  657. if (!netif_running(dev))
  658. return -EINVAL;
  659. if (!priv->phydev)
  660. return -ENODEV;
  661. return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
  662. }
  663. static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
  664. {
  665. unsigned int new_bit_map = 0x0;
  666. int mask = 0x1 << (max_qs - 1), i;
  667. for (i = 0; i < max_qs; i++) {
  668. if (bit_map & mask)
  669. new_bit_map = new_bit_map + (1 << i);
  670. mask = mask >> 0x1;
  671. }
  672. return new_bit_map;
  673. }
  674. static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
  675. u32 class)
  676. {
  677. u32 rqfpr = FPR_FILER_MASK;
  678. u32 rqfcr = 0x0;
  679. rqfar--;
  680. rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
  681. ftp_rqfpr[rqfar] = rqfpr;
  682. ftp_rqfcr[rqfar] = rqfcr;
  683. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  684. rqfar--;
  685. rqfcr = RQFCR_CMP_NOMATCH;
  686. ftp_rqfpr[rqfar] = rqfpr;
  687. ftp_rqfcr[rqfar] = rqfcr;
  688. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  689. rqfar--;
  690. rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
  691. rqfpr = class;
  692. ftp_rqfcr[rqfar] = rqfcr;
  693. ftp_rqfpr[rqfar] = rqfpr;
  694. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  695. rqfar--;
  696. rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
  697. rqfpr = class;
  698. ftp_rqfcr[rqfar] = rqfcr;
  699. ftp_rqfpr[rqfar] = rqfpr;
  700. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  701. return rqfar;
  702. }
  703. static void gfar_init_filer_table(struct gfar_private *priv)
  704. {
  705. int i = 0x0;
  706. u32 rqfar = MAX_FILER_IDX;
  707. u32 rqfcr = 0x0;
  708. u32 rqfpr = FPR_FILER_MASK;
  709. /* Default rule */
  710. rqfcr = RQFCR_CMP_MATCH;
  711. ftp_rqfcr[rqfar] = rqfcr;
  712. ftp_rqfpr[rqfar] = rqfpr;
  713. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  714. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
  715. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
  716. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
  717. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
  718. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
  719. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
  720. /* cur_filer_idx indicated the fisrt non-masked rule */
  721. priv->cur_filer_idx = rqfar;
  722. /* Rest are masked rules */
  723. rqfcr = RQFCR_CMP_NOMATCH;
  724. for (i = 0; i < rqfar; i++) {
  725. ftp_rqfcr[i] = rqfcr;
  726. ftp_rqfpr[i] = rqfpr;
  727. gfar_write_filer(priv, i, rqfcr, rqfpr);
  728. }
  729. }
  730. /* Set up the ethernet device structure, private data,
  731. * and anything else we need before we start */
  732. static int gfar_probe(struct of_device *ofdev,
  733. const struct of_device_id *match)
  734. {
  735. u32 tempval;
  736. struct net_device *dev = NULL;
  737. struct gfar_private *priv = NULL;
  738. struct gfar __iomem *regs = NULL;
  739. int err = 0, i, grp_idx = 0;
  740. int len_devname;
  741. u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
  742. u32 isrg = 0;
  743. u32 __iomem *baddr;
  744. err = gfar_of_init(ofdev, &dev);
  745. if (err)
  746. return err;
  747. priv = netdev_priv(dev);
  748. priv->ndev = dev;
  749. priv->ofdev = ofdev;
  750. priv->node = ofdev->node;
  751. SET_NETDEV_DEV(dev, &ofdev->dev);
  752. spin_lock_init(&priv->bflock);
  753. INIT_WORK(&priv->reset_task, gfar_reset_task);
  754. dev_set_drvdata(&ofdev->dev, priv);
  755. regs = priv->gfargrp[0].regs;
  756. /* Stop the DMA engine now, in case it was running before */
  757. /* (The firmware could have used it, and left it running). */
  758. gfar_halt(dev);
  759. /* Reset MAC layer */
  760. gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
  761. /* We need to delay at least 3 TX clocks */
  762. udelay(2);
  763. tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
  764. gfar_write(&regs->maccfg1, tempval);
  765. /* Initialize MACCFG2. */
  766. gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  767. /* Initialize ECNTRL */
  768. gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  769. /* Set the dev->base_addr to the gfar reg region */
  770. dev->base_addr = (unsigned long) regs;
  771. SET_NETDEV_DEV(dev, &ofdev->dev);
  772. /* Fill in the dev structure */
  773. dev->watchdog_timeo = TX_TIMEOUT;
  774. dev->mtu = 1500;
  775. dev->netdev_ops = &gfar_netdev_ops;
  776. dev->ethtool_ops = &gfar_ethtool_ops;
  777. /* Register for napi ...We are registering NAPI for each grp */
  778. for (i = 0; i < priv->num_grps; i++)
  779. netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
  780. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
  781. priv->rx_csum_enable = 1;
  782. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
  783. } else
  784. priv->rx_csum_enable = 0;
  785. priv->vlgrp = NULL;
  786. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
  787. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  788. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
  789. priv->extended_hash = 1;
  790. priv->hash_width = 9;
  791. priv->hash_regs[0] = &regs->igaddr0;
  792. priv->hash_regs[1] = &regs->igaddr1;
  793. priv->hash_regs[2] = &regs->igaddr2;
  794. priv->hash_regs[3] = &regs->igaddr3;
  795. priv->hash_regs[4] = &regs->igaddr4;
  796. priv->hash_regs[5] = &regs->igaddr5;
  797. priv->hash_regs[6] = &regs->igaddr6;
  798. priv->hash_regs[7] = &regs->igaddr7;
  799. priv->hash_regs[8] = &regs->gaddr0;
  800. priv->hash_regs[9] = &regs->gaddr1;
  801. priv->hash_regs[10] = &regs->gaddr2;
  802. priv->hash_regs[11] = &regs->gaddr3;
  803. priv->hash_regs[12] = &regs->gaddr4;
  804. priv->hash_regs[13] = &regs->gaddr5;
  805. priv->hash_regs[14] = &regs->gaddr6;
  806. priv->hash_regs[15] = &regs->gaddr7;
  807. } else {
  808. priv->extended_hash = 0;
  809. priv->hash_width = 8;
  810. priv->hash_regs[0] = &regs->gaddr0;
  811. priv->hash_regs[1] = &regs->gaddr1;
  812. priv->hash_regs[2] = &regs->gaddr2;
  813. priv->hash_regs[3] = &regs->gaddr3;
  814. priv->hash_regs[4] = &regs->gaddr4;
  815. priv->hash_regs[5] = &regs->gaddr5;
  816. priv->hash_regs[6] = &regs->gaddr6;
  817. priv->hash_regs[7] = &regs->gaddr7;
  818. }
  819. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
  820. priv->padding = DEFAULT_PADDING;
  821. else
  822. priv->padding = 0;
  823. if (dev->features & NETIF_F_IP_CSUM)
  824. dev->hard_header_len += GMAC_FCB_LEN;
  825. /* Program the isrg regs only if number of grps > 1 */
  826. if (priv->num_grps > 1) {
  827. baddr = &regs->isrg0;
  828. for (i = 0; i < priv->num_grps; i++) {
  829. isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
  830. isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
  831. gfar_write(baddr, isrg);
  832. baddr++;
  833. isrg = 0x0;
  834. }
  835. }
  836. /* Need to reverse the bit maps as bit_map's MSB is q0
  837. * but, for_each_bit parses from right to left, which
  838. * basically reverses the queue numbers */
  839. for (i = 0; i< priv->num_grps; i++) {
  840. priv->gfargrp[i].tx_bit_map = reverse_bitmap(
  841. priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
  842. priv->gfargrp[i].rx_bit_map = reverse_bitmap(
  843. priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
  844. }
  845. /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
  846. * also assign queues to groups */
  847. for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
  848. priv->gfargrp[grp_idx].num_rx_queues = 0x0;
  849. for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
  850. priv->num_rx_queues) {
  851. priv->gfargrp[grp_idx].num_rx_queues++;
  852. priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
  853. rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
  854. rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
  855. }
  856. priv->gfargrp[grp_idx].num_tx_queues = 0x0;
  857. for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map,
  858. priv->num_tx_queues) {
  859. priv->gfargrp[grp_idx].num_tx_queues++;
  860. priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
  861. tstat = tstat | (TSTAT_CLEAR_THALT >> i);
  862. tqueue = tqueue | (TQUEUE_EN0 >> i);
  863. }
  864. priv->gfargrp[grp_idx].rstat = rstat;
  865. priv->gfargrp[grp_idx].tstat = tstat;
  866. rstat = tstat =0;
  867. }
  868. gfar_write(&regs->rqueue, rqueue);
  869. gfar_write(&regs->tqueue, tqueue);
  870. priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
  871. /* Initializing some of the rx/tx queue level parameters */
  872. for (i = 0; i < priv->num_tx_queues; i++) {
  873. priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
  874. priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
  875. priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
  876. priv->tx_queue[i]->txic = DEFAULT_TXIC;
  877. }
  878. for (i = 0; i < priv->num_rx_queues; i++) {
  879. priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
  880. priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
  881. priv->rx_queue[i]->rxic = DEFAULT_RXIC;
  882. }
  883. /* enable filer if using multiple RX queues*/
  884. if(priv->num_rx_queues > 1)
  885. priv->rx_filer_enable = 1;
  886. /* Enable most messages by default */
  887. priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  888. /* Carrier starts down, phylib will bring it up */
  889. netif_carrier_off(dev);
  890. err = register_netdev(dev);
  891. if (err) {
  892. printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
  893. dev->name);
  894. goto register_fail;
  895. }
  896. device_init_wakeup(&dev->dev,
  897. priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  898. /* fill out IRQ number and name fields */
  899. len_devname = strlen(dev->name);
  900. for (i = 0; i < priv->num_grps; i++) {
  901. strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
  902. len_devname);
  903. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  904. strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
  905. "_g", sizeof("_g"));
  906. priv->gfargrp[i].int_name_tx[
  907. strlen(priv->gfargrp[i].int_name_tx)] = i+48;
  908. strncpy(&priv->gfargrp[i].int_name_tx[strlen(
  909. priv->gfargrp[i].int_name_tx)],
  910. "_tx", sizeof("_tx") + 1);
  911. strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
  912. len_devname);
  913. strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
  914. "_g", sizeof("_g"));
  915. priv->gfargrp[i].int_name_rx[
  916. strlen(priv->gfargrp[i].int_name_rx)] = i+48;
  917. strncpy(&priv->gfargrp[i].int_name_rx[strlen(
  918. priv->gfargrp[i].int_name_rx)],
  919. "_rx", sizeof("_rx") + 1);
  920. strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
  921. len_devname);
  922. strncpy(&priv->gfargrp[i].int_name_er[len_devname],
  923. "_g", sizeof("_g"));
  924. priv->gfargrp[i].int_name_er[strlen(
  925. priv->gfargrp[i].int_name_er)] = i+48;
  926. strncpy(&priv->gfargrp[i].int_name_er[strlen(\
  927. priv->gfargrp[i].int_name_er)],
  928. "_er", sizeof("_er") + 1);
  929. } else
  930. priv->gfargrp[i].int_name_tx[len_devname] = '\0';
  931. }
  932. /* Initialize the filer table */
  933. gfar_init_filer_table(priv);
  934. /* Create all the sysfs files */
  935. gfar_init_sysfs(dev);
  936. /* Print out the device info */
  937. printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
  938. /* Even more device info helps when determining which kernel */
  939. /* provided which set of benchmarks. */
  940. printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
  941. for (i = 0; i < priv->num_rx_queues; i++)
  942. printk(KERN_INFO "%s: :RX BD ring size for Q[%d]: %d\n",
  943. dev->name, i, priv->rx_queue[i]->rx_ring_size);
  944. for(i = 0; i < priv->num_tx_queues; i++)
  945. printk(KERN_INFO "%s:TX BD ring size for Q[%d]: %d\n",
  946. dev->name, i, priv->tx_queue[i]->tx_ring_size);
  947. return 0;
  948. register_fail:
  949. unmap_group_regs(priv);
  950. free_tx_pointers(priv);
  951. free_rx_pointers(priv);
  952. if (priv->phy_node)
  953. of_node_put(priv->phy_node);
  954. if (priv->tbi_node)
  955. of_node_put(priv->tbi_node);
  956. free_netdev(dev);
  957. return err;
  958. }
  959. static int gfar_remove(struct of_device *ofdev)
  960. {
  961. struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
  962. if (priv->phy_node)
  963. of_node_put(priv->phy_node);
  964. if (priv->tbi_node)
  965. of_node_put(priv->tbi_node);
  966. dev_set_drvdata(&ofdev->dev, NULL);
  967. unregister_netdev(priv->ndev);
  968. unmap_group_regs(priv);
  969. free_netdev(priv->ndev);
  970. return 0;
  971. }
  972. #ifdef CONFIG_PM
  973. static int gfar_suspend(struct device *dev)
  974. {
  975. struct gfar_private *priv = dev_get_drvdata(dev);
  976. struct net_device *ndev = priv->ndev;
  977. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  978. unsigned long flags;
  979. u32 tempval;
  980. int magic_packet = priv->wol_en &&
  981. (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  982. netif_device_detach(ndev);
  983. if (netif_running(ndev)) {
  984. local_irq_save(flags);
  985. lock_tx_qs(priv);
  986. lock_rx_qs(priv);
  987. gfar_halt_nodisable(ndev);
  988. /* Disable Tx, and Rx if wake-on-LAN is disabled. */
  989. tempval = gfar_read(&regs->maccfg1);
  990. tempval &= ~MACCFG1_TX_EN;
  991. if (!magic_packet)
  992. tempval &= ~MACCFG1_RX_EN;
  993. gfar_write(&regs->maccfg1, tempval);
  994. unlock_rx_qs(priv);
  995. unlock_tx_qs(priv);
  996. local_irq_restore(flags);
  997. disable_napi(priv);
  998. if (magic_packet) {
  999. /* Enable interrupt on Magic Packet */
  1000. gfar_write(&regs->imask, IMASK_MAG);
  1001. /* Enable Magic Packet mode */
  1002. tempval = gfar_read(&regs->maccfg2);
  1003. tempval |= MACCFG2_MPEN;
  1004. gfar_write(&regs->maccfg2, tempval);
  1005. } else {
  1006. phy_stop(priv->phydev);
  1007. }
  1008. }
  1009. return 0;
  1010. }
  1011. static int gfar_resume(struct device *dev)
  1012. {
  1013. struct gfar_private *priv = dev_get_drvdata(dev);
  1014. struct net_device *ndev = priv->ndev;
  1015. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1016. unsigned long flags;
  1017. u32 tempval;
  1018. int magic_packet = priv->wol_en &&
  1019. (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  1020. if (!netif_running(ndev)) {
  1021. netif_device_attach(ndev);
  1022. return 0;
  1023. }
  1024. if (!magic_packet && priv->phydev)
  1025. phy_start(priv->phydev);
  1026. /* Disable Magic Packet mode, in case something
  1027. * else woke us up.
  1028. */
  1029. local_irq_save(flags);
  1030. lock_tx_qs(priv);
  1031. lock_rx_qs(priv);
  1032. tempval = gfar_read(&regs->maccfg2);
  1033. tempval &= ~MACCFG2_MPEN;
  1034. gfar_write(&regs->maccfg2, tempval);
  1035. gfar_start(ndev);
  1036. unlock_rx_qs(priv);
  1037. unlock_tx_qs(priv);
  1038. local_irq_restore(flags);
  1039. netif_device_attach(ndev);
  1040. enable_napi(priv);
  1041. return 0;
  1042. }
  1043. static int gfar_restore(struct device *dev)
  1044. {
  1045. struct gfar_private *priv = dev_get_drvdata(dev);
  1046. struct net_device *ndev = priv->ndev;
  1047. if (!netif_running(ndev))
  1048. return 0;
  1049. gfar_init_bds(ndev);
  1050. init_registers(ndev);
  1051. gfar_set_mac_address(ndev);
  1052. gfar_init_mac(ndev);
  1053. gfar_start(ndev);
  1054. priv->oldlink = 0;
  1055. priv->oldspeed = 0;
  1056. priv->oldduplex = -1;
  1057. if (priv->phydev)
  1058. phy_start(priv->phydev);
  1059. netif_device_attach(ndev);
  1060. enable_napi(priv);
  1061. return 0;
  1062. }
  1063. static struct dev_pm_ops gfar_pm_ops = {
  1064. .suspend = gfar_suspend,
  1065. .resume = gfar_resume,
  1066. .freeze = gfar_suspend,
  1067. .thaw = gfar_resume,
  1068. .restore = gfar_restore,
  1069. };
  1070. #define GFAR_PM_OPS (&gfar_pm_ops)
  1071. static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
  1072. {
  1073. return gfar_suspend(&ofdev->dev);
  1074. }
  1075. static int gfar_legacy_resume(struct of_device *ofdev)
  1076. {
  1077. return gfar_resume(&ofdev->dev);
  1078. }
  1079. #else
  1080. #define GFAR_PM_OPS NULL
  1081. #define gfar_legacy_suspend NULL
  1082. #define gfar_legacy_resume NULL
  1083. #endif
  1084. /* Reads the controller's registers to determine what interface
  1085. * connects it to the PHY.
  1086. */
  1087. static phy_interface_t gfar_get_interface(struct net_device *dev)
  1088. {
  1089. struct gfar_private *priv = netdev_priv(dev);
  1090. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1091. u32 ecntrl;
  1092. ecntrl = gfar_read(&regs->ecntrl);
  1093. if (ecntrl & ECNTRL_SGMII_MODE)
  1094. return PHY_INTERFACE_MODE_SGMII;
  1095. if (ecntrl & ECNTRL_TBI_MODE) {
  1096. if (ecntrl & ECNTRL_REDUCED_MODE)
  1097. return PHY_INTERFACE_MODE_RTBI;
  1098. else
  1099. return PHY_INTERFACE_MODE_TBI;
  1100. }
  1101. if (ecntrl & ECNTRL_REDUCED_MODE) {
  1102. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  1103. return PHY_INTERFACE_MODE_RMII;
  1104. else {
  1105. phy_interface_t interface = priv->interface;
  1106. /*
  1107. * This isn't autodetected right now, so it must
  1108. * be set by the device tree or platform code.
  1109. */
  1110. if (interface == PHY_INTERFACE_MODE_RGMII_ID)
  1111. return PHY_INTERFACE_MODE_RGMII_ID;
  1112. return PHY_INTERFACE_MODE_RGMII;
  1113. }
  1114. }
  1115. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
  1116. return PHY_INTERFACE_MODE_GMII;
  1117. return PHY_INTERFACE_MODE_MII;
  1118. }
  1119. /* Initializes driver's PHY state, and attaches to the PHY.
  1120. * Returns 0 on success.
  1121. */
  1122. static int init_phy(struct net_device *dev)
  1123. {
  1124. struct gfar_private *priv = netdev_priv(dev);
  1125. uint gigabit_support =
  1126. priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
  1127. SUPPORTED_1000baseT_Full : 0;
  1128. phy_interface_t interface;
  1129. priv->oldlink = 0;
  1130. priv->oldspeed = 0;
  1131. priv->oldduplex = -1;
  1132. interface = gfar_get_interface(dev);
  1133. priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
  1134. interface);
  1135. if (!priv->phydev)
  1136. priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
  1137. interface);
  1138. if (!priv->phydev) {
  1139. dev_err(&dev->dev, "could not attach to PHY\n");
  1140. return -ENODEV;
  1141. }
  1142. if (interface == PHY_INTERFACE_MODE_SGMII)
  1143. gfar_configure_serdes(dev);
  1144. /* Remove any features not supported by the controller */
  1145. priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
  1146. priv->phydev->advertising = priv->phydev->supported;
  1147. return 0;
  1148. }
  1149. /*
  1150. * Initialize TBI PHY interface for communicating with the
  1151. * SERDES lynx PHY on the chip. We communicate with this PHY
  1152. * through the MDIO bus on each controller, treating it as a
  1153. * "normal" PHY at the address found in the TBIPA register. We assume
  1154. * that the TBIPA register is valid. Either the MDIO bus code will set
  1155. * it to a value that doesn't conflict with other PHYs on the bus, or the
  1156. * value doesn't matter, as there are no other PHYs on the bus.
  1157. */
  1158. static void gfar_configure_serdes(struct net_device *dev)
  1159. {
  1160. struct gfar_private *priv = netdev_priv(dev);
  1161. struct phy_device *tbiphy;
  1162. if (!priv->tbi_node) {
  1163. dev_warn(&dev->dev, "error: SGMII mode requires that the "
  1164. "device tree specify a tbi-handle\n");
  1165. return;
  1166. }
  1167. tbiphy = of_phy_find_device(priv->tbi_node);
  1168. if (!tbiphy) {
  1169. dev_err(&dev->dev, "error: Could not get TBI device\n");
  1170. return;
  1171. }
  1172. /*
  1173. * If the link is already up, we must already be ok, and don't need to
  1174. * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
  1175. * everything for us? Resetting it takes the link down and requires
  1176. * several seconds for it to come back.
  1177. */
  1178. if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
  1179. return;
  1180. /* Single clk mode, mii mode off(for serdes communication) */
  1181. phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
  1182. phy_write(tbiphy, MII_ADVERTISE,
  1183. ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
  1184. ADVERTISE_1000XPSE_ASYM);
  1185. phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
  1186. BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
  1187. }
  1188. static void init_registers(struct net_device *dev)
  1189. {
  1190. struct gfar_private *priv = netdev_priv(dev);
  1191. struct gfar __iomem *regs = NULL;
  1192. int i = 0;
  1193. for (i = 0; i < priv->num_grps; i++) {
  1194. regs = priv->gfargrp[i].regs;
  1195. /* Clear IEVENT */
  1196. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  1197. /* Initialize IMASK */
  1198. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1199. }
  1200. regs = priv->gfargrp[0].regs;
  1201. /* Init hash registers to zero */
  1202. gfar_write(&regs->igaddr0, 0);
  1203. gfar_write(&regs->igaddr1, 0);
  1204. gfar_write(&regs->igaddr2, 0);
  1205. gfar_write(&regs->igaddr3, 0);
  1206. gfar_write(&regs->igaddr4, 0);
  1207. gfar_write(&regs->igaddr5, 0);
  1208. gfar_write(&regs->igaddr6, 0);
  1209. gfar_write(&regs->igaddr7, 0);
  1210. gfar_write(&regs->gaddr0, 0);
  1211. gfar_write(&regs->gaddr1, 0);
  1212. gfar_write(&regs->gaddr2, 0);
  1213. gfar_write(&regs->gaddr3, 0);
  1214. gfar_write(&regs->gaddr4, 0);
  1215. gfar_write(&regs->gaddr5, 0);
  1216. gfar_write(&regs->gaddr6, 0);
  1217. gfar_write(&regs->gaddr7, 0);
  1218. /* Zero out the rmon mib registers if it has them */
  1219. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
  1220. memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
  1221. /* Mask off the CAM interrupts */
  1222. gfar_write(&regs->rmon.cam1, 0xffffffff);
  1223. gfar_write(&regs->rmon.cam2, 0xffffffff);
  1224. }
  1225. /* Initialize the max receive buffer length */
  1226. gfar_write(&regs->mrblr, priv->rx_buffer_size);
  1227. /* Initialize the Minimum Frame Length Register */
  1228. gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
  1229. }
  1230. /* Halt the receive and transmit queues */
  1231. static void gfar_halt_nodisable(struct net_device *dev)
  1232. {
  1233. struct gfar_private *priv = netdev_priv(dev);
  1234. struct gfar __iomem *regs = NULL;
  1235. u32 tempval;
  1236. int i = 0;
  1237. for (i = 0; i < priv->num_grps; i++) {
  1238. regs = priv->gfargrp[i].regs;
  1239. /* Mask all interrupts */
  1240. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1241. /* Clear all interrupts */
  1242. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  1243. }
  1244. regs = priv->gfargrp[0].regs;
  1245. /* Stop the DMA, and wait for it to stop */
  1246. tempval = gfar_read(&regs->dmactrl);
  1247. if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
  1248. != (DMACTRL_GRS | DMACTRL_GTS)) {
  1249. tempval |= (DMACTRL_GRS | DMACTRL_GTS);
  1250. gfar_write(&regs->dmactrl, tempval);
  1251. while (!(gfar_read(&regs->ievent) &
  1252. (IEVENT_GRSC | IEVENT_GTSC)))
  1253. cpu_relax();
  1254. }
  1255. }
  1256. /* Halt the receive and transmit queues */
  1257. void gfar_halt(struct net_device *dev)
  1258. {
  1259. struct gfar_private *priv = netdev_priv(dev);
  1260. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1261. u32 tempval;
  1262. gfar_halt_nodisable(dev);
  1263. /* Disable Rx and Tx */
  1264. tempval = gfar_read(&regs->maccfg1);
  1265. tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
  1266. gfar_write(&regs->maccfg1, tempval);
  1267. }
  1268. static void free_grp_irqs(struct gfar_priv_grp *grp)
  1269. {
  1270. free_irq(grp->interruptError, grp);
  1271. free_irq(grp->interruptTransmit, grp);
  1272. free_irq(grp->interruptReceive, grp);
  1273. }
  1274. void stop_gfar(struct net_device *dev)
  1275. {
  1276. struct gfar_private *priv = netdev_priv(dev);
  1277. unsigned long flags;
  1278. int i;
  1279. phy_stop(priv->phydev);
  1280. /* Lock it down */
  1281. local_irq_save(flags);
  1282. lock_tx_qs(priv);
  1283. lock_rx_qs(priv);
  1284. gfar_halt(dev);
  1285. unlock_rx_qs(priv);
  1286. unlock_tx_qs(priv);
  1287. local_irq_restore(flags);
  1288. /* Free the IRQs */
  1289. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1290. for (i = 0; i < priv->num_grps; i++)
  1291. free_grp_irqs(&priv->gfargrp[i]);
  1292. } else {
  1293. for (i = 0; i < priv->num_grps; i++)
  1294. free_irq(priv->gfargrp[i].interruptTransmit,
  1295. &priv->gfargrp[i]);
  1296. }
  1297. free_skb_resources(priv);
  1298. }
  1299. static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
  1300. {
  1301. struct txbd8 *txbdp;
  1302. struct gfar_private *priv = netdev_priv(tx_queue->dev);
  1303. int i, j;
  1304. txbdp = tx_queue->tx_bd_base;
  1305. for (i = 0; i < tx_queue->tx_ring_size; i++) {
  1306. if (!tx_queue->tx_skbuff[i])
  1307. continue;
  1308. dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
  1309. txbdp->length, DMA_TO_DEVICE);
  1310. txbdp->lstatus = 0;
  1311. for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
  1312. j++) {
  1313. txbdp++;
  1314. dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
  1315. txbdp->length, DMA_TO_DEVICE);
  1316. }
  1317. txbdp++;
  1318. dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
  1319. tx_queue->tx_skbuff[i] = NULL;
  1320. }
  1321. kfree(tx_queue->tx_skbuff);
  1322. }
  1323. static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
  1324. {
  1325. struct rxbd8 *rxbdp;
  1326. struct gfar_private *priv = netdev_priv(rx_queue->dev);
  1327. int i;
  1328. rxbdp = rx_queue->rx_bd_base;
  1329. for (i = 0; i < rx_queue->rx_ring_size; i++) {
  1330. if (rx_queue->rx_skbuff[i]) {
  1331. dma_unmap_single(&priv->ofdev->dev,
  1332. rxbdp->bufPtr, priv->rx_buffer_size,
  1333. DMA_FROM_DEVICE);
  1334. dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
  1335. rx_queue->rx_skbuff[i] = NULL;
  1336. }
  1337. rxbdp->lstatus = 0;
  1338. rxbdp->bufPtr = 0;
  1339. rxbdp++;
  1340. }
  1341. kfree(rx_queue->rx_skbuff);
  1342. }
  1343. /* If there are any tx skbs or rx skbs still around, free them.
  1344. * Then free tx_skbuff and rx_skbuff */
  1345. static void free_skb_resources(struct gfar_private *priv)
  1346. {
  1347. struct gfar_priv_tx_q *tx_queue = NULL;
  1348. struct gfar_priv_rx_q *rx_queue = NULL;
  1349. int i;
  1350. /* Go through all the buffer descriptors and free their data buffers */
  1351. for (i = 0; i < priv->num_tx_queues; i++) {
  1352. tx_queue = priv->tx_queue[i];
  1353. if(!tx_queue->tx_skbuff)
  1354. free_skb_tx_queue(tx_queue);
  1355. }
  1356. for (i = 0; i < priv->num_rx_queues; i++) {
  1357. rx_queue = priv->rx_queue[i];
  1358. if(!rx_queue->rx_skbuff)
  1359. free_skb_rx_queue(rx_queue);
  1360. }
  1361. dma_free_coherent(&priv->ofdev->dev,
  1362. sizeof(struct txbd8) * priv->total_tx_ring_size +
  1363. sizeof(struct rxbd8) * priv->total_rx_ring_size,
  1364. priv->tx_queue[0]->tx_bd_base,
  1365. priv->tx_queue[0]->tx_bd_dma_base);
  1366. }
  1367. void gfar_start(struct net_device *dev)
  1368. {
  1369. struct gfar_private *priv = netdev_priv(dev);
  1370. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1371. u32 tempval;
  1372. int i = 0;
  1373. /* Enable Rx and Tx in MACCFG1 */
  1374. tempval = gfar_read(&regs->maccfg1);
  1375. tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
  1376. gfar_write(&regs->maccfg1, tempval);
  1377. /* Initialize DMACTRL to have WWR and WOP */
  1378. tempval = gfar_read(&regs->dmactrl);
  1379. tempval |= DMACTRL_INIT_SETTINGS;
  1380. gfar_write(&regs->dmactrl, tempval);
  1381. /* Make sure we aren't stopped */
  1382. tempval = gfar_read(&regs->dmactrl);
  1383. tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
  1384. gfar_write(&regs->dmactrl, tempval);
  1385. for (i = 0; i < priv->num_grps; i++) {
  1386. regs = priv->gfargrp[i].regs;
  1387. /* Clear THLT/RHLT, so that the DMA starts polling now */
  1388. gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
  1389. gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
  1390. /* Unmask the interrupts we look for */
  1391. gfar_write(&regs->imask, IMASK_DEFAULT);
  1392. }
  1393. dev->trans_start = jiffies;
  1394. }
  1395. void gfar_configure_coalescing(struct gfar_private *priv,
  1396. unsigned long tx_mask, unsigned long rx_mask)
  1397. {
  1398. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1399. u32 __iomem *baddr;
  1400. int i = 0;
  1401. /* Backward compatible case ---- even if we enable
  1402. * multiple queues, there's only single reg to program
  1403. */
  1404. gfar_write(&regs->txic, 0);
  1405. if(likely(priv->tx_queue[0]->txcoalescing))
  1406. gfar_write(&regs->txic, priv->tx_queue[0]->txic);
  1407. gfar_write(&regs->rxic, 0);
  1408. if(unlikely(priv->rx_queue[0]->rxcoalescing))
  1409. gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
  1410. if (priv->mode == MQ_MG_MODE) {
  1411. baddr = &regs->txic0;
  1412. for_each_bit (i, &tx_mask, priv->num_tx_queues) {
  1413. if (likely(priv->tx_queue[i]->txcoalescing)) {
  1414. gfar_write(baddr + i, 0);
  1415. gfar_write(baddr + i, priv->tx_queue[i]->txic);
  1416. }
  1417. }
  1418. baddr = &regs->rxic0;
  1419. for_each_bit (i, &rx_mask, priv->num_rx_queues) {
  1420. if (likely(priv->rx_queue[i]->rxcoalescing)) {
  1421. gfar_write(baddr + i, 0);
  1422. gfar_write(baddr + i, priv->rx_queue[i]->rxic);
  1423. }
  1424. }
  1425. }
  1426. }
  1427. static int register_grp_irqs(struct gfar_priv_grp *grp)
  1428. {
  1429. struct gfar_private *priv = grp->priv;
  1430. struct net_device *dev = priv->ndev;
  1431. int err;
  1432. /* If the device has multiple interrupts, register for
  1433. * them. Otherwise, only register for the one */
  1434. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1435. /* Install our interrupt handlers for Error,
  1436. * Transmit, and Receive */
  1437. if ((err = request_irq(grp->interruptError, gfar_error, 0,
  1438. grp->int_name_er,grp)) < 0) {
  1439. if (netif_msg_intr(priv))
  1440. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  1441. dev->name, grp->interruptError);
  1442. goto err_irq_fail;
  1443. }
  1444. if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
  1445. 0, grp->int_name_tx, grp)) < 0) {
  1446. if (netif_msg_intr(priv))
  1447. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  1448. dev->name, grp->interruptTransmit);
  1449. goto tx_irq_fail;
  1450. }
  1451. if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
  1452. grp->int_name_rx, grp)) < 0) {
  1453. if (netif_msg_intr(priv))
  1454. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  1455. dev->name, grp->interruptReceive);
  1456. goto rx_irq_fail;
  1457. }
  1458. } else {
  1459. if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
  1460. grp->int_name_tx, grp)) < 0) {
  1461. if (netif_msg_intr(priv))
  1462. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  1463. dev->name, grp->interruptTransmit);
  1464. goto err_irq_fail;
  1465. }
  1466. }
  1467. return 0;
  1468. rx_irq_fail:
  1469. free_irq(grp->interruptTransmit, grp);
  1470. tx_irq_fail:
  1471. free_irq(grp->interruptError, grp);
  1472. err_irq_fail:
  1473. return err;
  1474. }
  1475. /* Bring the controller up and running */
  1476. int startup_gfar(struct net_device *ndev)
  1477. {
  1478. struct gfar_private *priv = netdev_priv(ndev);
  1479. struct gfar __iomem *regs = NULL;
  1480. int err, i, j;
  1481. for (i = 0; i < priv->num_grps; i++) {
  1482. regs= priv->gfargrp[i].regs;
  1483. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1484. }
  1485. regs= priv->gfargrp[0].regs;
  1486. err = gfar_alloc_skb_resources(ndev);
  1487. if (err)
  1488. return err;
  1489. gfar_init_mac(ndev);
  1490. for (i = 0; i < priv->num_grps; i++) {
  1491. err = register_grp_irqs(&priv->gfargrp[i]);
  1492. if (err) {
  1493. for (j = 0; j < i; j++)
  1494. free_grp_irqs(&priv->gfargrp[j]);
  1495. goto irq_fail;
  1496. }
  1497. }
  1498. /* Start the controller */
  1499. gfar_start(ndev);
  1500. phy_start(priv->phydev);
  1501. gfar_configure_coalescing(priv, 0xFF, 0xFF);
  1502. return 0;
  1503. irq_fail:
  1504. free_skb_resources(priv);
  1505. return err;
  1506. }
  1507. /* Called when something needs to use the ethernet device */
  1508. /* Returns 0 for success. */
  1509. static int gfar_enet_open(struct net_device *dev)
  1510. {
  1511. struct gfar_private *priv = netdev_priv(dev);
  1512. int err;
  1513. enable_napi(priv);
  1514. skb_queue_head_init(&priv->rx_recycle);
  1515. /* Initialize a bunch of registers */
  1516. init_registers(dev);
  1517. gfar_set_mac_address(dev);
  1518. err = init_phy(dev);
  1519. if (err) {
  1520. disable_napi(priv);
  1521. return err;
  1522. }
  1523. err = startup_gfar(dev);
  1524. if (err) {
  1525. disable_napi(priv);
  1526. return err;
  1527. }
  1528. netif_tx_start_all_queues(dev);
  1529. device_set_wakeup_enable(&dev->dev, priv->wol_en);
  1530. return err;
  1531. }
  1532. static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
  1533. {
  1534. struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
  1535. memset(fcb, 0, GMAC_FCB_LEN);
  1536. return fcb;
  1537. }
  1538. static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
  1539. {
  1540. u8 flags = 0;
  1541. /* If we're here, it's a IP packet with a TCP or UDP
  1542. * payload. We set it to checksum, using a pseudo-header
  1543. * we provide
  1544. */
  1545. flags = TXFCB_DEFAULT;
  1546. /* Tell the controller what the protocol is */
  1547. /* And provide the already calculated phcs */
  1548. if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
  1549. flags |= TXFCB_UDP;
  1550. fcb->phcs = udp_hdr(skb)->check;
  1551. } else
  1552. fcb->phcs = tcp_hdr(skb)->check;
  1553. /* l3os is the distance between the start of the
  1554. * frame (skb->data) and the start of the IP hdr.
  1555. * l4os is the distance between the start of the
  1556. * l3 hdr and the l4 hdr */
  1557. fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
  1558. fcb->l4os = skb_network_header_len(skb);
  1559. fcb->flags = flags;
  1560. }
  1561. void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
  1562. {
  1563. fcb->flags |= TXFCB_VLN;
  1564. fcb->vlctl = vlan_tx_tag_get(skb);
  1565. }
  1566. static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
  1567. struct txbd8 *base, int ring_size)
  1568. {
  1569. struct txbd8 *new_bd = bdp + stride;
  1570. return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
  1571. }
  1572. static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
  1573. int ring_size)
  1574. {
  1575. return skip_txbd(bdp, 1, base, ring_size);
  1576. }
  1577. /* This is called by the kernel when a frame is ready for transmission. */
  1578. /* It is pointed to by the dev->hard_start_xmit function pointer */
  1579. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1580. {
  1581. struct gfar_private *priv = netdev_priv(dev);
  1582. struct gfar_priv_tx_q *tx_queue = NULL;
  1583. struct netdev_queue *txq;
  1584. struct gfar __iomem *regs = NULL;
  1585. struct txfcb *fcb = NULL;
  1586. struct txbd8 *txbdp, *txbdp_start, *base;
  1587. u32 lstatus;
  1588. int i, rq = 0;
  1589. u32 bufaddr;
  1590. unsigned long flags;
  1591. unsigned int nr_frags, length;
  1592. rq = skb->queue_mapping;
  1593. tx_queue = priv->tx_queue[rq];
  1594. txq = netdev_get_tx_queue(dev, rq);
  1595. base = tx_queue->tx_bd_base;
  1596. regs = tx_queue->grp->regs;
  1597. /* make space for additional header when fcb is needed */
  1598. if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
  1599. (priv->vlgrp && vlan_tx_tag_present(skb))) &&
  1600. (skb_headroom(skb) < GMAC_FCB_LEN)) {
  1601. struct sk_buff *skb_new;
  1602. skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
  1603. if (!skb_new) {
  1604. dev->stats.tx_errors++;
  1605. kfree_skb(skb);
  1606. return NETDEV_TX_OK;
  1607. }
  1608. kfree_skb(skb);
  1609. skb = skb_new;
  1610. }
  1611. /* total number of fragments in the SKB */
  1612. nr_frags = skb_shinfo(skb)->nr_frags;
  1613. /* check if there is space to queue this packet */
  1614. if ((nr_frags+1) > tx_queue->num_txbdfree) {
  1615. /* no space, stop the queue */
  1616. netif_tx_stop_queue(txq);
  1617. dev->stats.tx_fifo_errors++;
  1618. return NETDEV_TX_BUSY;
  1619. }
  1620. /* Update transmit stats */
  1621. txq->tx_bytes += skb->len;
  1622. txq->tx_packets ++;
  1623. txbdp = txbdp_start = tx_queue->cur_tx;
  1624. if (nr_frags == 0) {
  1625. lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
  1626. } else {
  1627. /* Place the fragment addresses and lengths into the TxBDs */
  1628. for (i = 0; i < nr_frags; i++) {
  1629. /* Point at the next BD, wrapping as needed */
  1630. txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
  1631. length = skb_shinfo(skb)->frags[i].size;
  1632. lstatus = txbdp->lstatus | length |
  1633. BD_LFLAG(TXBD_READY);
  1634. /* Handle the last BD specially */
  1635. if (i == nr_frags - 1)
  1636. lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
  1637. bufaddr = dma_map_page(&priv->ofdev->dev,
  1638. skb_shinfo(skb)->frags[i].page,
  1639. skb_shinfo(skb)->frags[i].page_offset,
  1640. length,
  1641. DMA_TO_DEVICE);
  1642. /* set the TxBD length and buffer pointer */
  1643. txbdp->bufPtr = bufaddr;
  1644. txbdp->lstatus = lstatus;
  1645. }
  1646. lstatus = txbdp_start->lstatus;
  1647. }
  1648. /* Set up checksumming */
  1649. if (CHECKSUM_PARTIAL == skb->ip_summed) {
  1650. fcb = gfar_add_fcb(skb);
  1651. lstatus |= BD_LFLAG(TXBD_TOE);
  1652. gfar_tx_checksum(skb, fcb);
  1653. }
  1654. if (priv->vlgrp && vlan_tx_tag_present(skb)) {
  1655. if (unlikely(NULL == fcb)) {
  1656. fcb = gfar_add_fcb(skb);
  1657. lstatus |= BD_LFLAG(TXBD_TOE);
  1658. }
  1659. gfar_tx_vlan(skb, fcb);
  1660. }
  1661. /* setup the TxBD length and buffer pointer for the first BD */
  1662. tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
  1663. txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
  1664. skb_headlen(skb), DMA_TO_DEVICE);
  1665. lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
  1666. /*
  1667. * We can work in parallel with gfar_clean_tx_ring(), except
  1668. * when modifying num_txbdfree. Note that we didn't grab the lock
  1669. * when we were reading the num_txbdfree and checking for available
  1670. * space, that's because outside of this function it can only grow,
  1671. * and once we've got needed space, it cannot suddenly disappear.
  1672. *
  1673. * The lock also protects us from gfar_error(), which can modify
  1674. * regs->tstat and thus retrigger the transfers, which is why we
  1675. * also must grab the lock before setting ready bit for the first
  1676. * to be transmitted BD.
  1677. */
  1678. spin_lock_irqsave(&tx_queue->txlock, flags);
  1679. /*
  1680. * The powerpc-specific eieio() is used, as wmb() has too strong
  1681. * semantics (it requires synchronization between cacheable and
  1682. * uncacheable mappings, which eieio doesn't provide and which we
  1683. * don't need), thus requiring a more expensive sync instruction. At
  1684. * some point, the set of architecture-independent barrier functions
  1685. * should be expanded to include weaker barriers.
  1686. */
  1687. eieio();
  1688. txbdp_start->lstatus = lstatus;
  1689. /* Update the current skb pointer to the next entry we will use
  1690. * (wrapping if necessary) */
  1691. tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
  1692. TX_RING_MOD_MASK(tx_queue->tx_ring_size);
  1693. tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
  1694. /* reduce TxBD free count */
  1695. tx_queue->num_txbdfree -= (nr_frags + 1);
  1696. dev->trans_start = jiffies;
  1697. /* If the next BD still needs to be cleaned up, then the bds
  1698. are full. We need to tell the kernel to stop sending us stuff. */
  1699. if (!tx_queue->num_txbdfree) {
  1700. netif_tx_stop_queue(txq);
  1701. dev->stats.tx_fifo_errors++;
  1702. }
  1703. /* Tell the DMA to go go go */
  1704. gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
  1705. /* Unlock priv */
  1706. spin_unlock_irqrestore(&tx_queue->txlock, flags);
  1707. return NETDEV_TX_OK;
  1708. }
  1709. /* Stops the kernel queue, and halts the controller */
  1710. static int gfar_close(struct net_device *dev)
  1711. {
  1712. struct gfar_private *priv = netdev_priv(dev);
  1713. disable_napi(priv);
  1714. skb_queue_purge(&priv->rx_recycle);
  1715. cancel_work_sync(&priv->reset_task);
  1716. stop_gfar(dev);
  1717. /* Disconnect from the PHY */
  1718. phy_disconnect(priv->phydev);
  1719. priv->phydev = NULL;
  1720. netif_tx_stop_all_queues(dev);
  1721. return 0;
  1722. }
  1723. /* Changes the mac address if the controller is not running. */
  1724. static int gfar_set_mac_address(struct net_device *dev)
  1725. {
  1726. gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
  1727. return 0;
  1728. }
  1729. /* Enables and disables VLAN insertion/extraction */
  1730. static void gfar_vlan_rx_register(struct net_device *dev,
  1731. struct vlan_group *grp)
  1732. {
  1733. struct gfar_private *priv = netdev_priv(dev);
  1734. struct gfar __iomem *regs = NULL;
  1735. unsigned long flags;
  1736. u32 tempval;
  1737. regs = priv->gfargrp[0].regs;
  1738. local_irq_save(flags);
  1739. lock_rx_qs(priv);
  1740. priv->vlgrp = grp;
  1741. if (grp) {
  1742. /* Enable VLAN tag insertion */
  1743. tempval = gfar_read(&regs->tctrl);
  1744. tempval |= TCTRL_VLINS;
  1745. gfar_write(&regs->tctrl, tempval);
  1746. /* Enable VLAN tag extraction */
  1747. tempval = gfar_read(&regs->rctrl);
  1748. tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
  1749. gfar_write(&regs->rctrl, tempval);
  1750. } else {
  1751. /* Disable VLAN tag insertion */
  1752. tempval = gfar_read(&regs->tctrl);
  1753. tempval &= ~TCTRL_VLINS;
  1754. gfar_write(&regs->tctrl, tempval);
  1755. /* Disable VLAN tag extraction */
  1756. tempval = gfar_read(&regs->rctrl);
  1757. tempval &= ~RCTRL_VLEX;
  1758. /* If parse is no longer required, then disable parser */
  1759. if (tempval & RCTRL_REQ_PARSER)
  1760. tempval |= RCTRL_PRSDEP_INIT;
  1761. else
  1762. tempval &= ~RCTRL_PRSDEP_INIT;
  1763. gfar_write(&regs->rctrl, tempval);
  1764. }
  1765. gfar_change_mtu(dev, dev->mtu);
  1766. unlock_rx_qs(priv);
  1767. local_irq_restore(flags);
  1768. }
  1769. static int gfar_change_mtu(struct net_device *dev, int new_mtu)
  1770. {
  1771. int tempsize, tempval;
  1772. struct gfar_private *priv = netdev_priv(dev);
  1773. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1774. int oldsize = priv->rx_buffer_size;
  1775. int frame_size = new_mtu + ETH_HLEN;
  1776. if (priv->vlgrp)
  1777. frame_size += VLAN_HLEN;
  1778. if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
  1779. if (netif_msg_drv(priv))
  1780. printk(KERN_ERR "%s: Invalid MTU setting\n",
  1781. dev->name);
  1782. return -EINVAL;
  1783. }
  1784. if (gfar_uses_fcb(priv))
  1785. frame_size += GMAC_FCB_LEN;
  1786. frame_size += priv->padding;
  1787. tempsize =
  1788. (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
  1789. INCREMENTAL_BUFFER_SIZE;
  1790. /* Only stop and start the controller if it isn't already
  1791. * stopped, and we changed something */
  1792. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  1793. stop_gfar(dev);
  1794. priv->rx_buffer_size = tempsize;
  1795. dev->mtu = new_mtu;
  1796. gfar_write(&regs->mrblr, priv->rx_buffer_size);
  1797. gfar_write(&regs->maxfrm, priv->rx_buffer_size);
  1798. /* If the mtu is larger than the max size for standard
  1799. * ethernet frames (ie, a jumbo frame), then set maccfg2
  1800. * to allow huge frames, and to check the length */
  1801. tempval = gfar_read(&regs->maccfg2);
  1802. if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
  1803. tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  1804. else
  1805. tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  1806. gfar_write(&regs->maccfg2, tempval);
  1807. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  1808. startup_gfar(dev);
  1809. return 0;
  1810. }
  1811. /* gfar_reset_task gets scheduled when a packet has not been
  1812. * transmitted after a set amount of time.
  1813. * For now, assume that clearing out all the structures, and
  1814. * starting over will fix the problem.
  1815. */
  1816. static void gfar_reset_task(struct work_struct *work)
  1817. {
  1818. struct gfar_private *priv = container_of(work, struct gfar_private,
  1819. reset_task);
  1820. struct net_device *dev = priv->ndev;
  1821. if (dev->flags & IFF_UP) {
  1822. netif_tx_stop_all_queues(dev);
  1823. stop_gfar(dev);
  1824. startup_gfar(dev);
  1825. netif_tx_start_all_queues(dev);
  1826. }
  1827. netif_tx_schedule_all(dev);
  1828. }
  1829. static void gfar_timeout(struct net_device *dev)
  1830. {
  1831. struct gfar_private *priv = netdev_priv(dev);
  1832. dev->stats.tx_errors++;
  1833. schedule_work(&priv->reset_task);
  1834. }
  1835. /* Interrupt Handler for Transmit complete */
  1836. static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
  1837. {
  1838. struct net_device *dev = tx_queue->dev;
  1839. struct gfar_private *priv = netdev_priv(dev);
  1840. struct gfar_priv_rx_q *rx_queue = NULL;
  1841. struct txbd8 *bdp;
  1842. struct txbd8 *lbdp = NULL;
  1843. struct txbd8 *base = tx_queue->tx_bd_base;
  1844. struct sk_buff *skb;
  1845. int skb_dirtytx;
  1846. int tx_ring_size = tx_queue->tx_ring_size;
  1847. int frags = 0;
  1848. int i;
  1849. int howmany = 0;
  1850. u32 lstatus;
  1851. rx_queue = priv->rx_queue[tx_queue->qindex];
  1852. bdp = tx_queue->dirty_tx;
  1853. skb_dirtytx = tx_queue->skb_dirtytx;
  1854. while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
  1855. unsigned long flags;
  1856. frags = skb_shinfo(skb)->nr_frags;
  1857. lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
  1858. lstatus = lbdp->lstatus;
  1859. /* Only clean completed frames */
  1860. if ((lstatus & BD_LFLAG(TXBD_READY)) &&
  1861. (lstatus & BD_LENGTH_MASK))
  1862. break;
  1863. dma_unmap_single(&priv->ofdev->dev,
  1864. bdp->bufPtr,
  1865. bdp->length,
  1866. DMA_TO_DEVICE);
  1867. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  1868. bdp = next_txbd(bdp, base, tx_ring_size);
  1869. for (i = 0; i < frags; i++) {
  1870. dma_unmap_page(&priv->ofdev->dev,
  1871. bdp->bufPtr,
  1872. bdp->length,
  1873. DMA_TO_DEVICE);
  1874. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  1875. bdp = next_txbd(bdp, base, tx_ring_size);
  1876. }
  1877. /*
  1878. * If there's room in the queue (limit it to rx_buffer_size)
  1879. * we add this skb back into the pool, if it's the right size
  1880. */
  1881. if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
  1882. skb_recycle_check(skb, priv->rx_buffer_size +
  1883. RXBUF_ALIGNMENT))
  1884. __skb_queue_head(&priv->rx_recycle, skb);
  1885. else
  1886. dev_kfree_skb_any(skb);
  1887. tx_queue->tx_skbuff[skb_dirtytx] = NULL;
  1888. skb_dirtytx = (skb_dirtytx + 1) &
  1889. TX_RING_MOD_MASK(tx_ring_size);
  1890. howmany++;
  1891. spin_lock_irqsave(&tx_queue->txlock, flags);
  1892. tx_queue->num_txbdfree += frags + 1;
  1893. spin_unlock_irqrestore(&tx_queue->txlock, flags);
  1894. }
  1895. /* If we freed a buffer, we can restart transmission, if necessary */
  1896. if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
  1897. netif_wake_subqueue(dev, tx_queue->qindex);
  1898. /* Update dirty indicators */
  1899. tx_queue->skb_dirtytx = skb_dirtytx;
  1900. tx_queue->dirty_tx = bdp;
  1901. return howmany;
  1902. }
  1903. static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
  1904. {
  1905. unsigned long flags;
  1906. spin_lock_irqsave(&gfargrp->grplock, flags);
  1907. if (napi_schedule_prep(&gfargrp->napi)) {
  1908. gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
  1909. __napi_schedule(&gfargrp->napi);
  1910. } else {
  1911. /*
  1912. * Clear IEVENT, so interrupts aren't called again
  1913. * because of the packets that have already arrived.
  1914. */
  1915. gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
  1916. }
  1917. spin_unlock_irqrestore(&gfargrp->grplock, flags);
  1918. }
  1919. /* Interrupt Handler for Transmit complete */
  1920. static irqreturn_t gfar_transmit(int irq, void *grp_id)
  1921. {
  1922. gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
  1923. return IRQ_HANDLED;
  1924. }
  1925. static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  1926. struct sk_buff *skb)
  1927. {
  1928. struct net_device *dev = rx_queue->dev;
  1929. struct gfar_private *priv = netdev_priv(dev);
  1930. dma_addr_t buf;
  1931. buf = dma_map_single(&priv->ofdev->dev, skb->data,
  1932. priv->rx_buffer_size, DMA_FROM_DEVICE);
  1933. gfar_init_rxbdp(rx_queue, bdp, buf);
  1934. }
  1935. struct sk_buff * gfar_new_skb(struct net_device *dev)
  1936. {
  1937. unsigned int alignamount;
  1938. struct gfar_private *priv = netdev_priv(dev);
  1939. struct sk_buff *skb = NULL;
  1940. skb = __skb_dequeue(&priv->rx_recycle);
  1941. if (!skb)
  1942. skb = netdev_alloc_skb(dev,
  1943. priv->rx_buffer_size + RXBUF_ALIGNMENT);
  1944. if (!skb)
  1945. return NULL;
  1946. alignamount = RXBUF_ALIGNMENT -
  1947. (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
  1948. /* We need the data buffer to be aligned properly. We will reserve
  1949. * as many bytes as needed to align the data properly
  1950. */
  1951. skb_reserve(skb, alignamount);
  1952. return skb;
  1953. }
  1954. static inline void count_errors(unsigned short status, struct net_device *dev)
  1955. {
  1956. struct gfar_private *priv = netdev_priv(dev);
  1957. struct net_device_stats *stats = &dev->stats;
  1958. struct gfar_extra_stats *estats = &priv->extra_stats;
  1959. /* If the packet was truncated, none of the other errors
  1960. * matter */
  1961. if (status & RXBD_TRUNCATED) {
  1962. stats->rx_length_errors++;
  1963. estats->rx_trunc++;
  1964. return;
  1965. }
  1966. /* Count the errors, if there were any */
  1967. if (status & (RXBD_LARGE | RXBD_SHORT)) {
  1968. stats->rx_length_errors++;
  1969. if (status & RXBD_LARGE)
  1970. estats->rx_large++;
  1971. else
  1972. estats->rx_short++;
  1973. }
  1974. if (status & RXBD_NONOCTET) {
  1975. stats->rx_frame_errors++;
  1976. estats->rx_nonoctet++;
  1977. }
  1978. if (status & RXBD_CRCERR) {
  1979. estats->rx_crcerr++;
  1980. stats->rx_crc_errors++;
  1981. }
  1982. if (status & RXBD_OVERRUN) {
  1983. estats->rx_overrun++;
  1984. stats->rx_crc_errors++;
  1985. }
  1986. }
  1987. irqreturn_t gfar_receive(int irq, void *grp_id)
  1988. {
  1989. gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
  1990. return IRQ_HANDLED;
  1991. }
  1992. static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
  1993. {
  1994. /* If valid headers were found, and valid sums
  1995. * were verified, then we tell the kernel that no
  1996. * checksumming is necessary. Otherwise, it is */
  1997. if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
  1998. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1999. else
  2000. skb->ip_summed = CHECKSUM_NONE;
  2001. }
  2002. /* gfar_process_frame() -- handle one incoming packet if skb
  2003. * isn't NULL. */
  2004. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  2005. int amount_pull)
  2006. {
  2007. struct gfar_private *priv = netdev_priv(dev);
  2008. struct rxfcb *fcb = NULL;
  2009. int ret;
  2010. /* fcb is at the beginning if exists */
  2011. fcb = (struct rxfcb *)skb->data;
  2012. /* Remove the FCB from the skb */
  2013. skb_set_queue_mapping(skb, fcb->rq);
  2014. /* Remove the padded bytes, if there are any */
  2015. if (amount_pull)
  2016. skb_pull(skb, amount_pull);
  2017. if (priv->rx_csum_enable)
  2018. gfar_rx_checksum(skb, fcb);
  2019. /* Tell the skb what kind of packet this is */
  2020. skb->protocol = eth_type_trans(skb, dev);
  2021. /* Send the packet up the stack */
  2022. if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
  2023. ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
  2024. else
  2025. ret = netif_receive_skb(skb);
  2026. if (NET_RX_DROP == ret)
  2027. priv->extra_stats.kernel_dropped++;
  2028. return 0;
  2029. }
  2030. /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
  2031. * until the budget/quota has been reached. Returns the number
  2032. * of frames handled
  2033. */
  2034. int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
  2035. {
  2036. struct net_device *dev = rx_queue->dev;
  2037. struct rxbd8 *bdp, *base;
  2038. struct sk_buff *skb;
  2039. int pkt_len;
  2040. int amount_pull;
  2041. int howmany = 0;
  2042. struct gfar_private *priv = netdev_priv(dev);
  2043. /* Get the first full descriptor */
  2044. bdp = rx_queue->cur_rx;
  2045. base = rx_queue->rx_bd_base;
  2046. amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
  2047. priv->padding;
  2048. while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
  2049. struct sk_buff *newskb;
  2050. rmb();
  2051. /* Add another skb for the future */
  2052. newskb = gfar_new_skb(dev);
  2053. skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
  2054. dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
  2055. priv->rx_buffer_size, DMA_FROM_DEVICE);
  2056. /* We drop the frame if we failed to allocate a new buffer */
  2057. if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
  2058. bdp->status & RXBD_ERR)) {
  2059. count_errors(bdp->status, dev);
  2060. if (unlikely(!newskb))
  2061. newskb = skb;
  2062. else if (skb) {
  2063. /*
  2064. * We need to reset ->data to what it
  2065. * was before gfar_new_skb() re-aligned
  2066. * it to an RXBUF_ALIGNMENT boundary
  2067. * before we put the skb back on the
  2068. * recycle list.
  2069. */
  2070. skb->data = skb->head + NET_SKB_PAD;
  2071. __skb_queue_head(&priv->rx_recycle, skb);
  2072. }
  2073. } else {
  2074. /* Increment the number of packets */
  2075. rx_queue->stats.rx_packets++;
  2076. howmany++;
  2077. if (likely(skb)) {
  2078. pkt_len = bdp->length - ETH_FCS_LEN;
  2079. /* Remove the FCS from the packet length */
  2080. skb_put(skb, pkt_len);
  2081. rx_queue->stats.rx_bytes += pkt_len;
  2082. gfar_process_frame(dev, skb, amount_pull);
  2083. } else {
  2084. if (netif_msg_rx_err(priv))
  2085. printk(KERN_WARNING
  2086. "%s: Missing skb!\n", dev->name);
  2087. rx_queue->stats.rx_dropped++;
  2088. priv->extra_stats.rx_skbmissing++;
  2089. }
  2090. }
  2091. rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
  2092. /* Setup the new bdp */
  2093. gfar_new_rxbdp(rx_queue, bdp, newskb);
  2094. /* Update to the next pointer */
  2095. bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
  2096. /* update to point at the next skb */
  2097. rx_queue->skb_currx =
  2098. (rx_queue->skb_currx + 1) &
  2099. RX_RING_MOD_MASK(rx_queue->rx_ring_size);
  2100. }
  2101. /* Update the current rxbd pointer to be the next one */
  2102. rx_queue->cur_rx = bdp;
  2103. return howmany;
  2104. }
  2105. static int gfar_poll(struct napi_struct *napi, int budget)
  2106. {
  2107. struct gfar_priv_grp *gfargrp = container_of(napi,
  2108. struct gfar_priv_grp, napi);
  2109. struct gfar_private *priv = gfargrp->priv;
  2110. struct gfar __iomem *regs = gfargrp->regs;
  2111. struct gfar_priv_tx_q *tx_queue = NULL;
  2112. struct gfar_priv_rx_q *rx_queue = NULL;
  2113. int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
  2114. int tx_cleaned = 0, i, left_over_budget = budget;
  2115. unsigned long serviced_queues = 0;
  2116. int num_queues = 0;
  2117. num_queues = gfargrp->num_rx_queues;
  2118. budget_per_queue = budget/num_queues;
  2119. /* Clear IEVENT, so interrupts aren't called again
  2120. * because of the packets that have already arrived */
  2121. gfar_write(&regs->ievent, IEVENT_RTX_MASK);
  2122. while (num_queues && left_over_budget) {
  2123. budget_per_queue = left_over_budget/num_queues;
  2124. left_over_budget = 0;
  2125. for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
  2126. if (test_bit(i, &serviced_queues))
  2127. continue;
  2128. rx_queue = priv->rx_queue[i];
  2129. tx_queue = priv->tx_queue[rx_queue->qindex];
  2130. tx_cleaned += gfar_clean_tx_ring(tx_queue);
  2131. rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
  2132. budget_per_queue);
  2133. rx_cleaned += rx_cleaned_per_queue;
  2134. if(rx_cleaned_per_queue < budget_per_queue) {
  2135. left_over_budget = left_over_budget +
  2136. (budget_per_queue - rx_cleaned_per_queue);
  2137. set_bit(i, &serviced_queues);
  2138. num_queues--;
  2139. }
  2140. }
  2141. }
  2142. if (tx_cleaned)
  2143. return budget;
  2144. if (rx_cleaned < budget) {
  2145. napi_complete(napi);
  2146. /* Clear the halt bit in RSTAT */
  2147. gfar_write(&regs->rstat, gfargrp->rstat);
  2148. gfar_write(&regs->imask, IMASK_DEFAULT);
  2149. /* If we are coalescing interrupts, update the timer */
  2150. /* Otherwise, clear it */
  2151. gfar_configure_coalescing(priv,
  2152. gfargrp->rx_bit_map, gfargrp->tx_bit_map);
  2153. }
  2154. return rx_cleaned;
  2155. }
  2156. #ifdef CONFIG_NET_POLL_CONTROLLER
  2157. /*
  2158. * Polling 'interrupt' - used by things like netconsole to send skbs
  2159. * without having to re-enable interrupts. It's not called while
  2160. * the interrupt routine is executing.
  2161. */
  2162. static void gfar_netpoll(struct net_device *dev)
  2163. {
  2164. struct gfar_private *priv = netdev_priv(dev);
  2165. int i = 0;
  2166. /* If the device has multiple interrupts, run tx/rx */
  2167. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  2168. for (i = 0; i < priv->num_grps; i++) {
  2169. disable_irq(priv->gfargrp[i].interruptTransmit);
  2170. disable_irq(priv->gfargrp[i].interruptReceive);
  2171. disable_irq(priv->gfargrp[i].interruptError);
  2172. gfar_interrupt(priv->gfargrp[i].interruptTransmit,
  2173. &priv->gfargrp[i]);
  2174. enable_irq(priv->gfargrp[i].interruptError);
  2175. enable_irq(priv->gfargrp[i].interruptReceive);
  2176. enable_irq(priv->gfargrp[i].interruptTransmit);
  2177. }
  2178. } else {
  2179. for (i = 0; i < priv->num_grps; i++) {
  2180. disable_irq(priv->gfargrp[i].interruptTransmit);
  2181. gfar_interrupt(priv->gfargrp[i].interruptTransmit,
  2182. &priv->gfargrp[i]);
  2183. enable_irq(priv->gfargrp[i].interruptTransmit);
  2184. }
  2185. }
  2186. }
  2187. #endif
  2188. /* The interrupt handler for devices with one interrupt */
  2189. static irqreturn_t gfar_interrupt(int irq, void *grp_id)
  2190. {
  2191. struct gfar_priv_grp *gfargrp = grp_id;
  2192. /* Save ievent for future reference */
  2193. u32 events = gfar_read(&gfargrp->regs->ievent);
  2194. /* Check for reception */
  2195. if (events & IEVENT_RX_MASK)
  2196. gfar_receive(irq, grp_id);
  2197. /* Check for transmit completion */
  2198. if (events & IEVENT_TX_MASK)
  2199. gfar_transmit(irq, grp_id);
  2200. /* Check for errors */
  2201. if (events & IEVENT_ERR_MASK)
  2202. gfar_error(irq, grp_id);
  2203. return IRQ_HANDLED;
  2204. }
  2205. /* Called every time the controller might need to be made
  2206. * aware of new link state. The PHY code conveys this
  2207. * information through variables in the phydev structure, and this
  2208. * function converts those variables into the appropriate
  2209. * register values, and can bring down the device if needed.
  2210. */
  2211. static void adjust_link(struct net_device *dev)
  2212. {
  2213. struct gfar_private *priv = netdev_priv(dev);
  2214. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2215. unsigned long flags;
  2216. struct phy_device *phydev = priv->phydev;
  2217. int new_state = 0;
  2218. local_irq_save(flags);
  2219. lock_tx_qs(priv);
  2220. if (phydev->link) {
  2221. u32 tempval = gfar_read(&regs->maccfg2);
  2222. u32 ecntrl = gfar_read(&regs->ecntrl);
  2223. /* Now we make sure that we can be in full duplex mode.
  2224. * If not, we operate in half-duplex mode. */
  2225. if (phydev->duplex != priv->oldduplex) {
  2226. new_state = 1;
  2227. if (!(phydev->duplex))
  2228. tempval &= ~(MACCFG2_FULL_DUPLEX);
  2229. else
  2230. tempval |= MACCFG2_FULL_DUPLEX;
  2231. priv->oldduplex = phydev->duplex;
  2232. }
  2233. if (phydev->speed != priv->oldspeed) {
  2234. new_state = 1;
  2235. switch (phydev->speed) {
  2236. case 1000:
  2237. tempval =
  2238. ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
  2239. ecntrl &= ~(ECNTRL_R100);
  2240. break;
  2241. case 100:
  2242. case 10:
  2243. tempval =
  2244. ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
  2245. /* Reduced mode distinguishes
  2246. * between 10 and 100 */
  2247. if (phydev->speed == SPEED_100)
  2248. ecntrl |= ECNTRL_R100;
  2249. else
  2250. ecntrl &= ~(ECNTRL_R100);
  2251. break;
  2252. default:
  2253. if (netif_msg_link(priv))
  2254. printk(KERN_WARNING
  2255. "%s: Ack! Speed (%d) is not 10/100/1000!\n",
  2256. dev->name, phydev->speed);
  2257. break;
  2258. }
  2259. priv->oldspeed = phydev->speed;
  2260. }
  2261. gfar_write(&regs->maccfg2, tempval);
  2262. gfar_write(&regs->ecntrl, ecntrl);
  2263. if (!priv->oldlink) {
  2264. new_state = 1;
  2265. priv->oldlink = 1;
  2266. }
  2267. } else if (priv->oldlink) {
  2268. new_state = 1;
  2269. priv->oldlink = 0;
  2270. priv->oldspeed = 0;
  2271. priv->oldduplex = -1;
  2272. }
  2273. if (new_state && netif_msg_link(priv))
  2274. phy_print_status(phydev);
  2275. unlock_tx_qs(priv);
  2276. local_irq_restore(flags);
  2277. }
  2278. /* Update the hash table based on the current list of multicast
  2279. * addresses we subscribe to. Also, change the promiscuity of
  2280. * the device based on the flags (this function is called
  2281. * whenever dev->flags is changed */
  2282. static void gfar_set_multi(struct net_device *dev)
  2283. {
  2284. struct dev_mc_list *mc_ptr;
  2285. struct gfar_private *priv = netdev_priv(dev);
  2286. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2287. u32 tempval;
  2288. if (dev->flags & IFF_PROMISC) {
  2289. /* Set RCTRL to PROM */
  2290. tempval = gfar_read(&regs->rctrl);
  2291. tempval |= RCTRL_PROM;
  2292. gfar_write(&regs->rctrl, tempval);
  2293. } else {
  2294. /* Set RCTRL to not PROM */
  2295. tempval = gfar_read(&regs->rctrl);
  2296. tempval &= ~(RCTRL_PROM);
  2297. gfar_write(&regs->rctrl, tempval);
  2298. }
  2299. if (dev->flags & IFF_ALLMULTI) {
  2300. /* Set the hash to rx all multicast frames */
  2301. gfar_write(&regs->igaddr0, 0xffffffff);
  2302. gfar_write(&regs->igaddr1, 0xffffffff);
  2303. gfar_write(&regs->igaddr2, 0xffffffff);
  2304. gfar_write(&regs->igaddr3, 0xffffffff);
  2305. gfar_write(&regs->igaddr4, 0xffffffff);
  2306. gfar_write(&regs->igaddr5, 0xffffffff);
  2307. gfar_write(&regs->igaddr6, 0xffffffff);
  2308. gfar_write(&regs->igaddr7, 0xffffffff);
  2309. gfar_write(&regs->gaddr0, 0xffffffff);
  2310. gfar_write(&regs->gaddr1, 0xffffffff);
  2311. gfar_write(&regs->gaddr2, 0xffffffff);
  2312. gfar_write(&regs->gaddr3, 0xffffffff);
  2313. gfar_write(&regs->gaddr4, 0xffffffff);
  2314. gfar_write(&regs->gaddr5, 0xffffffff);
  2315. gfar_write(&regs->gaddr6, 0xffffffff);
  2316. gfar_write(&regs->gaddr7, 0xffffffff);
  2317. } else {
  2318. int em_num;
  2319. int idx;
  2320. /* zero out the hash */
  2321. gfar_write(&regs->igaddr0, 0x0);
  2322. gfar_write(&regs->igaddr1, 0x0);
  2323. gfar_write(&regs->igaddr2, 0x0);
  2324. gfar_write(&regs->igaddr3, 0x0);
  2325. gfar_write(&regs->igaddr4, 0x0);
  2326. gfar_write(&regs->igaddr5, 0x0);
  2327. gfar_write(&regs->igaddr6, 0x0);
  2328. gfar_write(&regs->igaddr7, 0x0);
  2329. gfar_write(&regs->gaddr0, 0x0);
  2330. gfar_write(&regs->gaddr1, 0x0);
  2331. gfar_write(&regs->gaddr2, 0x0);
  2332. gfar_write(&regs->gaddr3, 0x0);
  2333. gfar_write(&regs->gaddr4, 0x0);
  2334. gfar_write(&regs->gaddr5, 0x0);
  2335. gfar_write(&regs->gaddr6, 0x0);
  2336. gfar_write(&regs->gaddr7, 0x0);
  2337. /* If we have extended hash tables, we need to
  2338. * clear the exact match registers to prepare for
  2339. * setting them */
  2340. if (priv->extended_hash) {
  2341. em_num = GFAR_EM_NUM + 1;
  2342. gfar_clear_exact_match(dev);
  2343. idx = 1;
  2344. } else {
  2345. idx = 0;
  2346. em_num = 0;
  2347. }
  2348. if (dev->mc_count == 0)
  2349. return;
  2350. /* Parse the list, and set the appropriate bits */
  2351. for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
  2352. if (idx < em_num) {
  2353. gfar_set_mac_for_addr(dev, idx,
  2354. mc_ptr->dmi_addr);
  2355. idx++;
  2356. } else
  2357. gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
  2358. }
  2359. }
  2360. return;
  2361. }
  2362. /* Clears each of the exact match registers to zero, so they
  2363. * don't interfere with normal reception */
  2364. static void gfar_clear_exact_match(struct net_device *dev)
  2365. {
  2366. int idx;
  2367. u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
  2368. for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
  2369. gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
  2370. }
  2371. /* Set the appropriate hash bit for the given addr */
  2372. /* The algorithm works like so:
  2373. * 1) Take the Destination Address (ie the multicast address), and
  2374. * do a CRC on it (little endian), and reverse the bits of the
  2375. * result.
  2376. * 2) Use the 8 most significant bits as a hash into a 256-entry
  2377. * table. The table is controlled through 8 32-bit registers:
  2378. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
  2379. * gaddr7. This means that the 3 most significant bits in the
  2380. * hash index which gaddr register to use, and the 5 other bits
  2381. * indicate which bit (assuming an IBM numbering scheme, which
  2382. * for PowerPC (tm) is usually the case) in the register holds
  2383. * the entry. */
  2384. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
  2385. {
  2386. u32 tempval;
  2387. struct gfar_private *priv = netdev_priv(dev);
  2388. u32 result = ether_crc(MAC_ADDR_LEN, addr);
  2389. int width = priv->hash_width;
  2390. u8 whichbit = (result >> (32 - width)) & 0x1f;
  2391. u8 whichreg = result >> (32 - width + 5);
  2392. u32 value = (1 << (31-whichbit));
  2393. tempval = gfar_read(priv->hash_regs[whichreg]);
  2394. tempval |= value;
  2395. gfar_write(priv->hash_regs[whichreg], tempval);
  2396. return;
  2397. }
  2398. /* There are multiple MAC Address register pairs on some controllers
  2399. * This function sets the numth pair to a given address
  2400. */
  2401. static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
  2402. {
  2403. struct gfar_private *priv = netdev_priv(dev);
  2404. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2405. int idx;
  2406. char tmpbuf[MAC_ADDR_LEN];
  2407. u32 tempval;
  2408. u32 __iomem *macptr = &regs->macstnaddr1;
  2409. macptr += num*2;
  2410. /* Now copy it into the mac registers backwards, cuz */
  2411. /* little endian is silly */
  2412. for (idx = 0; idx < MAC_ADDR_LEN; idx++)
  2413. tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
  2414. gfar_write(macptr, *((u32 *) (tmpbuf)));
  2415. tempval = *((u32 *) (tmpbuf + 4));
  2416. gfar_write(macptr+1, tempval);
  2417. }
  2418. /* GFAR error interrupt handler */
  2419. static irqreturn_t gfar_error(int irq, void *grp_id)
  2420. {
  2421. struct gfar_priv_grp *gfargrp = grp_id;
  2422. struct gfar __iomem *regs = gfargrp->regs;
  2423. struct gfar_private *priv= gfargrp->priv;
  2424. struct net_device *dev = priv->ndev;
  2425. /* Save ievent for future reference */
  2426. u32 events = gfar_read(&regs->ievent);
  2427. /* Clear IEVENT */
  2428. gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
  2429. /* Magic Packet is not an error. */
  2430. if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
  2431. (events & IEVENT_MAG))
  2432. events &= ~IEVENT_MAG;
  2433. /* Hmm... */
  2434. if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
  2435. printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
  2436. dev->name, events, gfar_read(&regs->imask));
  2437. /* Update the error counters */
  2438. if (events & IEVENT_TXE) {
  2439. dev->stats.tx_errors++;
  2440. if (events & IEVENT_LC)
  2441. dev->stats.tx_window_errors++;
  2442. if (events & IEVENT_CRL)
  2443. dev->stats.tx_aborted_errors++;
  2444. if (events & IEVENT_XFUN) {
  2445. unsigned long flags;
  2446. if (netif_msg_tx_err(priv))
  2447. printk(KERN_DEBUG "%s: TX FIFO underrun, "
  2448. "packet dropped.\n", dev->name);
  2449. dev->stats.tx_dropped++;
  2450. priv->extra_stats.tx_underrun++;
  2451. local_irq_save(flags);
  2452. lock_tx_qs(priv);
  2453. /* Reactivate the Tx Queues */
  2454. gfar_write(&regs->tstat, gfargrp->tstat);
  2455. unlock_tx_qs(priv);
  2456. local_irq_restore(flags);
  2457. }
  2458. if (netif_msg_tx_err(priv))
  2459. printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
  2460. }
  2461. if (events & IEVENT_BSY) {
  2462. dev->stats.rx_errors++;
  2463. priv->extra_stats.rx_bsy++;
  2464. gfar_receive(irq, grp_id);
  2465. if (netif_msg_rx_err(priv))
  2466. printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
  2467. dev->name, gfar_read(&regs->rstat));
  2468. }
  2469. if (events & IEVENT_BABR) {
  2470. dev->stats.rx_errors++;
  2471. priv->extra_stats.rx_babr++;
  2472. if (netif_msg_rx_err(priv))
  2473. printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
  2474. }
  2475. if (events & IEVENT_EBERR) {
  2476. priv->extra_stats.eberr++;
  2477. if (netif_msg_rx_err(priv))
  2478. printk(KERN_DEBUG "%s: bus error\n", dev->name);
  2479. }
  2480. if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
  2481. printk(KERN_DEBUG "%s: control frame\n", dev->name);
  2482. if (events & IEVENT_BABT) {
  2483. priv->extra_stats.tx_babt++;
  2484. if (netif_msg_tx_err(priv))
  2485. printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
  2486. }
  2487. return IRQ_HANDLED;
  2488. }
  2489. static struct of_device_id gfar_match[] =
  2490. {
  2491. {
  2492. .type = "network",
  2493. .compatible = "gianfar",
  2494. },
  2495. {
  2496. .compatible = "fsl,etsec2",
  2497. },
  2498. {},
  2499. };
  2500. MODULE_DEVICE_TABLE(of, gfar_match);
  2501. /* Structure for a device driver */
  2502. static struct of_platform_driver gfar_driver = {
  2503. .name = "fsl-gianfar",
  2504. .match_table = gfar_match,
  2505. .probe = gfar_probe,
  2506. .remove = gfar_remove,
  2507. .suspend = gfar_legacy_suspend,
  2508. .resume = gfar_legacy_resume,
  2509. .driver.pm = GFAR_PM_OPS,
  2510. };
  2511. static int __init gfar_init(void)
  2512. {
  2513. return of_register_platform_driver(&gfar_driver);
  2514. }
  2515. static void __exit gfar_exit(void)
  2516. {
  2517. of_unregister_platform_driver(&gfar_driver);
  2518. }
  2519. module_init(gfar_init);
  2520. module_exit(gfar_exit);