smsc75xx.c 52 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/bitrev.h>
  29. #include <linux/crc16.h>
  30. #include <linux/crc32.h>
  31. #include <linux/usb/usbnet.h>
  32. #include <linux/slab.h>
  33. #include "smsc75xx.h"
  34. #define SMSC_CHIPNAME "smsc75xx"
  35. #define SMSC_DRIVER_VERSION "1.0.0"
  36. #define HS_USB_PKT_SIZE (512)
  37. #define FS_USB_PKT_SIZE (64)
  38. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  39. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  40. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  41. #define MAX_SINGLE_PACKET_SIZE (9000)
  42. #define LAN75XX_EEPROM_MAGIC (0x7500)
  43. #define EEPROM_MAC_OFFSET (0x01)
  44. #define DEFAULT_TX_CSUM_ENABLE (true)
  45. #define DEFAULT_RX_CSUM_ENABLE (true)
  46. #define DEFAULT_TSO_ENABLE (true)
  47. #define SMSC75XX_INTERNAL_PHY_ID (1)
  48. #define SMSC75XX_TX_OVERHEAD (8)
  49. #define MAX_RX_FIFO_SIZE (20 * 1024)
  50. #define MAX_TX_FIFO_SIZE (12 * 1024)
  51. #define USB_VENDOR_ID_SMSC (0x0424)
  52. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  53. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  54. #define RXW_PADDING 2
  55. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  56. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  57. #define SUSPEND_SUSPEND0 (0x01)
  58. #define SUSPEND_SUSPEND1 (0x02)
  59. #define SUSPEND_SUSPEND2 (0x04)
  60. #define SUSPEND_SUSPEND3 (0x08)
  61. #define SUSPEND_REMOTEWAKE (0x10)
  62. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  63. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  64. #define check_warn(ret, fmt, args...) \
  65. ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); })
  66. #define check_warn_return(ret, fmt, args...) \
  67. ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } })
  68. #define check_warn_goto_done(ret, fmt, args...) \
  69. ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } })
  70. struct smsc75xx_priv {
  71. struct usbnet *dev;
  72. u32 rfe_ctl;
  73. u32 wolopts;
  74. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  75. struct mutex dataport_mutex;
  76. spinlock_t rfe_ctl_lock;
  77. struct work_struct set_multicast;
  78. u8 suspend_flags;
  79. };
  80. struct usb_context {
  81. struct usb_ctrlrequest req;
  82. struct usbnet *dev;
  83. };
  84. static bool turbo_mode = true;
  85. module_param(turbo_mode, bool, 0644);
  86. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  87. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  88. u32 *data, int in_pm)
  89. {
  90. u32 buf;
  91. int ret;
  92. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  93. BUG_ON(!dev);
  94. if (!in_pm)
  95. fn = usbnet_read_cmd;
  96. else
  97. fn = usbnet_read_cmd_nopm;
  98. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  99. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  100. 0, index, &buf, 4);
  101. if (unlikely(ret < 0))
  102. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  103. index, ret);
  104. le32_to_cpus(&buf);
  105. *data = buf;
  106. return ret;
  107. }
  108. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  109. u32 data, int in_pm)
  110. {
  111. u32 buf;
  112. int ret;
  113. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  114. BUG_ON(!dev);
  115. if (!in_pm)
  116. fn = usbnet_write_cmd;
  117. else
  118. fn = usbnet_write_cmd_nopm;
  119. buf = data;
  120. cpu_to_le32s(&buf);
  121. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  122. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  123. 0, index, &buf, 4);
  124. if (unlikely(ret < 0))
  125. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  126. index, ret);
  127. return ret;
  128. }
  129. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  130. u32 *data)
  131. {
  132. return __smsc75xx_read_reg(dev, index, data, 1);
  133. }
  134. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  135. u32 data)
  136. {
  137. return __smsc75xx_write_reg(dev, index, data, 1);
  138. }
  139. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  140. u32 *data)
  141. {
  142. return __smsc75xx_read_reg(dev, index, data, 0);
  143. }
  144. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  145. u32 data)
  146. {
  147. return __smsc75xx_write_reg(dev, index, data, 0);
  148. }
  149. static int smsc75xx_set_feature(struct usbnet *dev, u32 feature)
  150. {
  151. if (WARN_ON_ONCE(!dev))
  152. return -EINVAL;
  153. return usbnet_write_cmd_nopm(dev, USB_REQ_SET_FEATURE,
  154. USB_DIR_OUT | USB_RECIP_DEVICE,
  155. feature, 0, NULL, 0);
  156. }
  157. static int smsc75xx_clear_feature(struct usbnet *dev, u32 feature)
  158. {
  159. if (WARN_ON_ONCE(!dev))
  160. return -EINVAL;
  161. return usbnet_write_cmd_nopm(dev, USB_REQ_CLEAR_FEATURE,
  162. USB_DIR_OUT | USB_RECIP_DEVICE,
  163. feature, 0, NULL, 0);
  164. }
  165. /* Loop until the read is completed with timeout
  166. * called with phy_mutex held */
  167. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  168. int in_pm)
  169. {
  170. unsigned long start_time = jiffies;
  171. u32 val;
  172. int ret;
  173. do {
  174. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  175. check_warn_return(ret, "Error reading MII_ACCESS\n");
  176. if (!(val & MII_ACCESS_BUSY))
  177. return 0;
  178. } while (!time_after(jiffies, start_time + HZ));
  179. return -EIO;
  180. }
  181. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  182. int in_pm)
  183. {
  184. struct usbnet *dev = netdev_priv(netdev);
  185. u32 val, addr;
  186. int ret;
  187. mutex_lock(&dev->phy_mutex);
  188. /* confirm MII not busy */
  189. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  190. check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_read\n");
  191. /* set the address, index & direction (read from PHY) */
  192. phy_id &= dev->mii.phy_id_mask;
  193. idx &= dev->mii.reg_num_mask;
  194. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  195. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  196. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  197. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  198. check_warn_goto_done(ret, "Error writing MII_ACCESS\n");
  199. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  200. check_warn_goto_done(ret, "Timed out reading MII reg %02X\n", idx);
  201. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  202. check_warn_goto_done(ret, "Error reading MII_DATA\n");
  203. ret = (u16)(val & 0xFFFF);
  204. done:
  205. mutex_unlock(&dev->phy_mutex);
  206. return ret;
  207. }
  208. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  209. int idx, int regval, int in_pm)
  210. {
  211. struct usbnet *dev = netdev_priv(netdev);
  212. u32 val, addr;
  213. int ret;
  214. mutex_lock(&dev->phy_mutex);
  215. /* confirm MII not busy */
  216. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  217. check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_write\n");
  218. val = regval;
  219. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  220. check_warn_goto_done(ret, "Error writing MII_DATA\n");
  221. /* set the address, index & direction (write to PHY) */
  222. phy_id &= dev->mii.phy_id_mask;
  223. idx &= dev->mii.reg_num_mask;
  224. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  225. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  226. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  227. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  228. check_warn_goto_done(ret, "Error writing MII_ACCESS\n");
  229. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  230. check_warn_goto_done(ret, "Timed out writing MII reg %02X\n", idx);
  231. done:
  232. mutex_unlock(&dev->phy_mutex);
  233. }
  234. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  235. int idx)
  236. {
  237. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  238. }
  239. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  240. int idx, int regval)
  241. {
  242. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  243. }
  244. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  245. {
  246. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  247. }
  248. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  249. int regval)
  250. {
  251. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  252. }
  253. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  254. {
  255. unsigned long start_time = jiffies;
  256. u32 val;
  257. int ret;
  258. do {
  259. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  260. check_warn_return(ret, "Error reading E2P_CMD\n");
  261. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  262. break;
  263. udelay(40);
  264. } while (!time_after(jiffies, start_time + HZ));
  265. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  266. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  267. return -EIO;
  268. }
  269. return 0;
  270. }
  271. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  272. {
  273. unsigned long start_time = jiffies;
  274. u32 val;
  275. int ret;
  276. do {
  277. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  278. check_warn_return(ret, "Error reading E2P_CMD\n");
  279. if (!(val & E2P_CMD_BUSY))
  280. return 0;
  281. udelay(40);
  282. } while (!time_after(jiffies, start_time + HZ));
  283. netdev_warn(dev->net, "EEPROM is busy\n");
  284. return -EIO;
  285. }
  286. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  287. u8 *data)
  288. {
  289. u32 val;
  290. int i, ret;
  291. BUG_ON(!dev);
  292. BUG_ON(!data);
  293. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  294. if (ret)
  295. return ret;
  296. for (i = 0; i < length; i++) {
  297. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  298. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  299. check_warn_return(ret, "Error writing E2P_CMD\n");
  300. ret = smsc75xx_wait_eeprom(dev);
  301. if (ret < 0)
  302. return ret;
  303. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  304. check_warn_return(ret, "Error reading E2P_DATA\n");
  305. data[i] = val & 0xFF;
  306. offset++;
  307. }
  308. return 0;
  309. }
  310. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  311. u8 *data)
  312. {
  313. u32 val;
  314. int i, ret;
  315. BUG_ON(!dev);
  316. BUG_ON(!data);
  317. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  318. if (ret)
  319. return ret;
  320. /* Issue write/erase enable command */
  321. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  322. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  323. check_warn_return(ret, "Error writing E2P_CMD\n");
  324. ret = smsc75xx_wait_eeprom(dev);
  325. if (ret < 0)
  326. return ret;
  327. for (i = 0; i < length; i++) {
  328. /* Fill data register */
  329. val = data[i];
  330. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  331. check_warn_return(ret, "Error writing E2P_DATA\n");
  332. /* Send "write" command */
  333. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  334. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  335. check_warn_return(ret, "Error writing E2P_CMD\n");
  336. ret = smsc75xx_wait_eeprom(dev);
  337. if (ret < 0)
  338. return ret;
  339. offset++;
  340. }
  341. return 0;
  342. }
  343. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  344. {
  345. int i, ret;
  346. for (i = 0; i < 100; i++) {
  347. u32 dp_sel;
  348. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  349. check_warn_return(ret, "Error reading DP_SEL\n");
  350. if (dp_sel & DP_SEL_DPRDY)
  351. return 0;
  352. udelay(40);
  353. }
  354. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  355. return -EIO;
  356. }
  357. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  358. u32 length, u32 *buf)
  359. {
  360. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  361. u32 dp_sel;
  362. int i, ret;
  363. mutex_lock(&pdata->dataport_mutex);
  364. ret = smsc75xx_dataport_wait_not_busy(dev);
  365. check_warn_goto_done(ret, "smsc75xx_dataport_write busy on entry\n");
  366. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  367. check_warn_goto_done(ret, "Error reading DP_SEL\n");
  368. dp_sel &= ~DP_SEL_RSEL;
  369. dp_sel |= ram_select;
  370. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  371. check_warn_goto_done(ret, "Error writing DP_SEL\n");
  372. for (i = 0; i < length; i++) {
  373. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  374. check_warn_goto_done(ret, "Error writing DP_ADDR\n");
  375. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  376. check_warn_goto_done(ret, "Error writing DP_DATA\n");
  377. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  378. check_warn_goto_done(ret, "Error writing DP_CMD\n");
  379. ret = smsc75xx_dataport_wait_not_busy(dev);
  380. check_warn_goto_done(ret, "smsc75xx_dataport_write timeout\n");
  381. }
  382. done:
  383. mutex_unlock(&pdata->dataport_mutex);
  384. return ret;
  385. }
  386. /* returns hash bit number for given MAC address */
  387. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  388. {
  389. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  390. }
  391. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  392. {
  393. struct smsc75xx_priv *pdata =
  394. container_of(param, struct smsc75xx_priv, set_multicast);
  395. struct usbnet *dev = pdata->dev;
  396. int ret;
  397. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  398. pdata->rfe_ctl);
  399. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  400. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  401. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  402. check_warn(ret, "Error writing RFE_CRL\n");
  403. }
  404. static void smsc75xx_set_multicast(struct net_device *netdev)
  405. {
  406. struct usbnet *dev = netdev_priv(netdev);
  407. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  408. unsigned long flags;
  409. int i;
  410. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  411. pdata->rfe_ctl &=
  412. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  413. pdata->rfe_ctl |= RFE_CTL_AB;
  414. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  415. pdata->multicast_hash_table[i] = 0;
  416. if (dev->net->flags & IFF_PROMISC) {
  417. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  418. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  419. } else if (dev->net->flags & IFF_ALLMULTI) {
  420. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  421. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  422. } else if (!netdev_mc_empty(dev->net)) {
  423. struct netdev_hw_addr *ha;
  424. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  425. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  426. netdev_for_each_mc_addr(ha, netdev) {
  427. u32 bitnum = smsc75xx_hash(ha->addr);
  428. pdata->multicast_hash_table[bitnum / 32] |=
  429. (1 << (bitnum % 32));
  430. }
  431. } else {
  432. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  433. pdata->rfe_ctl |= RFE_CTL_DPF;
  434. }
  435. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  436. /* defer register writes to a sleepable context */
  437. schedule_work(&pdata->set_multicast);
  438. }
  439. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  440. u16 lcladv, u16 rmtadv)
  441. {
  442. u32 flow = 0, fct_flow = 0;
  443. int ret;
  444. if (duplex == DUPLEX_FULL) {
  445. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  446. if (cap & FLOW_CTRL_TX) {
  447. flow = (FLOW_TX_FCEN | 0xFFFF);
  448. /* set fct_flow thresholds to 20% and 80% */
  449. fct_flow = (8 << 8) | 32;
  450. }
  451. if (cap & FLOW_CTRL_RX)
  452. flow |= FLOW_RX_FCEN;
  453. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  454. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  455. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  456. } else {
  457. netif_dbg(dev, link, dev->net, "half duplex\n");
  458. }
  459. ret = smsc75xx_write_reg(dev, FLOW, flow);
  460. check_warn_return(ret, "Error writing FLOW\n");
  461. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  462. check_warn_return(ret, "Error writing FCT_FLOW\n");
  463. return 0;
  464. }
  465. static int smsc75xx_link_reset(struct usbnet *dev)
  466. {
  467. struct mii_if_info *mii = &dev->mii;
  468. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  469. u16 lcladv, rmtadv;
  470. int ret;
  471. /* write to clear phy interrupt status */
  472. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  473. PHY_INT_SRC_CLEAR_ALL);
  474. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  475. check_warn_return(ret, "Error writing INT_STS\n");
  476. mii_check_media(mii, 1, 1);
  477. mii_ethtool_gset(&dev->mii, &ecmd);
  478. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  479. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  480. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  481. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  482. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  483. }
  484. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  485. {
  486. u32 intdata;
  487. if (urb->actual_length != 4) {
  488. netdev_warn(dev->net, "unexpected urb length %d\n",
  489. urb->actual_length);
  490. return;
  491. }
  492. memcpy(&intdata, urb->transfer_buffer, 4);
  493. le32_to_cpus(&intdata);
  494. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  495. if (intdata & INT_ENP_PHY_INT)
  496. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  497. else
  498. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  499. intdata);
  500. }
  501. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  502. {
  503. return MAX_EEPROM_SIZE;
  504. }
  505. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  506. struct ethtool_eeprom *ee, u8 *data)
  507. {
  508. struct usbnet *dev = netdev_priv(netdev);
  509. ee->magic = LAN75XX_EEPROM_MAGIC;
  510. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  511. }
  512. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  513. struct ethtool_eeprom *ee, u8 *data)
  514. {
  515. struct usbnet *dev = netdev_priv(netdev);
  516. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  517. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  518. ee->magic);
  519. return -EINVAL;
  520. }
  521. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  522. }
  523. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  524. struct ethtool_wolinfo *wolinfo)
  525. {
  526. struct usbnet *dev = netdev_priv(net);
  527. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  528. wolinfo->supported = SUPPORTED_WAKE;
  529. wolinfo->wolopts = pdata->wolopts;
  530. }
  531. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  532. struct ethtool_wolinfo *wolinfo)
  533. {
  534. struct usbnet *dev = netdev_priv(net);
  535. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  536. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  537. return 0;
  538. }
  539. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  540. .get_link = usbnet_get_link,
  541. .nway_reset = usbnet_nway_reset,
  542. .get_drvinfo = usbnet_get_drvinfo,
  543. .get_msglevel = usbnet_get_msglevel,
  544. .set_msglevel = usbnet_set_msglevel,
  545. .get_settings = usbnet_get_settings,
  546. .set_settings = usbnet_set_settings,
  547. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  548. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  549. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  550. .get_wol = smsc75xx_ethtool_get_wol,
  551. .set_wol = smsc75xx_ethtool_set_wol,
  552. };
  553. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  554. {
  555. struct usbnet *dev = netdev_priv(netdev);
  556. if (!netif_running(netdev))
  557. return -EINVAL;
  558. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  559. }
  560. static void smsc75xx_init_mac_address(struct usbnet *dev)
  561. {
  562. /* try reading mac address from EEPROM */
  563. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  564. dev->net->dev_addr) == 0) {
  565. if (is_valid_ether_addr(dev->net->dev_addr)) {
  566. /* eeprom values are valid so use them */
  567. netif_dbg(dev, ifup, dev->net,
  568. "MAC address read from EEPROM\n");
  569. return;
  570. }
  571. }
  572. /* no eeprom, or eeprom values are invalid. generate random MAC */
  573. eth_hw_addr_random(dev->net);
  574. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  575. }
  576. static int smsc75xx_set_mac_address(struct usbnet *dev)
  577. {
  578. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  579. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  580. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  581. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  582. check_warn_return(ret, "Failed to write RX_ADDRH: %d\n", ret);
  583. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  584. check_warn_return(ret, "Failed to write RX_ADDRL: %d\n", ret);
  585. addr_hi |= ADDR_FILTX_FB_VALID;
  586. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  587. check_warn_return(ret, "Failed to write ADDR_FILTX: %d\n", ret);
  588. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  589. check_warn_return(ret, "Failed to write ADDR_FILTX+4: %d\n", ret);
  590. return 0;
  591. }
  592. static int smsc75xx_phy_initialize(struct usbnet *dev)
  593. {
  594. int bmcr, ret, timeout = 0;
  595. /* Initialize MII structure */
  596. dev->mii.dev = dev->net;
  597. dev->mii.mdio_read = smsc75xx_mdio_read;
  598. dev->mii.mdio_write = smsc75xx_mdio_write;
  599. dev->mii.phy_id_mask = 0x1f;
  600. dev->mii.reg_num_mask = 0x1f;
  601. dev->mii.supports_gmii = 1;
  602. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  603. /* reset phy and wait for reset to complete */
  604. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  605. do {
  606. msleep(10);
  607. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  608. check_warn_return(bmcr, "Error reading MII_BMCR\n");
  609. timeout++;
  610. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  611. if (timeout >= 100) {
  612. netdev_warn(dev->net, "timeout on PHY Reset\n");
  613. return -EIO;
  614. }
  615. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  616. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  617. ADVERTISE_PAUSE_ASYM);
  618. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  619. ADVERTISE_1000FULL);
  620. /* read and write to clear phy interrupt status */
  621. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  622. check_warn_return(ret, "Error reading PHY_INT_SRC\n");
  623. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  624. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  625. PHY_INT_MASK_DEFAULT);
  626. mii_nway_restart(&dev->mii);
  627. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  628. return 0;
  629. }
  630. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  631. {
  632. int ret = 0;
  633. u32 buf;
  634. bool rxenabled;
  635. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  636. check_warn_return(ret, "Failed to read MAC_RX: %d\n", ret);
  637. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  638. if (rxenabled) {
  639. buf &= ~MAC_RX_RXEN;
  640. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  641. check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
  642. }
  643. /* add 4 to size for FCS */
  644. buf &= ~MAC_RX_MAX_SIZE;
  645. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  646. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  647. check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
  648. if (rxenabled) {
  649. buf |= MAC_RX_RXEN;
  650. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  651. check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
  652. }
  653. return 0;
  654. }
  655. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  656. {
  657. struct usbnet *dev = netdev_priv(netdev);
  658. int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu);
  659. check_warn_return(ret, "Failed to set mac rx frame length\n");
  660. return usbnet_change_mtu(netdev, new_mtu);
  661. }
  662. /* Enable or disable Rx checksum offload engine */
  663. static int smsc75xx_set_features(struct net_device *netdev,
  664. netdev_features_t features)
  665. {
  666. struct usbnet *dev = netdev_priv(netdev);
  667. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  668. unsigned long flags;
  669. int ret;
  670. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  671. if (features & NETIF_F_RXCSUM)
  672. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  673. else
  674. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  675. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  676. /* it's racing here! */
  677. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  678. check_warn_return(ret, "Error writing RFE_CTL\n");
  679. return 0;
  680. }
  681. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  682. {
  683. int timeout = 0;
  684. do {
  685. u32 buf;
  686. int ret;
  687. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  688. check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
  689. if (buf & PMT_CTL_DEV_RDY)
  690. return 0;
  691. msleep(10);
  692. timeout++;
  693. } while (timeout < 100);
  694. netdev_warn(dev->net, "timeout waiting for device ready\n");
  695. return -EIO;
  696. }
  697. static int smsc75xx_reset(struct usbnet *dev)
  698. {
  699. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  700. u32 buf;
  701. int ret = 0, timeout;
  702. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  703. ret = smsc75xx_wait_ready(dev, 0);
  704. check_warn_return(ret, "device not ready in smsc75xx_reset\n");
  705. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  706. check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
  707. buf |= HW_CFG_LRST;
  708. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  709. check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
  710. timeout = 0;
  711. do {
  712. msleep(10);
  713. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  714. check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
  715. timeout++;
  716. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  717. if (timeout >= 100) {
  718. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  719. return -EIO;
  720. }
  721. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  722. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  723. check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
  724. buf |= PMT_CTL_PHY_RST;
  725. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  726. check_warn_return(ret, "Failed to write PMT_CTL: %d\n", ret);
  727. timeout = 0;
  728. do {
  729. msleep(10);
  730. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  731. check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
  732. timeout++;
  733. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  734. if (timeout >= 100) {
  735. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  736. return -EIO;
  737. }
  738. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  739. smsc75xx_init_mac_address(dev);
  740. ret = smsc75xx_set_mac_address(dev);
  741. check_warn_return(ret, "Failed to set mac address\n");
  742. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  743. dev->net->dev_addr);
  744. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  745. check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
  746. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  747. buf);
  748. buf |= HW_CFG_BIR;
  749. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  750. check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
  751. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  752. check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
  753. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  754. buf);
  755. if (!turbo_mode) {
  756. buf = 0;
  757. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  758. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  759. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  760. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  761. } else {
  762. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  763. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  764. }
  765. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  766. (ulong)dev->rx_urb_size);
  767. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  768. check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret);
  769. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  770. check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret);
  771. netif_dbg(dev, ifup, dev->net,
  772. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  773. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  774. check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret);
  775. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  776. check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret);
  777. netif_dbg(dev, ifup, dev->net,
  778. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  779. if (turbo_mode) {
  780. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  781. check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
  782. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  783. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  784. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  785. check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
  786. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  787. check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
  788. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  789. }
  790. /* set FIFO sizes */
  791. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  792. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  793. check_warn_return(ret, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  794. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  795. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  796. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  797. check_warn_return(ret, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  798. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  799. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  800. check_warn_return(ret, "Failed to write INT_STS: %d\n", ret);
  801. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  802. check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
  803. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  804. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  805. check_warn_return(ret, "Failed to read E2P_CMD: %d\n", ret);
  806. /* only set default GPIO/LED settings if no EEPROM is detected */
  807. if (!(buf & E2P_CMD_LOADED)) {
  808. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  809. check_warn_return(ret, "Failed to read LED_GPIO_CFG: %d\n",
  810. ret);
  811. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  812. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  813. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  814. check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n",
  815. ret);
  816. }
  817. ret = smsc75xx_write_reg(dev, FLOW, 0);
  818. check_warn_return(ret, "Failed to write FLOW: %d\n", ret);
  819. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  820. check_warn_return(ret, "Failed to write FCT_FLOW: %d\n", ret);
  821. /* Don't need rfe_ctl_lock during initialisation */
  822. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  823. check_warn_return(ret, "Failed to read RFE_CTL: %d\n", ret);
  824. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  825. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  826. check_warn_return(ret, "Failed to write RFE_CTL: %d\n", ret);
  827. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  828. check_warn_return(ret, "Failed to read RFE_CTL: %d\n", ret);
  829. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  830. pdata->rfe_ctl);
  831. /* Enable or disable checksum offload engines */
  832. smsc75xx_set_features(dev->net, dev->net->features);
  833. smsc75xx_set_multicast(dev->net);
  834. ret = smsc75xx_phy_initialize(dev);
  835. check_warn_return(ret, "Failed to initialize PHY: %d\n", ret);
  836. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  837. check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret);
  838. /* enable PHY interrupts */
  839. buf |= INT_ENP_PHY_INT;
  840. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  841. check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret);
  842. /* allow mac to detect speed and duplex from phy */
  843. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  844. check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret);
  845. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  846. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  847. check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
  848. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  849. check_warn_return(ret, "Failed to read MAC_TX: %d\n", ret);
  850. buf |= MAC_TX_TXEN;
  851. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  852. check_warn_return(ret, "Failed to write MAC_TX: %d\n", ret);
  853. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  854. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  855. check_warn_return(ret, "Failed to read FCT_TX_CTL: %d\n", ret);
  856. buf |= FCT_TX_CTL_EN;
  857. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  858. check_warn_return(ret, "Failed to write FCT_TX_CTL: %d\n", ret);
  859. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  860. ret = smsc75xx_set_rx_max_frame_length(dev, 1514);
  861. check_warn_return(ret, "Failed to set max rx frame length\n");
  862. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  863. check_warn_return(ret, "Failed to read MAC_RX: %d\n", ret);
  864. buf |= MAC_RX_RXEN;
  865. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  866. check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
  867. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  868. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  869. check_warn_return(ret, "Failed to read FCT_RX_CTL: %d\n", ret);
  870. buf |= FCT_RX_CTL_EN;
  871. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  872. check_warn_return(ret, "Failed to write FCT_RX_CTL: %d\n", ret);
  873. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  874. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  875. return 0;
  876. }
  877. static const struct net_device_ops smsc75xx_netdev_ops = {
  878. .ndo_open = usbnet_open,
  879. .ndo_stop = usbnet_stop,
  880. .ndo_start_xmit = usbnet_start_xmit,
  881. .ndo_tx_timeout = usbnet_tx_timeout,
  882. .ndo_change_mtu = smsc75xx_change_mtu,
  883. .ndo_set_mac_address = eth_mac_addr,
  884. .ndo_validate_addr = eth_validate_addr,
  885. .ndo_do_ioctl = smsc75xx_ioctl,
  886. .ndo_set_rx_mode = smsc75xx_set_multicast,
  887. .ndo_set_features = smsc75xx_set_features,
  888. };
  889. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  890. {
  891. struct smsc75xx_priv *pdata = NULL;
  892. int ret;
  893. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  894. ret = usbnet_get_endpoints(dev, intf);
  895. check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret);
  896. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  897. GFP_KERNEL);
  898. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  899. if (!pdata) {
  900. netdev_warn(dev->net, "Unable to allocate smsc75xx_priv\n");
  901. return -ENOMEM;
  902. }
  903. pdata->dev = dev;
  904. spin_lock_init(&pdata->rfe_ctl_lock);
  905. mutex_init(&pdata->dataport_mutex);
  906. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  907. if (DEFAULT_TX_CSUM_ENABLE) {
  908. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  909. if (DEFAULT_TSO_ENABLE)
  910. dev->net->features |= NETIF_F_SG |
  911. NETIF_F_TSO | NETIF_F_TSO6;
  912. }
  913. if (DEFAULT_RX_CSUM_ENABLE)
  914. dev->net->features |= NETIF_F_RXCSUM;
  915. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  916. NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM;
  917. /* Init all registers */
  918. ret = smsc75xx_reset(dev);
  919. check_warn_return(ret, "smsc75xx_reset error %d\n", ret);
  920. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  921. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  922. dev->net->flags |= IFF_MULTICAST;
  923. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  924. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  925. return 0;
  926. }
  927. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  928. {
  929. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  930. if (pdata) {
  931. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  932. kfree(pdata);
  933. pdata = NULL;
  934. dev->data[0] = 0;
  935. }
  936. }
  937. static u16 smsc_crc(const u8 *buffer, size_t len)
  938. {
  939. return bitrev16(crc16(0xFFFF, buffer, len));
  940. }
  941. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  942. u32 wuf_mask1)
  943. {
  944. int cfg_base = WUF_CFGX + filter * 4;
  945. int mask_base = WUF_MASKX + filter * 16;
  946. int ret;
  947. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  948. check_warn_return(ret, "Error writing WUF_CFGX\n");
  949. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  950. check_warn_return(ret, "Error writing WUF_MASKX\n");
  951. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  952. check_warn_return(ret, "Error writing WUF_MASKX\n");
  953. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  954. check_warn_return(ret, "Error writing WUF_MASKX\n");
  955. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  956. check_warn_return(ret, "Error writing WUF_MASKX\n");
  957. return 0;
  958. }
  959. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  960. {
  961. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  962. u32 val;
  963. int ret;
  964. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  965. check_warn_return(ret, "Error reading PMT_CTL\n");
  966. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  967. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  968. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  969. check_warn_return(ret, "Error writing PMT_CTL\n");
  970. smsc75xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
  971. pdata->suspend_flags |= SUSPEND_SUSPEND0 | SUSPEND_REMOTEWAKE;
  972. return 0;
  973. }
  974. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  975. {
  976. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  977. u32 val;
  978. int ret;
  979. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  980. check_warn_return(ret, "Error reading PMT_CTL\n");
  981. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  982. val |= PMT_CTL_SUS_MODE_1;
  983. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  984. check_warn_return(ret, "Error writing PMT_CTL\n");
  985. /* clear wol status, enable energy detection */
  986. val &= ~PMT_CTL_WUPS;
  987. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  988. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  989. check_warn_return(ret, "Error writing PMT_CTL\n");
  990. smsc75xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
  991. pdata->suspend_flags |= SUSPEND_SUSPEND1 | SUSPEND_REMOTEWAKE;
  992. return 0;
  993. }
  994. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  995. {
  996. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  997. u32 val;
  998. int ret;
  999. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1000. check_warn_return(ret, "Error reading PMT_CTL\n");
  1001. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1002. val |= PMT_CTL_SUS_MODE_2;
  1003. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1004. check_warn_return(ret, "Error writing PMT_CTL\n");
  1005. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1006. return 0;
  1007. }
  1008. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1009. {
  1010. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1011. u32 val;
  1012. int ret;
  1013. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1014. check_warn_return(ret, "Error reading FCT_RX_CTL\n");
  1015. if (val & FCT_RX_CTL_RXUSED) {
  1016. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1017. return -EBUSY;
  1018. }
  1019. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1020. check_warn_return(ret, "Error reading PMT_CTL\n");
  1021. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1022. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1023. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1024. check_warn_return(ret, "Error writing PMT_CTL\n");
  1025. /* clear wol status */
  1026. val &= ~PMT_CTL_WUPS;
  1027. val |= PMT_CTL_WUPS_WOL;
  1028. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1029. check_warn_return(ret, "Error writing PMT_CTL\n");
  1030. smsc75xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
  1031. pdata->suspend_flags |= SUSPEND_SUSPEND3 | SUSPEND_REMOTEWAKE;
  1032. return 0;
  1033. }
  1034. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1035. {
  1036. struct mii_if_info *mii = &dev->mii;
  1037. int ret;
  1038. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1039. /* read to clear */
  1040. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1041. check_warn_return(ret, "Error reading PHY_INT_SRC\n");
  1042. /* enable interrupt source */
  1043. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1044. check_warn_return(ret, "Error reading PHY_INT_MASK\n");
  1045. ret |= mask;
  1046. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1047. return 0;
  1048. }
  1049. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1050. {
  1051. struct mii_if_info *mii = &dev->mii;
  1052. int ret;
  1053. /* first, a dummy read, needed to latch some MII phys */
  1054. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1055. check_warn_return(ret, "Error reading MII_BMSR\n");
  1056. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1057. check_warn_return(ret, "Error reading MII_BMSR\n");
  1058. return !!(ret & BMSR_LSTATUS);
  1059. }
  1060. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1061. {
  1062. int ret;
  1063. if (!netif_running(dev->net)) {
  1064. /* interface is ifconfig down so fully power down hw */
  1065. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1066. return smsc75xx_enter_suspend2(dev);
  1067. }
  1068. if (!link_up) {
  1069. /* link is down so enter EDPD mode */
  1070. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1071. /* enable PHY wakeup events for if cable is attached */
  1072. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1073. PHY_INT_MASK_ANEG_COMP);
  1074. check_warn_return(ret, "error enabling PHY wakeup ints\n");
  1075. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1076. return smsc75xx_enter_suspend1(dev);
  1077. }
  1078. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1079. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1080. PHY_INT_MASK_LINK_DOWN);
  1081. check_warn_return(ret, "error enabling PHY wakeup ints\n");
  1082. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1083. return smsc75xx_enter_suspend3(dev);
  1084. }
  1085. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1086. {
  1087. struct usbnet *dev = usb_get_intfdata(intf);
  1088. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1089. u32 val, link_up;
  1090. int ret;
  1091. ret = usbnet_suspend(intf, message);
  1092. check_warn_goto_done(ret, "usbnet_suspend error\n");
  1093. if (pdata->suspend_flags) {
  1094. netdev_warn(dev->net, "error during last resume\n");
  1095. pdata->suspend_flags = 0;
  1096. }
  1097. /* determine if link is up using only _nopm functions */
  1098. link_up = smsc75xx_link_ok_nopm(dev);
  1099. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1100. ret = smsc75xx_autosuspend(dev, link_up);
  1101. goto done;
  1102. }
  1103. /* if we get this far we're not autosuspending */
  1104. /* if no wol options set, or if link is down and we're not waking on
  1105. * PHY activity, enter lowest power SUSPEND2 mode
  1106. */
  1107. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1108. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1109. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1110. /* disable energy detect (link up) & wake up events */
  1111. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1112. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1113. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1114. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1115. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1116. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1117. check_warn_goto_done(ret, "Error reading PMT_CTL\n");
  1118. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1119. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1120. check_warn_goto_done(ret, "Error writing PMT_CTL\n");
  1121. ret = smsc75xx_enter_suspend2(dev);
  1122. goto done;
  1123. }
  1124. if (pdata->wolopts & WAKE_PHY) {
  1125. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1126. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1127. check_warn_goto_done(ret, "error enabling PHY wakeup ints\n");
  1128. /* if link is down then configure EDPD and enter SUSPEND1,
  1129. * otherwise enter SUSPEND0 below
  1130. */
  1131. if (!link_up) {
  1132. struct mii_if_info *mii = &dev->mii;
  1133. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1134. /* enable energy detect power-down mode */
  1135. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1136. PHY_MODE_CTRL_STS);
  1137. check_warn_goto_done(ret, "Error reading PHY_MODE_CTRL_STS\n");
  1138. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1139. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1140. PHY_MODE_CTRL_STS, ret);
  1141. /* enter SUSPEND1 mode */
  1142. ret = smsc75xx_enter_suspend1(dev);
  1143. goto done;
  1144. }
  1145. }
  1146. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1147. int i, filter = 0;
  1148. /* disable all filters */
  1149. for (i = 0; i < WUF_NUM; i++) {
  1150. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1151. check_warn_goto_done(ret, "Error writing WUF_CFGX\n");
  1152. }
  1153. if (pdata->wolopts & WAKE_MCAST) {
  1154. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1155. netdev_info(dev->net, "enabling multicast detection\n");
  1156. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1157. | smsc_crc(mcast, 3);
  1158. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1159. check_warn_goto_done(ret, "Error writing wakeup filter\n");
  1160. }
  1161. if (pdata->wolopts & WAKE_ARP) {
  1162. const u8 arp[] = {0x08, 0x06};
  1163. netdev_info(dev->net, "enabling ARP detection\n");
  1164. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1165. | smsc_crc(arp, 2);
  1166. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1167. check_warn_goto_done(ret, "Error writing wakeup filter\n");
  1168. }
  1169. /* clear any pending pattern match packet status */
  1170. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1171. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1172. val |= WUCSR_WUFR;
  1173. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1174. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1175. netdev_info(dev->net, "enabling packet match detection\n");
  1176. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1177. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1178. val |= WUCSR_WUEN;
  1179. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1180. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1181. } else {
  1182. netdev_info(dev->net, "disabling packet match detection\n");
  1183. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1184. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1185. val &= ~WUCSR_WUEN;
  1186. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1187. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1188. }
  1189. /* disable magic, bcast & unicast wakeup sources */
  1190. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1191. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1192. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1193. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1194. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1195. if (pdata->wolopts & WAKE_PHY) {
  1196. netdev_info(dev->net, "enabling PHY wakeup\n");
  1197. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1198. check_warn_goto_done(ret, "Error reading PMT_CTL\n");
  1199. /* clear wol status, enable energy detection */
  1200. val &= ~PMT_CTL_WUPS;
  1201. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1202. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1203. check_warn_goto_done(ret, "Error writing PMT_CTL\n");
  1204. }
  1205. if (pdata->wolopts & WAKE_MAGIC) {
  1206. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1207. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1208. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1209. /* clear any pending magic packet status */
  1210. val |= WUCSR_MPR | WUCSR_MPEN;
  1211. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1212. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1213. }
  1214. if (pdata->wolopts & WAKE_BCAST) {
  1215. netdev_info(dev->net, "enabling broadcast detection\n");
  1216. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1217. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1218. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1219. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1220. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1221. }
  1222. if (pdata->wolopts & WAKE_UCAST) {
  1223. netdev_info(dev->net, "enabling unicast detection\n");
  1224. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1225. check_warn_goto_done(ret, "Error reading WUCSR\n");
  1226. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1227. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1228. check_warn_goto_done(ret, "Error writing WUCSR\n");
  1229. }
  1230. /* enable receiver to enable frame reception */
  1231. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1232. check_warn_goto_done(ret, "Failed to read MAC_RX: %d\n", ret);
  1233. val |= MAC_RX_RXEN;
  1234. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1235. check_warn_goto_done(ret, "Failed to write MAC_RX: %d\n", ret);
  1236. /* some wol options are enabled, so enter SUSPEND0 */
  1237. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1238. ret = smsc75xx_enter_suspend0(dev);
  1239. done:
  1240. if (ret)
  1241. usbnet_resume(intf);
  1242. return ret;
  1243. }
  1244. static int smsc75xx_resume(struct usb_interface *intf)
  1245. {
  1246. struct usbnet *dev = usb_get_intfdata(intf);
  1247. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1248. u8 suspend_flags = pdata->suspend_flags;
  1249. int ret;
  1250. u32 val;
  1251. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1252. /* do this first to ensure it's cleared even in error case */
  1253. pdata->suspend_flags = 0;
  1254. if (suspend_flags & SUSPEND_REMOTEWAKE) {
  1255. ret = smsc75xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
  1256. check_warn_return(ret, "Error disabling remote wakeup\n");
  1257. }
  1258. if (suspend_flags & SUSPEND_ALLMODES) {
  1259. /* Disable wakeup sources */
  1260. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1261. check_warn_return(ret, "Error reading WUCSR\n");
  1262. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1263. | WUCSR_BCST_EN);
  1264. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1265. check_warn_return(ret, "Error writing WUCSR\n");
  1266. /* clear wake-up status */
  1267. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1268. check_warn_return(ret, "Error reading PMT_CTL\n");
  1269. val &= ~PMT_CTL_WOL_EN;
  1270. val |= PMT_CTL_WUPS;
  1271. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1272. check_warn_return(ret, "Error writing PMT_CTL\n");
  1273. }
  1274. if (suspend_flags & SUSPEND_SUSPEND2) {
  1275. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1276. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1277. check_warn_return(ret, "Error reading PMT_CTL\n");
  1278. val |= PMT_CTL_PHY_PWRUP;
  1279. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1280. check_warn_return(ret, "Error writing PMT_CTL\n");
  1281. }
  1282. ret = smsc75xx_wait_ready(dev, 1);
  1283. check_warn_return(ret, "device not ready in smsc75xx_resume\n");
  1284. return usbnet_resume(intf);
  1285. }
  1286. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1287. u32 rx_cmd_a, u32 rx_cmd_b)
  1288. {
  1289. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1290. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1291. skb->ip_summed = CHECKSUM_NONE;
  1292. } else {
  1293. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1294. skb->ip_summed = CHECKSUM_COMPLETE;
  1295. }
  1296. }
  1297. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1298. {
  1299. while (skb->len > 0) {
  1300. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1301. struct sk_buff *ax_skb;
  1302. unsigned char *packet;
  1303. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1304. le32_to_cpus(&rx_cmd_a);
  1305. skb_pull(skb, 4);
  1306. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1307. le32_to_cpus(&rx_cmd_b);
  1308. skb_pull(skb, 4 + RXW_PADDING);
  1309. packet = skb->data;
  1310. /* get the packet length */
  1311. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1312. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1313. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1314. netif_dbg(dev, rx_err, dev->net,
  1315. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1316. dev->net->stats.rx_errors++;
  1317. dev->net->stats.rx_dropped++;
  1318. if (rx_cmd_a & RX_CMD_A_FCS)
  1319. dev->net->stats.rx_crc_errors++;
  1320. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1321. dev->net->stats.rx_frame_errors++;
  1322. } else {
  1323. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  1324. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  1325. netif_dbg(dev, rx_err, dev->net,
  1326. "size err rx_cmd_a=0x%08x\n",
  1327. rx_cmd_a);
  1328. return 0;
  1329. }
  1330. /* last frame in this batch */
  1331. if (skb->len == size) {
  1332. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1333. rx_cmd_b);
  1334. skb_trim(skb, skb->len - 4); /* remove fcs */
  1335. skb->truesize = size + sizeof(struct sk_buff);
  1336. return 1;
  1337. }
  1338. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1339. if (unlikely(!ax_skb)) {
  1340. netdev_warn(dev->net, "Error allocating skb\n");
  1341. return 0;
  1342. }
  1343. ax_skb->len = size;
  1344. ax_skb->data = packet;
  1345. skb_set_tail_pointer(ax_skb, size);
  1346. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1347. rx_cmd_b);
  1348. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1349. ax_skb->truesize = size + sizeof(struct sk_buff);
  1350. usbnet_skb_return(dev, ax_skb);
  1351. }
  1352. skb_pull(skb, size);
  1353. /* padding bytes before the next frame starts */
  1354. if (skb->len)
  1355. skb_pull(skb, align_count);
  1356. }
  1357. if (unlikely(skb->len < 0)) {
  1358. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1359. return 0;
  1360. }
  1361. return 1;
  1362. }
  1363. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1364. struct sk_buff *skb, gfp_t flags)
  1365. {
  1366. u32 tx_cmd_a, tx_cmd_b;
  1367. skb_linearize(skb);
  1368. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1369. struct sk_buff *skb2 =
  1370. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1371. dev_kfree_skb_any(skb);
  1372. skb = skb2;
  1373. if (!skb)
  1374. return NULL;
  1375. }
  1376. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1377. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1378. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1379. if (skb_is_gso(skb)) {
  1380. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1381. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1382. tx_cmd_a |= TX_CMD_A_LSO;
  1383. } else {
  1384. tx_cmd_b = 0;
  1385. }
  1386. skb_push(skb, 4);
  1387. cpu_to_le32s(&tx_cmd_b);
  1388. memcpy(skb->data, &tx_cmd_b, 4);
  1389. skb_push(skb, 4);
  1390. cpu_to_le32s(&tx_cmd_a);
  1391. memcpy(skb->data, &tx_cmd_a, 4);
  1392. return skb;
  1393. }
  1394. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1395. {
  1396. dev->intf->needs_remote_wakeup = on;
  1397. return 0;
  1398. }
  1399. static const struct driver_info smsc75xx_info = {
  1400. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1401. .bind = smsc75xx_bind,
  1402. .unbind = smsc75xx_unbind,
  1403. .link_reset = smsc75xx_link_reset,
  1404. .reset = smsc75xx_reset,
  1405. .rx_fixup = smsc75xx_rx_fixup,
  1406. .tx_fixup = smsc75xx_tx_fixup,
  1407. .status = smsc75xx_status,
  1408. .manage_power = smsc75xx_manage_power,
  1409. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1410. };
  1411. static const struct usb_device_id products[] = {
  1412. {
  1413. /* SMSC7500 USB Gigabit Ethernet Device */
  1414. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1415. .driver_info = (unsigned long) &smsc75xx_info,
  1416. },
  1417. {
  1418. /* SMSC7500 USB Gigabit Ethernet Device */
  1419. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1420. .driver_info = (unsigned long) &smsc75xx_info,
  1421. },
  1422. { }, /* END */
  1423. };
  1424. MODULE_DEVICE_TABLE(usb, products);
  1425. static struct usb_driver smsc75xx_driver = {
  1426. .name = SMSC_CHIPNAME,
  1427. .id_table = products,
  1428. .probe = usbnet_probe,
  1429. .suspend = smsc75xx_suspend,
  1430. .resume = smsc75xx_resume,
  1431. .reset_resume = smsc75xx_resume,
  1432. .disconnect = usbnet_disconnect,
  1433. .disable_hub_initiated_lpm = 1,
  1434. .supports_autosuspend = 1,
  1435. };
  1436. module_usb_driver(smsc75xx_driver);
  1437. MODULE_AUTHOR("Nancy Lin");
  1438. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1439. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1440. MODULE_LICENSE("GPL");