mcbsp.c 24 KB

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  1. /*
  2. * linux/arch/arm/plat-omap/mcbsp.c
  3. *
  4. * Copyright (C) 2004 Nokia Corporation
  5. * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
  6. *
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Multichannel mode not supported.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/wait.h>
  19. #include <linux/completion.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/err.h>
  22. #include <linux/clk.h>
  23. #include <linux/delay.h>
  24. #include <linux/io.h>
  25. #include <mach/dma.h>
  26. #include <mach/mcbsp.h>
  27. struct omap_mcbsp **mcbsp_ptr;
  28. int omap_mcbsp_count;
  29. void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  30. {
  31. if (cpu_class_is_omap1() || cpu_is_omap2420())
  32. __raw_writew((u16)val, io_base + reg);
  33. else
  34. __raw_writel(val, io_base + reg);
  35. }
  36. int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  37. {
  38. if (cpu_class_is_omap1() || cpu_is_omap2420())
  39. return __raw_readw(io_base + reg);
  40. else
  41. return __raw_readl(io_base + reg);
  42. }
  43. #define OMAP_MCBSP_READ(base, reg) \
  44. omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  45. #define OMAP_MCBSP_WRITE(base, reg, val) \
  46. omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  47. #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
  48. #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
  49. static void omap_mcbsp_dump_reg(u8 id)
  50. {
  51. struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  52. dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  53. dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
  54. OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  55. dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
  56. OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  57. dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
  58. OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  59. dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
  60. OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  61. dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  62. OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  63. dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  64. OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  65. dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
  66. OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  67. dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
  68. OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  69. dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
  70. OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  71. dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
  72. OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  73. dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  74. OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  75. dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  76. OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  77. dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
  78. OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  79. dev_dbg(mcbsp->dev, "***********************\n");
  80. }
  81. static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  82. {
  83. struct omap_mcbsp *mcbsp_tx = dev_id;
  84. dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
  85. OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
  86. complete(&mcbsp_tx->tx_irq_completion);
  87. return IRQ_HANDLED;
  88. }
  89. static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
  90. {
  91. struct omap_mcbsp *mcbsp_rx = dev_id;
  92. dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
  93. OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
  94. complete(&mcbsp_rx->rx_irq_completion);
  95. return IRQ_HANDLED;
  96. }
  97. static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
  98. {
  99. struct omap_mcbsp *mcbsp_dma_tx = data;
  100. dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
  101. OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
  102. /* We can free the channels */
  103. omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
  104. mcbsp_dma_tx->dma_tx_lch = -1;
  105. complete(&mcbsp_dma_tx->tx_dma_completion);
  106. }
  107. static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
  108. {
  109. struct omap_mcbsp *mcbsp_dma_rx = data;
  110. dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
  111. OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
  112. /* We can free the channels */
  113. omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
  114. mcbsp_dma_rx->dma_rx_lch = -1;
  115. complete(&mcbsp_dma_rx->rx_dma_completion);
  116. }
  117. /*
  118. * omap_mcbsp_config simply write a config to the
  119. * appropriate McBSP.
  120. * You either call this function or set the McBSP registers
  121. * by yourself before calling omap_mcbsp_start().
  122. */
  123. void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
  124. {
  125. struct omap_mcbsp *mcbsp;
  126. void __iomem *io_base;
  127. if (!omap_mcbsp_check_valid_id(id)) {
  128. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  129. return;
  130. }
  131. mcbsp = id_to_mcbsp_ptr(id);
  132. io_base = mcbsp->io_base;
  133. dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
  134. mcbsp->id, mcbsp->phys_base);
  135. /* We write the given config */
  136. OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
  137. OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
  138. OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
  139. OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
  140. OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
  141. OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
  142. OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
  143. OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
  144. OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
  145. OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
  146. OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
  147. }
  148. EXPORT_SYMBOL(omap_mcbsp_config);
  149. /*
  150. * We can choose between IRQ based or polled IO.
  151. * This needs to be called before omap_mcbsp_request().
  152. */
  153. int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
  154. {
  155. struct omap_mcbsp *mcbsp;
  156. if (!omap_mcbsp_check_valid_id(id)) {
  157. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  158. return -ENODEV;
  159. }
  160. mcbsp = id_to_mcbsp_ptr(id);
  161. spin_lock(&mcbsp->lock);
  162. if (!mcbsp->free) {
  163. dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
  164. mcbsp->id);
  165. spin_unlock(&mcbsp->lock);
  166. return -EINVAL;
  167. }
  168. mcbsp->io_type = io_type;
  169. spin_unlock(&mcbsp->lock);
  170. return 0;
  171. }
  172. EXPORT_SYMBOL(omap_mcbsp_set_io_type);
  173. int omap_mcbsp_request(unsigned int id)
  174. {
  175. struct omap_mcbsp *mcbsp;
  176. int err;
  177. if (!omap_mcbsp_check_valid_id(id)) {
  178. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  179. return -ENODEV;
  180. }
  181. mcbsp = id_to_mcbsp_ptr(id);
  182. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
  183. mcbsp->pdata->ops->request(id);
  184. clk_enable(mcbsp->clk);
  185. spin_lock(&mcbsp->lock);
  186. if (!mcbsp->free) {
  187. dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
  188. mcbsp->id);
  189. spin_unlock(&mcbsp->lock);
  190. return -1;
  191. }
  192. mcbsp->free = 0;
  193. spin_unlock(&mcbsp->lock);
  194. if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
  195. /* We need to get IRQs here */
  196. err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
  197. 0, "McBSP", (void *)mcbsp);
  198. if (err != 0) {
  199. dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
  200. "for McBSP%d\n", mcbsp->tx_irq,
  201. mcbsp->id);
  202. return err;
  203. }
  204. init_completion(&mcbsp->tx_irq_completion);
  205. err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
  206. 0, "McBSP", (void *)mcbsp);
  207. if (err != 0) {
  208. dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
  209. "for McBSP%d\n", mcbsp->rx_irq,
  210. mcbsp->id);
  211. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  212. return err;
  213. }
  214. init_completion(&mcbsp->rx_irq_completion);
  215. }
  216. return 0;
  217. }
  218. EXPORT_SYMBOL(omap_mcbsp_request);
  219. void omap_mcbsp_free(unsigned int id)
  220. {
  221. struct omap_mcbsp *mcbsp;
  222. if (!omap_mcbsp_check_valid_id(id)) {
  223. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  224. return;
  225. }
  226. mcbsp = id_to_mcbsp_ptr(id);
  227. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  228. mcbsp->pdata->ops->free(id);
  229. clk_disable(mcbsp->clk);
  230. spin_lock(&mcbsp->lock);
  231. if (mcbsp->free) {
  232. dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
  233. mcbsp->id);
  234. spin_unlock(&mcbsp->lock);
  235. return;
  236. }
  237. mcbsp->free = 1;
  238. spin_unlock(&mcbsp->lock);
  239. if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
  240. /* Free IRQs */
  241. free_irq(mcbsp->rx_irq, (void *)mcbsp);
  242. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  243. }
  244. }
  245. EXPORT_SYMBOL(omap_mcbsp_free);
  246. /*
  247. * Here we start the McBSP, by enabling the sample
  248. * generator, both transmitter and receivers,
  249. * and the frame sync.
  250. */
  251. void omap_mcbsp_start(unsigned int id)
  252. {
  253. struct omap_mcbsp *mcbsp;
  254. void __iomem *io_base;
  255. u16 w;
  256. if (!omap_mcbsp_check_valid_id(id)) {
  257. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  258. return;
  259. }
  260. mcbsp = id_to_mcbsp_ptr(id);
  261. io_base = mcbsp->io_base;
  262. mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
  263. mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
  264. /* Start the sample generator */
  265. w = OMAP_MCBSP_READ(io_base, SPCR2);
  266. OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
  267. /* Enable transmitter and receiver */
  268. w = OMAP_MCBSP_READ(io_base, SPCR2);
  269. OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
  270. w = OMAP_MCBSP_READ(io_base, SPCR1);
  271. OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
  272. udelay(100);
  273. /* Start frame sync */
  274. w = OMAP_MCBSP_READ(io_base, SPCR2);
  275. OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
  276. /* Dump McBSP Regs */
  277. omap_mcbsp_dump_reg(id);
  278. }
  279. EXPORT_SYMBOL(omap_mcbsp_start);
  280. void omap_mcbsp_stop(unsigned int id)
  281. {
  282. struct omap_mcbsp *mcbsp;
  283. void __iomem *io_base;
  284. u16 w;
  285. if (!omap_mcbsp_check_valid_id(id)) {
  286. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  287. return;
  288. }
  289. mcbsp = id_to_mcbsp_ptr(id);
  290. io_base = mcbsp->io_base;
  291. /* Reset transmitter */
  292. w = OMAP_MCBSP_READ(io_base, SPCR2);
  293. OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
  294. /* Reset receiver */
  295. w = OMAP_MCBSP_READ(io_base, SPCR1);
  296. OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
  297. /* Reset the sample rate generator */
  298. w = OMAP_MCBSP_READ(io_base, SPCR2);
  299. OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
  300. }
  301. EXPORT_SYMBOL(omap_mcbsp_stop);
  302. /* polled mcbsp i/o operations */
  303. int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
  304. {
  305. struct omap_mcbsp *mcbsp;
  306. void __iomem *base;
  307. if (!omap_mcbsp_check_valid_id(id)) {
  308. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  309. return -ENODEV;
  310. }
  311. mcbsp = id_to_mcbsp_ptr(id);
  312. base = mcbsp->io_base;
  313. writew(buf, base + OMAP_MCBSP_REG_DXR1);
  314. /* if frame sync error - clear the error */
  315. if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
  316. /* clear error */
  317. writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
  318. base + OMAP_MCBSP_REG_SPCR2);
  319. /* resend */
  320. return -1;
  321. } else {
  322. /* wait for transmit confirmation */
  323. int attemps = 0;
  324. while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
  325. if (attemps++ > 1000) {
  326. writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
  327. (~XRST),
  328. base + OMAP_MCBSP_REG_SPCR2);
  329. udelay(10);
  330. writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
  331. (XRST),
  332. base + OMAP_MCBSP_REG_SPCR2);
  333. udelay(10);
  334. dev_err(mcbsp->dev, "Could not write to"
  335. " McBSP%d Register\n", mcbsp->id);
  336. return -2;
  337. }
  338. }
  339. }
  340. return 0;
  341. }
  342. EXPORT_SYMBOL(omap_mcbsp_pollwrite);
  343. int omap_mcbsp_pollread(unsigned int id, u16 *buf)
  344. {
  345. struct omap_mcbsp *mcbsp;
  346. void __iomem *base;
  347. if (!omap_mcbsp_check_valid_id(id)) {
  348. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  349. return -ENODEV;
  350. }
  351. mcbsp = id_to_mcbsp_ptr(id);
  352. base = mcbsp->io_base;
  353. /* if frame sync error - clear the error */
  354. if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
  355. /* clear error */
  356. writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
  357. base + OMAP_MCBSP_REG_SPCR1);
  358. /* resend */
  359. return -1;
  360. } else {
  361. /* wait for recieve confirmation */
  362. int attemps = 0;
  363. while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
  364. if (attemps++ > 1000) {
  365. writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
  366. (~RRST),
  367. base + OMAP_MCBSP_REG_SPCR1);
  368. udelay(10);
  369. writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
  370. (RRST),
  371. base + OMAP_MCBSP_REG_SPCR1);
  372. udelay(10);
  373. dev_err(mcbsp->dev, "Could not read from"
  374. " McBSP%d Register\n", mcbsp->id);
  375. return -2;
  376. }
  377. }
  378. }
  379. *buf = readw(base + OMAP_MCBSP_REG_DRR1);
  380. return 0;
  381. }
  382. EXPORT_SYMBOL(omap_mcbsp_pollread);
  383. /*
  384. * IRQ based word transmission.
  385. */
  386. void omap_mcbsp_xmit_word(unsigned int id, u32 word)
  387. {
  388. struct omap_mcbsp *mcbsp;
  389. void __iomem *io_base;
  390. omap_mcbsp_word_length word_length;
  391. if (!omap_mcbsp_check_valid_id(id)) {
  392. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  393. return;
  394. }
  395. mcbsp = id_to_mcbsp_ptr(id);
  396. io_base = mcbsp->io_base;
  397. word_length = mcbsp->tx_word_length;
  398. wait_for_completion(&mcbsp->tx_irq_completion);
  399. if (word_length > OMAP_MCBSP_WORD_16)
  400. OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
  401. OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
  402. }
  403. EXPORT_SYMBOL(omap_mcbsp_xmit_word);
  404. u32 omap_mcbsp_recv_word(unsigned int id)
  405. {
  406. struct omap_mcbsp *mcbsp;
  407. void __iomem *io_base;
  408. u16 word_lsb, word_msb = 0;
  409. omap_mcbsp_word_length word_length;
  410. if (!omap_mcbsp_check_valid_id(id)) {
  411. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  412. return -ENODEV;
  413. }
  414. mcbsp = id_to_mcbsp_ptr(id);
  415. word_length = mcbsp->rx_word_length;
  416. io_base = mcbsp->io_base;
  417. wait_for_completion(&mcbsp->rx_irq_completion);
  418. if (word_length > OMAP_MCBSP_WORD_16)
  419. word_msb = OMAP_MCBSP_READ(io_base, DRR2);
  420. word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
  421. return (word_lsb | (word_msb << 16));
  422. }
  423. EXPORT_SYMBOL(omap_mcbsp_recv_word);
  424. int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
  425. {
  426. struct omap_mcbsp *mcbsp;
  427. void __iomem *io_base;
  428. omap_mcbsp_word_length tx_word_length;
  429. omap_mcbsp_word_length rx_word_length;
  430. u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
  431. if (!omap_mcbsp_check_valid_id(id)) {
  432. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  433. return -ENODEV;
  434. }
  435. mcbsp = id_to_mcbsp_ptr(id);
  436. io_base = mcbsp->io_base;
  437. tx_word_length = mcbsp->tx_word_length;
  438. rx_word_length = mcbsp->rx_word_length;
  439. if (tx_word_length != rx_word_length)
  440. return -EINVAL;
  441. /* First we wait for the transmitter to be ready */
  442. spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
  443. while (!(spcr2 & XRDY)) {
  444. spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
  445. if (attempts++ > 1000) {
  446. /* We must reset the transmitter */
  447. OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
  448. udelay(10);
  449. OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
  450. udelay(10);
  451. dev_err(mcbsp->dev, "McBSP%d transmitter not "
  452. "ready\n", mcbsp->id);
  453. return -EAGAIN;
  454. }
  455. }
  456. /* Now we can push the data */
  457. if (tx_word_length > OMAP_MCBSP_WORD_16)
  458. OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
  459. OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
  460. /* We wait for the receiver to be ready */
  461. spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
  462. while (!(spcr1 & RRDY)) {
  463. spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
  464. if (attempts++ > 1000) {
  465. /* We must reset the receiver */
  466. OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
  467. udelay(10);
  468. OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
  469. udelay(10);
  470. dev_err(mcbsp->dev, "McBSP%d receiver not "
  471. "ready\n", mcbsp->id);
  472. return -EAGAIN;
  473. }
  474. }
  475. /* Receiver is ready, let's read the dummy data */
  476. if (rx_word_length > OMAP_MCBSP_WORD_16)
  477. word_msb = OMAP_MCBSP_READ(io_base, DRR2);
  478. word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
  479. return 0;
  480. }
  481. EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
  482. int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
  483. {
  484. struct omap_mcbsp *mcbsp;
  485. u32 clock_word = 0;
  486. void __iomem *io_base;
  487. omap_mcbsp_word_length tx_word_length;
  488. omap_mcbsp_word_length rx_word_length;
  489. u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
  490. if (!omap_mcbsp_check_valid_id(id)) {
  491. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  492. return -ENODEV;
  493. }
  494. mcbsp = id_to_mcbsp_ptr(id);
  495. io_base = mcbsp->io_base;
  496. tx_word_length = mcbsp->tx_word_length;
  497. rx_word_length = mcbsp->rx_word_length;
  498. if (tx_word_length != rx_word_length)
  499. return -EINVAL;
  500. /* First we wait for the transmitter to be ready */
  501. spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
  502. while (!(spcr2 & XRDY)) {
  503. spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
  504. if (attempts++ > 1000) {
  505. /* We must reset the transmitter */
  506. OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
  507. udelay(10);
  508. OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
  509. udelay(10);
  510. dev_err(mcbsp->dev, "McBSP%d transmitter not "
  511. "ready\n", mcbsp->id);
  512. return -EAGAIN;
  513. }
  514. }
  515. /* We first need to enable the bus clock */
  516. if (tx_word_length > OMAP_MCBSP_WORD_16)
  517. OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
  518. OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
  519. /* We wait for the receiver to be ready */
  520. spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
  521. while (!(spcr1 & RRDY)) {
  522. spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
  523. if (attempts++ > 1000) {
  524. /* We must reset the receiver */
  525. OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
  526. udelay(10);
  527. OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
  528. udelay(10);
  529. dev_err(mcbsp->dev, "McBSP%d receiver not "
  530. "ready\n", mcbsp->id);
  531. return -EAGAIN;
  532. }
  533. }
  534. /* Receiver is ready, there is something for us */
  535. if (rx_word_length > OMAP_MCBSP_WORD_16)
  536. word_msb = OMAP_MCBSP_READ(io_base, DRR2);
  537. word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
  538. word[0] = (word_lsb | (word_msb << 16));
  539. return 0;
  540. }
  541. EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
  542. /*
  543. * Simple DMA based buffer rx/tx routines.
  544. * Nothing fancy, just a single buffer tx/rx through DMA.
  545. * The DMA resources are released once the transfer is done.
  546. * For anything fancier, you should use your own customized DMA
  547. * routines and callbacks.
  548. */
  549. int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
  550. unsigned int length)
  551. {
  552. struct omap_mcbsp *mcbsp;
  553. int dma_tx_ch;
  554. int src_port = 0;
  555. int dest_port = 0;
  556. int sync_dev = 0;
  557. if (!omap_mcbsp_check_valid_id(id)) {
  558. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  559. return -ENODEV;
  560. }
  561. mcbsp = id_to_mcbsp_ptr(id);
  562. if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
  563. omap_mcbsp_tx_dma_callback,
  564. mcbsp,
  565. &dma_tx_ch)) {
  566. dev_err(mcbsp->dev, " Unable to request DMA channel for "
  567. "McBSP%d TX. Trying IRQ based TX\n",
  568. mcbsp->id);
  569. return -EAGAIN;
  570. }
  571. mcbsp->dma_tx_lch = dma_tx_ch;
  572. dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
  573. dma_tx_ch);
  574. init_completion(&mcbsp->tx_dma_completion);
  575. if (cpu_class_is_omap1()) {
  576. src_port = OMAP_DMA_PORT_TIPB;
  577. dest_port = OMAP_DMA_PORT_EMIFF;
  578. }
  579. if (cpu_class_is_omap2())
  580. sync_dev = mcbsp->dma_tx_sync;
  581. omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
  582. OMAP_DMA_DATA_TYPE_S16,
  583. length >> 1, 1,
  584. OMAP_DMA_SYNC_ELEMENT,
  585. sync_dev, 0);
  586. omap_set_dma_dest_params(mcbsp->dma_tx_lch,
  587. src_port,
  588. OMAP_DMA_AMODE_CONSTANT,
  589. mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
  590. 0, 0);
  591. omap_set_dma_src_params(mcbsp->dma_tx_lch,
  592. dest_port,
  593. OMAP_DMA_AMODE_POST_INC,
  594. buffer,
  595. 0, 0);
  596. omap_start_dma(mcbsp->dma_tx_lch);
  597. wait_for_completion(&mcbsp->tx_dma_completion);
  598. return 0;
  599. }
  600. EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
  601. int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
  602. unsigned int length)
  603. {
  604. struct omap_mcbsp *mcbsp;
  605. int dma_rx_ch;
  606. int src_port = 0;
  607. int dest_port = 0;
  608. int sync_dev = 0;
  609. if (!omap_mcbsp_check_valid_id(id)) {
  610. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  611. return -ENODEV;
  612. }
  613. mcbsp = id_to_mcbsp_ptr(id);
  614. if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
  615. omap_mcbsp_rx_dma_callback,
  616. mcbsp,
  617. &dma_rx_ch)) {
  618. dev_err(mcbsp->dev, "Unable to request DMA channel for "
  619. "McBSP%d RX. Trying IRQ based RX\n",
  620. mcbsp->id);
  621. return -EAGAIN;
  622. }
  623. mcbsp->dma_rx_lch = dma_rx_ch;
  624. dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
  625. dma_rx_ch);
  626. init_completion(&mcbsp->rx_dma_completion);
  627. if (cpu_class_is_omap1()) {
  628. src_port = OMAP_DMA_PORT_TIPB;
  629. dest_port = OMAP_DMA_PORT_EMIFF;
  630. }
  631. if (cpu_class_is_omap2())
  632. sync_dev = mcbsp->dma_rx_sync;
  633. omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
  634. OMAP_DMA_DATA_TYPE_S16,
  635. length >> 1, 1,
  636. OMAP_DMA_SYNC_ELEMENT,
  637. sync_dev, 0);
  638. omap_set_dma_src_params(mcbsp->dma_rx_lch,
  639. src_port,
  640. OMAP_DMA_AMODE_CONSTANT,
  641. mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
  642. 0, 0);
  643. omap_set_dma_dest_params(mcbsp->dma_rx_lch,
  644. dest_port,
  645. OMAP_DMA_AMODE_POST_INC,
  646. buffer,
  647. 0, 0);
  648. omap_start_dma(mcbsp->dma_rx_lch);
  649. wait_for_completion(&mcbsp->rx_dma_completion);
  650. return 0;
  651. }
  652. EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
  653. /*
  654. * SPI wrapper.
  655. * Since SPI setup is much simpler than the generic McBSP one,
  656. * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
  657. * Once this is done, you can call omap_mcbsp_start().
  658. */
  659. void omap_mcbsp_set_spi_mode(unsigned int id,
  660. const struct omap_mcbsp_spi_cfg *spi_cfg)
  661. {
  662. struct omap_mcbsp *mcbsp;
  663. struct omap_mcbsp_reg_cfg mcbsp_cfg;
  664. if (!omap_mcbsp_check_valid_id(id)) {
  665. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  666. return;
  667. }
  668. mcbsp = id_to_mcbsp_ptr(id);
  669. memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
  670. /* SPI has only one frame */
  671. mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
  672. mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
  673. /* Clock stop mode */
  674. if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
  675. mcbsp_cfg.spcr1 |= (1 << 12);
  676. else
  677. mcbsp_cfg.spcr1 |= (3 << 11);
  678. /* Set clock parities */
  679. if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
  680. mcbsp_cfg.pcr0 |= CLKRP;
  681. else
  682. mcbsp_cfg.pcr0 &= ~CLKRP;
  683. if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
  684. mcbsp_cfg.pcr0 &= ~CLKXP;
  685. else
  686. mcbsp_cfg.pcr0 |= CLKXP;
  687. /* Set SCLKME to 0 and CLKSM to 1 */
  688. mcbsp_cfg.pcr0 &= ~SCLKME;
  689. mcbsp_cfg.srgr2 |= CLKSM;
  690. /* Set FSXP */
  691. if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
  692. mcbsp_cfg.pcr0 &= ~FSXP;
  693. else
  694. mcbsp_cfg.pcr0 |= FSXP;
  695. if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
  696. mcbsp_cfg.pcr0 |= CLKXM;
  697. mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
  698. mcbsp_cfg.pcr0 |= FSXM;
  699. mcbsp_cfg.srgr2 &= ~FSGM;
  700. mcbsp_cfg.xcr2 |= XDATDLY(1);
  701. mcbsp_cfg.rcr2 |= RDATDLY(1);
  702. } else {
  703. mcbsp_cfg.pcr0 &= ~CLKXM;
  704. mcbsp_cfg.srgr1 |= CLKGDV(1);
  705. mcbsp_cfg.pcr0 &= ~FSXM;
  706. mcbsp_cfg.xcr2 &= ~XDATDLY(3);
  707. mcbsp_cfg.rcr2 &= ~RDATDLY(3);
  708. }
  709. mcbsp_cfg.xcr2 &= ~XPHASE;
  710. mcbsp_cfg.rcr2 &= ~RPHASE;
  711. omap_mcbsp_config(id, &mcbsp_cfg);
  712. }
  713. EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
  714. /*
  715. * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  716. * 730 has only 2 McBSP, and both of them are MPU peripherals.
  717. */
  718. static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
  719. {
  720. struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
  721. struct omap_mcbsp *mcbsp;
  722. int id = pdev->id - 1;
  723. int ret = 0;
  724. if (!pdata) {
  725. dev_err(&pdev->dev, "McBSP device initialized without"
  726. "platform data\n");
  727. ret = -EINVAL;
  728. goto exit;
  729. }
  730. dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
  731. if (id >= omap_mcbsp_count) {
  732. dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
  733. ret = -EINVAL;
  734. goto exit;
  735. }
  736. mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
  737. if (!mcbsp) {
  738. ret = -ENOMEM;
  739. goto exit;
  740. }
  741. mcbsp_ptr[id] = mcbsp;
  742. spin_lock_init(&mcbsp->lock);
  743. mcbsp->id = id + 1;
  744. mcbsp->free = 1;
  745. mcbsp->dma_tx_lch = -1;
  746. mcbsp->dma_rx_lch = -1;
  747. mcbsp->phys_base = pdata->phys_base;
  748. mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
  749. if (!mcbsp->io_base) {
  750. ret = -ENOMEM;
  751. goto err_ioremap;
  752. }
  753. /* Default I/O is IRQ based */
  754. mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
  755. mcbsp->tx_irq = pdata->tx_irq;
  756. mcbsp->rx_irq = pdata->rx_irq;
  757. mcbsp->dma_rx_sync = pdata->dma_rx_sync;
  758. mcbsp->dma_tx_sync = pdata->dma_tx_sync;
  759. if (pdata->clk_name)
  760. mcbsp->clk = clk_get(&pdev->dev, pdata->clk_name);
  761. if (IS_ERR(mcbsp->clk)) {
  762. dev_err(&pdev->dev,
  763. "Invalid clock configuration for McBSP%d.\n",
  764. mcbsp->id);
  765. ret = PTR_ERR(mcbsp->clk);
  766. goto err_clk;
  767. }
  768. mcbsp->pdata = pdata;
  769. mcbsp->dev = &pdev->dev;
  770. platform_set_drvdata(pdev, mcbsp);
  771. return 0;
  772. err_clk:
  773. iounmap(mcbsp->io_base);
  774. err_ioremap:
  775. mcbsp->free = 0;
  776. exit:
  777. return ret;
  778. }
  779. static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
  780. {
  781. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  782. platform_set_drvdata(pdev, NULL);
  783. if (mcbsp) {
  784. if (mcbsp->pdata && mcbsp->pdata->ops &&
  785. mcbsp->pdata->ops->free)
  786. mcbsp->pdata->ops->free(mcbsp->id);
  787. clk_disable(mcbsp->clk);
  788. clk_put(mcbsp->clk);
  789. iounmap(mcbsp->io_base);
  790. mcbsp->clk = NULL;
  791. mcbsp->free = 0;
  792. mcbsp->dev = NULL;
  793. }
  794. return 0;
  795. }
  796. static struct platform_driver omap_mcbsp_driver = {
  797. .probe = omap_mcbsp_probe,
  798. .remove = __devexit_p(omap_mcbsp_remove),
  799. .driver = {
  800. .name = "omap-mcbsp",
  801. },
  802. };
  803. int __init omap_mcbsp_init(void)
  804. {
  805. /* Register the McBSP driver */
  806. return platform_driver_register(&omap_mcbsp_driver);
  807. }