kirkwood.dtsi 4.4 KB

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  1. /include/ "skeleton.dtsi"
  2. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  3. / {
  4. compatible = "marvell,kirkwood";
  5. interrupt-parent = <&intc>;
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. device_type = "cpu";
  11. compatible = "marvell,feroceon";
  12. clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
  13. clock-names = "cpu_clk", "ddrclk", "powersave";
  14. };
  15. };
  16. aliases {
  17. gpio0 = &gpio0;
  18. gpio1 = &gpio1;
  19. };
  20. intc: interrupt-controller {
  21. compatible = "marvell,orion-intc", "marvell,intc";
  22. interrupt-controller;
  23. #interrupt-cells = <1>;
  24. reg = <0xf1020204 0x04>,
  25. <0xf1020214 0x04>;
  26. };
  27. mbus {
  28. compatible = "marvell,kirkwood-mbus", "simple-bus";
  29. #address-cells = <2>;
  30. #size-cells = <1>;
  31. controller = <&mbusc>;
  32. pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
  33. pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
  34. };
  35. ocp@f1000000 {
  36. compatible = "simple-bus";
  37. ranges = <0x00000000 0xf1000000 0x0100000
  38. 0xf4000000 0xf4000000 0x0000400
  39. 0xf5000000 0xf5000000 0x0000400>;
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. mbusc: mbus-controller@20000 {
  43. compatible = "marvell,mbus-controller";
  44. reg = <0x20000 0x80>, <0x1500 0x20>;
  45. };
  46. core_clk: core-clocks@10030 {
  47. compatible = "marvell,kirkwood-core-clock";
  48. reg = <0x10030 0x4>;
  49. #clock-cells = <1>;
  50. };
  51. gpio0: gpio@10100 {
  52. compatible = "marvell,orion-gpio";
  53. #gpio-cells = <2>;
  54. gpio-controller;
  55. reg = <0x10100 0x40>;
  56. ngpios = <32>;
  57. interrupt-controller;
  58. #interrupt-cells = <2>;
  59. interrupts = <35>, <36>, <37>, <38>;
  60. clocks = <&gate_clk 7>;
  61. };
  62. gpio1: gpio@10140 {
  63. compatible = "marvell,orion-gpio";
  64. #gpio-cells = <2>;
  65. gpio-controller;
  66. reg = <0x10140 0x40>;
  67. ngpios = <18>;
  68. interrupt-controller;
  69. #interrupt-cells = <2>;
  70. interrupts = <39>, <40>, <41>;
  71. clocks = <&gate_clk 7>;
  72. };
  73. serial@12000 {
  74. compatible = "ns16550a";
  75. reg = <0x12000 0x100>;
  76. reg-shift = <2>;
  77. interrupts = <33>;
  78. clocks = <&gate_clk 7>;
  79. status = "disabled";
  80. };
  81. serial@12100 {
  82. compatible = "ns16550a";
  83. reg = <0x12100 0x100>;
  84. reg-shift = <2>;
  85. interrupts = <34>;
  86. clocks = <&gate_clk 7>;
  87. status = "disabled";
  88. };
  89. spi@10600 {
  90. compatible = "marvell,orion-spi";
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. cell-index = <0>;
  94. interrupts = <23>;
  95. reg = <0x10600 0x28>;
  96. clocks = <&gate_clk 7>;
  97. status = "disabled";
  98. };
  99. gate_clk: clock-gating-control@2011c {
  100. compatible = "marvell,kirkwood-gating-clock";
  101. reg = <0x2011c 0x4>;
  102. clocks = <&core_clk 0>;
  103. #clock-cells = <1>;
  104. };
  105. wdt@20300 {
  106. compatible = "marvell,orion-wdt";
  107. reg = <0x20300 0x28>;
  108. clocks = <&gate_clk 7>;
  109. status = "okay";
  110. };
  111. xor@60800 {
  112. compatible = "marvell,orion-xor";
  113. reg = <0x60800 0x100
  114. 0x60A00 0x100>;
  115. status = "okay";
  116. clocks = <&gate_clk 8>;
  117. xor00 {
  118. interrupts = <5>;
  119. dmacap,memcpy;
  120. dmacap,xor;
  121. };
  122. xor01 {
  123. interrupts = <6>;
  124. dmacap,memcpy;
  125. dmacap,xor;
  126. dmacap,memset;
  127. };
  128. };
  129. xor@60900 {
  130. compatible = "marvell,orion-xor";
  131. reg = <0x60900 0x100
  132. 0xd0B00 0x100>;
  133. status = "okay";
  134. clocks = <&gate_clk 16>;
  135. xor00 {
  136. interrupts = <7>;
  137. dmacap,memcpy;
  138. dmacap,xor;
  139. };
  140. xor01 {
  141. interrupts = <8>;
  142. dmacap,memcpy;
  143. dmacap,xor;
  144. dmacap,memset;
  145. };
  146. };
  147. ehci@50000 {
  148. compatible = "marvell,orion-ehci";
  149. reg = <0x50000 0x1000>;
  150. interrupts = <19>;
  151. clocks = <&gate_clk 3>;
  152. status = "okay";
  153. };
  154. nand@3000000 {
  155. #address-cells = <1>;
  156. #size-cells = <1>;
  157. cle = <0>;
  158. ale = <1>;
  159. bank-width = <1>;
  160. compatible = "marvell,orion-nand";
  161. reg = <0xf4000000 0x400>;
  162. chip-delay = <25>;
  163. /* set partition map and/or chip-delay in board dts */
  164. clocks = <&gate_clk 7>;
  165. status = "disabled";
  166. };
  167. i2c@11000 {
  168. compatible = "marvell,mv64xxx-i2c";
  169. reg = <0x11000 0x20>;
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. interrupts = <29>;
  173. clock-frequency = <100000>;
  174. clocks = <&gate_clk 7>;
  175. status = "disabled";
  176. };
  177. crypto@30000 {
  178. compatible = "marvell,orion-crypto";
  179. reg = <0x30000 0x10000>,
  180. <0xf5000000 0x800>;
  181. reg-names = "regs", "sram";
  182. interrupts = <22>;
  183. clocks = <&gate_clk 17>;
  184. status = "okay";
  185. };
  186. };
  187. };