twl4030.c 64 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. struct snd_pcm_substream *master_substream;
  122. struct snd_pcm_substream *slave_substream;
  123. unsigned int configured;
  124. unsigned int rate;
  125. unsigned int sample_bits;
  126. unsigned int channels;
  127. unsigned int sysclk;
  128. /* Headset output state handling */
  129. unsigned int hsl_enabled;
  130. unsigned int hsr_enabled;
  131. };
  132. /*
  133. * read twl4030 register cache
  134. */
  135. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  136. unsigned int reg)
  137. {
  138. u8 *cache = codec->reg_cache;
  139. if (reg >= TWL4030_CACHEREGNUM)
  140. return -EIO;
  141. return cache[reg];
  142. }
  143. /*
  144. * write twl4030 register cache
  145. */
  146. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  147. u8 reg, u8 value)
  148. {
  149. u8 *cache = codec->reg_cache;
  150. if (reg >= TWL4030_CACHEREGNUM)
  151. return;
  152. cache[reg] = value;
  153. }
  154. /*
  155. * write to the twl4030 register space
  156. */
  157. static int twl4030_write(struct snd_soc_codec *codec,
  158. unsigned int reg, unsigned int value)
  159. {
  160. twl4030_write_reg_cache(codec, reg, value);
  161. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  162. }
  163. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  164. {
  165. struct twl4030_priv *twl4030 = codec->private_data;
  166. u8 mode;
  167. if (enable == twl4030->codec_powered)
  168. return;
  169. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  170. if (enable)
  171. mode |= TWL4030_CODECPDZ;
  172. else
  173. mode &= ~TWL4030_CODECPDZ;
  174. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  175. twl4030->codec_powered = enable;
  176. /* REVISIT: this delay is present in TI sample drivers */
  177. /* but there seems to be no TRM requirement for it */
  178. udelay(10);
  179. }
  180. static void twl4030_init_chip(struct snd_soc_codec *codec)
  181. {
  182. int i;
  183. /* clear CODECPDZ prior to setting register defaults */
  184. twl4030_codec_enable(codec, 0);
  185. /* set all audio section registers to reasonable defaults */
  186. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  187. twl4030_write(codec, i, twl4030_reg[i]);
  188. }
  189. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  190. {
  191. struct twl4030_priv *twl4030 = codec->private_data;
  192. u8 reg_val;
  193. if (mute == twl4030->codec_muted)
  194. return;
  195. if (mute) {
  196. /* Bypass the reg_cache and mute the volumes
  197. * Headset mute is done in it's own event handler
  198. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  199. */
  200. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  201. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. reg_val & (~TWL4030_EAR_GAIN),
  203. TWL4030_REG_EAR_CTL);
  204. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  205. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  206. reg_val & (~TWL4030_PREDL_GAIN),
  207. TWL4030_REG_PREDL_CTL);
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  209. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  210. reg_val & (~TWL4030_PREDR_GAIN),
  211. TWL4030_REG_PREDL_CTL);
  212. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  213. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  214. reg_val & (~TWL4030_PRECKL_GAIN),
  215. TWL4030_REG_PRECKL_CTL);
  216. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  217. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  218. reg_val & (~TWL4030_PRECKR_GAIN),
  219. TWL4030_REG_PRECKR_CTL);
  220. /* Disable PLL */
  221. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  222. reg_val &= ~TWL4030_APLL_EN;
  223. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  224. } else {
  225. /* Restore the volumes
  226. * Headset mute is done in it's own event handler
  227. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  228. */
  229. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  230. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  231. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  232. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  233. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  234. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  235. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  236. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  237. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  238. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  239. /* Enable PLL */
  240. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  241. reg_val |= TWL4030_APLL_EN;
  242. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  243. }
  244. twl4030->codec_muted = mute;
  245. }
  246. static void twl4030_power_up(struct snd_soc_codec *codec)
  247. {
  248. struct twl4030_priv *twl4030 = codec->private_data;
  249. u8 anamicl, regmisc1, byte;
  250. int i = 0;
  251. if (twl4030->codec_powered)
  252. return;
  253. /* set CODECPDZ to turn on codec */
  254. twl4030_codec_enable(codec, 1);
  255. /* initiate offset cancellation */
  256. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  257. twl4030_write(codec, TWL4030_REG_ANAMICL,
  258. anamicl | TWL4030_CNCL_OFFSET_START);
  259. /* wait for offset cancellation to complete */
  260. do {
  261. /* this takes a little while, so don't slam i2c */
  262. udelay(2000);
  263. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  264. TWL4030_REG_ANAMICL);
  265. } while ((i++ < 100) &&
  266. ((byte & TWL4030_CNCL_OFFSET_START) ==
  267. TWL4030_CNCL_OFFSET_START));
  268. /* Make sure that the reg_cache has the same value as the HW */
  269. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  270. /* anti-pop when changing analog gain */
  271. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  272. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  273. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  274. /* toggle CODECPDZ as per TRM */
  275. twl4030_codec_enable(codec, 0);
  276. twl4030_codec_enable(codec, 1);
  277. }
  278. /*
  279. * Unconditional power down
  280. */
  281. static void twl4030_power_down(struct snd_soc_codec *codec)
  282. {
  283. /* power down */
  284. twl4030_codec_enable(codec, 0);
  285. }
  286. /* Earpiece */
  287. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  288. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  289. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  290. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  291. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  292. };
  293. /* PreDrive Left */
  294. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  295. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  296. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  297. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  298. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  299. };
  300. /* PreDrive Right */
  301. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  302. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  303. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  304. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  305. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  306. };
  307. /* Headset Left */
  308. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  309. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  310. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  311. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  312. };
  313. /* Headset Right */
  314. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  315. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  316. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  317. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  318. };
  319. /* Carkit Left */
  320. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  321. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  322. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  323. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  324. };
  325. /* Carkit Right */
  326. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  327. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  328. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  329. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  330. };
  331. /* Handsfree Left */
  332. static const char *twl4030_handsfreel_texts[] =
  333. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  334. static const struct soc_enum twl4030_handsfreel_enum =
  335. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  336. ARRAY_SIZE(twl4030_handsfreel_texts),
  337. twl4030_handsfreel_texts);
  338. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  339. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  340. /* Handsfree Right */
  341. static const char *twl4030_handsfreer_texts[] =
  342. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  343. static const struct soc_enum twl4030_handsfreer_enum =
  344. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  345. ARRAY_SIZE(twl4030_handsfreer_texts),
  346. twl4030_handsfreer_texts);
  347. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  348. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  349. /* Vibra */
  350. /* Vibra audio path selection */
  351. static const char *twl4030_vibra_texts[] =
  352. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  353. static const struct soc_enum twl4030_vibra_enum =
  354. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  355. ARRAY_SIZE(twl4030_vibra_texts),
  356. twl4030_vibra_texts);
  357. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  358. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  359. /* Vibra path selection: local vibrator (PWM) or audio driven */
  360. static const char *twl4030_vibrapath_texts[] =
  361. {"Local vibrator", "Audio"};
  362. static const struct soc_enum twl4030_vibrapath_enum =
  363. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  364. ARRAY_SIZE(twl4030_vibrapath_texts),
  365. twl4030_vibrapath_texts);
  366. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  367. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  368. /* Left analog microphone selection */
  369. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  370. SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
  371. SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
  372. SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
  373. SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
  374. };
  375. /* Right analog microphone selection */
  376. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  377. SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
  378. SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
  379. };
  380. /* TX1 L/R Analog/Digital microphone selection */
  381. static const char *twl4030_micpathtx1_texts[] =
  382. {"Analog", "Digimic0"};
  383. static const struct soc_enum twl4030_micpathtx1_enum =
  384. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  385. ARRAY_SIZE(twl4030_micpathtx1_texts),
  386. twl4030_micpathtx1_texts);
  387. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  388. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  389. /* TX2 L/R Analog/Digital microphone selection */
  390. static const char *twl4030_micpathtx2_texts[] =
  391. {"Analog", "Digimic1"};
  392. static const struct soc_enum twl4030_micpathtx2_enum =
  393. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  394. ARRAY_SIZE(twl4030_micpathtx2_texts),
  395. twl4030_micpathtx2_texts);
  396. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  397. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  398. /* Analog bypass for AudioR1 */
  399. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  400. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  401. /* Analog bypass for AudioL1 */
  402. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  403. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  404. /* Analog bypass for AudioR2 */
  405. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  406. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  407. /* Analog bypass for AudioL2 */
  408. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  409. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  410. /* Analog bypass for Voice */
  411. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  412. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  413. /* Digital bypass gain, 0 mutes the bypass */
  414. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  415. TLV_DB_RANGE_HEAD(2),
  416. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  417. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  418. };
  419. /* Digital bypass left (TX1L -> RX2L) */
  420. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  421. SOC_DAPM_SINGLE_TLV("Volume",
  422. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  423. twl4030_dapm_dbypass_tlv);
  424. /* Digital bypass right (TX1R -> RX2R) */
  425. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  426. SOC_DAPM_SINGLE_TLV("Volume",
  427. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  428. twl4030_dapm_dbypass_tlv);
  429. /*
  430. * Voice Sidetone GAIN volume control:
  431. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  432. */
  433. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  434. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  435. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  436. SOC_DAPM_SINGLE_TLV("Volume",
  437. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  438. twl4030_dapm_dbypassv_tlv);
  439. static int micpath_event(struct snd_soc_dapm_widget *w,
  440. struct snd_kcontrol *kcontrol, int event)
  441. {
  442. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  443. unsigned char adcmicsel, micbias_ctl;
  444. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  445. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  446. /* Prepare the bits for the given TX path:
  447. * shift_l == 0: TX1 microphone path
  448. * shift_l == 2: TX2 microphone path */
  449. if (e->shift_l) {
  450. /* TX2 microphone path */
  451. if (adcmicsel & TWL4030_TX2IN_SEL)
  452. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  453. else
  454. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  455. } else {
  456. /* TX1 microphone path */
  457. if (adcmicsel & TWL4030_TX1IN_SEL)
  458. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  459. else
  460. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  461. }
  462. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  463. return 0;
  464. }
  465. static int handsfree_event(struct snd_soc_dapm_widget *w,
  466. struct snd_kcontrol *kcontrol, int event)
  467. {
  468. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  469. unsigned char hs_ctl;
  470. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  471. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  472. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  473. twl4030_write(w->codec, e->reg, hs_ctl);
  474. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  475. twl4030_write(w->codec, e->reg, hs_ctl);
  476. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  477. twl4030_write(w->codec, e->reg, hs_ctl);
  478. } else {
  479. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  480. | TWL4030_HF_CTL_HB_EN);
  481. twl4030_write(w->codec, e->reg, hs_ctl);
  482. }
  483. return 0;
  484. }
  485. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  486. {
  487. unsigned char hs_gain, hs_pop;
  488. struct twl4030_priv *twl4030 = codec->private_data;
  489. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  490. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  491. 8388608, 16777216, 33554432, 67108864};
  492. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  493. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  494. if (ramp) {
  495. /* Headset ramp-up according to the TRM */
  496. hs_pop |= TWL4030_VMID_EN;
  497. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  498. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  499. hs_pop |= TWL4030_RAMP_EN;
  500. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  501. } else {
  502. /* Headset ramp-down _not_ according to
  503. * the TRM, but in a way that it is working */
  504. hs_pop &= ~TWL4030_RAMP_EN;
  505. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  506. /* Wait ramp delay time + 1, so the VMID can settle */
  507. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  508. twl4030->sysclk) + 1);
  509. /* Bypass the reg_cache to mute the headset */
  510. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  511. hs_gain & (~0x0f),
  512. TWL4030_REG_HS_GAIN_SET);
  513. hs_pop &= ~TWL4030_VMID_EN;
  514. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  515. }
  516. }
  517. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  518. struct snd_kcontrol *kcontrol, int event)
  519. {
  520. struct twl4030_priv *twl4030 = w->codec->private_data;
  521. switch (event) {
  522. case SND_SOC_DAPM_POST_PMU:
  523. /* Do the ramp-up only once */
  524. if (!twl4030->hsr_enabled)
  525. headset_ramp(w->codec, 1);
  526. twl4030->hsl_enabled = 1;
  527. break;
  528. case SND_SOC_DAPM_POST_PMD:
  529. /* Do the ramp-down only if both headsetL/R is disabled */
  530. if (!twl4030->hsr_enabled)
  531. headset_ramp(w->codec, 0);
  532. twl4030->hsl_enabled = 0;
  533. break;
  534. }
  535. return 0;
  536. }
  537. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  538. struct snd_kcontrol *kcontrol, int event)
  539. {
  540. struct twl4030_priv *twl4030 = w->codec->private_data;
  541. switch (event) {
  542. case SND_SOC_DAPM_POST_PMU:
  543. /* Do the ramp-up only once */
  544. if (!twl4030->hsl_enabled)
  545. headset_ramp(w->codec, 1);
  546. twl4030->hsr_enabled = 1;
  547. break;
  548. case SND_SOC_DAPM_POST_PMD:
  549. /* Do the ramp-down only if both headsetL/R is disabled */
  550. if (!twl4030->hsl_enabled)
  551. headset_ramp(w->codec, 0);
  552. twl4030->hsr_enabled = 0;
  553. break;
  554. }
  555. return 0;
  556. }
  557. static int bypass_event(struct snd_soc_dapm_widget *w,
  558. struct snd_kcontrol *kcontrol, int event)
  559. {
  560. struct soc_mixer_control *m =
  561. (struct soc_mixer_control *)w->kcontrols->private_value;
  562. struct twl4030_priv *twl4030 = w->codec->private_data;
  563. unsigned char reg, misc;
  564. reg = twl4030_read_reg_cache(w->codec, m->reg);
  565. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  566. /* Analog bypass */
  567. if (reg & (1 << m->shift))
  568. twl4030->bypass_state |=
  569. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  570. else
  571. twl4030->bypass_state &=
  572. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  573. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  574. /* Analog voice bypass */
  575. if (reg & (1 << m->shift))
  576. twl4030->bypass_state |= (1 << 4);
  577. else
  578. twl4030->bypass_state &= ~(1 << 4);
  579. } else if (m->reg == TWL4030_REG_VSTPGA) {
  580. /* Voice digital bypass */
  581. if (reg)
  582. twl4030->bypass_state |= (1 << 5);
  583. else
  584. twl4030->bypass_state &= ~(1 << 5);
  585. } else {
  586. /* Digital bypass */
  587. if (reg & (0x7 << m->shift))
  588. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  589. else
  590. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  591. }
  592. /* Enable master analog loopback mode if any analog switch is enabled*/
  593. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  594. if (twl4030->bypass_state & 0x1F)
  595. misc |= TWL4030_FMLOOP_EN;
  596. else
  597. misc &= ~TWL4030_FMLOOP_EN;
  598. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  599. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  600. if (twl4030->bypass_state)
  601. twl4030_codec_mute(w->codec, 0);
  602. else
  603. twl4030_codec_mute(w->codec, 1);
  604. }
  605. return 0;
  606. }
  607. /*
  608. * Some of the gain controls in TWL (mostly those which are associated with
  609. * the outputs) are implemented in an interesting way:
  610. * 0x0 : Power down (mute)
  611. * 0x1 : 6dB
  612. * 0x2 : 0 dB
  613. * 0x3 : -6 dB
  614. * Inverting not going to help with these.
  615. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  616. */
  617. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  618. xinvert, tlv_array) \
  619. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  620. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  621. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  622. .tlv.p = (tlv_array), \
  623. .info = snd_soc_info_volsw, \
  624. .get = snd_soc_get_volsw_twl4030, \
  625. .put = snd_soc_put_volsw_twl4030, \
  626. .private_value = (unsigned long)&(struct soc_mixer_control) \
  627. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  628. .max = xmax, .invert = xinvert} }
  629. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  630. xinvert, tlv_array) \
  631. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  632. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  633. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  634. .tlv.p = (tlv_array), \
  635. .info = snd_soc_info_volsw_2r, \
  636. .get = snd_soc_get_volsw_r2_twl4030,\
  637. .put = snd_soc_put_volsw_r2_twl4030, \
  638. .private_value = (unsigned long)&(struct soc_mixer_control) \
  639. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  640. .rshift = xshift, .max = xmax, .invert = xinvert} }
  641. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  642. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  643. xinvert, tlv_array)
  644. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  645. struct snd_ctl_elem_value *ucontrol)
  646. {
  647. struct soc_mixer_control *mc =
  648. (struct soc_mixer_control *)kcontrol->private_value;
  649. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  650. unsigned int reg = mc->reg;
  651. unsigned int shift = mc->shift;
  652. unsigned int rshift = mc->rshift;
  653. int max = mc->max;
  654. int mask = (1 << fls(max)) - 1;
  655. ucontrol->value.integer.value[0] =
  656. (snd_soc_read(codec, reg) >> shift) & mask;
  657. if (ucontrol->value.integer.value[0])
  658. ucontrol->value.integer.value[0] =
  659. max + 1 - ucontrol->value.integer.value[0];
  660. if (shift != rshift) {
  661. ucontrol->value.integer.value[1] =
  662. (snd_soc_read(codec, reg) >> rshift) & mask;
  663. if (ucontrol->value.integer.value[1])
  664. ucontrol->value.integer.value[1] =
  665. max + 1 - ucontrol->value.integer.value[1];
  666. }
  667. return 0;
  668. }
  669. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  670. struct snd_ctl_elem_value *ucontrol)
  671. {
  672. struct soc_mixer_control *mc =
  673. (struct soc_mixer_control *)kcontrol->private_value;
  674. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  675. unsigned int reg = mc->reg;
  676. unsigned int shift = mc->shift;
  677. unsigned int rshift = mc->rshift;
  678. int max = mc->max;
  679. int mask = (1 << fls(max)) - 1;
  680. unsigned short val, val2, val_mask;
  681. val = (ucontrol->value.integer.value[0] & mask);
  682. val_mask = mask << shift;
  683. if (val)
  684. val = max + 1 - val;
  685. val = val << shift;
  686. if (shift != rshift) {
  687. val2 = (ucontrol->value.integer.value[1] & mask);
  688. val_mask |= mask << rshift;
  689. if (val2)
  690. val2 = max + 1 - val2;
  691. val |= val2 << rshift;
  692. }
  693. return snd_soc_update_bits(codec, reg, val_mask, val);
  694. }
  695. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  696. struct snd_ctl_elem_value *ucontrol)
  697. {
  698. struct soc_mixer_control *mc =
  699. (struct soc_mixer_control *)kcontrol->private_value;
  700. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  701. unsigned int reg = mc->reg;
  702. unsigned int reg2 = mc->rreg;
  703. unsigned int shift = mc->shift;
  704. int max = mc->max;
  705. int mask = (1<<fls(max))-1;
  706. ucontrol->value.integer.value[0] =
  707. (snd_soc_read(codec, reg) >> shift) & mask;
  708. ucontrol->value.integer.value[1] =
  709. (snd_soc_read(codec, reg2) >> shift) & mask;
  710. if (ucontrol->value.integer.value[0])
  711. ucontrol->value.integer.value[0] =
  712. max + 1 - ucontrol->value.integer.value[0];
  713. if (ucontrol->value.integer.value[1])
  714. ucontrol->value.integer.value[1] =
  715. max + 1 - ucontrol->value.integer.value[1];
  716. return 0;
  717. }
  718. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  719. struct snd_ctl_elem_value *ucontrol)
  720. {
  721. struct soc_mixer_control *mc =
  722. (struct soc_mixer_control *)kcontrol->private_value;
  723. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  724. unsigned int reg = mc->reg;
  725. unsigned int reg2 = mc->rreg;
  726. unsigned int shift = mc->shift;
  727. int max = mc->max;
  728. int mask = (1 << fls(max)) - 1;
  729. int err;
  730. unsigned short val, val2, val_mask;
  731. val_mask = mask << shift;
  732. val = (ucontrol->value.integer.value[0] & mask);
  733. val2 = (ucontrol->value.integer.value[1] & mask);
  734. if (val)
  735. val = max + 1 - val;
  736. if (val2)
  737. val2 = max + 1 - val2;
  738. val = val << shift;
  739. val2 = val2 << shift;
  740. err = snd_soc_update_bits(codec, reg, val_mask, val);
  741. if (err < 0)
  742. return err;
  743. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  744. return err;
  745. }
  746. /* Codec operation modes */
  747. static const char *twl4030_op_modes_texts[] = {
  748. "Option 2 (voice/audio)", "Option 1 (audio)"
  749. };
  750. static const struct soc_enum twl4030_op_modes_enum =
  751. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  752. ARRAY_SIZE(twl4030_op_modes_texts),
  753. twl4030_op_modes_texts);
  754. int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  755. struct snd_ctl_elem_value *ucontrol)
  756. {
  757. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  758. struct twl4030_priv *twl4030 = codec->private_data;
  759. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  760. unsigned short val;
  761. unsigned short mask, bitmask;
  762. if (twl4030->configured) {
  763. printk(KERN_ERR "twl4030 operation mode cannot be "
  764. "changed on-the-fly\n");
  765. return -EBUSY;
  766. }
  767. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  768. ;
  769. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  770. return -EINVAL;
  771. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  772. mask = (bitmask - 1) << e->shift_l;
  773. if (e->shift_l != e->shift_r) {
  774. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  775. return -EINVAL;
  776. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  777. mask |= (bitmask - 1) << e->shift_r;
  778. }
  779. return snd_soc_update_bits(codec, e->reg, mask, val);
  780. }
  781. /*
  782. * FGAIN volume control:
  783. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  784. */
  785. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  786. /*
  787. * CGAIN volume control:
  788. * 0 dB to 12 dB in 6 dB steps
  789. * value 2 and 3 means 12 dB
  790. */
  791. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  792. /*
  793. * Voice Downlink GAIN volume control:
  794. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  795. */
  796. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  797. /*
  798. * Analog playback gain
  799. * -24 dB to 12 dB in 2 dB steps
  800. */
  801. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  802. /*
  803. * Gain controls tied to outputs
  804. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  805. */
  806. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  807. /*
  808. * Gain control for earpiece amplifier
  809. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  810. */
  811. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  812. /*
  813. * Capture gain after the ADCs
  814. * from 0 dB to 31 dB in 1 dB steps
  815. */
  816. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  817. /*
  818. * Gain control for input amplifiers
  819. * 0 dB to 30 dB in 6 dB steps
  820. */
  821. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  822. static const char *twl4030_rampdelay_texts[] = {
  823. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  824. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  825. "3495/2581/1748 ms"
  826. };
  827. static const struct soc_enum twl4030_rampdelay_enum =
  828. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  829. ARRAY_SIZE(twl4030_rampdelay_texts),
  830. twl4030_rampdelay_texts);
  831. /* Vibra H-bridge direction mode */
  832. static const char *twl4030_vibradirmode_texts[] = {
  833. "Vibra H-bridge direction", "Audio data MSB",
  834. };
  835. static const struct soc_enum twl4030_vibradirmode_enum =
  836. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  837. ARRAY_SIZE(twl4030_vibradirmode_texts),
  838. twl4030_vibradirmode_texts);
  839. /* Vibra H-bridge direction */
  840. static const char *twl4030_vibradir_texts[] = {
  841. "Positive polarity", "Negative polarity",
  842. };
  843. static const struct soc_enum twl4030_vibradir_enum =
  844. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  845. ARRAY_SIZE(twl4030_vibradir_texts),
  846. twl4030_vibradir_texts);
  847. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  848. /* Codec operation mode control */
  849. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  850. snd_soc_get_enum_double,
  851. snd_soc_put_twl4030_opmode_enum_double),
  852. /* Common playback gain controls */
  853. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  854. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  855. 0, 0x3f, 0, digital_fine_tlv),
  856. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  857. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  858. 0, 0x3f, 0, digital_fine_tlv),
  859. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  860. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  861. 6, 0x2, 0, digital_coarse_tlv),
  862. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  863. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  864. 6, 0x2, 0, digital_coarse_tlv),
  865. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  866. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  867. 3, 0x12, 1, analog_tlv),
  868. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  869. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  870. 3, 0x12, 1, analog_tlv),
  871. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  872. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  873. 1, 1, 0),
  874. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  875. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  876. 1, 1, 0),
  877. /* Common voice downlink gain controls */
  878. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  879. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  880. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  881. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  882. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  883. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  884. /* Separate output gain controls */
  885. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  886. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  887. 4, 3, 0, output_tvl),
  888. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  889. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  890. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  891. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  892. 4, 3, 0, output_tvl),
  893. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  894. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  895. /* Common capture gain controls */
  896. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  897. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  898. 0, 0x1f, 0, digital_capture_tlv),
  899. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  900. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  901. 0, 0x1f, 0, digital_capture_tlv),
  902. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  903. 0, 3, 5, 0, input_gain_tlv),
  904. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  905. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  906. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  907. };
  908. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  909. /* Left channel inputs */
  910. SND_SOC_DAPM_INPUT("MAINMIC"),
  911. SND_SOC_DAPM_INPUT("HSMIC"),
  912. SND_SOC_DAPM_INPUT("AUXL"),
  913. SND_SOC_DAPM_INPUT("CARKITMIC"),
  914. /* Right channel inputs */
  915. SND_SOC_DAPM_INPUT("SUBMIC"),
  916. SND_SOC_DAPM_INPUT("AUXR"),
  917. /* Digital microphones (Stereo) */
  918. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  919. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  920. /* Outputs */
  921. SND_SOC_DAPM_OUTPUT("OUTL"),
  922. SND_SOC_DAPM_OUTPUT("OUTR"),
  923. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  924. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  925. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  926. SND_SOC_DAPM_OUTPUT("HSOL"),
  927. SND_SOC_DAPM_OUTPUT("HSOR"),
  928. SND_SOC_DAPM_OUTPUT("CARKITL"),
  929. SND_SOC_DAPM_OUTPUT("CARKITR"),
  930. SND_SOC_DAPM_OUTPUT("HFL"),
  931. SND_SOC_DAPM_OUTPUT("HFR"),
  932. SND_SOC_DAPM_OUTPUT("VIBRA"),
  933. /* DACs */
  934. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  935. SND_SOC_NOPM, 0, 0),
  936. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  937. SND_SOC_NOPM, 0, 0),
  938. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  939. SND_SOC_NOPM, 0, 0),
  940. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  941. SND_SOC_NOPM, 0, 0),
  942. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  943. SND_SOC_NOPM, 0, 0),
  944. /* Analog bypasses */
  945. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  946. &twl4030_dapm_abypassr1_control, bypass_event,
  947. SND_SOC_DAPM_POST_REG),
  948. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  949. &twl4030_dapm_abypassl1_control,
  950. bypass_event, SND_SOC_DAPM_POST_REG),
  951. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  952. &twl4030_dapm_abypassr2_control,
  953. bypass_event, SND_SOC_DAPM_POST_REG),
  954. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  955. &twl4030_dapm_abypassl2_control,
  956. bypass_event, SND_SOC_DAPM_POST_REG),
  957. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  958. &twl4030_dapm_abypassv_control,
  959. bypass_event, SND_SOC_DAPM_POST_REG),
  960. /* Digital bypasses */
  961. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  962. &twl4030_dapm_dbypassl_control, bypass_event,
  963. SND_SOC_DAPM_POST_REG),
  964. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  965. &twl4030_dapm_dbypassr_control, bypass_event,
  966. SND_SOC_DAPM_POST_REG),
  967. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  968. &twl4030_dapm_dbypassv_control, bypass_event,
  969. SND_SOC_DAPM_POST_REG),
  970. /* Digital mixers, power control for the physical DACs */
  971. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  972. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  973. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  974. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  975. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  976. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  977. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  978. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  979. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  980. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  981. /* Analog mixers, power control for the physical PGAs */
  982. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  983. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  984. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  985. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  986. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  987. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  988. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  989. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  990. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  991. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  992. /* Output MIXER controls */
  993. /* Earpiece */
  994. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  995. &twl4030_dapm_earpiece_controls[0],
  996. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  997. /* PreDrivL/R */
  998. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  999. &twl4030_dapm_predrivel_controls[0],
  1000. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1001. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1002. &twl4030_dapm_predriver_controls[0],
  1003. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1004. /* HeadsetL/R */
  1005. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1006. &twl4030_dapm_hsol_controls[0],
  1007. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1008. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1009. 0, 0, NULL, 0, headsetlpga_event,
  1010. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1011. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1012. &twl4030_dapm_hsor_controls[0],
  1013. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1014. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1015. 0, 0, NULL, 0, headsetrpga_event,
  1016. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1017. /* CarkitL/R */
  1018. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1019. &twl4030_dapm_carkitl_controls[0],
  1020. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1021. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1022. &twl4030_dapm_carkitr_controls[0],
  1023. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1024. /* Output MUX controls */
  1025. /* HandsfreeL/R */
  1026. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  1027. &twl4030_dapm_handsfreel_control, handsfree_event,
  1028. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1029. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  1030. &twl4030_dapm_handsfreer_control, handsfree_event,
  1031. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1032. /* Vibra */
  1033. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1034. &twl4030_dapm_vibra_control),
  1035. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1036. &twl4030_dapm_vibrapath_control),
  1037. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1038. capture */
  1039. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1040. SND_SOC_NOPM, 0, 0),
  1041. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1042. SND_SOC_NOPM, 0, 0),
  1043. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1044. SND_SOC_NOPM, 0, 0),
  1045. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1046. SND_SOC_NOPM, 0, 0),
  1047. /* Analog/Digital mic path selection.
  1048. TX1 Left/Right: either analog Left/Right or Digimic0
  1049. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1050. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1051. &twl4030_dapm_micpathtx1_control, micpath_event,
  1052. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1053. SND_SOC_DAPM_POST_REG),
  1054. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1055. &twl4030_dapm_micpathtx2_control, micpath_event,
  1056. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1057. SND_SOC_DAPM_POST_REG),
  1058. /* Analog input mixers for the capture amplifiers */
  1059. SND_SOC_DAPM_MIXER("Analog Left Capture Route",
  1060. TWL4030_REG_ANAMICL, 4, 0,
  1061. &twl4030_dapm_analoglmic_controls[0],
  1062. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1063. SND_SOC_DAPM_MIXER("Analog Right Capture Route",
  1064. TWL4030_REG_ANAMICR, 4, 0,
  1065. &twl4030_dapm_analogrmic_controls[0],
  1066. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1067. SND_SOC_DAPM_PGA("ADC Physical Left",
  1068. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1069. SND_SOC_DAPM_PGA("ADC Physical Right",
  1070. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1071. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1072. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1073. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1074. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1075. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1076. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1077. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1078. };
  1079. static const struct snd_soc_dapm_route intercon[] = {
  1080. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1081. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1082. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1083. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1084. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1085. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1086. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1087. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1088. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1089. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1090. /* Internal playback routings */
  1091. /* Earpiece */
  1092. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1093. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1094. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1095. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1096. /* PreDrivL */
  1097. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1098. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1099. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1100. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1101. /* PreDrivR */
  1102. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1103. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1104. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1105. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1106. /* HeadsetL */
  1107. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1108. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1109. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1110. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1111. /* HeadsetR */
  1112. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1113. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1114. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1115. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1116. /* CarkitL */
  1117. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1118. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1119. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1120. /* CarkitR */
  1121. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1122. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1123. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1124. /* HandsfreeL */
  1125. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1126. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1127. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1128. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1129. /* HandsfreeR */
  1130. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1131. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1132. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1133. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1134. /* Vibra */
  1135. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1136. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1137. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1138. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1139. /* outputs */
  1140. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1141. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1142. {"EARPIECE", NULL, "Earpiece Mixer"},
  1143. {"PREDRIVEL", NULL, "PredriveL Mixer"},
  1144. {"PREDRIVER", NULL, "PredriveR Mixer"},
  1145. {"HSOL", NULL, "HeadsetL PGA"},
  1146. {"HSOR", NULL, "HeadsetR PGA"},
  1147. {"CARKITL", NULL, "CarkitL Mixer"},
  1148. {"CARKITR", NULL, "CarkitR Mixer"},
  1149. {"HFL", NULL, "HandsfreeL Mux"},
  1150. {"HFR", NULL, "HandsfreeR Mux"},
  1151. {"Vibra Route", "Audio", "Vibra Mux"},
  1152. {"VIBRA", NULL, "Vibra Route"},
  1153. /* Capture path */
  1154. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  1155. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  1156. {"Analog Left Capture Route", "AUXL", "AUXL"},
  1157. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  1158. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  1159. {"Analog Right Capture Route", "AUXR", "AUXR"},
  1160. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  1161. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  1162. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1163. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1164. /* TX1 Left capture path */
  1165. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1166. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1167. /* TX1 Right capture path */
  1168. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1169. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1170. /* TX2 Left capture path */
  1171. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1172. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1173. /* TX2 Right capture path */
  1174. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1175. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1176. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1177. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1178. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1179. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1180. /* Analog bypass routes */
  1181. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1182. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1183. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1184. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1185. {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
  1186. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1187. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1188. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1189. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1190. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1191. /* Digital bypass routes */
  1192. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1193. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1194. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1195. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1196. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1197. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1198. };
  1199. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1200. {
  1201. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1202. ARRAY_SIZE(twl4030_dapm_widgets));
  1203. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1204. snd_soc_dapm_new_widgets(codec);
  1205. return 0;
  1206. }
  1207. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1208. enum snd_soc_bias_level level)
  1209. {
  1210. struct twl4030_priv *twl4030 = codec->private_data;
  1211. switch (level) {
  1212. case SND_SOC_BIAS_ON:
  1213. twl4030_codec_mute(codec, 0);
  1214. break;
  1215. case SND_SOC_BIAS_PREPARE:
  1216. twl4030_power_up(codec);
  1217. if (twl4030->bypass_state)
  1218. twl4030_codec_mute(codec, 0);
  1219. else
  1220. twl4030_codec_mute(codec, 1);
  1221. break;
  1222. case SND_SOC_BIAS_STANDBY:
  1223. twl4030_power_up(codec);
  1224. if (twl4030->bypass_state)
  1225. twl4030_codec_mute(codec, 0);
  1226. else
  1227. twl4030_codec_mute(codec, 1);
  1228. break;
  1229. case SND_SOC_BIAS_OFF:
  1230. twl4030_power_down(codec);
  1231. break;
  1232. }
  1233. codec->bias_level = level;
  1234. return 0;
  1235. }
  1236. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1237. struct snd_pcm_substream *mst_substream)
  1238. {
  1239. struct snd_pcm_substream *slv_substream;
  1240. /* Pick the stream, which need to be constrained */
  1241. if (mst_substream == twl4030->master_substream)
  1242. slv_substream = twl4030->slave_substream;
  1243. else if (mst_substream == twl4030->slave_substream)
  1244. slv_substream = twl4030->master_substream;
  1245. else /* This should not happen.. */
  1246. return;
  1247. /* Set the constraints according to the already configured stream */
  1248. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1249. SNDRV_PCM_HW_PARAM_RATE,
  1250. twl4030->rate,
  1251. twl4030->rate);
  1252. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1253. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1254. twl4030->sample_bits,
  1255. twl4030->sample_bits);
  1256. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1257. SNDRV_PCM_HW_PARAM_CHANNELS,
  1258. twl4030->channels,
  1259. twl4030->channels);
  1260. }
  1261. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1262. * capture has to be enabled/disabled. */
  1263. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1264. int enable)
  1265. {
  1266. u8 reg, mask;
  1267. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1268. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1269. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1270. else
  1271. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1272. if (enable)
  1273. reg |= mask;
  1274. else
  1275. reg &= ~mask;
  1276. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1277. }
  1278. static int twl4030_startup(struct snd_pcm_substream *substream,
  1279. struct snd_soc_dai *dai)
  1280. {
  1281. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1282. struct snd_soc_device *socdev = rtd->socdev;
  1283. struct snd_soc_codec *codec = socdev->card->codec;
  1284. struct twl4030_priv *twl4030 = codec->private_data;
  1285. if (twl4030->master_substream) {
  1286. twl4030->slave_substream = substream;
  1287. /* The DAI has one configuration for playback and capture, so
  1288. * if the DAI has been already configured then constrain this
  1289. * substream to match it. */
  1290. if (twl4030->configured)
  1291. twl4030_constraints(twl4030, twl4030->master_substream);
  1292. } else {
  1293. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1294. TWL4030_OPTION_1)) {
  1295. /* In option2 4 channel is not supported, set the
  1296. * constraint for the first stream for channels, the
  1297. * second stream will 'inherit' this cosntraint */
  1298. snd_pcm_hw_constraint_minmax(substream->runtime,
  1299. SNDRV_PCM_HW_PARAM_CHANNELS,
  1300. 2, 2);
  1301. }
  1302. twl4030->master_substream = substream;
  1303. }
  1304. return 0;
  1305. }
  1306. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1307. struct snd_soc_dai *dai)
  1308. {
  1309. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1310. struct snd_soc_device *socdev = rtd->socdev;
  1311. struct snd_soc_codec *codec = socdev->card->codec;
  1312. struct twl4030_priv *twl4030 = codec->private_data;
  1313. if (twl4030->master_substream == substream)
  1314. twl4030->master_substream = twl4030->slave_substream;
  1315. twl4030->slave_substream = NULL;
  1316. /* If all streams are closed, or the remaining stream has not yet
  1317. * been configured than set the DAI as not configured. */
  1318. if (!twl4030->master_substream)
  1319. twl4030->configured = 0;
  1320. else if (!twl4030->master_substream->runtime->channels)
  1321. twl4030->configured = 0;
  1322. /* If the closing substream had 4 channel, do the necessary cleanup */
  1323. if (substream->runtime->channels == 4)
  1324. twl4030_tdm_enable(codec, substream->stream, 0);
  1325. }
  1326. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1327. struct snd_pcm_hw_params *params,
  1328. struct snd_soc_dai *dai)
  1329. {
  1330. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1331. struct snd_soc_device *socdev = rtd->socdev;
  1332. struct snd_soc_codec *codec = socdev->card->codec;
  1333. struct twl4030_priv *twl4030 = codec->private_data;
  1334. u8 mode, old_mode, format, old_format;
  1335. /* If the substream has 4 channel, do the necessary setup */
  1336. if (params_channels(params) == 4) {
  1337. /* Safety check: are we in the correct operating mode? */
  1338. if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1339. TWL4030_OPTION_1))
  1340. twl4030_tdm_enable(codec, substream->stream, 1);
  1341. else
  1342. return -EINVAL;
  1343. }
  1344. if (twl4030->configured)
  1345. /* Ignoring hw_params for already configured DAI */
  1346. return 0;
  1347. /* bit rate */
  1348. old_mode = twl4030_read_reg_cache(codec,
  1349. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1350. mode = old_mode & ~TWL4030_APLL_RATE;
  1351. switch (params_rate(params)) {
  1352. case 8000:
  1353. mode |= TWL4030_APLL_RATE_8000;
  1354. break;
  1355. case 11025:
  1356. mode |= TWL4030_APLL_RATE_11025;
  1357. break;
  1358. case 12000:
  1359. mode |= TWL4030_APLL_RATE_12000;
  1360. break;
  1361. case 16000:
  1362. mode |= TWL4030_APLL_RATE_16000;
  1363. break;
  1364. case 22050:
  1365. mode |= TWL4030_APLL_RATE_22050;
  1366. break;
  1367. case 24000:
  1368. mode |= TWL4030_APLL_RATE_24000;
  1369. break;
  1370. case 32000:
  1371. mode |= TWL4030_APLL_RATE_32000;
  1372. break;
  1373. case 44100:
  1374. mode |= TWL4030_APLL_RATE_44100;
  1375. break;
  1376. case 48000:
  1377. mode |= TWL4030_APLL_RATE_48000;
  1378. break;
  1379. case 96000:
  1380. mode |= TWL4030_APLL_RATE_96000;
  1381. break;
  1382. default:
  1383. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1384. params_rate(params));
  1385. return -EINVAL;
  1386. }
  1387. if (mode != old_mode) {
  1388. /* change rate and set CODECPDZ */
  1389. twl4030_codec_enable(codec, 0);
  1390. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1391. twl4030_codec_enable(codec, 1);
  1392. }
  1393. /* sample size */
  1394. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1395. format = old_format;
  1396. format &= ~TWL4030_DATA_WIDTH;
  1397. switch (params_format(params)) {
  1398. case SNDRV_PCM_FORMAT_S16_LE:
  1399. format |= TWL4030_DATA_WIDTH_16S_16W;
  1400. break;
  1401. case SNDRV_PCM_FORMAT_S24_LE:
  1402. format |= TWL4030_DATA_WIDTH_32S_24W;
  1403. break;
  1404. default:
  1405. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1406. params_format(params));
  1407. return -EINVAL;
  1408. }
  1409. if (format != old_format) {
  1410. /* clear CODECPDZ before changing format (codec requirement) */
  1411. twl4030_codec_enable(codec, 0);
  1412. /* change format */
  1413. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1414. /* set CODECPDZ afterwards */
  1415. twl4030_codec_enable(codec, 1);
  1416. }
  1417. /* Store the important parameters for the DAI configuration and set
  1418. * the DAI as configured */
  1419. twl4030->configured = 1;
  1420. twl4030->rate = params_rate(params);
  1421. twl4030->sample_bits = hw_param_interval(params,
  1422. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1423. twl4030->channels = params_channels(params);
  1424. /* If both playback and capture streams are open, and one of them
  1425. * is setting the hw parameters right now (since we are here), set
  1426. * constraints to the other stream to match the current one. */
  1427. if (twl4030->slave_substream)
  1428. twl4030_constraints(twl4030, substream);
  1429. return 0;
  1430. }
  1431. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1432. int clk_id, unsigned int freq, int dir)
  1433. {
  1434. struct snd_soc_codec *codec = codec_dai->codec;
  1435. struct twl4030_priv *twl4030 = codec->private_data;
  1436. u8 infreq;
  1437. switch (freq) {
  1438. case 19200000:
  1439. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1440. twl4030->sysclk = 19200;
  1441. break;
  1442. case 26000000:
  1443. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1444. twl4030->sysclk = 26000;
  1445. break;
  1446. case 38400000:
  1447. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1448. twl4030->sysclk = 38400;
  1449. break;
  1450. default:
  1451. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1452. freq);
  1453. return -EINVAL;
  1454. }
  1455. infreq |= TWL4030_APLL_EN;
  1456. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1457. return 0;
  1458. }
  1459. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1460. unsigned int fmt)
  1461. {
  1462. struct snd_soc_codec *codec = codec_dai->codec;
  1463. u8 old_format, format;
  1464. /* get format */
  1465. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1466. format = old_format;
  1467. /* set master/slave audio interface */
  1468. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1469. case SND_SOC_DAIFMT_CBM_CFM:
  1470. format &= ~(TWL4030_AIF_SLAVE_EN);
  1471. format &= ~(TWL4030_CLK256FS_EN);
  1472. break;
  1473. case SND_SOC_DAIFMT_CBS_CFS:
  1474. format |= TWL4030_AIF_SLAVE_EN;
  1475. format |= TWL4030_CLK256FS_EN;
  1476. break;
  1477. default:
  1478. return -EINVAL;
  1479. }
  1480. /* interface format */
  1481. format &= ~TWL4030_AIF_FORMAT;
  1482. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1483. case SND_SOC_DAIFMT_I2S:
  1484. format |= TWL4030_AIF_FORMAT_CODEC;
  1485. break;
  1486. case SND_SOC_DAIFMT_DSP_A:
  1487. format |= TWL4030_AIF_FORMAT_TDM;
  1488. break;
  1489. default:
  1490. return -EINVAL;
  1491. }
  1492. if (format != old_format) {
  1493. /* clear CODECPDZ before changing format (codec requirement) */
  1494. twl4030_codec_enable(codec, 0);
  1495. /* change format */
  1496. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1497. /* set CODECPDZ afterwards */
  1498. twl4030_codec_enable(codec, 1);
  1499. }
  1500. return 0;
  1501. }
  1502. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1503. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1504. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1505. int enable)
  1506. {
  1507. u8 reg, mask;
  1508. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1509. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1510. mask = TWL4030_ARXL1_VRX_EN;
  1511. else
  1512. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1513. if (enable)
  1514. reg |= mask;
  1515. else
  1516. reg &= ~mask;
  1517. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1518. }
  1519. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1520. struct snd_soc_dai *dai)
  1521. {
  1522. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1523. struct snd_soc_device *socdev = rtd->socdev;
  1524. struct snd_soc_codec *codec = socdev->card->codec;
  1525. u8 infreq;
  1526. u8 mode;
  1527. /* If the system master clock is not 26MHz, the voice PCM interface is
  1528. * not avilable.
  1529. */
  1530. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1531. & TWL4030_APLL_INFREQ;
  1532. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1533. printk(KERN_ERR "TWL4030 voice startup: "
  1534. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1535. return -EINVAL;
  1536. }
  1537. /* If the codec mode is not option2, the voice PCM interface is not
  1538. * avilable.
  1539. */
  1540. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1541. & TWL4030_OPT_MODE;
  1542. if (mode != TWL4030_OPTION_2) {
  1543. printk(KERN_ERR "TWL4030 voice startup: "
  1544. "the codec mode is not option2\n");
  1545. return -EINVAL;
  1546. }
  1547. return 0;
  1548. }
  1549. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1550. struct snd_soc_dai *dai)
  1551. {
  1552. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1553. struct snd_soc_device *socdev = rtd->socdev;
  1554. struct snd_soc_codec *codec = socdev->card->codec;
  1555. /* Enable voice digital filters */
  1556. twl4030_voice_enable(codec, substream->stream, 0);
  1557. }
  1558. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1559. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1560. {
  1561. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1562. struct snd_soc_device *socdev = rtd->socdev;
  1563. struct snd_soc_codec *codec = socdev->card->codec;
  1564. u8 old_mode, mode;
  1565. /* Enable voice digital filters */
  1566. twl4030_voice_enable(codec, substream->stream, 1);
  1567. /* bit rate */
  1568. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1569. & ~(TWL4030_CODECPDZ);
  1570. mode = old_mode;
  1571. switch (params_rate(params)) {
  1572. case 8000:
  1573. mode &= ~(TWL4030_SEL_16K);
  1574. break;
  1575. case 16000:
  1576. mode |= TWL4030_SEL_16K;
  1577. break;
  1578. default:
  1579. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1580. params_rate(params));
  1581. return -EINVAL;
  1582. }
  1583. if (mode != old_mode) {
  1584. /* change rate and set CODECPDZ */
  1585. twl4030_codec_enable(codec, 0);
  1586. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1587. twl4030_codec_enable(codec, 1);
  1588. }
  1589. return 0;
  1590. }
  1591. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1592. int clk_id, unsigned int freq, int dir)
  1593. {
  1594. struct snd_soc_codec *codec = codec_dai->codec;
  1595. u8 infreq;
  1596. switch (freq) {
  1597. case 26000000:
  1598. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1599. break;
  1600. default:
  1601. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1602. freq);
  1603. return -EINVAL;
  1604. }
  1605. infreq |= TWL4030_APLL_EN;
  1606. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1607. return 0;
  1608. }
  1609. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1610. unsigned int fmt)
  1611. {
  1612. struct snd_soc_codec *codec = codec_dai->codec;
  1613. u8 old_format, format;
  1614. /* get format */
  1615. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1616. format = old_format;
  1617. /* set master/slave audio interface */
  1618. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1619. case SND_SOC_DAIFMT_CBS_CFM:
  1620. format &= ~(TWL4030_VIF_SLAVE_EN);
  1621. break;
  1622. case SND_SOC_DAIFMT_CBS_CFS:
  1623. format |= TWL4030_VIF_SLAVE_EN;
  1624. break;
  1625. default:
  1626. return -EINVAL;
  1627. }
  1628. /* clock inversion */
  1629. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1630. case SND_SOC_DAIFMT_IB_NF:
  1631. format &= ~(TWL4030_VIF_FORMAT);
  1632. break;
  1633. case SND_SOC_DAIFMT_NB_IF:
  1634. format |= TWL4030_VIF_FORMAT;
  1635. break;
  1636. default:
  1637. return -EINVAL;
  1638. }
  1639. if (format != old_format) {
  1640. /* change format and set CODECPDZ */
  1641. twl4030_codec_enable(codec, 0);
  1642. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1643. twl4030_codec_enable(codec, 1);
  1644. }
  1645. return 0;
  1646. }
  1647. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1648. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1649. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1650. .startup = twl4030_startup,
  1651. .shutdown = twl4030_shutdown,
  1652. .hw_params = twl4030_hw_params,
  1653. .set_sysclk = twl4030_set_dai_sysclk,
  1654. .set_fmt = twl4030_set_dai_fmt,
  1655. };
  1656. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1657. .startup = twl4030_voice_startup,
  1658. .shutdown = twl4030_voice_shutdown,
  1659. .hw_params = twl4030_voice_hw_params,
  1660. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1661. .set_fmt = twl4030_voice_set_dai_fmt,
  1662. };
  1663. struct snd_soc_dai twl4030_dai[] = {
  1664. {
  1665. .name = "twl4030",
  1666. .playback = {
  1667. .stream_name = "HiFi Playback",
  1668. .channels_min = 2,
  1669. .channels_max = 4,
  1670. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1671. .formats = TWL4030_FORMATS,},
  1672. .capture = {
  1673. .stream_name = "Capture",
  1674. .channels_min = 2,
  1675. .channels_max = 4,
  1676. .rates = TWL4030_RATES,
  1677. .formats = TWL4030_FORMATS,},
  1678. .ops = &twl4030_dai_ops,
  1679. },
  1680. {
  1681. .name = "twl4030 Voice",
  1682. .playback = {
  1683. .stream_name = "Voice Playback",
  1684. .channels_min = 1,
  1685. .channels_max = 1,
  1686. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1687. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1688. .capture = {
  1689. .stream_name = "Capture",
  1690. .channels_min = 1,
  1691. .channels_max = 2,
  1692. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1693. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1694. .ops = &twl4030_dai_voice_ops,
  1695. },
  1696. };
  1697. EXPORT_SYMBOL_GPL(twl4030_dai);
  1698. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1699. {
  1700. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1701. struct snd_soc_codec *codec = socdev->card->codec;
  1702. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1703. return 0;
  1704. }
  1705. static int twl4030_resume(struct platform_device *pdev)
  1706. {
  1707. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1708. struct snd_soc_codec *codec = socdev->card->codec;
  1709. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1710. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1711. return 0;
  1712. }
  1713. /*
  1714. * initialize the driver
  1715. * register the mixer and dsp interfaces with the kernel
  1716. */
  1717. static int twl4030_init(struct snd_soc_device *socdev)
  1718. {
  1719. struct snd_soc_codec *codec = socdev->card->codec;
  1720. struct twl4030_setup_data *setup = socdev->codec_data;
  1721. struct twl4030_priv *twl4030 = codec->private_data;
  1722. int ret = 0;
  1723. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1724. codec->name = "twl4030";
  1725. codec->owner = THIS_MODULE;
  1726. codec->read = twl4030_read_reg_cache;
  1727. codec->write = twl4030_write;
  1728. codec->set_bias_level = twl4030_set_bias_level;
  1729. codec->dai = twl4030_dai;
  1730. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1731. codec->reg_cache_size = sizeof(twl4030_reg);
  1732. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1733. GFP_KERNEL);
  1734. if (codec->reg_cache == NULL)
  1735. return -ENOMEM;
  1736. /* Configuration for headset ramp delay from setup data */
  1737. if (setup) {
  1738. unsigned char hs_pop;
  1739. if (setup->sysclk)
  1740. twl4030->sysclk = setup->sysclk;
  1741. else
  1742. twl4030->sysclk = 26000;
  1743. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1744. hs_pop &= ~TWL4030_RAMP_DELAY;
  1745. hs_pop |= (setup->ramp_delay_value << 2);
  1746. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1747. } else {
  1748. twl4030->sysclk = 26000;
  1749. }
  1750. /* register pcms */
  1751. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1752. if (ret < 0) {
  1753. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1754. goto pcm_err;
  1755. }
  1756. twl4030_init_chip(codec);
  1757. /* power on device */
  1758. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1759. snd_soc_add_controls(codec, twl4030_snd_controls,
  1760. ARRAY_SIZE(twl4030_snd_controls));
  1761. twl4030_add_widgets(codec);
  1762. ret = snd_soc_init_card(socdev);
  1763. if (ret < 0) {
  1764. printk(KERN_ERR "twl4030: failed to register card\n");
  1765. goto card_err;
  1766. }
  1767. return ret;
  1768. card_err:
  1769. snd_soc_free_pcms(socdev);
  1770. snd_soc_dapm_free(socdev);
  1771. pcm_err:
  1772. kfree(codec->reg_cache);
  1773. return ret;
  1774. }
  1775. static struct snd_soc_device *twl4030_socdev;
  1776. static int twl4030_probe(struct platform_device *pdev)
  1777. {
  1778. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1779. struct snd_soc_codec *codec;
  1780. struct twl4030_priv *twl4030;
  1781. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1782. if (codec == NULL)
  1783. return -ENOMEM;
  1784. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1785. if (twl4030 == NULL) {
  1786. kfree(codec);
  1787. return -ENOMEM;
  1788. }
  1789. codec->private_data = twl4030;
  1790. socdev->card->codec = codec;
  1791. mutex_init(&codec->mutex);
  1792. INIT_LIST_HEAD(&codec->dapm_widgets);
  1793. INIT_LIST_HEAD(&codec->dapm_paths);
  1794. twl4030_socdev = socdev;
  1795. twl4030_init(socdev);
  1796. return 0;
  1797. }
  1798. static int twl4030_remove(struct platform_device *pdev)
  1799. {
  1800. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1801. struct snd_soc_codec *codec = socdev->card->codec;
  1802. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1803. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1804. snd_soc_free_pcms(socdev);
  1805. snd_soc_dapm_free(socdev);
  1806. kfree(codec->private_data);
  1807. kfree(codec);
  1808. return 0;
  1809. }
  1810. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1811. .probe = twl4030_probe,
  1812. .remove = twl4030_remove,
  1813. .suspend = twl4030_suspend,
  1814. .resume = twl4030_resume,
  1815. };
  1816. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1817. static int __init twl4030_modinit(void)
  1818. {
  1819. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1820. }
  1821. module_init(twl4030_modinit);
  1822. static void __exit twl4030_exit(void)
  1823. {
  1824. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1825. }
  1826. module_exit(twl4030_exit);
  1827. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1828. MODULE_AUTHOR("Steve Sakoman");
  1829. MODULE_LICENSE("GPL");