synclink_cs.c 118 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/config.h>
  36. #include <linux/module.h>
  37. #include <linux/errno.h>
  38. #include <linux/signal.h>
  39. #include <linux/sched.h>
  40. #include <linux/timer.h>
  41. #include <linux/time.h>
  42. #include <linux/interrupt.h>
  43. #include <linux/pci.h>
  44. #include <linux/tty.h>
  45. #include <linux/tty_flip.h>
  46. #include <linux/serial.h>
  47. #include <linux/major.h>
  48. #include <linux/string.h>
  49. #include <linux/fcntl.h>
  50. #include <linux/ptrace.h>
  51. #include <linux/ioport.h>
  52. #include <linux/mm.h>
  53. #include <linux/slab.h>
  54. #include <linux/netdevice.h>
  55. #include <linux/vmalloc.h>
  56. #include <linux/init.h>
  57. #include <asm/serial.h>
  58. #include <linux/delay.h>
  59. #include <linux/ioctl.h>
  60. #include <asm/system.h>
  61. #include <asm/io.h>
  62. #include <asm/irq.h>
  63. #include <asm/dma.h>
  64. #include <linux/bitops.h>
  65. #include <asm/types.h>
  66. #include <linux/termios.h>
  67. #include <linux/workqueue.h>
  68. #include <linux/hdlc.h>
  69. #include <pcmcia/cs_types.h>
  70. #include <pcmcia/cs.h>
  71. #include <pcmcia/cistpl.h>
  72. #include <pcmcia/cisreg.h>
  73. #include <pcmcia/ds.h>
  74. #ifdef CONFIG_HDLC_MODULE
  75. #define CONFIG_HDLC 1
  76. #endif
  77. #define GET_USER(error,value,addr) error = get_user(value,addr)
  78. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81. #include <asm/uaccess.h>
  82. #include "linux/synclink.h"
  83. static MGSL_PARAMS default_params = {
  84. MGSL_MODE_HDLC, /* unsigned long mode */
  85. 0, /* unsigned char loopback; */
  86. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  87. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  88. 0, /* unsigned long clock_speed; */
  89. 0xff, /* unsigned char addr_filter; */
  90. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  91. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  92. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  93. 9600, /* unsigned long data_rate; */
  94. 8, /* unsigned char data_bits; */
  95. 1, /* unsigned char stop_bits; */
  96. ASYNC_PARITY_NONE /* unsigned char parity; */
  97. };
  98. typedef struct
  99. {
  100. int count;
  101. unsigned char status;
  102. char data[1];
  103. } RXBUF;
  104. /* The queue of BH actions to be performed */
  105. #define BH_RECEIVE 1
  106. #define BH_TRANSMIT 2
  107. #define BH_STATUS 4
  108. #define IO_PIN_SHUTDOWN_LIMIT 100
  109. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  110. struct _input_signal_events {
  111. int ri_up;
  112. int ri_down;
  113. int dsr_up;
  114. int dsr_down;
  115. int dcd_up;
  116. int dcd_down;
  117. int cts_up;
  118. int cts_down;
  119. };
  120. /*
  121. * Device instance data structure
  122. */
  123. typedef struct _mgslpc_info {
  124. void *if_ptr; /* General purpose pointer (used by SPPP) */
  125. int magic;
  126. int flags;
  127. int count; /* count of opens */
  128. int line;
  129. unsigned short close_delay;
  130. unsigned short closing_wait; /* time to wait before closing */
  131. struct mgsl_icount icount;
  132. struct tty_struct *tty;
  133. int timeout;
  134. int x_char; /* xon/xoff character */
  135. int blocked_open; /* # of blocked opens */
  136. unsigned char read_status_mask;
  137. unsigned char ignore_status_mask;
  138. unsigned char *tx_buf;
  139. int tx_put;
  140. int tx_get;
  141. int tx_count;
  142. /* circular list of fixed length rx buffers */
  143. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  144. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  145. int rx_put; /* index of next empty rx buffer */
  146. int rx_get; /* index of next full rx buffer */
  147. int rx_buf_size; /* size in bytes of single rx buffer */
  148. int rx_buf_count; /* total number of rx buffers */
  149. int rx_frame_count; /* number of full rx buffers */
  150. wait_queue_head_t open_wait;
  151. wait_queue_head_t close_wait;
  152. wait_queue_head_t status_event_wait_q;
  153. wait_queue_head_t event_wait_q;
  154. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  155. struct _mgslpc_info *next_device; /* device list link */
  156. unsigned short imra_value;
  157. unsigned short imrb_value;
  158. unsigned char pim_value;
  159. spinlock_t lock;
  160. struct work_struct task; /* task structure for scheduling bh */
  161. u32 max_frame_size;
  162. u32 pending_bh;
  163. int bh_running;
  164. int bh_requested;
  165. int dcd_chkcount; /* check counts to prevent */
  166. int cts_chkcount; /* too many IRQs if a signal */
  167. int dsr_chkcount; /* is floating */
  168. int ri_chkcount;
  169. int rx_enabled;
  170. int rx_overflow;
  171. int tx_enabled;
  172. int tx_active;
  173. int tx_aborting;
  174. u32 idle_mode;
  175. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  176. char device_name[25]; /* device instance name */
  177. unsigned int io_base; /* base I/O address of adapter */
  178. unsigned int irq_level;
  179. MGSL_PARAMS params; /* communications parameters */
  180. unsigned char serial_signals; /* current serial signal states */
  181. char irq_occurred; /* for diagnostics use */
  182. char testing_irq;
  183. unsigned int init_error; /* startup error (DIAGS) */
  184. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  185. BOOLEAN drop_rts_on_tx_done;
  186. struct _input_signal_events input_signal_events;
  187. /* PCMCIA support */
  188. dev_link_t link;
  189. dev_node_t node;
  190. int stop;
  191. /* SPPP/Cisco HDLC device parts */
  192. int netcount;
  193. int dosyncppp;
  194. spinlock_t netlock;
  195. #ifdef CONFIG_HDLC
  196. struct net_device *netdev;
  197. #endif
  198. } MGSLPC_INFO;
  199. #define MGSLPC_MAGIC 0x5402
  200. /*
  201. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  202. */
  203. #define TXBUFSIZE 4096
  204. #define CHA 0x00 /* channel A offset */
  205. #define CHB 0x40 /* channel B offset */
  206. /*
  207. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  208. */
  209. #undef PVR
  210. #define RXFIFO 0
  211. #define TXFIFO 0
  212. #define STAR 0x20
  213. #define CMDR 0x20
  214. #define RSTA 0x21
  215. #define PRE 0x21
  216. #define MODE 0x22
  217. #define TIMR 0x23
  218. #define XAD1 0x24
  219. #define XAD2 0x25
  220. #define RAH1 0x26
  221. #define RAH2 0x27
  222. #define DAFO 0x27
  223. #define RAL1 0x28
  224. #define RFC 0x28
  225. #define RHCR 0x29
  226. #define RAL2 0x29
  227. #define RBCL 0x2a
  228. #define XBCL 0x2a
  229. #define RBCH 0x2b
  230. #define XBCH 0x2b
  231. #define CCR0 0x2c
  232. #define CCR1 0x2d
  233. #define CCR2 0x2e
  234. #define CCR3 0x2f
  235. #define VSTR 0x34
  236. #define BGR 0x34
  237. #define RLCR 0x35
  238. #define AML 0x36
  239. #define AMH 0x37
  240. #define GIS 0x38
  241. #define IVA 0x38
  242. #define IPC 0x39
  243. #define ISR 0x3a
  244. #define IMR 0x3a
  245. #define PVR 0x3c
  246. #define PIS 0x3d
  247. #define PIM 0x3d
  248. #define PCR 0x3e
  249. #define CCR4 0x3f
  250. // IMR/ISR
  251. #define IRQ_BREAK_ON BIT15 // rx break detected
  252. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  253. #define IRQ_ALLSENT BIT13 // all sent
  254. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  255. #define IRQ_TIMER BIT11 // timer interrupt
  256. #define IRQ_CTS BIT10 // CTS status change
  257. #define IRQ_TXREPEAT BIT9 // tx message repeat
  258. #define IRQ_TXFIFO BIT8 // transmit pool ready
  259. #define IRQ_RXEOM BIT7 // receive message end
  260. #define IRQ_EXITHUNT BIT6 // receive frame start
  261. #define IRQ_RXTIME BIT6 // rx char timeout
  262. #define IRQ_DCD BIT2 // carrier detect status change
  263. #define IRQ_OVERRUN BIT1 // receive frame overflow
  264. #define IRQ_RXFIFO BIT0 // receive pool full
  265. // STAR
  266. #define XFW BIT6 // transmit FIFO write enable
  267. #define CEC BIT2 // command executing
  268. #define CTS BIT1 // CTS state
  269. #define PVR_DTR BIT0
  270. #define PVR_DSR BIT1
  271. #define PVR_RI BIT2
  272. #define PVR_AUTOCTS BIT3
  273. #define PVR_RS232 0x20 /* 0010b */
  274. #define PVR_V35 0xe0 /* 1110b */
  275. #define PVR_RS422 0x40 /* 0100b */
  276. /* Register access functions */
  277. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  278. #define read_reg(info, reg) inb((info)->io_base + (reg))
  279. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  280. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  281. #define set_reg_bits(info, reg, mask) \
  282. write_reg(info, (reg), \
  283. (unsigned char) (read_reg(info, (reg)) | (mask)))
  284. #define clear_reg_bits(info, reg, mask) \
  285. write_reg(info, (reg), \
  286. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  287. /*
  288. * interrupt enable/disable routines
  289. */
  290. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  291. {
  292. if (channel == CHA) {
  293. info->imra_value |= mask;
  294. write_reg16(info, CHA + IMR, info->imra_value);
  295. } else {
  296. info->imrb_value |= mask;
  297. write_reg16(info, CHB + IMR, info->imrb_value);
  298. }
  299. }
  300. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  301. {
  302. if (channel == CHA) {
  303. info->imra_value &= ~mask;
  304. write_reg16(info, CHA + IMR, info->imra_value);
  305. } else {
  306. info->imrb_value &= ~mask;
  307. write_reg16(info, CHB + IMR, info->imrb_value);
  308. }
  309. }
  310. #define port_irq_disable(info, mask) \
  311. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  312. #define port_irq_enable(info, mask) \
  313. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  314. static void rx_start(MGSLPC_INFO *info);
  315. static void rx_stop(MGSLPC_INFO *info);
  316. static void tx_start(MGSLPC_INFO *info);
  317. static void tx_stop(MGSLPC_INFO *info);
  318. static void tx_set_idle(MGSLPC_INFO *info);
  319. static void get_signals(MGSLPC_INFO *info);
  320. static void set_signals(MGSLPC_INFO *info);
  321. static void reset_device(MGSLPC_INFO *info);
  322. static void hdlc_mode(MGSLPC_INFO *info);
  323. static void async_mode(MGSLPC_INFO *info);
  324. static void tx_timeout(unsigned long context);
  325. static int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg);
  326. #ifdef CONFIG_HDLC
  327. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  328. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  329. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  330. static int hdlcdev_init(MGSLPC_INFO *info);
  331. static void hdlcdev_exit(MGSLPC_INFO *info);
  332. #endif
  333. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  334. static BOOLEAN register_test(MGSLPC_INFO *info);
  335. static BOOLEAN irq_test(MGSLPC_INFO *info);
  336. static int adapter_test(MGSLPC_INFO *info);
  337. static int claim_resources(MGSLPC_INFO *info);
  338. static void release_resources(MGSLPC_INFO *info);
  339. static void mgslpc_add_device(MGSLPC_INFO *info);
  340. static void mgslpc_remove_device(MGSLPC_INFO *info);
  341. static int rx_get_frame(MGSLPC_INFO *info);
  342. static void rx_reset_buffers(MGSLPC_INFO *info);
  343. static int rx_alloc_buffers(MGSLPC_INFO *info);
  344. static void rx_free_buffers(MGSLPC_INFO *info);
  345. static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs);
  346. /*
  347. * Bottom half interrupt handlers
  348. */
  349. static void bh_handler(void* Context);
  350. static void bh_transmit(MGSLPC_INFO *info);
  351. static void bh_status(MGSLPC_INFO *info);
  352. /*
  353. * ioctl handlers
  354. */
  355. static int tiocmget(struct tty_struct *tty, struct file *file);
  356. static int tiocmset(struct tty_struct *tty, struct file *file,
  357. unsigned int set, unsigned int clear);
  358. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  359. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  360. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params);
  361. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  362. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  363. static int set_txenable(MGSLPC_INFO *info, int enable);
  364. static int tx_abort(MGSLPC_INFO *info);
  365. static int set_rxenable(MGSLPC_INFO *info, int enable);
  366. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  367. static MGSLPC_INFO *mgslpc_device_list = NULL;
  368. static int mgslpc_device_count = 0;
  369. /*
  370. * Set this param to non-zero to load eax with the
  371. * .text section address and breakpoint on module load.
  372. * This is useful for use with gdb and add-symbol-file command.
  373. */
  374. static int break_on_load=0;
  375. /*
  376. * Driver major number, defaults to zero to get auto
  377. * assigned major number. May be forced as module parameter.
  378. */
  379. static int ttymajor=0;
  380. static int debug_level = 0;
  381. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  382. static int dosyncppp[MAX_DEVICE_COUNT] = {1,1,1,1};
  383. module_param(break_on_load, bool, 0);
  384. module_param(ttymajor, int, 0);
  385. module_param(debug_level, int, 0);
  386. module_param_array(maxframe, int, NULL, 0);
  387. module_param_array(dosyncppp, int, NULL, 0);
  388. MODULE_LICENSE("GPL");
  389. static char *driver_name = "SyncLink PC Card driver";
  390. static char *driver_version = "$Revision: 4.34 $";
  391. static struct tty_driver *serial_driver;
  392. /* number of characters left in xmit buffer before we ask for more */
  393. #define WAKEUP_CHARS 256
  394. static void mgslpc_change_params(MGSLPC_INFO *info);
  395. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  396. /* PCMCIA prototypes */
  397. static void mgslpc_config(dev_link_t *link);
  398. static void mgslpc_release(u_long arg);
  399. static int mgslpc_event(event_t event, int priority,
  400. event_callback_args_t *args);
  401. static dev_link_t *mgslpc_attach(void);
  402. static void mgslpc_detach(struct pcmcia_device *p_dev);
  403. static dev_info_t dev_info = "synclink_cs";
  404. /*
  405. * 1st function defined in .text section. Calling this function in
  406. * init_module() followed by a breakpoint allows a remote debugger
  407. * (gdb) to get the .text address for the add-symbol-file command.
  408. * This allows remote debugging of dynamically loadable modules.
  409. */
  410. static void* mgslpc_get_text_ptr(void)
  411. {
  412. return mgslpc_get_text_ptr;
  413. }
  414. /**
  415. * line discipline callback wrappers
  416. *
  417. * The wrappers maintain line discipline references
  418. * while calling into the line discipline.
  419. *
  420. * ldisc_flush_buffer - flush line discipline receive buffers
  421. * ldisc_receive_buf - pass receive data to line discipline
  422. */
  423. static void ldisc_flush_buffer(struct tty_struct *tty)
  424. {
  425. struct tty_ldisc *ld = tty_ldisc_ref(tty);
  426. if (ld) {
  427. if (ld->flush_buffer)
  428. ld->flush_buffer(tty);
  429. tty_ldisc_deref(ld);
  430. }
  431. }
  432. static void ldisc_receive_buf(struct tty_struct *tty,
  433. const __u8 *data, char *flags, int count)
  434. {
  435. struct tty_ldisc *ld;
  436. if (!tty)
  437. return;
  438. ld = tty_ldisc_ref(tty);
  439. if (ld) {
  440. if (ld->receive_buf)
  441. ld->receive_buf(tty, data, flags, count);
  442. tty_ldisc_deref(ld);
  443. }
  444. }
  445. static dev_link_t *mgslpc_attach(void)
  446. {
  447. MGSLPC_INFO *info;
  448. dev_link_t *link;
  449. client_reg_t client_reg;
  450. int ret;
  451. if (debug_level >= DEBUG_LEVEL_INFO)
  452. printk("mgslpc_attach\n");
  453. info = (MGSLPC_INFO *)kmalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  454. if (!info) {
  455. printk("Error can't allocate device instance data\n");
  456. return NULL;
  457. }
  458. memset(info, 0, sizeof(MGSLPC_INFO));
  459. info->magic = MGSLPC_MAGIC;
  460. INIT_WORK(&info->task, bh_handler, info);
  461. info->max_frame_size = 4096;
  462. info->close_delay = 5*HZ/10;
  463. info->closing_wait = 30*HZ;
  464. init_waitqueue_head(&info->open_wait);
  465. init_waitqueue_head(&info->close_wait);
  466. init_waitqueue_head(&info->status_event_wait_q);
  467. init_waitqueue_head(&info->event_wait_q);
  468. spin_lock_init(&info->lock);
  469. spin_lock_init(&info->netlock);
  470. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  471. info->idle_mode = HDLC_TXIDLE_FLAGS;
  472. info->imra_value = 0xffff;
  473. info->imrb_value = 0xffff;
  474. info->pim_value = 0xff;
  475. link = &info->link;
  476. link->priv = info;
  477. /* Initialize the dev_link_t structure */
  478. /* Interrupt setup */
  479. link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
  480. link->irq.IRQInfo1 = IRQ_LEVEL_ID;
  481. link->irq.Handler = NULL;
  482. link->conf.Attributes = 0;
  483. link->conf.Vcc = 50;
  484. link->conf.IntType = INT_MEMORY_AND_IO;
  485. /* Register with Card Services */
  486. link->next = NULL;
  487. client_reg.dev_info = &dev_info;
  488. client_reg.Version = 0x0210;
  489. client_reg.event_callback_args.client_data = link;
  490. ret = pcmcia_register_client(&link->handle, &client_reg);
  491. if (ret != CS_SUCCESS) {
  492. cs_error(link->handle, RegisterClient, ret);
  493. mgslpc_detach(link->handle);
  494. return NULL;
  495. }
  496. mgslpc_add_device(info);
  497. return link;
  498. }
  499. /* Card has been inserted.
  500. */
  501. #define CS_CHECK(fn, ret) \
  502. do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
  503. static void mgslpc_config(dev_link_t *link)
  504. {
  505. client_handle_t handle = link->handle;
  506. MGSLPC_INFO *info = link->priv;
  507. tuple_t tuple;
  508. cisparse_t parse;
  509. int last_fn, last_ret;
  510. u_char buf[64];
  511. config_info_t conf;
  512. cistpl_cftable_entry_t dflt = { 0 };
  513. cistpl_cftable_entry_t *cfg;
  514. if (debug_level >= DEBUG_LEVEL_INFO)
  515. printk("mgslpc_config(0x%p)\n", link);
  516. /* read CONFIG tuple to find its configuration registers */
  517. tuple.DesiredTuple = CISTPL_CONFIG;
  518. tuple.Attributes = 0;
  519. tuple.TupleData = buf;
  520. tuple.TupleDataMax = sizeof(buf);
  521. tuple.TupleOffset = 0;
  522. CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
  523. CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
  524. CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
  525. link->conf.ConfigBase = parse.config.base;
  526. link->conf.Present = parse.config.rmask[0];
  527. /* Configure card */
  528. link->state |= DEV_CONFIG;
  529. /* Look up the current Vcc */
  530. CS_CHECK(GetConfigurationInfo, pcmcia_get_configuration_info(handle, &conf));
  531. link->conf.Vcc = conf.Vcc;
  532. /* get CIS configuration entry */
  533. tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
  534. CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
  535. cfg = &(parse.cftable_entry);
  536. CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
  537. CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
  538. if (cfg->flags & CISTPL_CFTABLE_DEFAULT) dflt = *cfg;
  539. if (cfg->index == 0)
  540. goto cs_failed;
  541. link->conf.ConfigIndex = cfg->index;
  542. link->conf.Attributes |= CONF_ENABLE_IRQ;
  543. /* IO window settings */
  544. link->io.NumPorts1 = 0;
  545. if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
  546. cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt.io;
  547. link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
  548. if (!(io->flags & CISTPL_IO_8BIT))
  549. link->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
  550. if (!(io->flags & CISTPL_IO_16BIT))
  551. link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
  552. link->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
  553. link->io.BasePort1 = io->win[0].base;
  554. link->io.NumPorts1 = io->win[0].len;
  555. CS_CHECK(RequestIO, pcmcia_request_io(link->handle, &link->io));
  556. }
  557. link->conf.Attributes = CONF_ENABLE_IRQ;
  558. link->conf.Vcc = 50;
  559. link->conf.IntType = INT_MEMORY_AND_IO;
  560. link->conf.ConfigIndex = 8;
  561. link->conf.Present = PRESENT_OPTION;
  562. link->irq.Attributes |= IRQ_HANDLE_PRESENT;
  563. link->irq.Handler = mgslpc_isr;
  564. link->irq.Instance = info;
  565. CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq));
  566. CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf));
  567. info->io_base = link->io.BasePort1;
  568. info->irq_level = link->irq.AssignedIRQ;
  569. /* add to linked list of devices */
  570. sprintf(info->node.dev_name, "mgslpc0");
  571. info->node.major = info->node.minor = 0;
  572. link->dev = &info->node;
  573. printk(KERN_INFO "%s: index 0x%02x:",
  574. info->node.dev_name, link->conf.ConfigIndex);
  575. if (link->conf.Attributes & CONF_ENABLE_IRQ)
  576. printk(", irq %d", link->irq.AssignedIRQ);
  577. if (link->io.NumPorts1)
  578. printk(", io 0x%04x-0x%04x", link->io.BasePort1,
  579. link->io.BasePort1+link->io.NumPorts1-1);
  580. printk("\n");
  581. link->state &= ~DEV_CONFIG_PENDING;
  582. return;
  583. cs_failed:
  584. cs_error(link->handle, last_fn, last_ret);
  585. mgslpc_release((u_long)link);
  586. }
  587. /* Card has been removed.
  588. * Unregister device and release PCMCIA configuration.
  589. * If device is open, postpone until it is closed.
  590. */
  591. static void mgslpc_release(u_long arg)
  592. {
  593. dev_link_t *link = (dev_link_t *)arg;
  594. if (debug_level >= DEBUG_LEVEL_INFO)
  595. printk("mgslpc_release(0x%p)\n", link);
  596. /* Unlink the device chain */
  597. link->dev = NULL;
  598. link->state &= ~DEV_CONFIG;
  599. pcmcia_release_configuration(link->handle);
  600. if (link->io.NumPorts1)
  601. pcmcia_release_io(link->handle, &link->io);
  602. if (link->irq.AssignedIRQ)
  603. pcmcia_release_irq(link->handle, &link->irq);
  604. }
  605. static void mgslpc_detach(struct pcmcia_device *p_dev)
  606. {
  607. dev_link_t *link = dev_to_instance(p_dev);
  608. if (debug_level >= DEBUG_LEVEL_INFO)
  609. printk("mgslpc_detach(0x%p)\n", link);
  610. if (link->state & DEV_CONFIG) {
  611. ((MGSLPC_INFO *)link->priv)->stop = 1;
  612. mgslpc_release((u_long)link);
  613. }
  614. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  615. }
  616. static int mgslpc_suspend(struct pcmcia_device *dev)
  617. {
  618. dev_link_t *link = dev_to_instance(dev);
  619. MGSLPC_INFO *info = link->priv;
  620. link->state |= DEV_SUSPEND;
  621. info->stop = 1;
  622. if (link->state & DEV_CONFIG)
  623. pcmcia_release_configuration(link->handle);
  624. return 0;
  625. }
  626. static int mgslpc_resume(struct pcmcia_device *dev)
  627. {
  628. dev_link_t *link = dev_to_instance(dev);
  629. MGSLPC_INFO *info = link->priv;
  630. link->state &= ~DEV_SUSPEND;
  631. if (link->state & DEV_CONFIG)
  632. pcmcia_request_configuration(link->handle, &link->conf);
  633. info->stop = 0;
  634. return 0;
  635. }
  636. static int mgslpc_event(event_t event, int priority,
  637. event_callback_args_t *args)
  638. {
  639. dev_link_t *link = args->client_data;
  640. if (debug_level >= DEBUG_LEVEL_INFO)
  641. printk("mgslpc_event(0x%06x)\n", event);
  642. switch (event) {
  643. case CS_EVENT_CARD_INSERTION:
  644. link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
  645. mgslpc_config(link);
  646. break;
  647. }
  648. return 0;
  649. }
  650. static inline int mgslpc_paranoia_check(MGSLPC_INFO *info,
  651. char *name, const char *routine)
  652. {
  653. #ifdef MGSLPC_PARANOIA_CHECK
  654. static const char *badmagic =
  655. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  656. static const char *badinfo =
  657. "Warning: null mgslpc_info for (%s) in %s\n";
  658. if (!info) {
  659. printk(badinfo, name, routine);
  660. return 1;
  661. }
  662. if (info->magic != MGSLPC_MAGIC) {
  663. printk(badmagic, name, routine);
  664. return 1;
  665. }
  666. #else
  667. if (!info)
  668. return 1;
  669. #endif
  670. return 0;
  671. }
  672. #define CMD_RXFIFO BIT7 // release current rx FIFO
  673. #define CMD_RXRESET BIT6 // receiver reset
  674. #define CMD_RXFIFO_READ BIT5
  675. #define CMD_START_TIMER BIT4
  676. #define CMD_TXFIFO BIT3 // release current tx FIFO
  677. #define CMD_TXEOM BIT1 // transmit end message
  678. #define CMD_TXRESET BIT0 // transmit reset
  679. static BOOLEAN wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  680. {
  681. int i = 0;
  682. /* wait for command completion */
  683. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  684. udelay(1);
  685. if (i++ == 1000)
  686. return FALSE;
  687. }
  688. return TRUE;
  689. }
  690. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  691. {
  692. wait_command_complete(info, channel);
  693. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  694. }
  695. static void tx_pause(struct tty_struct *tty)
  696. {
  697. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  698. unsigned long flags;
  699. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  700. return;
  701. if (debug_level >= DEBUG_LEVEL_INFO)
  702. printk("tx_pause(%s)\n",info->device_name);
  703. spin_lock_irqsave(&info->lock,flags);
  704. if (info->tx_enabled)
  705. tx_stop(info);
  706. spin_unlock_irqrestore(&info->lock,flags);
  707. }
  708. static void tx_release(struct tty_struct *tty)
  709. {
  710. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  711. unsigned long flags;
  712. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  713. return;
  714. if (debug_level >= DEBUG_LEVEL_INFO)
  715. printk("tx_release(%s)\n",info->device_name);
  716. spin_lock_irqsave(&info->lock,flags);
  717. if (!info->tx_enabled)
  718. tx_start(info);
  719. spin_unlock_irqrestore(&info->lock,flags);
  720. }
  721. /* Return next bottom half action to perform.
  722. * or 0 if nothing to do.
  723. */
  724. static int bh_action(MGSLPC_INFO *info)
  725. {
  726. unsigned long flags;
  727. int rc = 0;
  728. spin_lock_irqsave(&info->lock,flags);
  729. if (info->pending_bh & BH_RECEIVE) {
  730. info->pending_bh &= ~BH_RECEIVE;
  731. rc = BH_RECEIVE;
  732. } else if (info->pending_bh & BH_TRANSMIT) {
  733. info->pending_bh &= ~BH_TRANSMIT;
  734. rc = BH_TRANSMIT;
  735. } else if (info->pending_bh & BH_STATUS) {
  736. info->pending_bh &= ~BH_STATUS;
  737. rc = BH_STATUS;
  738. }
  739. if (!rc) {
  740. /* Mark BH routine as complete */
  741. info->bh_running = 0;
  742. info->bh_requested = 0;
  743. }
  744. spin_unlock_irqrestore(&info->lock,flags);
  745. return rc;
  746. }
  747. void bh_handler(void* Context)
  748. {
  749. MGSLPC_INFO *info = (MGSLPC_INFO*)Context;
  750. int action;
  751. if (!info)
  752. return;
  753. if (debug_level >= DEBUG_LEVEL_BH)
  754. printk( "%s(%d):bh_handler(%s) entry\n",
  755. __FILE__,__LINE__,info->device_name);
  756. info->bh_running = 1;
  757. while((action = bh_action(info)) != 0) {
  758. /* Process work item */
  759. if ( debug_level >= DEBUG_LEVEL_BH )
  760. printk( "%s(%d):bh_handler() work item action=%d\n",
  761. __FILE__,__LINE__,action);
  762. switch (action) {
  763. case BH_RECEIVE:
  764. while(rx_get_frame(info));
  765. break;
  766. case BH_TRANSMIT:
  767. bh_transmit(info);
  768. break;
  769. case BH_STATUS:
  770. bh_status(info);
  771. break;
  772. default:
  773. /* unknown work item ID */
  774. printk("Unknown work item ID=%08X!\n", action);
  775. break;
  776. }
  777. }
  778. if (debug_level >= DEBUG_LEVEL_BH)
  779. printk( "%s(%d):bh_handler(%s) exit\n",
  780. __FILE__,__LINE__,info->device_name);
  781. }
  782. void bh_transmit(MGSLPC_INFO *info)
  783. {
  784. struct tty_struct *tty = info->tty;
  785. if (debug_level >= DEBUG_LEVEL_BH)
  786. printk("bh_transmit() entry on %s\n", info->device_name);
  787. if (tty) {
  788. tty_wakeup(tty);
  789. wake_up_interruptible(&tty->write_wait);
  790. }
  791. }
  792. void bh_status(MGSLPC_INFO *info)
  793. {
  794. info->ri_chkcount = 0;
  795. info->dsr_chkcount = 0;
  796. info->dcd_chkcount = 0;
  797. info->cts_chkcount = 0;
  798. }
  799. /* eom: non-zero = end of frame */
  800. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  801. {
  802. unsigned char data[2];
  803. unsigned char fifo_count, read_count, i;
  804. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  805. if (debug_level >= DEBUG_LEVEL_ISR)
  806. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  807. if (!info->rx_enabled)
  808. return;
  809. if (info->rx_frame_count >= info->rx_buf_count) {
  810. /* no more free buffers */
  811. issue_command(info, CHA, CMD_RXRESET);
  812. info->pending_bh |= BH_RECEIVE;
  813. info->rx_overflow = 1;
  814. info->icount.buf_overrun++;
  815. return;
  816. }
  817. if (eom) {
  818. /* end of frame, get FIFO count from RBCL register */
  819. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  820. fifo_count = 32;
  821. } else
  822. fifo_count = 32;
  823. do {
  824. if (fifo_count == 1) {
  825. read_count = 1;
  826. data[0] = read_reg(info, CHA + RXFIFO);
  827. } else {
  828. read_count = 2;
  829. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  830. }
  831. fifo_count -= read_count;
  832. if (!fifo_count && eom)
  833. buf->status = data[--read_count];
  834. for (i = 0; i < read_count; i++) {
  835. if (buf->count >= info->max_frame_size) {
  836. /* frame too large, reset receiver and reset current buffer */
  837. issue_command(info, CHA, CMD_RXRESET);
  838. buf->count = 0;
  839. return;
  840. }
  841. *(buf->data + buf->count) = data[i];
  842. buf->count++;
  843. }
  844. } while (fifo_count);
  845. if (eom) {
  846. info->pending_bh |= BH_RECEIVE;
  847. info->rx_frame_count++;
  848. info->rx_put++;
  849. if (info->rx_put >= info->rx_buf_count)
  850. info->rx_put = 0;
  851. }
  852. issue_command(info, CHA, CMD_RXFIFO);
  853. }
  854. static void rx_ready_async(MGSLPC_INFO *info, int tcd)
  855. {
  856. unsigned char data, status;
  857. int fifo_count;
  858. struct tty_struct *tty = info->tty;
  859. struct mgsl_icount *icount = &info->icount;
  860. if (tcd) {
  861. /* early termination, get FIFO count from RBCL register */
  862. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  863. /* Zero fifo count could mean 0 or 32 bytes available.
  864. * If BIT5 of STAR is set then at least 1 byte is available.
  865. */
  866. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  867. fifo_count = 32;
  868. } else
  869. fifo_count = 32;
  870. /* Flush received async data to receive data buffer. */
  871. while (fifo_count) {
  872. data = read_reg(info, CHA + RXFIFO);
  873. status = read_reg(info, CHA + RXFIFO);
  874. fifo_count -= 2;
  875. if (tty->flip.count >= TTY_FLIPBUF_SIZE)
  876. break;
  877. *tty->flip.char_buf_ptr = data;
  878. icount->rx++;
  879. *tty->flip.flag_buf_ptr = 0;
  880. // if no frameing/crc error then save data
  881. // BIT7:parity error
  882. // BIT6:framing error
  883. if (status & (BIT7 + BIT6)) {
  884. if (status & BIT7)
  885. icount->parity++;
  886. else
  887. icount->frame++;
  888. /* discard char if tty control flags say so */
  889. if (status & info->ignore_status_mask)
  890. continue;
  891. status &= info->read_status_mask;
  892. if (status & BIT7)
  893. *tty->flip.flag_buf_ptr = TTY_PARITY;
  894. else if (status & BIT6)
  895. *tty->flip.flag_buf_ptr = TTY_FRAME;
  896. }
  897. tty->flip.flag_buf_ptr++;
  898. tty->flip.char_buf_ptr++;
  899. tty->flip.count++;
  900. }
  901. issue_command(info, CHA, CMD_RXFIFO);
  902. if (debug_level >= DEBUG_LEVEL_ISR) {
  903. printk("%s(%d):rx_ready_async count=%d\n",
  904. __FILE__,__LINE__,tty->flip.count);
  905. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  906. __FILE__,__LINE__,icount->rx,icount->brk,
  907. icount->parity,icount->frame,icount->overrun);
  908. }
  909. if (tty->flip.count)
  910. tty_flip_buffer_push(tty);
  911. }
  912. static void tx_done(MGSLPC_INFO *info)
  913. {
  914. if (!info->tx_active)
  915. return;
  916. info->tx_active = 0;
  917. info->tx_aborting = 0;
  918. if (info->params.mode == MGSL_MODE_ASYNC)
  919. return;
  920. info->tx_count = info->tx_put = info->tx_get = 0;
  921. del_timer(&info->tx_timer);
  922. if (info->drop_rts_on_tx_done) {
  923. get_signals(info);
  924. if (info->serial_signals & SerialSignal_RTS) {
  925. info->serial_signals &= ~SerialSignal_RTS;
  926. set_signals(info);
  927. }
  928. info->drop_rts_on_tx_done = 0;
  929. }
  930. #ifdef CONFIG_HDLC
  931. if (info->netcount)
  932. hdlcdev_tx_done(info);
  933. else
  934. #endif
  935. {
  936. if (info->tty->stopped || info->tty->hw_stopped) {
  937. tx_stop(info);
  938. return;
  939. }
  940. info->pending_bh |= BH_TRANSMIT;
  941. }
  942. }
  943. static void tx_ready(MGSLPC_INFO *info)
  944. {
  945. unsigned char fifo_count = 32;
  946. int c;
  947. if (debug_level >= DEBUG_LEVEL_ISR)
  948. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  949. if (info->params.mode == MGSL_MODE_HDLC) {
  950. if (!info->tx_active)
  951. return;
  952. } else {
  953. if (info->tty->stopped || info->tty->hw_stopped) {
  954. tx_stop(info);
  955. return;
  956. }
  957. if (!info->tx_count)
  958. info->tx_active = 0;
  959. }
  960. if (!info->tx_count)
  961. return;
  962. while (info->tx_count && fifo_count) {
  963. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  964. if (c == 1) {
  965. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  966. } else {
  967. write_reg16(info, CHA + TXFIFO,
  968. *((unsigned short*)(info->tx_buf + info->tx_get)));
  969. }
  970. info->tx_count -= c;
  971. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  972. fifo_count -= c;
  973. }
  974. if (info->params.mode == MGSL_MODE_ASYNC) {
  975. if (info->tx_count < WAKEUP_CHARS)
  976. info->pending_bh |= BH_TRANSMIT;
  977. issue_command(info, CHA, CMD_TXFIFO);
  978. } else {
  979. if (info->tx_count)
  980. issue_command(info, CHA, CMD_TXFIFO);
  981. else
  982. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  983. }
  984. }
  985. static void cts_change(MGSLPC_INFO *info)
  986. {
  987. get_signals(info);
  988. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  989. irq_disable(info, CHB, IRQ_CTS);
  990. info->icount.cts++;
  991. if (info->serial_signals & SerialSignal_CTS)
  992. info->input_signal_events.cts_up++;
  993. else
  994. info->input_signal_events.cts_down++;
  995. wake_up_interruptible(&info->status_event_wait_q);
  996. wake_up_interruptible(&info->event_wait_q);
  997. if (info->flags & ASYNC_CTS_FLOW) {
  998. if (info->tty->hw_stopped) {
  999. if (info->serial_signals & SerialSignal_CTS) {
  1000. if (debug_level >= DEBUG_LEVEL_ISR)
  1001. printk("CTS tx start...");
  1002. if (info->tty)
  1003. info->tty->hw_stopped = 0;
  1004. tx_start(info);
  1005. info->pending_bh |= BH_TRANSMIT;
  1006. return;
  1007. }
  1008. } else {
  1009. if (!(info->serial_signals & SerialSignal_CTS)) {
  1010. if (debug_level >= DEBUG_LEVEL_ISR)
  1011. printk("CTS tx stop...");
  1012. if (info->tty)
  1013. info->tty->hw_stopped = 1;
  1014. tx_stop(info);
  1015. }
  1016. }
  1017. }
  1018. info->pending_bh |= BH_STATUS;
  1019. }
  1020. static void dcd_change(MGSLPC_INFO *info)
  1021. {
  1022. get_signals(info);
  1023. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1024. irq_disable(info, CHB, IRQ_DCD);
  1025. info->icount.dcd++;
  1026. if (info->serial_signals & SerialSignal_DCD) {
  1027. info->input_signal_events.dcd_up++;
  1028. }
  1029. else
  1030. info->input_signal_events.dcd_down++;
  1031. #ifdef CONFIG_HDLC
  1032. if (info->netcount)
  1033. hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, info->netdev);
  1034. #endif
  1035. wake_up_interruptible(&info->status_event_wait_q);
  1036. wake_up_interruptible(&info->event_wait_q);
  1037. if (info->flags & ASYNC_CHECK_CD) {
  1038. if (debug_level >= DEBUG_LEVEL_ISR)
  1039. printk("%s CD now %s...", info->device_name,
  1040. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  1041. if (info->serial_signals & SerialSignal_DCD)
  1042. wake_up_interruptible(&info->open_wait);
  1043. else {
  1044. if (debug_level >= DEBUG_LEVEL_ISR)
  1045. printk("doing serial hangup...");
  1046. if (info->tty)
  1047. tty_hangup(info->tty);
  1048. }
  1049. }
  1050. info->pending_bh |= BH_STATUS;
  1051. }
  1052. static void dsr_change(MGSLPC_INFO *info)
  1053. {
  1054. get_signals(info);
  1055. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1056. port_irq_disable(info, PVR_DSR);
  1057. info->icount.dsr++;
  1058. if (info->serial_signals & SerialSignal_DSR)
  1059. info->input_signal_events.dsr_up++;
  1060. else
  1061. info->input_signal_events.dsr_down++;
  1062. wake_up_interruptible(&info->status_event_wait_q);
  1063. wake_up_interruptible(&info->event_wait_q);
  1064. info->pending_bh |= BH_STATUS;
  1065. }
  1066. static void ri_change(MGSLPC_INFO *info)
  1067. {
  1068. get_signals(info);
  1069. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1070. port_irq_disable(info, PVR_RI);
  1071. info->icount.rng++;
  1072. if (info->serial_signals & SerialSignal_RI)
  1073. info->input_signal_events.ri_up++;
  1074. else
  1075. info->input_signal_events.ri_down++;
  1076. wake_up_interruptible(&info->status_event_wait_q);
  1077. wake_up_interruptible(&info->event_wait_q);
  1078. info->pending_bh |= BH_STATUS;
  1079. }
  1080. /* Interrupt service routine entry point.
  1081. *
  1082. * Arguments:
  1083. *
  1084. * irq interrupt number that caused interrupt
  1085. * dev_id device ID supplied during interrupt registration
  1086. * regs interrupted processor context
  1087. */
  1088. static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs)
  1089. {
  1090. MGSLPC_INFO * info = (MGSLPC_INFO *)dev_id;
  1091. unsigned short isr;
  1092. unsigned char gis, pis;
  1093. int count=0;
  1094. if (debug_level >= DEBUG_LEVEL_ISR)
  1095. printk("mgslpc_isr(%d) entry.\n", irq);
  1096. if (!info)
  1097. return IRQ_NONE;
  1098. if (!(info->link.state & DEV_CONFIG))
  1099. return IRQ_HANDLED;
  1100. spin_lock(&info->lock);
  1101. while ((gis = read_reg(info, CHA + GIS))) {
  1102. if (debug_level >= DEBUG_LEVEL_ISR)
  1103. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  1104. if ((gis & 0x70) || count > 1000) {
  1105. printk("synclink_cs:hardware failed or ejected\n");
  1106. break;
  1107. }
  1108. count++;
  1109. if (gis & (BIT1 + BIT0)) {
  1110. isr = read_reg16(info, CHB + ISR);
  1111. if (isr & IRQ_DCD)
  1112. dcd_change(info);
  1113. if (isr & IRQ_CTS)
  1114. cts_change(info);
  1115. }
  1116. if (gis & (BIT3 + BIT2))
  1117. {
  1118. isr = read_reg16(info, CHA + ISR);
  1119. if (isr & IRQ_TIMER) {
  1120. info->irq_occurred = 1;
  1121. irq_disable(info, CHA, IRQ_TIMER);
  1122. }
  1123. /* receive IRQs */
  1124. if (isr & IRQ_EXITHUNT) {
  1125. info->icount.exithunt++;
  1126. wake_up_interruptible(&info->event_wait_q);
  1127. }
  1128. if (isr & IRQ_BREAK_ON) {
  1129. info->icount.brk++;
  1130. if (info->flags & ASYNC_SAK)
  1131. do_SAK(info->tty);
  1132. }
  1133. if (isr & IRQ_RXTIME) {
  1134. issue_command(info, CHA, CMD_RXFIFO_READ);
  1135. }
  1136. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1137. if (info->params.mode == MGSL_MODE_HDLC)
  1138. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1139. else
  1140. rx_ready_async(info, isr & IRQ_RXEOM);
  1141. }
  1142. /* transmit IRQs */
  1143. if (isr & IRQ_UNDERRUN) {
  1144. if (info->tx_aborting)
  1145. info->icount.txabort++;
  1146. else
  1147. info->icount.txunder++;
  1148. tx_done(info);
  1149. }
  1150. else if (isr & IRQ_ALLSENT) {
  1151. info->icount.txok++;
  1152. tx_done(info);
  1153. }
  1154. else if (isr & IRQ_TXFIFO)
  1155. tx_ready(info);
  1156. }
  1157. if (gis & BIT7) {
  1158. pis = read_reg(info, CHA + PIS);
  1159. if (pis & BIT1)
  1160. dsr_change(info);
  1161. if (pis & BIT2)
  1162. ri_change(info);
  1163. }
  1164. }
  1165. /* Request bottom half processing if there's something
  1166. * for it to do and the bh is not already running
  1167. */
  1168. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1169. if ( debug_level >= DEBUG_LEVEL_ISR )
  1170. printk("%s(%d):%s queueing bh task.\n",
  1171. __FILE__,__LINE__,info->device_name);
  1172. schedule_work(&info->task);
  1173. info->bh_requested = 1;
  1174. }
  1175. spin_unlock(&info->lock);
  1176. if (debug_level >= DEBUG_LEVEL_ISR)
  1177. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1178. __FILE__,__LINE__,irq);
  1179. return IRQ_HANDLED;
  1180. }
  1181. /* Initialize and start device.
  1182. */
  1183. static int startup(MGSLPC_INFO * info)
  1184. {
  1185. int retval = 0;
  1186. if (debug_level >= DEBUG_LEVEL_INFO)
  1187. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1188. if (info->flags & ASYNC_INITIALIZED)
  1189. return 0;
  1190. if (!info->tx_buf) {
  1191. /* allocate a page of memory for a transmit buffer */
  1192. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1193. if (!info->tx_buf) {
  1194. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1195. __FILE__,__LINE__,info->device_name);
  1196. return -ENOMEM;
  1197. }
  1198. }
  1199. info->pending_bh = 0;
  1200. memset(&info->icount, 0, sizeof(info->icount));
  1201. init_timer(&info->tx_timer);
  1202. info->tx_timer.data = (unsigned long)info;
  1203. info->tx_timer.function = tx_timeout;
  1204. /* Allocate and claim adapter resources */
  1205. retval = claim_resources(info);
  1206. /* perform existance check and diagnostics */
  1207. if ( !retval )
  1208. retval = adapter_test(info);
  1209. if ( retval ) {
  1210. if (capable(CAP_SYS_ADMIN) && info->tty)
  1211. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1212. release_resources(info);
  1213. return retval;
  1214. }
  1215. /* program hardware for current parameters */
  1216. mgslpc_change_params(info);
  1217. if (info->tty)
  1218. clear_bit(TTY_IO_ERROR, &info->tty->flags);
  1219. info->flags |= ASYNC_INITIALIZED;
  1220. return 0;
  1221. }
  1222. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1223. */
  1224. static void shutdown(MGSLPC_INFO * info)
  1225. {
  1226. unsigned long flags;
  1227. if (!(info->flags & ASYNC_INITIALIZED))
  1228. return;
  1229. if (debug_level >= DEBUG_LEVEL_INFO)
  1230. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1231. __FILE__,__LINE__, info->device_name );
  1232. /* clear status wait queue because status changes */
  1233. /* can't happen after shutting down the hardware */
  1234. wake_up_interruptible(&info->status_event_wait_q);
  1235. wake_up_interruptible(&info->event_wait_q);
  1236. del_timer(&info->tx_timer);
  1237. if (info->tx_buf) {
  1238. free_page((unsigned long) info->tx_buf);
  1239. info->tx_buf = NULL;
  1240. }
  1241. spin_lock_irqsave(&info->lock,flags);
  1242. rx_stop(info);
  1243. tx_stop(info);
  1244. /* TODO:disable interrupts instead of reset to preserve signal states */
  1245. reset_device(info);
  1246. if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
  1247. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1248. set_signals(info);
  1249. }
  1250. spin_unlock_irqrestore(&info->lock,flags);
  1251. release_resources(info);
  1252. if (info->tty)
  1253. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1254. info->flags &= ~ASYNC_INITIALIZED;
  1255. }
  1256. static void mgslpc_program_hw(MGSLPC_INFO *info)
  1257. {
  1258. unsigned long flags;
  1259. spin_lock_irqsave(&info->lock,flags);
  1260. rx_stop(info);
  1261. tx_stop(info);
  1262. info->tx_count = info->tx_put = info->tx_get = 0;
  1263. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1264. hdlc_mode(info);
  1265. else
  1266. async_mode(info);
  1267. set_signals(info);
  1268. info->dcd_chkcount = 0;
  1269. info->cts_chkcount = 0;
  1270. info->ri_chkcount = 0;
  1271. info->dsr_chkcount = 0;
  1272. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1273. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1274. get_signals(info);
  1275. if (info->netcount || info->tty->termios->c_cflag & CREAD)
  1276. rx_start(info);
  1277. spin_unlock_irqrestore(&info->lock,flags);
  1278. }
  1279. /* Reconfigure adapter based on new parameters
  1280. */
  1281. static void mgslpc_change_params(MGSLPC_INFO *info)
  1282. {
  1283. unsigned cflag;
  1284. int bits_per_char;
  1285. if (!info->tty || !info->tty->termios)
  1286. return;
  1287. if (debug_level >= DEBUG_LEVEL_INFO)
  1288. printk("%s(%d):mgslpc_change_params(%s)\n",
  1289. __FILE__,__LINE__, info->device_name );
  1290. cflag = info->tty->termios->c_cflag;
  1291. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1292. /* otherwise assert DTR and RTS */
  1293. if (cflag & CBAUD)
  1294. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1295. else
  1296. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1297. /* byte size and parity */
  1298. switch (cflag & CSIZE) {
  1299. case CS5: info->params.data_bits = 5; break;
  1300. case CS6: info->params.data_bits = 6; break;
  1301. case CS7: info->params.data_bits = 7; break;
  1302. case CS8: info->params.data_bits = 8; break;
  1303. default: info->params.data_bits = 7; break;
  1304. }
  1305. if (cflag & CSTOPB)
  1306. info->params.stop_bits = 2;
  1307. else
  1308. info->params.stop_bits = 1;
  1309. info->params.parity = ASYNC_PARITY_NONE;
  1310. if (cflag & PARENB) {
  1311. if (cflag & PARODD)
  1312. info->params.parity = ASYNC_PARITY_ODD;
  1313. else
  1314. info->params.parity = ASYNC_PARITY_EVEN;
  1315. #ifdef CMSPAR
  1316. if (cflag & CMSPAR)
  1317. info->params.parity = ASYNC_PARITY_SPACE;
  1318. #endif
  1319. }
  1320. /* calculate number of jiffies to transmit a full
  1321. * FIFO (32 bytes) at specified data rate
  1322. */
  1323. bits_per_char = info->params.data_bits +
  1324. info->params.stop_bits + 1;
  1325. /* if port data rate is set to 460800 or less then
  1326. * allow tty settings to override, otherwise keep the
  1327. * current data rate.
  1328. */
  1329. if (info->params.data_rate <= 460800) {
  1330. info->params.data_rate = tty_get_baud_rate(info->tty);
  1331. }
  1332. if ( info->params.data_rate ) {
  1333. info->timeout = (32*HZ*bits_per_char) /
  1334. info->params.data_rate;
  1335. }
  1336. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1337. if (cflag & CRTSCTS)
  1338. info->flags |= ASYNC_CTS_FLOW;
  1339. else
  1340. info->flags &= ~ASYNC_CTS_FLOW;
  1341. if (cflag & CLOCAL)
  1342. info->flags &= ~ASYNC_CHECK_CD;
  1343. else
  1344. info->flags |= ASYNC_CHECK_CD;
  1345. /* process tty input control flags */
  1346. info->read_status_mask = 0;
  1347. if (I_INPCK(info->tty))
  1348. info->read_status_mask |= BIT7 | BIT6;
  1349. if (I_IGNPAR(info->tty))
  1350. info->ignore_status_mask |= BIT7 | BIT6;
  1351. mgslpc_program_hw(info);
  1352. }
  1353. /* Add a character to the transmit buffer
  1354. */
  1355. static void mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1356. {
  1357. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1358. unsigned long flags;
  1359. if (debug_level >= DEBUG_LEVEL_INFO) {
  1360. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1361. __FILE__,__LINE__,ch,info->device_name);
  1362. }
  1363. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1364. return;
  1365. if (!tty || !info->tx_buf)
  1366. return;
  1367. spin_lock_irqsave(&info->lock,flags);
  1368. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1369. if (info->tx_count < TXBUFSIZE - 1) {
  1370. info->tx_buf[info->tx_put++] = ch;
  1371. info->tx_put &= TXBUFSIZE-1;
  1372. info->tx_count++;
  1373. }
  1374. }
  1375. spin_unlock_irqrestore(&info->lock,flags);
  1376. }
  1377. /* Enable transmitter so remaining characters in the
  1378. * transmit buffer are sent.
  1379. */
  1380. static void mgslpc_flush_chars(struct tty_struct *tty)
  1381. {
  1382. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1383. unsigned long flags;
  1384. if (debug_level >= DEBUG_LEVEL_INFO)
  1385. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1386. __FILE__,__LINE__,info->device_name,info->tx_count);
  1387. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1388. return;
  1389. if (info->tx_count <= 0 || tty->stopped ||
  1390. tty->hw_stopped || !info->tx_buf)
  1391. return;
  1392. if (debug_level >= DEBUG_LEVEL_INFO)
  1393. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1394. __FILE__,__LINE__,info->device_name);
  1395. spin_lock_irqsave(&info->lock,flags);
  1396. if (!info->tx_active)
  1397. tx_start(info);
  1398. spin_unlock_irqrestore(&info->lock,flags);
  1399. }
  1400. /* Send a block of data
  1401. *
  1402. * Arguments:
  1403. *
  1404. * tty pointer to tty information structure
  1405. * buf pointer to buffer containing send data
  1406. * count size of send data in bytes
  1407. *
  1408. * Returns: number of characters written
  1409. */
  1410. static int mgslpc_write(struct tty_struct * tty,
  1411. const unsigned char *buf, int count)
  1412. {
  1413. int c, ret = 0;
  1414. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1415. unsigned long flags;
  1416. if (debug_level >= DEBUG_LEVEL_INFO)
  1417. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1418. __FILE__,__LINE__,info->device_name,count);
  1419. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1420. !tty || !info->tx_buf)
  1421. goto cleanup;
  1422. if (info->params.mode == MGSL_MODE_HDLC) {
  1423. if (count > TXBUFSIZE) {
  1424. ret = -EIO;
  1425. goto cleanup;
  1426. }
  1427. if (info->tx_active)
  1428. goto cleanup;
  1429. else if (info->tx_count)
  1430. goto start;
  1431. }
  1432. for (;;) {
  1433. c = min(count,
  1434. min(TXBUFSIZE - info->tx_count - 1,
  1435. TXBUFSIZE - info->tx_put));
  1436. if (c <= 0)
  1437. break;
  1438. memcpy(info->tx_buf + info->tx_put, buf, c);
  1439. spin_lock_irqsave(&info->lock,flags);
  1440. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1441. info->tx_count += c;
  1442. spin_unlock_irqrestore(&info->lock,flags);
  1443. buf += c;
  1444. count -= c;
  1445. ret += c;
  1446. }
  1447. start:
  1448. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1449. spin_lock_irqsave(&info->lock,flags);
  1450. if (!info->tx_active)
  1451. tx_start(info);
  1452. spin_unlock_irqrestore(&info->lock,flags);
  1453. }
  1454. cleanup:
  1455. if (debug_level >= DEBUG_LEVEL_INFO)
  1456. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1457. __FILE__,__LINE__,info->device_name,ret);
  1458. return ret;
  1459. }
  1460. /* Return the count of free bytes in transmit buffer
  1461. */
  1462. static int mgslpc_write_room(struct tty_struct *tty)
  1463. {
  1464. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1465. int ret;
  1466. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1467. return 0;
  1468. if (info->params.mode == MGSL_MODE_HDLC) {
  1469. /* HDLC (frame oriented) mode */
  1470. if (info->tx_active)
  1471. return 0;
  1472. else
  1473. return HDLC_MAX_FRAME_SIZE;
  1474. } else {
  1475. ret = TXBUFSIZE - info->tx_count - 1;
  1476. if (ret < 0)
  1477. ret = 0;
  1478. }
  1479. if (debug_level >= DEBUG_LEVEL_INFO)
  1480. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1481. __FILE__,__LINE__, info->device_name, ret);
  1482. return ret;
  1483. }
  1484. /* Return the count of bytes in transmit buffer
  1485. */
  1486. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1487. {
  1488. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1489. int rc;
  1490. if (debug_level >= DEBUG_LEVEL_INFO)
  1491. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1492. __FILE__,__LINE__, info->device_name );
  1493. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1494. return 0;
  1495. if (info->params.mode == MGSL_MODE_HDLC)
  1496. rc = info->tx_active ? info->max_frame_size : 0;
  1497. else
  1498. rc = info->tx_count;
  1499. if (debug_level >= DEBUG_LEVEL_INFO)
  1500. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1501. __FILE__,__LINE__, info->device_name, rc);
  1502. return rc;
  1503. }
  1504. /* Discard all data in the send buffer
  1505. */
  1506. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1507. {
  1508. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1509. unsigned long flags;
  1510. if (debug_level >= DEBUG_LEVEL_INFO)
  1511. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1512. __FILE__,__LINE__, info->device_name );
  1513. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1514. return;
  1515. spin_lock_irqsave(&info->lock,flags);
  1516. info->tx_count = info->tx_put = info->tx_get = 0;
  1517. del_timer(&info->tx_timer);
  1518. spin_unlock_irqrestore(&info->lock,flags);
  1519. wake_up_interruptible(&tty->write_wait);
  1520. tty_wakeup(tty);
  1521. }
  1522. /* Send a high-priority XON/XOFF character
  1523. */
  1524. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1525. {
  1526. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1527. unsigned long flags;
  1528. if (debug_level >= DEBUG_LEVEL_INFO)
  1529. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1530. __FILE__,__LINE__, info->device_name, ch );
  1531. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1532. return;
  1533. info->x_char = ch;
  1534. if (ch) {
  1535. spin_lock_irqsave(&info->lock,flags);
  1536. if (!info->tx_enabled)
  1537. tx_start(info);
  1538. spin_unlock_irqrestore(&info->lock,flags);
  1539. }
  1540. }
  1541. /* Signal remote device to throttle send data (our receive data)
  1542. */
  1543. static void mgslpc_throttle(struct tty_struct * tty)
  1544. {
  1545. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1546. unsigned long flags;
  1547. if (debug_level >= DEBUG_LEVEL_INFO)
  1548. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1549. __FILE__,__LINE__, info->device_name );
  1550. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1551. return;
  1552. if (I_IXOFF(tty))
  1553. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1554. if (tty->termios->c_cflag & CRTSCTS) {
  1555. spin_lock_irqsave(&info->lock,flags);
  1556. info->serial_signals &= ~SerialSignal_RTS;
  1557. set_signals(info);
  1558. spin_unlock_irqrestore(&info->lock,flags);
  1559. }
  1560. }
  1561. /* Signal remote device to stop throttling send data (our receive data)
  1562. */
  1563. static void mgslpc_unthrottle(struct tty_struct * tty)
  1564. {
  1565. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1566. unsigned long flags;
  1567. if (debug_level >= DEBUG_LEVEL_INFO)
  1568. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1569. __FILE__,__LINE__, info->device_name );
  1570. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1571. return;
  1572. if (I_IXOFF(tty)) {
  1573. if (info->x_char)
  1574. info->x_char = 0;
  1575. else
  1576. mgslpc_send_xchar(tty, START_CHAR(tty));
  1577. }
  1578. if (tty->termios->c_cflag & CRTSCTS) {
  1579. spin_lock_irqsave(&info->lock,flags);
  1580. info->serial_signals |= SerialSignal_RTS;
  1581. set_signals(info);
  1582. spin_unlock_irqrestore(&info->lock,flags);
  1583. }
  1584. }
  1585. /* get the current serial statistics
  1586. */
  1587. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1588. {
  1589. int err;
  1590. if (debug_level >= DEBUG_LEVEL_INFO)
  1591. printk("get_params(%s)\n", info->device_name);
  1592. if (!user_icount) {
  1593. memset(&info->icount, 0, sizeof(info->icount));
  1594. } else {
  1595. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1596. if (err)
  1597. return -EFAULT;
  1598. }
  1599. return 0;
  1600. }
  1601. /* get the current serial parameters
  1602. */
  1603. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1604. {
  1605. int err;
  1606. if (debug_level >= DEBUG_LEVEL_INFO)
  1607. printk("get_params(%s)\n", info->device_name);
  1608. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1609. if (err)
  1610. return -EFAULT;
  1611. return 0;
  1612. }
  1613. /* set the serial parameters
  1614. *
  1615. * Arguments:
  1616. *
  1617. * info pointer to device instance data
  1618. * new_params user buffer containing new serial params
  1619. *
  1620. * Returns: 0 if success, otherwise error code
  1621. */
  1622. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params)
  1623. {
  1624. unsigned long flags;
  1625. MGSL_PARAMS tmp_params;
  1626. int err;
  1627. if (debug_level >= DEBUG_LEVEL_INFO)
  1628. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1629. info->device_name );
  1630. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1631. if (err) {
  1632. if ( debug_level >= DEBUG_LEVEL_INFO )
  1633. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1634. __FILE__,__LINE__,info->device_name);
  1635. return -EFAULT;
  1636. }
  1637. spin_lock_irqsave(&info->lock,flags);
  1638. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1639. spin_unlock_irqrestore(&info->lock,flags);
  1640. mgslpc_change_params(info);
  1641. return 0;
  1642. }
  1643. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1644. {
  1645. int err;
  1646. if (debug_level >= DEBUG_LEVEL_INFO)
  1647. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1648. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1649. if (err)
  1650. return -EFAULT;
  1651. return 0;
  1652. }
  1653. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1654. {
  1655. unsigned long flags;
  1656. if (debug_level >= DEBUG_LEVEL_INFO)
  1657. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1658. spin_lock_irqsave(&info->lock,flags);
  1659. info->idle_mode = idle_mode;
  1660. tx_set_idle(info);
  1661. spin_unlock_irqrestore(&info->lock,flags);
  1662. return 0;
  1663. }
  1664. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1665. {
  1666. int err;
  1667. if (debug_level >= DEBUG_LEVEL_INFO)
  1668. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1669. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1670. if (err)
  1671. return -EFAULT;
  1672. return 0;
  1673. }
  1674. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1675. {
  1676. unsigned long flags;
  1677. unsigned char val;
  1678. if (debug_level >= DEBUG_LEVEL_INFO)
  1679. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1680. spin_lock_irqsave(&info->lock,flags);
  1681. info->if_mode = if_mode;
  1682. val = read_reg(info, PVR) & 0x0f;
  1683. switch (info->if_mode)
  1684. {
  1685. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1686. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1687. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1688. }
  1689. write_reg(info, PVR, val);
  1690. spin_unlock_irqrestore(&info->lock,flags);
  1691. return 0;
  1692. }
  1693. static int set_txenable(MGSLPC_INFO * info, int enable)
  1694. {
  1695. unsigned long flags;
  1696. if (debug_level >= DEBUG_LEVEL_INFO)
  1697. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1698. spin_lock_irqsave(&info->lock,flags);
  1699. if (enable) {
  1700. if (!info->tx_enabled)
  1701. tx_start(info);
  1702. } else {
  1703. if (info->tx_enabled)
  1704. tx_stop(info);
  1705. }
  1706. spin_unlock_irqrestore(&info->lock,flags);
  1707. return 0;
  1708. }
  1709. static int tx_abort(MGSLPC_INFO * info)
  1710. {
  1711. unsigned long flags;
  1712. if (debug_level >= DEBUG_LEVEL_INFO)
  1713. printk("tx_abort(%s)\n", info->device_name);
  1714. spin_lock_irqsave(&info->lock,flags);
  1715. if (info->tx_active && info->tx_count &&
  1716. info->params.mode == MGSL_MODE_HDLC) {
  1717. /* clear data count so FIFO is not filled on next IRQ.
  1718. * This results in underrun and abort transmission.
  1719. */
  1720. info->tx_count = info->tx_put = info->tx_get = 0;
  1721. info->tx_aborting = TRUE;
  1722. }
  1723. spin_unlock_irqrestore(&info->lock,flags);
  1724. return 0;
  1725. }
  1726. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1727. {
  1728. unsigned long flags;
  1729. if (debug_level >= DEBUG_LEVEL_INFO)
  1730. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1731. spin_lock_irqsave(&info->lock,flags);
  1732. if (enable) {
  1733. if (!info->rx_enabled)
  1734. rx_start(info);
  1735. } else {
  1736. if (info->rx_enabled)
  1737. rx_stop(info);
  1738. }
  1739. spin_unlock_irqrestore(&info->lock,flags);
  1740. return 0;
  1741. }
  1742. /* wait for specified event to occur
  1743. *
  1744. * Arguments: info pointer to device instance data
  1745. * mask pointer to bitmask of events to wait for
  1746. * Return Value: 0 if successful and bit mask updated with
  1747. * of events triggerred,
  1748. * otherwise error code
  1749. */
  1750. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1751. {
  1752. unsigned long flags;
  1753. int s;
  1754. int rc=0;
  1755. struct mgsl_icount cprev, cnow;
  1756. int events;
  1757. int mask;
  1758. struct _input_signal_events oldsigs, newsigs;
  1759. DECLARE_WAITQUEUE(wait, current);
  1760. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1761. if (rc)
  1762. return -EFAULT;
  1763. if (debug_level >= DEBUG_LEVEL_INFO)
  1764. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1765. spin_lock_irqsave(&info->lock,flags);
  1766. /* return immediately if state matches requested events */
  1767. get_signals(info);
  1768. s = info->serial_signals;
  1769. events = mask &
  1770. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1771. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1772. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1773. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1774. if (events) {
  1775. spin_unlock_irqrestore(&info->lock,flags);
  1776. goto exit;
  1777. }
  1778. /* save current irq counts */
  1779. cprev = info->icount;
  1780. oldsigs = info->input_signal_events;
  1781. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1782. (mask & MgslEvent_ExitHuntMode))
  1783. irq_enable(info, CHA, IRQ_EXITHUNT);
  1784. set_current_state(TASK_INTERRUPTIBLE);
  1785. add_wait_queue(&info->event_wait_q, &wait);
  1786. spin_unlock_irqrestore(&info->lock,flags);
  1787. for(;;) {
  1788. schedule();
  1789. if (signal_pending(current)) {
  1790. rc = -ERESTARTSYS;
  1791. break;
  1792. }
  1793. /* get current irq counts */
  1794. spin_lock_irqsave(&info->lock,flags);
  1795. cnow = info->icount;
  1796. newsigs = info->input_signal_events;
  1797. set_current_state(TASK_INTERRUPTIBLE);
  1798. spin_unlock_irqrestore(&info->lock,flags);
  1799. /* if no change, wait aborted for some reason */
  1800. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1801. newsigs.dsr_down == oldsigs.dsr_down &&
  1802. newsigs.dcd_up == oldsigs.dcd_up &&
  1803. newsigs.dcd_down == oldsigs.dcd_down &&
  1804. newsigs.cts_up == oldsigs.cts_up &&
  1805. newsigs.cts_down == oldsigs.cts_down &&
  1806. newsigs.ri_up == oldsigs.ri_up &&
  1807. newsigs.ri_down == oldsigs.ri_down &&
  1808. cnow.exithunt == cprev.exithunt &&
  1809. cnow.rxidle == cprev.rxidle) {
  1810. rc = -EIO;
  1811. break;
  1812. }
  1813. events = mask &
  1814. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1815. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1816. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1817. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1818. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1819. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1820. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1821. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1822. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1823. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1824. if (events)
  1825. break;
  1826. cprev = cnow;
  1827. oldsigs = newsigs;
  1828. }
  1829. remove_wait_queue(&info->event_wait_q, &wait);
  1830. set_current_state(TASK_RUNNING);
  1831. if (mask & MgslEvent_ExitHuntMode) {
  1832. spin_lock_irqsave(&info->lock,flags);
  1833. if (!waitqueue_active(&info->event_wait_q))
  1834. irq_disable(info, CHA, IRQ_EXITHUNT);
  1835. spin_unlock_irqrestore(&info->lock,flags);
  1836. }
  1837. exit:
  1838. if (rc == 0)
  1839. PUT_USER(rc, events, mask_ptr);
  1840. return rc;
  1841. }
  1842. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1843. {
  1844. unsigned long flags;
  1845. int rc;
  1846. struct mgsl_icount cprev, cnow;
  1847. DECLARE_WAITQUEUE(wait, current);
  1848. /* save current irq counts */
  1849. spin_lock_irqsave(&info->lock,flags);
  1850. cprev = info->icount;
  1851. add_wait_queue(&info->status_event_wait_q, &wait);
  1852. set_current_state(TASK_INTERRUPTIBLE);
  1853. spin_unlock_irqrestore(&info->lock,flags);
  1854. for(;;) {
  1855. schedule();
  1856. if (signal_pending(current)) {
  1857. rc = -ERESTARTSYS;
  1858. break;
  1859. }
  1860. /* get new irq counts */
  1861. spin_lock_irqsave(&info->lock,flags);
  1862. cnow = info->icount;
  1863. set_current_state(TASK_INTERRUPTIBLE);
  1864. spin_unlock_irqrestore(&info->lock,flags);
  1865. /* if no change, wait aborted for some reason */
  1866. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1867. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1868. rc = -EIO;
  1869. break;
  1870. }
  1871. /* check for change in caller specified modem input */
  1872. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1873. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1874. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1875. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1876. rc = 0;
  1877. break;
  1878. }
  1879. cprev = cnow;
  1880. }
  1881. remove_wait_queue(&info->status_event_wait_q, &wait);
  1882. set_current_state(TASK_RUNNING);
  1883. return rc;
  1884. }
  1885. /* return the state of the serial control and status signals
  1886. */
  1887. static int tiocmget(struct tty_struct *tty, struct file *file)
  1888. {
  1889. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1890. unsigned int result;
  1891. unsigned long flags;
  1892. spin_lock_irqsave(&info->lock,flags);
  1893. get_signals(info);
  1894. spin_unlock_irqrestore(&info->lock,flags);
  1895. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1896. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1897. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1898. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1899. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1900. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1901. if (debug_level >= DEBUG_LEVEL_INFO)
  1902. printk("%s(%d):%s tiocmget() value=%08X\n",
  1903. __FILE__,__LINE__, info->device_name, result );
  1904. return result;
  1905. }
  1906. /* set modem control signals (DTR/RTS)
  1907. */
  1908. static int tiocmset(struct tty_struct *tty, struct file *file,
  1909. unsigned int set, unsigned int clear)
  1910. {
  1911. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1912. unsigned long flags;
  1913. if (debug_level >= DEBUG_LEVEL_INFO)
  1914. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1915. __FILE__,__LINE__,info->device_name, set, clear);
  1916. if (set & TIOCM_RTS)
  1917. info->serial_signals |= SerialSignal_RTS;
  1918. if (set & TIOCM_DTR)
  1919. info->serial_signals |= SerialSignal_DTR;
  1920. if (clear & TIOCM_RTS)
  1921. info->serial_signals &= ~SerialSignal_RTS;
  1922. if (clear & TIOCM_DTR)
  1923. info->serial_signals &= ~SerialSignal_DTR;
  1924. spin_lock_irqsave(&info->lock,flags);
  1925. set_signals(info);
  1926. spin_unlock_irqrestore(&info->lock,flags);
  1927. return 0;
  1928. }
  1929. /* Set or clear transmit break condition
  1930. *
  1931. * Arguments: tty pointer to tty instance data
  1932. * break_state -1=set break condition, 0=clear
  1933. */
  1934. static void mgslpc_break(struct tty_struct *tty, int break_state)
  1935. {
  1936. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1937. unsigned long flags;
  1938. if (debug_level >= DEBUG_LEVEL_INFO)
  1939. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1940. __FILE__,__LINE__, info->device_name, break_state);
  1941. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1942. return;
  1943. spin_lock_irqsave(&info->lock,flags);
  1944. if (break_state == -1)
  1945. set_reg_bits(info, CHA+DAFO, BIT6);
  1946. else
  1947. clear_reg_bits(info, CHA+DAFO, BIT6);
  1948. spin_unlock_irqrestore(&info->lock,flags);
  1949. }
  1950. /* Service an IOCTL request
  1951. *
  1952. * Arguments:
  1953. *
  1954. * tty pointer to tty instance data
  1955. * file pointer to associated file object for device
  1956. * cmd IOCTL command code
  1957. * arg command argument/context
  1958. *
  1959. * Return Value: 0 if success, otherwise error code
  1960. */
  1961. static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
  1962. unsigned int cmd, unsigned long arg)
  1963. {
  1964. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1965. if (debug_level >= DEBUG_LEVEL_INFO)
  1966. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1967. info->device_name, cmd );
  1968. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1969. return -ENODEV;
  1970. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1971. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  1972. if (tty->flags & (1 << TTY_IO_ERROR))
  1973. return -EIO;
  1974. }
  1975. return ioctl_common(info, cmd, arg);
  1976. }
  1977. int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg)
  1978. {
  1979. int error;
  1980. struct mgsl_icount cnow; /* kernel counter temps */
  1981. struct serial_icounter_struct __user *p_cuser; /* user space */
  1982. void __user *argp = (void __user *)arg;
  1983. unsigned long flags;
  1984. switch (cmd) {
  1985. case MGSL_IOCGPARAMS:
  1986. return get_params(info, argp);
  1987. case MGSL_IOCSPARAMS:
  1988. return set_params(info, argp);
  1989. case MGSL_IOCGTXIDLE:
  1990. return get_txidle(info, argp);
  1991. case MGSL_IOCSTXIDLE:
  1992. return set_txidle(info, (int)arg);
  1993. case MGSL_IOCGIF:
  1994. return get_interface(info, argp);
  1995. case MGSL_IOCSIF:
  1996. return set_interface(info,(int)arg);
  1997. case MGSL_IOCTXENABLE:
  1998. return set_txenable(info,(int)arg);
  1999. case MGSL_IOCRXENABLE:
  2000. return set_rxenable(info,(int)arg);
  2001. case MGSL_IOCTXABORT:
  2002. return tx_abort(info);
  2003. case MGSL_IOCGSTATS:
  2004. return get_stats(info, argp);
  2005. case MGSL_IOCWAITEVENT:
  2006. return wait_events(info, argp);
  2007. case TIOCMIWAIT:
  2008. return modem_input_wait(info,(int)arg);
  2009. case TIOCGICOUNT:
  2010. spin_lock_irqsave(&info->lock,flags);
  2011. cnow = info->icount;
  2012. spin_unlock_irqrestore(&info->lock,flags);
  2013. p_cuser = argp;
  2014. PUT_USER(error,cnow.cts, &p_cuser->cts);
  2015. if (error) return error;
  2016. PUT_USER(error,cnow.dsr, &p_cuser->dsr);
  2017. if (error) return error;
  2018. PUT_USER(error,cnow.rng, &p_cuser->rng);
  2019. if (error) return error;
  2020. PUT_USER(error,cnow.dcd, &p_cuser->dcd);
  2021. if (error) return error;
  2022. PUT_USER(error,cnow.rx, &p_cuser->rx);
  2023. if (error) return error;
  2024. PUT_USER(error,cnow.tx, &p_cuser->tx);
  2025. if (error) return error;
  2026. PUT_USER(error,cnow.frame, &p_cuser->frame);
  2027. if (error) return error;
  2028. PUT_USER(error,cnow.overrun, &p_cuser->overrun);
  2029. if (error) return error;
  2030. PUT_USER(error,cnow.parity, &p_cuser->parity);
  2031. if (error) return error;
  2032. PUT_USER(error,cnow.brk, &p_cuser->brk);
  2033. if (error) return error;
  2034. PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
  2035. if (error) return error;
  2036. return 0;
  2037. default:
  2038. return -ENOIOCTLCMD;
  2039. }
  2040. return 0;
  2041. }
  2042. /* Set new termios settings
  2043. *
  2044. * Arguments:
  2045. *
  2046. * tty pointer to tty structure
  2047. * termios pointer to buffer to hold returned old termios
  2048. */
  2049. static void mgslpc_set_termios(struct tty_struct *tty, struct termios *old_termios)
  2050. {
  2051. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  2052. unsigned long flags;
  2053. if (debug_level >= DEBUG_LEVEL_INFO)
  2054. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  2055. tty->driver->name );
  2056. /* just return if nothing has changed */
  2057. if ((tty->termios->c_cflag == old_termios->c_cflag)
  2058. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  2059. == RELEVANT_IFLAG(old_termios->c_iflag)))
  2060. return;
  2061. mgslpc_change_params(info);
  2062. /* Handle transition to B0 status */
  2063. if (old_termios->c_cflag & CBAUD &&
  2064. !(tty->termios->c_cflag & CBAUD)) {
  2065. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  2066. spin_lock_irqsave(&info->lock,flags);
  2067. set_signals(info);
  2068. spin_unlock_irqrestore(&info->lock,flags);
  2069. }
  2070. /* Handle transition away from B0 status */
  2071. if (!(old_termios->c_cflag & CBAUD) &&
  2072. tty->termios->c_cflag & CBAUD) {
  2073. info->serial_signals |= SerialSignal_DTR;
  2074. if (!(tty->termios->c_cflag & CRTSCTS) ||
  2075. !test_bit(TTY_THROTTLED, &tty->flags)) {
  2076. info->serial_signals |= SerialSignal_RTS;
  2077. }
  2078. spin_lock_irqsave(&info->lock,flags);
  2079. set_signals(info);
  2080. spin_unlock_irqrestore(&info->lock,flags);
  2081. }
  2082. /* Handle turning off CRTSCTS */
  2083. if (old_termios->c_cflag & CRTSCTS &&
  2084. !(tty->termios->c_cflag & CRTSCTS)) {
  2085. tty->hw_stopped = 0;
  2086. tx_release(tty);
  2087. }
  2088. }
  2089. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  2090. {
  2091. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2092. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  2093. return;
  2094. if (debug_level >= DEBUG_LEVEL_INFO)
  2095. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  2096. __FILE__,__LINE__, info->device_name, info->count);
  2097. if (!info->count)
  2098. return;
  2099. if (tty_hung_up_p(filp))
  2100. goto cleanup;
  2101. if ((tty->count == 1) && (info->count != 1)) {
  2102. /*
  2103. * tty->count is 1 and the tty structure will be freed.
  2104. * info->count should be one in this case.
  2105. * if it's not, correct it so that the port is shutdown.
  2106. */
  2107. printk("mgslpc_close: bad refcount; tty->count is 1, "
  2108. "info->count is %d\n", info->count);
  2109. info->count = 1;
  2110. }
  2111. info->count--;
  2112. /* if at least one open remaining, leave hardware active */
  2113. if (info->count)
  2114. goto cleanup;
  2115. info->flags |= ASYNC_CLOSING;
  2116. /* set tty->closing to notify line discipline to
  2117. * only process XON/XOFF characters. Only the N_TTY
  2118. * discipline appears to use this (ppp does not).
  2119. */
  2120. tty->closing = 1;
  2121. /* wait for transmit data to clear all layers */
  2122. if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
  2123. if (debug_level >= DEBUG_LEVEL_INFO)
  2124. printk("%s(%d):mgslpc_close(%s) calling tty_wait_until_sent\n",
  2125. __FILE__,__LINE__, info->device_name );
  2126. tty_wait_until_sent(tty, info->closing_wait);
  2127. }
  2128. if (info->flags & ASYNC_INITIALIZED)
  2129. mgslpc_wait_until_sent(tty, info->timeout);
  2130. if (tty->driver->flush_buffer)
  2131. tty->driver->flush_buffer(tty);
  2132. ldisc_flush_buffer(tty);
  2133. shutdown(info);
  2134. tty->closing = 0;
  2135. info->tty = NULL;
  2136. if (info->blocked_open) {
  2137. if (info->close_delay) {
  2138. msleep_interruptible(jiffies_to_msecs(info->close_delay));
  2139. }
  2140. wake_up_interruptible(&info->open_wait);
  2141. }
  2142. info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
  2143. wake_up_interruptible(&info->close_wait);
  2144. cleanup:
  2145. if (debug_level >= DEBUG_LEVEL_INFO)
  2146. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  2147. tty->driver->name, info->count);
  2148. }
  2149. /* Wait until the transmitter is empty.
  2150. */
  2151. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  2152. {
  2153. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2154. unsigned long orig_jiffies, char_time;
  2155. if (!info )
  2156. return;
  2157. if (debug_level >= DEBUG_LEVEL_INFO)
  2158. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  2159. __FILE__,__LINE__, info->device_name );
  2160. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  2161. return;
  2162. if (!(info->flags & ASYNC_INITIALIZED))
  2163. goto exit;
  2164. orig_jiffies = jiffies;
  2165. /* Set check interval to 1/5 of estimated time to
  2166. * send a character, and make it at least 1. The check
  2167. * interval should also be less than the timeout.
  2168. * Note: use tight timings here to satisfy the NIST-PCTS.
  2169. */
  2170. if ( info->params.data_rate ) {
  2171. char_time = info->timeout/(32 * 5);
  2172. if (!char_time)
  2173. char_time++;
  2174. } else
  2175. char_time = 1;
  2176. if (timeout)
  2177. char_time = min_t(unsigned long, char_time, timeout);
  2178. if (info->params.mode == MGSL_MODE_HDLC) {
  2179. while (info->tx_active) {
  2180. msleep_interruptible(jiffies_to_msecs(char_time));
  2181. if (signal_pending(current))
  2182. break;
  2183. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2184. break;
  2185. }
  2186. } else {
  2187. while ((info->tx_count || info->tx_active) &&
  2188. info->tx_enabled) {
  2189. msleep_interruptible(jiffies_to_msecs(char_time));
  2190. if (signal_pending(current))
  2191. break;
  2192. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2193. break;
  2194. }
  2195. }
  2196. exit:
  2197. if (debug_level >= DEBUG_LEVEL_INFO)
  2198. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2199. __FILE__,__LINE__, info->device_name );
  2200. }
  2201. /* Called by tty_hangup() when a hangup is signaled.
  2202. * This is the same as closing all open files for the port.
  2203. */
  2204. static void mgslpc_hangup(struct tty_struct *tty)
  2205. {
  2206. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2207. if (debug_level >= DEBUG_LEVEL_INFO)
  2208. printk("%s(%d):mgslpc_hangup(%s)\n",
  2209. __FILE__,__LINE__, info->device_name );
  2210. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2211. return;
  2212. mgslpc_flush_buffer(tty);
  2213. shutdown(info);
  2214. info->count = 0;
  2215. info->flags &= ~ASYNC_NORMAL_ACTIVE;
  2216. info->tty = NULL;
  2217. wake_up_interruptible(&info->open_wait);
  2218. }
  2219. /* Block the current process until the specified port
  2220. * is ready to be opened.
  2221. */
  2222. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2223. MGSLPC_INFO *info)
  2224. {
  2225. DECLARE_WAITQUEUE(wait, current);
  2226. int retval;
  2227. int do_clocal = 0, extra_count = 0;
  2228. unsigned long flags;
  2229. if (debug_level >= DEBUG_LEVEL_INFO)
  2230. printk("%s(%d):block_til_ready on %s\n",
  2231. __FILE__,__LINE__, tty->driver->name );
  2232. if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
  2233. /* nonblock mode is set or port is not enabled */
  2234. /* just verify that callout device is not active */
  2235. info->flags |= ASYNC_NORMAL_ACTIVE;
  2236. return 0;
  2237. }
  2238. if (tty->termios->c_cflag & CLOCAL)
  2239. do_clocal = 1;
  2240. /* Wait for carrier detect and the line to become
  2241. * free (i.e., not in use by the callout). While we are in
  2242. * this loop, info->count is dropped by one, so that
  2243. * mgslpc_close() knows when to free things. We restore it upon
  2244. * exit, either normal or abnormal.
  2245. */
  2246. retval = 0;
  2247. add_wait_queue(&info->open_wait, &wait);
  2248. if (debug_level >= DEBUG_LEVEL_INFO)
  2249. printk("%s(%d):block_til_ready before block on %s count=%d\n",
  2250. __FILE__,__LINE__, tty->driver->name, info->count );
  2251. spin_lock_irqsave(&info->lock, flags);
  2252. if (!tty_hung_up_p(filp)) {
  2253. extra_count = 1;
  2254. info->count--;
  2255. }
  2256. spin_unlock_irqrestore(&info->lock, flags);
  2257. info->blocked_open++;
  2258. while (1) {
  2259. if ((tty->termios->c_cflag & CBAUD)) {
  2260. spin_lock_irqsave(&info->lock,flags);
  2261. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2262. set_signals(info);
  2263. spin_unlock_irqrestore(&info->lock,flags);
  2264. }
  2265. set_current_state(TASK_INTERRUPTIBLE);
  2266. if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
  2267. retval = (info->flags & ASYNC_HUP_NOTIFY) ?
  2268. -EAGAIN : -ERESTARTSYS;
  2269. break;
  2270. }
  2271. spin_lock_irqsave(&info->lock,flags);
  2272. get_signals(info);
  2273. spin_unlock_irqrestore(&info->lock,flags);
  2274. if (!(info->flags & ASYNC_CLOSING) &&
  2275. (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
  2276. break;
  2277. }
  2278. if (signal_pending(current)) {
  2279. retval = -ERESTARTSYS;
  2280. break;
  2281. }
  2282. if (debug_level >= DEBUG_LEVEL_INFO)
  2283. printk("%s(%d):block_til_ready blocking on %s count=%d\n",
  2284. __FILE__,__LINE__, tty->driver->name, info->count );
  2285. schedule();
  2286. }
  2287. set_current_state(TASK_RUNNING);
  2288. remove_wait_queue(&info->open_wait, &wait);
  2289. if (extra_count)
  2290. info->count++;
  2291. info->blocked_open--;
  2292. if (debug_level >= DEBUG_LEVEL_INFO)
  2293. printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
  2294. __FILE__,__LINE__, tty->driver->name, info->count );
  2295. if (!retval)
  2296. info->flags |= ASYNC_NORMAL_ACTIVE;
  2297. return retval;
  2298. }
  2299. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2300. {
  2301. MGSLPC_INFO *info;
  2302. int retval, line;
  2303. unsigned long flags;
  2304. /* verify range of specified line number */
  2305. line = tty->index;
  2306. if ((line < 0) || (line >= mgslpc_device_count)) {
  2307. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2308. __FILE__,__LINE__,line);
  2309. return -ENODEV;
  2310. }
  2311. /* find the info structure for the specified line */
  2312. info = mgslpc_device_list;
  2313. while(info && info->line != line)
  2314. info = info->next_device;
  2315. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2316. return -ENODEV;
  2317. tty->driver_data = info;
  2318. info->tty = tty;
  2319. if (debug_level >= DEBUG_LEVEL_INFO)
  2320. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2321. __FILE__,__LINE__,tty->driver->name, info->count);
  2322. /* If port is closing, signal caller to try again */
  2323. if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
  2324. if (info->flags & ASYNC_CLOSING)
  2325. interruptible_sleep_on(&info->close_wait);
  2326. retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
  2327. -EAGAIN : -ERESTARTSYS);
  2328. goto cleanup;
  2329. }
  2330. info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2331. spin_lock_irqsave(&info->netlock, flags);
  2332. if (info->netcount) {
  2333. retval = -EBUSY;
  2334. spin_unlock_irqrestore(&info->netlock, flags);
  2335. goto cleanup;
  2336. }
  2337. info->count++;
  2338. spin_unlock_irqrestore(&info->netlock, flags);
  2339. if (info->count == 1) {
  2340. /* 1st open on this device, init hardware */
  2341. retval = startup(info);
  2342. if (retval < 0)
  2343. goto cleanup;
  2344. }
  2345. retval = block_til_ready(tty, filp, info);
  2346. if (retval) {
  2347. if (debug_level >= DEBUG_LEVEL_INFO)
  2348. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2349. __FILE__,__LINE__, info->device_name, retval);
  2350. goto cleanup;
  2351. }
  2352. if (debug_level >= DEBUG_LEVEL_INFO)
  2353. printk("%s(%d):mgslpc_open(%s) success\n",
  2354. __FILE__,__LINE__, info->device_name);
  2355. retval = 0;
  2356. cleanup:
  2357. if (retval) {
  2358. if (tty->count == 1)
  2359. info->tty = NULL; /* tty layer will release tty struct */
  2360. if(info->count)
  2361. info->count--;
  2362. }
  2363. return retval;
  2364. }
  2365. /*
  2366. * /proc fs routines....
  2367. */
  2368. static inline int line_info(char *buf, MGSLPC_INFO *info)
  2369. {
  2370. char stat_buf[30];
  2371. int ret;
  2372. unsigned long flags;
  2373. ret = sprintf(buf, "%s:io:%04X irq:%d",
  2374. info->device_name, info->io_base, info->irq_level);
  2375. /* output current serial signal states */
  2376. spin_lock_irqsave(&info->lock,flags);
  2377. get_signals(info);
  2378. spin_unlock_irqrestore(&info->lock,flags);
  2379. stat_buf[0] = 0;
  2380. stat_buf[1] = 0;
  2381. if (info->serial_signals & SerialSignal_RTS)
  2382. strcat(stat_buf, "|RTS");
  2383. if (info->serial_signals & SerialSignal_CTS)
  2384. strcat(stat_buf, "|CTS");
  2385. if (info->serial_signals & SerialSignal_DTR)
  2386. strcat(stat_buf, "|DTR");
  2387. if (info->serial_signals & SerialSignal_DSR)
  2388. strcat(stat_buf, "|DSR");
  2389. if (info->serial_signals & SerialSignal_DCD)
  2390. strcat(stat_buf, "|CD");
  2391. if (info->serial_signals & SerialSignal_RI)
  2392. strcat(stat_buf, "|RI");
  2393. if (info->params.mode == MGSL_MODE_HDLC) {
  2394. ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
  2395. info->icount.txok, info->icount.rxok);
  2396. if (info->icount.txunder)
  2397. ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
  2398. if (info->icount.txabort)
  2399. ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
  2400. if (info->icount.rxshort)
  2401. ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
  2402. if (info->icount.rxlong)
  2403. ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
  2404. if (info->icount.rxover)
  2405. ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
  2406. if (info->icount.rxcrc)
  2407. ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
  2408. } else {
  2409. ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
  2410. info->icount.tx, info->icount.rx);
  2411. if (info->icount.frame)
  2412. ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
  2413. if (info->icount.parity)
  2414. ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
  2415. if (info->icount.brk)
  2416. ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
  2417. if (info->icount.overrun)
  2418. ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
  2419. }
  2420. /* Append serial signal status to end */
  2421. ret += sprintf(buf+ret, " %s\n", stat_buf+1);
  2422. ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2423. info->tx_active,info->bh_requested,info->bh_running,
  2424. info->pending_bh);
  2425. return ret;
  2426. }
  2427. /* Called to print information about devices
  2428. */
  2429. static int mgslpc_read_proc(char *page, char **start, off_t off, int count,
  2430. int *eof, void *data)
  2431. {
  2432. int len = 0, l;
  2433. off_t begin = 0;
  2434. MGSLPC_INFO *info;
  2435. len += sprintf(page, "synclink driver:%s\n", driver_version);
  2436. info = mgslpc_device_list;
  2437. while( info ) {
  2438. l = line_info(page + len, info);
  2439. len += l;
  2440. if (len+begin > off+count)
  2441. goto done;
  2442. if (len+begin < off) {
  2443. begin += len;
  2444. len = 0;
  2445. }
  2446. info = info->next_device;
  2447. }
  2448. *eof = 1;
  2449. done:
  2450. if (off >= len+begin)
  2451. return 0;
  2452. *start = page + (off-begin);
  2453. return ((count < begin+len-off) ? count : begin+len-off);
  2454. }
  2455. int rx_alloc_buffers(MGSLPC_INFO *info)
  2456. {
  2457. /* each buffer has header and data */
  2458. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2459. /* calculate total allocation size for 8 buffers */
  2460. info->rx_buf_total_size = info->rx_buf_size * 8;
  2461. /* limit total allocated memory */
  2462. if (info->rx_buf_total_size > 0x10000)
  2463. info->rx_buf_total_size = 0x10000;
  2464. /* calculate number of buffers */
  2465. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2466. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2467. if (info->rx_buf == NULL)
  2468. return -ENOMEM;
  2469. rx_reset_buffers(info);
  2470. return 0;
  2471. }
  2472. void rx_free_buffers(MGSLPC_INFO *info)
  2473. {
  2474. kfree(info->rx_buf);
  2475. info->rx_buf = NULL;
  2476. }
  2477. int claim_resources(MGSLPC_INFO *info)
  2478. {
  2479. if (rx_alloc_buffers(info) < 0 ) {
  2480. printk( "Cant allocate rx buffer %s\n", info->device_name);
  2481. release_resources(info);
  2482. return -ENODEV;
  2483. }
  2484. return 0;
  2485. }
  2486. void release_resources(MGSLPC_INFO *info)
  2487. {
  2488. if (debug_level >= DEBUG_LEVEL_INFO)
  2489. printk("release_resources(%s)\n", info->device_name);
  2490. rx_free_buffers(info);
  2491. }
  2492. /* Add the specified device instance data structure to the
  2493. * global linked list of devices and increment the device count.
  2494. *
  2495. * Arguments: info pointer to device instance data
  2496. */
  2497. void mgslpc_add_device(MGSLPC_INFO *info)
  2498. {
  2499. info->next_device = NULL;
  2500. info->line = mgslpc_device_count;
  2501. sprintf(info->device_name,"ttySLP%d",info->line);
  2502. if (info->line < MAX_DEVICE_COUNT) {
  2503. if (maxframe[info->line])
  2504. info->max_frame_size = maxframe[info->line];
  2505. info->dosyncppp = dosyncppp[info->line];
  2506. }
  2507. mgslpc_device_count++;
  2508. if (!mgslpc_device_list)
  2509. mgslpc_device_list = info;
  2510. else {
  2511. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2512. while( current_dev->next_device )
  2513. current_dev = current_dev->next_device;
  2514. current_dev->next_device = info;
  2515. }
  2516. if (info->max_frame_size < 4096)
  2517. info->max_frame_size = 4096;
  2518. else if (info->max_frame_size > 65535)
  2519. info->max_frame_size = 65535;
  2520. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2521. info->device_name, info->io_base, info->irq_level);
  2522. #ifdef CONFIG_HDLC
  2523. hdlcdev_init(info);
  2524. #endif
  2525. }
  2526. void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2527. {
  2528. MGSLPC_INFO *info = mgslpc_device_list;
  2529. MGSLPC_INFO *last = NULL;
  2530. while(info) {
  2531. if (info == remove_info) {
  2532. if (last)
  2533. last->next_device = info->next_device;
  2534. else
  2535. mgslpc_device_list = info->next_device;
  2536. #ifdef CONFIG_HDLC
  2537. hdlcdev_exit(info);
  2538. #endif
  2539. release_resources(info);
  2540. kfree(info);
  2541. mgslpc_device_count--;
  2542. return;
  2543. }
  2544. last = info;
  2545. info = info->next_device;
  2546. }
  2547. }
  2548. static struct pcmcia_device_id mgslpc_ids[] = {
  2549. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2550. PCMCIA_DEVICE_NULL
  2551. };
  2552. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2553. static struct pcmcia_driver mgslpc_driver = {
  2554. .owner = THIS_MODULE,
  2555. .drv = {
  2556. .name = "synclink_cs",
  2557. },
  2558. .attach = mgslpc_attach,
  2559. .event = mgslpc_event,
  2560. .remove = mgslpc_detach,
  2561. .id_table = mgslpc_ids,
  2562. .suspend = mgslpc_suspend,
  2563. .resume = mgslpc_resume,
  2564. };
  2565. static struct tty_operations mgslpc_ops = {
  2566. .open = mgslpc_open,
  2567. .close = mgslpc_close,
  2568. .write = mgslpc_write,
  2569. .put_char = mgslpc_put_char,
  2570. .flush_chars = mgslpc_flush_chars,
  2571. .write_room = mgslpc_write_room,
  2572. .chars_in_buffer = mgslpc_chars_in_buffer,
  2573. .flush_buffer = mgslpc_flush_buffer,
  2574. .ioctl = mgslpc_ioctl,
  2575. .throttle = mgslpc_throttle,
  2576. .unthrottle = mgslpc_unthrottle,
  2577. .send_xchar = mgslpc_send_xchar,
  2578. .break_ctl = mgslpc_break,
  2579. .wait_until_sent = mgslpc_wait_until_sent,
  2580. .read_proc = mgslpc_read_proc,
  2581. .set_termios = mgslpc_set_termios,
  2582. .stop = tx_pause,
  2583. .start = tx_release,
  2584. .hangup = mgslpc_hangup,
  2585. .tiocmget = tiocmget,
  2586. .tiocmset = tiocmset,
  2587. };
  2588. static void synclink_cs_cleanup(void)
  2589. {
  2590. int rc;
  2591. printk("Unloading %s: version %s\n", driver_name, driver_version);
  2592. while(mgslpc_device_list)
  2593. mgslpc_remove_device(mgslpc_device_list);
  2594. if (serial_driver) {
  2595. if ((rc = tty_unregister_driver(serial_driver)))
  2596. printk("%s(%d) failed to unregister tty driver err=%d\n",
  2597. __FILE__,__LINE__,rc);
  2598. put_tty_driver(serial_driver);
  2599. }
  2600. pcmcia_unregister_driver(&mgslpc_driver);
  2601. }
  2602. static int __init synclink_cs_init(void)
  2603. {
  2604. int rc;
  2605. if (break_on_load) {
  2606. mgslpc_get_text_ptr();
  2607. BREAKPOINT();
  2608. }
  2609. printk("%s %s\n", driver_name, driver_version);
  2610. if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
  2611. return rc;
  2612. serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
  2613. if (!serial_driver) {
  2614. rc = -ENOMEM;
  2615. goto error;
  2616. }
  2617. /* Initialize the tty_driver structure */
  2618. serial_driver->owner = THIS_MODULE;
  2619. serial_driver->driver_name = "synclink_cs";
  2620. serial_driver->name = "ttySLP";
  2621. serial_driver->major = ttymajor;
  2622. serial_driver->minor_start = 64;
  2623. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2624. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2625. serial_driver->init_termios = tty_std_termios;
  2626. serial_driver->init_termios.c_cflag =
  2627. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2628. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  2629. tty_set_operations(serial_driver, &mgslpc_ops);
  2630. if ((rc = tty_register_driver(serial_driver)) < 0) {
  2631. printk("%s(%d):Couldn't register serial driver\n",
  2632. __FILE__,__LINE__);
  2633. put_tty_driver(serial_driver);
  2634. serial_driver = NULL;
  2635. goto error;
  2636. }
  2637. printk("%s %s, tty major#%d\n",
  2638. driver_name, driver_version,
  2639. serial_driver->major);
  2640. return 0;
  2641. error:
  2642. synclink_cs_cleanup();
  2643. return rc;
  2644. }
  2645. static void __exit synclink_cs_exit(void)
  2646. {
  2647. synclink_cs_cleanup();
  2648. }
  2649. module_init(synclink_cs_init);
  2650. module_exit(synclink_cs_exit);
  2651. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2652. {
  2653. unsigned int M, N;
  2654. unsigned char val;
  2655. /* note:standard BRG mode is broken in V3.2 chip
  2656. * so enhanced mode is always used
  2657. */
  2658. if (rate) {
  2659. N = 3686400 / rate;
  2660. if (!N)
  2661. N = 1;
  2662. N >>= 1;
  2663. for (M = 1; N > 64 && M < 16; M++)
  2664. N >>= 1;
  2665. N--;
  2666. /* BGR[5..0] = N
  2667. * BGR[9..6] = M
  2668. * BGR[7..0] contained in BGR register
  2669. * BGR[9..8] contained in CCR2[7..6]
  2670. * divisor = (N+1)*2^M
  2671. *
  2672. * Note: M *must* not be zero (causes asymetric duty cycle)
  2673. */
  2674. write_reg(info, (unsigned char) (channel + BGR),
  2675. (unsigned char) ((M << 6) + N));
  2676. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2677. val |= ((M << 4) & 0xc0);
  2678. write_reg(info, (unsigned char) (channel + CCR2), val);
  2679. }
  2680. }
  2681. /* Enabled the AUX clock output at the specified frequency.
  2682. */
  2683. static void enable_auxclk(MGSLPC_INFO *info)
  2684. {
  2685. unsigned char val;
  2686. /* MODE
  2687. *
  2688. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2689. * 05 ADM Address Mode, 0 = no addr recognition
  2690. * 04 TMD Timer Mode, 0 = external
  2691. * 03 RAC Receiver Active, 0 = inactive
  2692. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2693. * 01 TRS Timer Resolution, 1=512
  2694. * 00 TLP Test Loop, 0 = no loop
  2695. *
  2696. * 1000 0010
  2697. */
  2698. val = 0x82;
  2699. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2700. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2701. val |= BIT2;
  2702. write_reg(info, CHB + MODE, val);
  2703. /* CCR0
  2704. *
  2705. * 07 PU Power Up, 1=active, 0=power down
  2706. * 06 MCE Master Clock Enable, 1=enabled
  2707. * 05 Reserved, 0
  2708. * 04..02 SC[2..0] Encoding
  2709. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2710. *
  2711. * 11000000
  2712. */
  2713. write_reg(info, CHB + CCR0, 0xc0);
  2714. /* CCR1
  2715. *
  2716. * 07 SFLG Shared Flag, 0 = disable shared flags
  2717. * 06 GALP Go Active On Loop, 0 = not used
  2718. * 05 GLP Go On Loop, 0 = not used
  2719. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2720. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2721. * 02..00 CM[2..0] Clock Mode
  2722. *
  2723. * 0001 0111
  2724. */
  2725. write_reg(info, CHB + CCR1, 0x17);
  2726. /* CCR2 (Channel B)
  2727. *
  2728. * 07..06 BGR[9..8] Baud rate bits 9..8
  2729. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2730. * 04 SSEL Clock source select, 1=submode b
  2731. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2732. * 02 RWX Read/Write Exchange 0=disabled
  2733. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2734. * 00 DIV, data inversion 0=disabled, 1=enabled
  2735. *
  2736. * 0011 1000
  2737. */
  2738. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2739. write_reg(info, CHB + CCR2, 0x38);
  2740. else
  2741. write_reg(info, CHB + CCR2, 0x30);
  2742. /* CCR4
  2743. *
  2744. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2745. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2746. * 05 TST1 Test Pin, 0=normal operation
  2747. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2748. * 03..02 Reserved, must be 0
  2749. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2750. *
  2751. * 0101 0000
  2752. */
  2753. write_reg(info, CHB + CCR4, 0x50);
  2754. /* if auxclk not enabled, set internal BRG so
  2755. * CTS transitions can be detected (requires TxC)
  2756. */
  2757. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2758. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2759. else
  2760. mgslpc_set_rate(info, CHB, 921600);
  2761. }
  2762. static void loopback_enable(MGSLPC_INFO *info)
  2763. {
  2764. unsigned char val;
  2765. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2766. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2767. write_reg(info, CHA + CCR1, val);
  2768. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2769. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2770. write_reg(info, CHA + CCR2, val);
  2771. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2772. if (info->params.clock_speed)
  2773. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2774. else
  2775. mgslpc_set_rate(info, CHA, 1843200);
  2776. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2777. val = read_reg(info, CHA + MODE) | BIT0;
  2778. write_reg(info, CHA + MODE, val);
  2779. }
  2780. void hdlc_mode(MGSLPC_INFO *info)
  2781. {
  2782. unsigned char val;
  2783. unsigned char clkmode, clksubmode;
  2784. /* disable all interrupts */
  2785. irq_disable(info, CHA, 0xffff);
  2786. irq_disable(info, CHB, 0xffff);
  2787. port_irq_disable(info, 0xff);
  2788. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2789. clkmode = clksubmode = 0;
  2790. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2791. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2792. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2793. clkmode = 7;
  2794. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2795. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2796. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2797. clkmode = 7;
  2798. clksubmode = 1;
  2799. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2800. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2801. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2802. clkmode = 6;
  2803. clksubmode = 1;
  2804. } else {
  2805. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2806. clkmode = 6;
  2807. }
  2808. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2809. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2810. clksubmode = 1;
  2811. }
  2812. /* MODE
  2813. *
  2814. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2815. * 05 ADM Address Mode, 0 = no addr recognition
  2816. * 04 TMD Timer Mode, 0 = external
  2817. * 03 RAC Receiver Active, 0 = inactive
  2818. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2819. * 01 TRS Timer Resolution, 1=512
  2820. * 00 TLP Test Loop, 0 = no loop
  2821. *
  2822. * 1000 0010
  2823. */
  2824. val = 0x82;
  2825. if (info->params.loopback)
  2826. val |= BIT0;
  2827. /* preserve RTS state */
  2828. if (info->serial_signals & SerialSignal_RTS)
  2829. val |= BIT2;
  2830. write_reg(info, CHA + MODE, val);
  2831. /* CCR0
  2832. *
  2833. * 07 PU Power Up, 1=active, 0=power down
  2834. * 06 MCE Master Clock Enable, 1=enabled
  2835. * 05 Reserved, 0
  2836. * 04..02 SC[2..0] Encoding
  2837. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2838. *
  2839. * 11000000
  2840. */
  2841. val = 0xc0;
  2842. switch (info->params.encoding)
  2843. {
  2844. case HDLC_ENCODING_NRZI:
  2845. val |= BIT3;
  2846. break;
  2847. case HDLC_ENCODING_BIPHASE_SPACE:
  2848. val |= BIT4;
  2849. break; // FM0
  2850. case HDLC_ENCODING_BIPHASE_MARK:
  2851. val |= BIT4 + BIT2;
  2852. break; // FM1
  2853. case HDLC_ENCODING_BIPHASE_LEVEL:
  2854. val |= BIT4 + BIT3;
  2855. break; // Manchester
  2856. }
  2857. write_reg(info, CHA + CCR0, val);
  2858. /* CCR1
  2859. *
  2860. * 07 SFLG Shared Flag, 0 = disable shared flags
  2861. * 06 GALP Go Active On Loop, 0 = not used
  2862. * 05 GLP Go On Loop, 0 = not used
  2863. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2864. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2865. * 02..00 CM[2..0] Clock Mode
  2866. *
  2867. * 0001 0000
  2868. */
  2869. val = 0x10 + clkmode;
  2870. write_reg(info, CHA + CCR1, val);
  2871. /* CCR2
  2872. *
  2873. * 07..06 BGR[9..8] Baud rate bits 9..8
  2874. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2875. * 04 SSEL Clock source select, 1=submode b
  2876. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2877. * 02 RWX Read/Write Exchange 0=disabled
  2878. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2879. * 00 DIV, data inversion 0=disabled, 1=enabled
  2880. *
  2881. * 0000 0000
  2882. */
  2883. val = 0x00;
  2884. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2885. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2886. val |= BIT5;
  2887. if (clksubmode)
  2888. val |= BIT4;
  2889. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2890. val |= BIT1;
  2891. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2892. val |= BIT0;
  2893. write_reg(info, CHA + CCR2, val);
  2894. /* CCR3
  2895. *
  2896. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2897. * 05 EPT Enable preamble transmission, 1=enabled
  2898. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2899. * 03 CRL CRC Reset Level, 0=FFFF
  2900. * 02 RCRC Rx CRC 0=On 1=Off
  2901. * 01 TCRC Tx CRC 0=On 1=Off
  2902. * 00 PSD DPLL Phase Shift Disable
  2903. *
  2904. * 0000 0000
  2905. */
  2906. val = 0x00;
  2907. if (info->params.crc_type == HDLC_CRC_NONE)
  2908. val |= BIT2 + BIT1;
  2909. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2910. val |= BIT5;
  2911. switch (info->params.preamble_length)
  2912. {
  2913. case HDLC_PREAMBLE_LENGTH_16BITS:
  2914. val |= BIT6;
  2915. break;
  2916. case HDLC_PREAMBLE_LENGTH_32BITS:
  2917. val |= BIT6;
  2918. break;
  2919. case HDLC_PREAMBLE_LENGTH_64BITS:
  2920. val |= BIT7 + BIT6;
  2921. break;
  2922. }
  2923. write_reg(info, CHA + CCR3, val);
  2924. /* PRE - Preamble pattern */
  2925. val = 0;
  2926. switch (info->params.preamble)
  2927. {
  2928. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2929. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2930. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2931. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2932. }
  2933. write_reg(info, CHA + PRE, val);
  2934. /* CCR4
  2935. *
  2936. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2937. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2938. * 05 TST1 Test Pin, 0=normal operation
  2939. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2940. * 03..02 Reserved, must be 0
  2941. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2942. *
  2943. * 0101 0000
  2944. */
  2945. val = 0x50;
  2946. write_reg(info, CHA + CCR4, val);
  2947. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2948. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2949. else
  2950. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2951. /* RLCR Receive length check register
  2952. *
  2953. * 7 1=enable receive length check
  2954. * 6..0 Max frame length = (RL + 1) * 32
  2955. */
  2956. write_reg(info, CHA + RLCR, 0);
  2957. /* XBCH Transmit Byte Count High
  2958. *
  2959. * 07 DMA mode, 0 = interrupt driven
  2960. * 06 NRM, 0=ABM (ignored)
  2961. * 05 CAS Carrier Auto Start
  2962. * 04 XC Transmit Continuously (ignored)
  2963. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2964. *
  2965. * 0000 0000
  2966. */
  2967. val = 0x00;
  2968. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2969. val |= BIT5;
  2970. write_reg(info, CHA + XBCH, val);
  2971. enable_auxclk(info);
  2972. if (info->params.loopback || info->testing_irq)
  2973. loopback_enable(info);
  2974. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2975. {
  2976. irq_enable(info, CHB, IRQ_CTS);
  2977. /* PVR[3] 1=AUTO CTS active */
  2978. set_reg_bits(info, CHA + PVR, BIT3);
  2979. } else
  2980. clear_reg_bits(info, CHA + PVR, BIT3);
  2981. irq_enable(info, CHA,
  2982. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2983. IRQ_UNDERRUN + IRQ_TXFIFO);
  2984. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2985. wait_command_complete(info, CHA);
  2986. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2987. /* Master clock mode enabled above to allow reset commands
  2988. * to complete even if no data clocks are present.
  2989. *
  2990. * Disable master clock mode for normal communications because
  2991. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2992. * IRQ when in master clock mode.
  2993. *
  2994. * Leave master clock mode enabled for IRQ test because the
  2995. * timer IRQ used by the test can only happen in master clock mode.
  2996. */
  2997. if (!info->testing_irq)
  2998. clear_reg_bits(info, CHA + CCR0, BIT6);
  2999. tx_set_idle(info);
  3000. tx_stop(info);
  3001. rx_stop(info);
  3002. }
  3003. void rx_stop(MGSLPC_INFO *info)
  3004. {
  3005. if (debug_level >= DEBUG_LEVEL_ISR)
  3006. printk("%s(%d):rx_stop(%s)\n",
  3007. __FILE__,__LINE__, info->device_name );
  3008. /* MODE:03 RAC Receiver Active, 0=inactive */
  3009. clear_reg_bits(info, CHA + MODE, BIT3);
  3010. info->rx_enabled = 0;
  3011. info->rx_overflow = 0;
  3012. }
  3013. void rx_start(MGSLPC_INFO *info)
  3014. {
  3015. if (debug_level >= DEBUG_LEVEL_ISR)
  3016. printk("%s(%d):rx_start(%s)\n",
  3017. __FILE__,__LINE__, info->device_name );
  3018. rx_reset_buffers(info);
  3019. info->rx_enabled = 0;
  3020. info->rx_overflow = 0;
  3021. /* MODE:03 RAC Receiver Active, 1=active */
  3022. set_reg_bits(info, CHA + MODE, BIT3);
  3023. info->rx_enabled = 1;
  3024. }
  3025. void tx_start(MGSLPC_INFO *info)
  3026. {
  3027. if (debug_level >= DEBUG_LEVEL_ISR)
  3028. printk("%s(%d):tx_start(%s)\n",
  3029. __FILE__,__LINE__, info->device_name );
  3030. if (info->tx_count) {
  3031. /* If auto RTS enabled and RTS is inactive, then assert */
  3032. /* RTS and set a flag indicating that the driver should */
  3033. /* negate RTS when the transmission completes. */
  3034. info->drop_rts_on_tx_done = 0;
  3035. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  3036. get_signals(info);
  3037. if (!(info->serial_signals & SerialSignal_RTS)) {
  3038. info->serial_signals |= SerialSignal_RTS;
  3039. set_signals(info);
  3040. info->drop_rts_on_tx_done = 1;
  3041. }
  3042. }
  3043. if (info->params.mode == MGSL_MODE_ASYNC) {
  3044. if (!info->tx_active) {
  3045. info->tx_active = 1;
  3046. tx_ready(info);
  3047. }
  3048. } else {
  3049. info->tx_active = 1;
  3050. tx_ready(info);
  3051. info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
  3052. add_timer(&info->tx_timer);
  3053. }
  3054. }
  3055. if (!info->tx_enabled)
  3056. info->tx_enabled = 1;
  3057. }
  3058. void tx_stop(MGSLPC_INFO *info)
  3059. {
  3060. if (debug_level >= DEBUG_LEVEL_ISR)
  3061. printk("%s(%d):tx_stop(%s)\n",
  3062. __FILE__,__LINE__, info->device_name );
  3063. del_timer(&info->tx_timer);
  3064. info->tx_enabled = 0;
  3065. info->tx_active = 0;
  3066. }
  3067. /* Reset the adapter to a known state and prepare it for further use.
  3068. */
  3069. void reset_device(MGSLPC_INFO *info)
  3070. {
  3071. /* power up both channels (set BIT7) */
  3072. write_reg(info, CHA + CCR0, 0x80);
  3073. write_reg(info, CHB + CCR0, 0x80);
  3074. write_reg(info, CHA + MODE, 0);
  3075. write_reg(info, CHB + MODE, 0);
  3076. /* disable all interrupts */
  3077. irq_disable(info, CHA, 0xffff);
  3078. irq_disable(info, CHB, 0xffff);
  3079. port_irq_disable(info, 0xff);
  3080. /* PCR Port Configuration Register
  3081. *
  3082. * 07..04 DEC[3..0] Serial I/F select outputs
  3083. * 03 output, 1=AUTO CTS control enabled
  3084. * 02 RI Ring Indicator input 0=active
  3085. * 01 DSR input 0=active
  3086. * 00 DTR output 0=active
  3087. *
  3088. * 0000 0110
  3089. */
  3090. write_reg(info, PCR, 0x06);
  3091. /* PVR Port Value Register
  3092. *
  3093. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  3094. * 03 AUTO CTS output 1=enabled
  3095. * 02 RI Ring Indicator input
  3096. * 01 DSR input
  3097. * 00 DTR output (1=inactive)
  3098. *
  3099. * 0000 0001
  3100. */
  3101. // write_reg(info, PVR, PVR_DTR);
  3102. /* IPC Interrupt Port Configuration
  3103. *
  3104. * 07 VIS 1=Masked interrupts visible
  3105. * 06..05 Reserved, 0
  3106. * 04..03 SLA Slave address, 00 ignored
  3107. * 02 CASM Cascading Mode, 1=daisy chain
  3108. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  3109. *
  3110. * 0000 0101
  3111. */
  3112. write_reg(info, IPC, 0x05);
  3113. }
  3114. void async_mode(MGSLPC_INFO *info)
  3115. {
  3116. unsigned char val;
  3117. /* disable all interrupts */
  3118. irq_disable(info, CHA, 0xffff);
  3119. irq_disable(info, CHB, 0xffff);
  3120. port_irq_disable(info, 0xff);
  3121. /* MODE
  3122. *
  3123. * 07 Reserved, 0
  3124. * 06 FRTS RTS State, 0=active
  3125. * 05 FCTS Flow Control on CTS
  3126. * 04 FLON Flow Control Enable
  3127. * 03 RAC Receiver Active, 0 = inactive
  3128. * 02 RTS 0=Auto RTS, 1=manual RTS
  3129. * 01 TRS Timer Resolution, 1=512
  3130. * 00 TLP Test Loop, 0 = no loop
  3131. *
  3132. * 0000 0110
  3133. */
  3134. val = 0x06;
  3135. if (info->params.loopback)
  3136. val |= BIT0;
  3137. /* preserve RTS state */
  3138. if (!(info->serial_signals & SerialSignal_RTS))
  3139. val |= BIT6;
  3140. write_reg(info, CHA + MODE, val);
  3141. /* CCR0
  3142. *
  3143. * 07 PU Power Up, 1=active, 0=power down
  3144. * 06 MCE Master Clock Enable, 1=enabled
  3145. * 05 Reserved, 0
  3146. * 04..02 SC[2..0] Encoding, 000=NRZ
  3147. * 01..00 SM[1..0] Serial Mode, 11=Async
  3148. *
  3149. * 1000 0011
  3150. */
  3151. write_reg(info, CHA + CCR0, 0x83);
  3152. /* CCR1
  3153. *
  3154. * 07..05 Reserved, 0
  3155. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  3156. * 03 BCR Bit Clock Rate, 1=16x
  3157. * 02..00 CM[2..0] Clock Mode, 111=BRG
  3158. *
  3159. * 0001 1111
  3160. */
  3161. write_reg(info, CHA + CCR1, 0x1f);
  3162. /* CCR2 (channel A)
  3163. *
  3164. * 07..06 BGR[9..8] Baud rate bits 9..8
  3165. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  3166. * 04 SSEL Clock source select, 1=submode b
  3167. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  3168. * 02 RWX Read/Write Exchange 0=disabled
  3169. * 01 Reserved, 0
  3170. * 00 DIV, data inversion 0=disabled, 1=enabled
  3171. *
  3172. * 0001 0000
  3173. */
  3174. write_reg(info, CHA + CCR2, 0x10);
  3175. /* CCR3
  3176. *
  3177. * 07..01 Reserved, 0
  3178. * 00 PSD DPLL Phase Shift Disable
  3179. *
  3180. * 0000 0000
  3181. */
  3182. write_reg(info, CHA + CCR3, 0);
  3183. /* CCR4
  3184. *
  3185. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  3186. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  3187. * 05 TST1 Test Pin, 0=normal operation
  3188. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  3189. * 03..00 Reserved, must be 0
  3190. *
  3191. * 0101 0000
  3192. */
  3193. write_reg(info, CHA + CCR4, 0x50);
  3194. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  3195. /* DAFO Data Format
  3196. *
  3197. * 07 Reserved, 0
  3198. * 06 XBRK transmit break, 0=normal operation
  3199. * 05 Stop bits (0=1, 1=2)
  3200. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  3201. * 02 PAREN Parity Enable
  3202. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  3203. *
  3204. */
  3205. val = 0x00;
  3206. if (info->params.data_bits != 8)
  3207. val |= BIT0; /* 7 bits */
  3208. if (info->params.stop_bits != 1)
  3209. val |= BIT5;
  3210. if (info->params.parity != ASYNC_PARITY_NONE)
  3211. {
  3212. val |= BIT2; /* Parity enable */
  3213. if (info->params.parity == ASYNC_PARITY_ODD)
  3214. val |= BIT3;
  3215. else
  3216. val |= BIT4;
  3217. }
  3218. write_reg(info, CHA + DAFO, val);
  3219. /* RFC Rx FIFO Control
  3220. *
  3221. * 07 Reserved, 0
  3222. * 06 DPS, 1=parity bit not stored in data byte
  3223. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  3224. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  3225. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  3226. * 01 Reserved, 0
  3227. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  3228. *
  3229. * 0101 1100
  3230. */
  3231. write_reg(info, CHA + RFC, 0x5c);
  3232. /* RLCR Receive length check register
  3233. *
  3234. * Max frame length = (RL + 1) * 32
  3235. */
  3236. write_reg(info, CHA + RLCR, 0);
  3237. /* XBCH Transmit Byte Count High
  3238. *
  3239. * 07 DMA mode, 0 = interrupt driven
  3240. * 06 NRM, 0=ABM (ignored)
  3241. * 05 CAS Carrier Auto Start
  3242. * 04 XC Transmit Continuously (ignored)
  3243. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  3244. *
  3245. * 0000 0000
  3246. */
  3247. val = 0x00;
  3248. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3249. val |= BIT5;
  3250. write_reg(info, CHA + XBCH, val);
  3251. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3252. irq_enable(info, CHA, IRQ_CTS);
  3253. /* MODE:03 RAC Receiver Active, 1=active */
  3254. set_reg_bits(info, CHA + MODE, BIT3);
  3255. enable_auxclk(info);
  3256. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3257. irq_enable(info, CHB, IRQ_CTS);
  3258. /* PVR[3] 1=AUTO CTS active */
  3259. set_reg_bits(info, CHA + PVR, BIT3);
  3260. } else
  3261. clear_reg_bits(info, CHA + PVR, BIT3);
  3262. irq_enable(info, CHA,
  3263. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3264. IRQ_ALLSENT + IRQ_TXFIFO);
  3265. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3266. wait_command_complete(info, CHA);
  3267. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3268. }
  3269. /* Set the HDLC idle mode for the transmitter.
  3270. */
  3271. void tx_set_idle(MGSLPC_INFO *info)
  3272. {
  3273. /* Note: ESCC2 only supports flags and one idle modes */
  3274. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3275. set_reg_bits(info, CHA + CCR1, BIT3);
  3276. else
  3277. clear_reg_bits(info, CHA + CCR1, BIT3);
  3278. }
  3279. /* get state of the V24 status (input) signals.
  3280. */
  3281. void get_signals(MGSLPC_INFO *info)
  3282. {
  3283. unsigned char status = 0;
  3284. /* preserve DTR and RTS */
  3285. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3286. if (read_reg(info, CHB + VSTR) & BIT7)
  3287. info->serial_signals |= SerialSignal_DCD;
  3288. if (read_reg(info, CHB + STAR) & BIT1)
  3289. info->serial_signals |= SerialSignal_CTS;
  3290. status = read_reg(info, CHA + PVR);
  3291. if (!(status & PVR_RI))
  3292. info->serial_signals |= SerialSignal_RI;
  3293. if (!(status & PVR_DSR))
  3294. info->serial_signals |= SerialSignal_DSR;
  3295. }
  3296. /* Set the state of DTR and RTS based on contents of
  3297. * serial_signals member of device extension.
  3298. */
  3299. void set_signals(MGSLPC_INFO *info)
  3300. {
  3301. unsigned char val;
  3302. val = read_reg(info, CHA + MODE);
  3303. if (info->params.mode == MGSL_MODE_ASYNC) {
  3304. if (info->serial_signals & SerialSignal_RTS)
  3305. val &= ~BIT6;
  3306. else
  3307. val |= BIT6;
  3308. } else {
  3309. if (info->serial_signals & SerialSignal_RTS)
  3310. val |= BIT2;
  3311. else
  3312. val &= ~BIT2;
  3313. }
  3314. write_reg(info, CHA + MODE, val);
  3315. if (info->serial_signals & SerialSignal_DTR)
  3316. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3317. else
  3318. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3319. }
  3320. void rx_reset_buffers(MGSLPC_INFO *info)
  3321. {
  3322. RXBUF *buf;
  3323. int i;
  3324. info->rx_put = 0;
  3325. info->rx_get = 0;
  3326. info->rx_frame_count = 0;
  3327. for (i=0 ; i < info->rx_buf_count ; i++) {
  3328. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3329. buf->status = buf->count = 0;
  3330. }
  3331. }
  3332. /* Attempt to return a received HDLC frame
  3333. * Only frames received without errors are returned.
  3334. *
  3335. * Returns 1 if frame returned, otherwise 0
  3336. */
  3337. int rx_get_frame(MGSLPC_INFO *info)
  3338. {
  3339. unsigned short status;
  3340. RXBUF *buf;
  3341. unsigned int framesize = 0;
  3342. unsigned long flags;
  3343. struct tty_struct *tty = info->tty;
  3344. int return_frame = 0;
  3345. if (info->rx_frame_count == 0)
  3346. return 0;
  3347. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3348. status = buf->status;
  3349. /* 07 VFR 1=valid frame
  3350. * 06 RDO 1=data overrun
  3351. * 05 CRC 1=OK, 0=error
  3352. * 04 RAB 1=frame aborted
  3353. */
  3354. if ((status & 0xf0) != 0xA0) {
  3355. if (!(status & BIT7) || (status & BIT4))
  3356. info->icount.rxabort++;
  3357. else if (status & BIT6)
  3358. info->icount.rxover++;
  3359. else if (!(status & BIT5)) {
  3360. info->icount.rxcrc++;
  3361. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3362. return_frame = 1;
  3363. }
  3364. framesize = 0;
  3365. #ifdef CONFIG_HDLC
  3366. {
  3367. struct net_device_stats *stats = hdlc_stats(info->netdev);
  3368. stats->rx_errors++;
  3369. stats->rx_frame_errors++;
  3370. }
  3371. #endif
  3372. } else
  3373. return_frame = 1;
  3374. if (return_frame)
  3375. framesize = buf->count;
  3376. if (debug_level >= DEBUG_LEVEL_BH)
  3377. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3378. __FILE__,__LINE__,info->device_name,status,framesize);
  3379. if (debug_level >= DEBUG_LEVEL_DATA)
  3380. trace_block(info, buf->data, framesize, 0);
  3381. if (framesize) {
  3382. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3383. framesize+1 > info->max_frame_size) ||
  3384. framesize > info->max_frame_size)
  3385. info->icount.rxlong++;
  3386. else {
  3387. if (status & BIT5)
  3388. info->icount.rxok++;
  3389. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3390. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3391. ++framesize;
  3392. }
  3393. #ifdef CONFIG_HDLC
  3394. if (info->netcount)
  3395. hdlcdev_rx(info, buf->data, framesize);
  3396. else
  3397. #endif
  3398. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3399. }
  3400. }
  3401. spin_lock_irqsave(&info->lock,flags);
  3402. buf->status = buf->count = 0;
  3403. info->rx_frame_count--;
  3404. info->rx_get++;
  3405. if (info->rx_get >= info->rx_buf_count)
  3406. info->rx_get = 0;
  3407. spin_unlock_irqrestore(&info->lock,flags);
  3408. return 1;
  3409. }
  3410. BOOLEAN register_test(MGSLPC_INFO *info)
  3411. {
  3412. static unsigned char patterns[] =
  3413. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3414. static unsigned int count = sizeof(patterns) / sizeof(patterns[0]);
  3415. unsigned int i;
  3416. BOOLEAN rc = TRUE;
  3417. unsigned long flags;
  3418. spin_lock_irqsave(&info->lock,flags);
  3419. reset_device(info);
  3420. for (i = 0; i < count; i++) {
  3421. write_reg(info, XAD1, patterns[i]);
  3422. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3423. if ((read_reg(info, XAD1) != patterns[i]) ||
  3424. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3425. rc = FALSE;
  3426. break;
  3427. }
  3428. }
  3429. spin_unlock_irqrestore(&info->lock,flags);
  3430. return rc;
  3431. }
  3432. BOOLEAN irq_test(MGSLPC_INFO *info)
  3433. {
  3434. unsigned long end_time;
  3435. unsigned long flags;
  3436. spin_lock_irqsave(&info->lock,flags);
  3437. reset_device(info);
  3438. info->testing_irq = TRUE;
  3439. hdlc_mode(info);
  3440. info->irq_occurred = FALSE;
  3441. /* init hdlc mode */
  3442. irq_enable(info, CHA, IRQ_TIMER);
  3443. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3444. issue_command(info, CHA, CMD_START_TIMER);
  3445. spin_unlock_irqrestore(&info->lock,flags);
  3446. end_time=100;
  3447. while(end_time-- && !info->irq_occurred) {
  3448. msleep_interruptible(10);
  3449. }
  3450. info->testing_irq = FALSE;
  3451. spin_lock_irqsave(&info->lock,flags);
  3452. reset_device(info);
  3453. spin_unlock_irqrestore(&info->lock,flags);
  3454. return info->irq_occurred ? TRUE : FALSE;
  3455. }
  3456. int adapter_test(MGSLPC_INFO *info)
  3457. {
  3458. if (!register_test(info)) {
  3459. info->init_error = DiagStatus_AddressFailure;
  3460. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3461. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3462. return -ENODEV;
  3463. }
  3464. if (!irq_test(info)) {
  3465. info->init_error = DiagStatus_IrqFailure;
  3466. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3467. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3468. return -ENODEV;
  3469. }
  3470. if (debug_level >= DEBUG_LEVEL_INFO)
  3471. printk("%s(%d):device %s passed diagnostics\n",
  3472. __FILE__,__LINE__,info->device_name);
  3473. return 0;
  3474. }
  3475. void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3476. {
  3477. int i;
  3478. int linecount;
  3479. if (xmit)
  3480. printk("%s tx data:\n",info->device_name);
  3481. else
  3482. printk("%s rx data:\n",info->device_name);
  3483. while(count) {
  3484. if (count > 16)
  3485. linecount = 16;
  3486. else
  3487. linecount = count;
  3488. for(i=0;i<linecount;i++)
  3489. printk("%02X ",(unsigned char)data[i]);
  3490. for(;i<17;i++)
  3491. printk(" ");
  3492. for(i=0;i<linecount;i++) {
  3493. if (data[i]>=040 && data[i]<=0176)
  3494. printk("%c",data[i]);
  3495. else
  3496. printk(".");
  3497. }
  3498. printk("\n");
  3499. data += linecount;
  3500. count -= linecount;
  3501. }
  3502. }
  3503. /* HDLC frame time out
  3504. * update stats and do tx completion processing
  3505. */
  3506. void tx_timeout(unsigned long context)
  3507. {
  3508. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3509. unsigned long flags;
  3510. if ( debug_level >= DEBUG_LEVEL_INFO )
  3511. printk( "%s(%d):tx_timeout(%s)\n",
  3512. __FILE__,__LINE__,info->device_name);
  3513. if(info->tx_active &&
  3514. info->params.mode == MGSL_MODE_HDLC) {
  3515. info->icount.txtimeout++;
  3516. }
  3517. spin_lock_irqsave(&info->lock,flags);
  3518. info->tx_active = 0;
  3519. info->tx_count = info->tx_put = info->tx_get = 0;
  3520. spin_unlock_irqrestore(&info->lock,flags);
  3521. #ifdef CONFIG_HDLC
  3522. if (info->netcount)
  3523. hdlcdev_tx_done(info);
  3524. else
  3525. #endif
  3526. bh_transmit(info);
  3527. }
  3528. #ifdef CONFIG_HDLC
  3529. /**
  3530. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3531. * set encoding and frame check sequence (FCS) options
  3532. *
  3533. * dev pointer to network device structure
  3534. * encoding serial encoding setting
  3535. * parity FCS setting
  3536. *
  3537. * returns 0 if success, otherwise error code
  3538. */
  3539. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3540. unsigned short parity)
  3541. {
  3542. MGSLPC_INFO *info = dev_to_port(dev);
  3543. unsigned char new_encoding;
  3544. unsigned short new_crctype;
  3545. /* return error if TTY interface open */
  3546. if (info->count)
  3547. return -EBUSY;
  3548. switch (encoding)
  3549. {
  3550. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3551. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3552. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3553. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3554. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3555. default: return -EINVAL;
  3556. }
  3557. switch (parity)
  3558. {
  3559. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3560. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3561. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3562. default: return -EINVAL;
  3563. }
  3564. info->params.encoding = new_encoding;
  3565. info->params.crc_type = new_crctype;;
  3566. /* if network interface up, reprogram hardware */
  3567. if (info->netcount)
  3568. mgslpc_program_hw(info);
  3569. return 0;
  3570. }
  3571. /**
  3572. * called by generic HDLC layer to send frame
  3573. *
  3574. * skb socket buffer containing HDLC frame
  3575. * dev pointer to network device structure
  3576. *
  3577. * returns 0 if success, otherwise error code
  3578. */
  3579. static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
  3580. {
  3581. MGSLPC_INFO *info = dev_to_port(dev);
  3582. struct net_device_stats *stats = hdlc_stats(dev);
  3583. unsigned long flags;
  3584. if (debug_level >= DEBUG_LEVEL_INFO)
  3585. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3586. /* stop sending until this frame completes */
  3587. netif_stop_queue(dev);
  3588. /* copy data to device buffers */
  3589. memcpy(info->tx_buf, skb->data, skb->len);
  3590. info->tx_get = 0;
  3591. info->tx_put = info->tx_count = skb->len;
  3592. /* update network statistics */
  3593. stats->tx_packets++;
  3594. stats->tx_bytes += skb->len;
  3595. /* done with socket buffer, so free it */
  3596. dev_kfree_skb(skb);
  3597. /* save start time for transmit timeout detection */
  3598. dev->trans_start = jiffies;
  3599. /* start hardware transmitter if necessary */
  3600. spin_lock_irqsave(&info->lock,flags);
  3601. if (!info->tx_active)
  3602. tx_start(info);
  3603. spin_unlock_irqrestore(&info->lock,flags);
  3604. return 0;
  3605. }
  3606. /**
  3607. * called by network layer when interface enabled
  3608. * claim resources and initialize hardware
  3609. *
  3610. * dev pointer to network device structure
  3611. *
  3612. * returns 0 if success, otherwise error code
  3613. */
  3614. static int hdlcdev_open(struct net_device *dev)
  3615. {
  3616. MGSLPC_INFO *info = dev_to_port(dev);
  3617. int rc;
  3618. unsigned long flags;
  3619. if (debug_level >= DEBUG_LEVEL_INFO)
  3620. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3621. /* generic HDLC layer open processing */
  3622. if ((rc = hdlc_open(dev)))
  3623. return rc;
  3624. /* arbitrate between network and tty opens */
  3625. spin_lock_irqsave(&info->netlock, flags);
  3626. if (info->count != 0 || info->netcount != 0) {
  3627. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3628. spin_unlock_irqrestore(&info->netlock, flags);
  3629. return -EBUSY;
  3630. }
  3631. info->netcount=1;
  3632. spin_unlock_irqrestore(&info->netlock, flags);
  3633. /* claim resources and init adapter */
  3634. if ((rc = startup(info)) != 0) {
  3635. spin_lock_irqsave(&info->netlock, flags);
  3636. info->netcount=0;
  3637. spin_unlock_irqrestore(&info->netlock, flags);
  3638. return rc;
  3639. }
  3640. /* assert DTR and RTS, apply hardware settings */
  3641. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3642. mgslpc_program_hw(info);
  3643. /* enable network layer transmit */
  3644. dev->trans_start = jiffies;
  3645. netif_start_queue(dev);
  3646. /* inform generic HDLC layer of current DCD status */
  3647. spin_lock_irqsave(&info->lock, flags);
  3648. get_signals(info);
  3649. spin_unlock_irqrestore(&info->lock, flags);
  3650. hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
  3651. return 0;
  3652. }
  3653. /**
  3654. * called by network layer when interface is disabled
  3655. * shutdown hardware and release resources
  3656. *
  3657. * dev pointer to network device structure
  3658. *
  3659. * returns 0 if success, otherwise error code
  3660. */
  3661. static int hdlcdev_close(struct net_device *dev)
  3662. {
  3663. MGSLPC_INFO *info = dev_to_port(dev);
  3664. unsigned long flags;
  3665. if (debug_level >= DEBUG_LEVEL_INFO)
  3666. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3667. netif_stop_queue(dev);
  3668. /* shutdown adapter and release resources */
  3669. shutdown(info);
  3670. hdlc_close(dev);
  3671. spin_lock_irqsave(&info->netlock, flags);
  3672. info->netcount=0;
  3673. spin_unlock_irqrestore(&info->netlock, flags);
  3674. return 0;
  3675. }
  3676. /**
  3677. * called by network layer to process IOCTL call to network device
  3678. *
  3679. * dev pointer to network device structure
  3680. * ifr pointer to network interface request structure
  3681. * cmd IOCTL command code
  3682. *
  3683. * returns 0 if success, otherwise error code
  3684. */
  3685. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3686. {
  3687. const size_t size = sizeof(sync_serial_settings);
  3688. sync_serial_settings new_line;
  3689. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3690. MGSLPC_INFO *info = dev_to_port(dev);
  3691. unsigned int flags;
  3692. if (debug_level >= DEBUG_LEVEL_INFO)
  3693. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3694. /* return error if TTY interface open */
  3695. if (info->count)
  3696. return -EBUSY;
  3697. if (cmd != SIOCWANDEV)
  3698. return hdlc_ioctl(dev, ifr, cmd);
  3699. switch(ifr->ifr_settings.type) {
  3700. case IF_GET_IFACE: /* return current sync_serial_settings */
  3701. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3702. if (ifr->ifr_settings.size < size) {
  3703. ifr->ifr_settings.size = size; /* data size wanted */
  3704. return -ENOBUFS;
  3705. }
  3706. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3707. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3708. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3709. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3710. switch (flags){
  3711. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3712. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3713. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3714. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3715. default: new_line.clock_type = CLOCK_DEFAULT;
  3716. }
  3717. new_line.clock_rate = info->params.clock_speed;
  3718. new_line.loopback = info->params.loopback ? 1:0;
  3719. if (copy_to_user(line, &new_line, size))
  3720. return -EFAULT;
  3721. return 0;
  3722. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3723. if(!capable(CAP_NET_ADMIN))
  3724. return -EPERM;
  3725. if (copy_from_user(&new_line, line, size))
  3726. return -EFAULT;
  3727. switch (new_line.clock_type)
  3728. {
  3729. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3730. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3731. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3732. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3733. case CLOCK_DEFAULT: flags = info->params.flags &
  3734. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3735. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3736. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3737. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3738. default: return -EINVAL;
  3739. }
  3740. if (new_line.loopback != 0 && new_line.loopback != 1)
  3741. return -EINVAL;
  3742. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3743. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3744. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3745. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3746. info->params.flags |= flags;
  3747. info->params.loopback = new_line.loopback;
  3748. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3749. info->params.clock_speed = new_line.clock_rate;
  3750. else
  3751. info->params.clock_speed = 0;
  3752. /* if network interface up, reprogram hardware */
  3753. if (info->netcount)
  3754. mgslpc_program_hw(info);
  3755. return 0;
  3756. default:
  3757. return hdlc_ioctl(dev, ifr, cmd);
  3758. }
  3759. }
  3760. /**
  3761. * called by network layer when transmit timeout is detected
  3762. *
  3763. * dev pointer to network device structure
  3764. */
  3765. static void hdlcdev_tx_timeout(struct net_device *dev)
  3766. {
  3767. MGSLPC_INFO *info = dev_to_port(dev);
  3768. struct net_device_stats *stats = hdlc_stats(dev);
  3769. unsigned long flags;
  3770. if (debug_level >= DEBUG_LEVEL_INFO)
  3771. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3772. stats->tx_errors++;
  3773. stats->tx_aborted_errors++;
  3774. spin_lock_irqsave(&info->lock,flags);
  3775. tx_stop(info);
  3776. spin_unlock_irqrestore(&info->lock,flags);
  3777. netif_wake_queue(dev);
  3778. }
  3779. /**
  3780. * called by device driver when transmit completes
  3781. * reenable network layer transmit if stopped
  3782. *
  3783. * info pointer to device instance information
  3784. */
  3785. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3786. {
  3787. if (netif_queue_stopped(info->netdev))
  3788. netif_wake_queue(info->netdev);
  3789. }
  3790. /**
  3791. * called by device driver when frame received
  3792. * pass frame to network layer
  3793. *
  3794. * info pointer to device instance information
  3795. * buf pointer to buffer contianing frame data
  3796. * size count of data bytes in buf
  3797. */
  3798. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3799. {
  3800. struct sk_buff *skb = dev_alloc_skb(size);
  3801. struct net_device *dev = info->netdev;
  3802. struct net_device_stats *stats = hdlc_stats(dev);
  3803. if (debug_level >= DEBUG_LEVEL_INFO)
  3804. printk("hdlcdev_rx(%s)\n",dev->name);
  3805. if (skb == NULL) {
  3806. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3807. stats->rx_dropped++;
  3808. return;
  3809. }
  3810. memcpy(skb_put(skb, size),buf,size);
  3811. skb->protocol = hdlc_type_trans(skb, info->netdev);
  3812. stats->rx_packets++;
  3813. stats->rx_bytes += size;
  3814. netif_rx(skb);
  3815. info->netdev->last_rx = jiffies;
  3816. }
  3817. /**
  3818. * called by device driver when adding device instance
  3819. * do generic HDLC initialization
  3820. *
  3821. * info pointer to device instance information
  3822. *
  3823. * returns 0 if success, otherwise error code
  3824. */
  3825. static int hdlcdev_init(MGSLPC_INFO *info)
  3826. {
  3827. int rc;
  3828. struct net_device *dev;
  3829. hdlc_device *hdlc;
  3830. /* allocate and initialize network and HDLC layer objects */
  3831. if (!(dev = alloc_hdlcdev(info))) {
  3832. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3833. return -ENOMEM;
  3834. }
  3835. /* for network layer reporting purposes only */
  3836. dev->base_addr = info->io_base;
  3837. dev->irq = info->irq_level;
  3838. /* network layer callbacks and settings */
  3839. dev->do_ioctl = hdlcdev_ioctl;
  3840. dev->open = hdlcdev_open;
  3841. dev->stop = hdlcdev_close;
  3842. dev->tx_timeout = hdlcdev_tx_timeout;
  3843. dev->watchdog_timeo = 10*HZ;
  3844. dev->tx_queue_len = 50;
  3845. /* generic HDLC layer callbacks and settings */
  3846. hdlc = dev_to_hdlc(dev);
  3847. hdlc->attach = hdlcdev_attach;
  3848. hdlc->xmit = hdlcdev_xmit;
  3849. /* register objects with HDLC layer */
  3850. if ((rc = register_hdlc_device(dev))) {
  3851. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3852. free_netdev(dev);
  3853. return rc;
  3854. }
  3855. info->netdev = dev;
  3856. return 0;
  3857. }
  3858. /**
  3859. * called by device driver when removing device instance
  3860. * do generic HDLC cleanup
  3861. *
  3862. * info pointer to device instance information
  3863. */
  3864. static void hdlcdev_exit(MGSLPC_INFO *info)
  3865. {
  3866. unregister_hdlc_device(info->netdev);
  3867. free_netdev(info->netdev);
  3868. info->netdev = NULL;
  3869. }
  3870. #endif /* CONFIG_HDLC */