s2io.c 174 KB

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  1. /************************************************************************
  2. * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
  3. * Copyright(c) 2002-2005 Neterion Inc.
  4. * This software may be used and distributed according to the terms of
  5. * the GNU General Public License (GPL), incorporated herein by reference.
  6. * Drivers based on or derived from this code fall under the GPL and must
  7. * retain the authorship, copyright and license notice. This file is not
  8. * a complete program and may only be used when the entire operating
  9. * system is licensed under the GPL.
  10. * See the file COPYING in this distribution for more information.
  11. *
  12. * Credits:
  13. * Jeff Garzik : For pointing out the improper error condition
  14. * check in the s2io_xmit routine and also some
  15. * issues in the Tx watch dog function. Also for
  16. * patiently answering all those innumerable
  17. * questions regaring the 2.6 porting issues.
  18. * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
  19. * macros available only in 2.6 Kernel.
  20. * Francois Romieu : For pointing out all code part that were
  21. * deprecated and also styling related comments.
  22. * Grant Grundler : For helping me get rid of some Architecture
  23. * dependent code.
  24. * Christopher Hellwig : Some more 2.6 specific issues in the driver.
  25. *
  26. * The module loadable parameters that are supported by the driver and a brief
  27. * explaination of all the variables.
  28. * rx_ring_num : This can be used to program the number of receive rings used
  29. * in the driver.
  30. * rx_ring_sz: This defines the number of descriptors each ring can have. This
  31. * is also an array of size 8.
  32. * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  33. * tx_fifo_len: This too is an array of 8. Each element defines the number of
  34. * Tx descriptors that can be associated with each corresponding FIFO.
  35. ************************************************************************/
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/types.h>
  39. #include <linux/errno.h>
  40. #include <linux/ioport.h>
  41. #include <linux/pci.h>
  42. #include <linux/dma-mapping.h>
  43. #include <linux/kernel.h>
  44. #include <linux/netdevice.h>
  45. #include <linux/etherdevice.h>
  46. #include <linux/skbuff.h>
  47. #include <linux/init.h>
  48. #include <linux/delay.h>
  49. #include <linux/stddef.h>
  50. #include <linux/ioctl.h>
  51. #include <linux/timex.h>
  52. #include <linux/sched.h>
  53. #include <linux/ethtool.h>
  54. #include <linux/version.h>
  55. #include <linux/workqueue.h>
  56. #include <linux/if_vlan.h>
  57. #include <asm/system.h>
  58. #include <asm/uaccess.h>
  59. #include <asm/io.h>
  60. /* local include */
  61. #include "s2io.h"
  62. #include "s2io-regs.h"
  63. #define DRV_VERSION "Version 2.0.9.1"
  64. /* S2io Driver name & version. */
  65. static char s2io_driver_name[] = "Neterion";
  66. static char s2io_driver_version[] = DRV_VERSION;
  67. static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  68. {
  69. int ret;
  70. ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  71. (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  72. return ret;
  73. }
  74. /*
  75. * Cards with following subsystem_id have a link state indication
  76. * problem, 600B, 600C, 600D, 640B, 640C and 640D.
  77. * macro below identifies these cards given the subsystem_id.
  78. */
  79. #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
  80. (dev_type == XFRAME_I_DEVICE) ? \
  81. ((((subid >= 0x600B) && (subid <= 0x600D)) || \
  82. ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
  83. #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
  84. ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
  85. #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
  86. #define PANIC 1
  87. #define LOW 2
  88. static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
  89. {
  90. int level = 0;
  91. mac_info_t *mac_control;
  92. mac_control = &sp->mac_control;
  93. if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
  94. level = LOW;
  95. if (rxb_size <= MAX_RXDS_PER_BLOCK) {
  96. level = PANIC;
  97. }
  98. }
  99. return level;
  100. }
  101. /* Ethtool related variables and Macros. */
  102. static char s2io_gstrings[][ETH_GSTRING_LEN] = {
  103. "Register test\t(offline)",
  104. "Eeprom test\t(offline)",
  105. "Link test\t(online)",
  106. "RLDRAM test\t(offline)",
  107. "BIST Test\t(offline)"
  108. };
  109. static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
  110. {"tmac_frms"},
  111. {"tmac_data_octets"},
  112. {"tmac_drop_frms"},
  113. {"tmac_mcst_frms"},
  114. {"tmac_bcst_frms"},
  115. {"tmac_pause_ctrl_frms"},
  116. {"tmac_any_err_frms"},
  117. {"tmac_vld_ip_octets"},
  118. {"tmac_vld_ip"},
  119. {"tmac_drop_ip"},
  120. {"tmac_icmp"},
  121. {"tmac_rst_tcp"},
  122. {"tmac_tcp"},
  123. {"tmac_udp"},
  124. {"rmac_vld_frms"},
  125. {"rmac_data_octets"},
  126. {"rmac_fcs_err_frms"},
  127. {"rmac_drop_frms"},
  128. {"rmac_vld_mcst_frms"},
  129. {"rmac_vld_bcst_frms"},
  130. {"rmac_in_rng_len_err_frms"},
  131. {"rmac_long_frms"},
  132. {"rmac_pause_ctrl_frms"},
  133. {"rmac_discarded_frms"},
  134. {"rmac_usized_frms"},
  135. {"rmac_osized_frms"},
  136. {"rmac_frag_frms"},
  137. {"rmac_jabber_frms"},
  138. {"rmac_ip"},
  139. {"rmac_ip_octets"},
  140. {"rmac_hdr_err_ip"},
  141. {"rmac_drop_ip"},
  142. {"rmac_icmp"},
  143. {"rmac_tcp"},
  144. {"rmac_udp"},
  145. {"rmac_err_drp_udp"},
  146. {"rmac_pause_cnt"},
  147. {"rmac_accepted_ip"},
  148. {"rmac_err_tcp"},
  149. {"\n DRIVER STATISTICS"},
  150. {"single_bit_ecc_errs"},
  151. {"double_bit_ecc_errs"},
  152. };
  153. #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
  154. #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
  155. #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
  156. #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
  157. #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
  158. init_timer(&timer); \
  159. timer.function = handle; \
  160. timer.data = (unsigned long) arg; \
  161. mod_timer(&timer, (jiffies + exp)) \
  162. /* Add the vlan */
  163. static void s2io_vlan_rx_register(struct net_device *dev,
  164. struct vlan_group *grp)
  165. {
  166. nic_t *nic = dev->priv;
  167. unsigned long flags;
  168. spin_lock_irqsave(&nic->tx_lock, flags);
  169. nic->vlgrp = grp;
  170. spin_unlock_irqrestore(&nic->tx_lock, flags);
  171. }
  172. /* Unregister the vlan */
  173. static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
  174. {
  175. nic_t *nic = dev->priv;
  176. unsigned long flags;
  177. spin_lock_irqsave(&nic->tx_lock, flags);
  178. if (nic->vlgrp)
  179. nic->vlgrp->vlan_devices[vid] = NULL;
  180. spin_unlock_irqrestore(&nic->tx_lock, flags);
  181. }
  182. /*
  183. * Constants to be programmed into the Xena's registers, to configure
  184. * the XAUI.
  185. */
  186. #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
  187. #define END_SIGN 0x0
  188. static u64 herc_act_dtx_cfg[] = {
  189. /* Set address */
  190. 0x8000051536750000ULL, 0x80000515367500E0ULL,
  191. /* Write data */
  192. 0x8000051536750004ULL, 0x80000515367500E4ULL,
  193. /* Set address */
  194. 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
  195. /* Write data */
  196. 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
  197. /* Set address */
  198. 0x801205150D440000ULL, 0x801205150D4400E0ULL,
  199. /* Write data */
  200. 0x801205150D440004ULL, 0x801205150D4400E4ULL,
  201. /* Set address */
  202. 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
  203. /* Write data */
  204. 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
  205. /* Done */
  206. END_SIGN
  207. };
  208. static u64 xena_mdio_cfg[] = {
  209. /* Reset PMA PLL */
  210. 0xC001010000000000ULL, 0xC0010100000000E0ULL,
  211. 0xC0010100008000E4ULL,
  212. /* Remove Reset from PMA PLL */
  213. 0xC001010000000000ULL, 0xC0010100000000E0ULL,
  214. 0xC0010100000000E4ULL,
  215. END_SIGN
  216. };
  217. static u64 xena_dtx_cfg[] = {
  218. 0x8000051500000000ULL, 0x80000515000000E0ULL,
  219. 0x80000515D93500E4ULL, 0x8001051500000000ULL,
  220. 0x80010515000000E0ULL, 0x80010515001E00E4ULL,
  221. 0x8002051500000000ULL, 0x80020515000000E0ULL,
  222. 0x80020515F21000E4ULL,
  223. /* Set PADLOOPBACKN */
  224. 0x8002051500000000ULL, 0x80020515000000E0ULL,
  225. 0x80020515B20000E4ULL, 0x8003051500000000ULL,
  226. 0x80030515000000E0ULL, 0x80030515B20000E4ULL,
  227. 0x8004051500000000ULL, 0x80040515000000E0ULL,
  228. 0x80040515B20000E4ULL, 0x8005051500000000ULL,
  229. 0x80050515000000E0ULL, 0x80050515B20000E4ULL,
  230. SWITCH_SIGN,
  231. /* Remove PADLOOPBACKN */
  232. 0x8002051500000000ULL, 0x80020515000000E0ULL,
  233. 0x80020515F20000E4ULL, 0x8003051500000000ULL,
  234. 0x80030515000000E0ULL, 0x80030515F20000E4ULL,
  235. 0x8004051500000000ULL, 0x80040515000000E0ULL,
  236. 0x80040515F20000E4ULL, 0x8005051500000000ULL,
  237. 0x80050515000000E0ULL, 0x80050515F20000E4ULL,
  238. END_SIGN
  239. };
  240. /*
  241. * Constants for Fixing the MacAddress problem seen mostly on
  242. * Alpha machines.
  243. */
  244. static u64 fix_mac[] = {
  245. 0x0060000000000000ULL, 0x0060600000000000ULL,
  246. 0x0040600000000000ULL, 0x0000600000000000ULL,
  247. 0x0020600000000000ULL, 0x0060600000000000ULL,
  248. 0x0020600000000000ULL, 0x0060600000000000ULL,
  249. 0x0020600000000000ULL, 0x0060600000000000ULL,
  250. 0x0020600000000000ULL, 0x0060600000000000ULL,
  251. 0x0020600000000000ULL, 0x0060600000000000ULL,
  252. 0x0020600000000000ULL, 0x0060600000000000ULL,
  253. 0x0020600000000000ULL, 0x0060600000000000ULL,
  254. 0x0020600000000000ULL, 0x0060600000000000ULL,
  255. 0x0020600000000000ULL, 0x0060600000000000ULL,
  256. 0x0020600000000000ULL, 0x0060600000000000ULL,
  257. 0x0020600000000000ULL, 0x0000600000000000ULL,
  258. 0x0040600000000000ULL, 0x0060600000000000ULL,
  259. END_SIGN
  260. };
  261. /* Module Loadable parameters. */
  262. static unsigned int tx_fifo_num = 1;
  263. static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
  264. {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
  265. static unsigned int rx_ring_num = 1;
  266. static unsigned int rx_ring_sz[MAX_RX_RINGS] =
  267. {[0 ...(MAX_RX_RINGS - 1)] = 0 };
  268. static unsigned int rts_frm_len[MAX_RX_RINGS] =
  269. {[0 ...(MAX_RX_RINGS - 1)] = 0 };
  270. static unsigned int use_continuous_tx_intrs = 1;
  271. static unsigned int rmac_pause_time = 65535;
  272. static unsigned int mc_pause_threshold_q0q3 = 187;
  273. static unsigned int mc_pause_threshold_q4q7 = 187;
  274. static unsigned int shared_splits;
  275. static unsigned int tmac_util_period = 5;
  276. static unsigned int rmac_util_period = 5;
  277. static unsigned int bimodal = 0;
  278. #ifndef CONFIG_S2IO_NAPI
  279. static unsigned int indicate_max_pkts;
  280. #endif
  281. /* Frequency of Rx desc syncs expressed as power of 2 */
  282. static unsigned int rxsync_frequency = 3;
  283. /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
  284. static unsigned int intr_type = 0;
  285. /*
  286. * S2IO device table.
  287. * This table lists all the devices that this driver supports.
  288. */
  289. static struct pci_device_id s2io_tbl[] __devinitdata = {
  290. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
  291. PCI_ANY_ID, PCI_ANY_ID},
  292. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
  293. PCI_ANY_ID, PCI_ANY_ID},
  294. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
  295. PCI_ANY_ID, PCI_ANY_ID},
  296. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
  297. PCI_ANY_ID, PCI_ANY_ID},
  298. {0,}
  299. };
  300. MODULE_DEVICE_TABLE(pci, s2io_tbl);
  301. static struct pci_driver s2io_driver = {
  302. .name = "S2IO",
  303. .id_table = s2io_tbl,
  304. .probe = s2io_init_nic,
  305. .remove = __devexit_p(s2io_rem_nic),
  306. };
  307. /* A simplifier macro used both by init and free shared_mem Fns(). */
  308. #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
  309. /**
  310. * init_shared_mem - Allocation and Initialization of Memory
  311. * @nic: Device private variable.
  312. * Description: The function allocates all the memory areas shared
  313. * between the NIC and the driver. This includes Tx descriptors,
  314. * Rx descriptors and the statistics block.
  315. */
  316. static int init_shared_mem(struct s2io_nic *nic)
  317. {
  318. u32 size;
  319. void *tmp_v_addr, *tmp_v_addr_next;
  320. dma_addr_t tmp_p_addr, tmp_p_addr_next;
  321. RxD_block_t *pre_rxd_blk = NULL;
  322. int i, j, blk_cnt, rx_sz, tx_sz;
  323. int lst_size, lst_per_page;
  324. struct net_device *dev = nic->dev;
  325. #ifdef CONFIG_2BUFF_MODE
  326. unsigned long tmp;
  327. buffAdd_t *ba;
  328. #endif
  329. mac_info_t *mac_control;
  330. struct config_param *config;
  331. mac_control = &nic->mac_control;
  332. config = &nic->config;
  333. /* Allocation and initialization of TXDLs in FIOFs */
  334. size = 0;
  335. for (i = 0; i < config->tx_fifo_num; i++) {
  336. size += config->tx_cfg[i].fifo_len;
  337. }
  338. if (size > MAX_AVAILABLE_TXDS) {
  339. DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
  340. __FUNCTION__);
  341. DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
  342. return FAILURE;
  343. }
  344. lst_size = (sizeof(TxD_t) * config->max_txds);
  345. tx_sz = lst_size * size;
  346. lst_per_page = PAGE_SIZE / lst_size;
  347. for (i = 0; i < config->tx_fifo_num; i++) {
  348. int fifo_len = config->tx_cfg[i].fifo_len;
  349. int list_holder_size = fifo_len * sizeof(list_info_hold_t);
  350. mac_control->fifos[i].list_info = kmalloc(list_holder_size,
  351. GFP_KERNEL);
  352. if (!mac_control->fifos[i].list_info) {
  353. DBG_PRINT(ERR_DBG,
  354. "Malloc failed for list_info\n");
  355. return -ENOMEM;
  356. }
  357. memset(mac_control->fifos[i].list_info, 0, list_holder_size);
  358. }
  359. for (i = 0; i < config->tx_fifo_num; i++) {
  360. int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
  361. lst_per_page);
  362. mac_control->fifos[i].tx_curr_put_info.offset = 0;
  363. mac_control->fifos[i].tx_curr_put_info.fifo_len =
  364. config->tx_cfg[i].fifo_len - 1;
  365. mac_control->fifos[i].tx_curr_get_info.offset = 0;
  366. mac_control->fifos[i].tx_curr_get_info.fifo_len =
  367. config->tx_cfg[i].fifo_len - 1;
  368. mac_control->fifos[i].fifo_no = i;
  369. mac_control->fifos[i].nic = nic;
  370. mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1;
  371. for (j = 0; j < page_num; j++) {
  372. int k = 0;
  373. dma_addr_t tmp_p;
  374. void *tmp_v;
  375. tmp_v = pci_alloc_consistent(nic->pdev,
  376. PAGE_SIZE, &tmp_p);
  377. if (!tmp_v) {
  378. DBG_PRINT(ERR_DBG,
  379. "pci_alloc_consistent ");
  380. DBG_PRINT(ERR_DBG, "failed for TxDL\n");
  381. return -ENOMEM;
  382. }
  383. /* If we got a zero DMA address(can happen on
  384. * certain platforms like PPC), reallocate.
  385. * Store virtual address of page we don't want,
  386. * to be freed later.
  387. */
  388. if (!tmp_p) {
  389. mac_control->zerodma_virt_addr = tmp_v;
  390. DBG_PRINT(INIT_DBG,
  391. "%s: Zero DMA address for TxDL. ", dev->name);
  392. DBG_PRINT(INIT_DBG,
  393. "Virtual address %p\n", tmp_v);
  394. tmp_v = pci_alloc_consistent(nic->pdev,
  395. PAGE_SIZE, &tmp_p);
  396. if (!tmp_v) {
  397. DBG_PRINT(ERR_DBG,
  398. "pci_alloc_consistent ");
  399. DBG_PRINT(ERR_DBG, "failed for TxDL\n");
  400. return -ENOMEM;
  401. }
  402. }
  403. while (k < lst_per_page) {
  404. int l = (j * lst_per_page) + k;
  405. if (l == config->tx_cfg[i].fifo_len)
  406. break;
  407. mac_control->fifos[i].list_info[l].list_virt_addr =
  408. tmp_v + (k * lst_size);
  409. mac_control->fifos[i].list_info[l].list_phy_addr =
  410. tmp_p + (k * lst_size);
  411. k++;
  412. }
  413. }
  414. }
  415. /* Allocation and initialization of RXDs in Rings */
  416. size = 0;
  417. for (i = 0; i < config->rx_ring_num; i++) {
  418. if (config->rx_cfg[i].num_rxd % (MAX_RXDS_PER_BLOCK + 1)) {
  419. DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
  420. DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
  421. i);
  422. DBG_PRINT(ERR_DBG, "RxDs per Block");
  423. return FAILURE;
  424. }
  425. size += config->rx_cfg[i].num_rxd;
  426. mac_control->rings[i].block_count =
  427. config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
  428. mac_control->rings[i].pkt_cnt =
  429. config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count;
  430. }
  431. size = (size * (sizeof(RxD_t)));
  432. rx_sz = size;
  433. for (i = 0; i < config->rx_ring_num; i++) {
  434. mac_control->rings[i].rx_curr_get_info.block_index = 0;
  435. mac_control->rings[i].rx_curr_get_info.offset = 0;
  436. mac_control->rings[i].rx_curr_get_info.ring_len =
  437. config->rx_cfg[i].num_rxd - 1;
  438. mac_control->rings[i].rx_curr_put_info.block_index = 0;
  439. mac_control->rings[i].rx_curr_put_info.offset = 0;
  440. mac_control->rings[i].rx_curr_put_info.ring_len =
  441. config->rx_cfg[i].num_rxd - 1;
  442. mac_control->rings[i].nic = nic;
  443. mac_control->rings[i].ring_no = i;
  444. blk_cnt =
  445. config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
  446. /* Allocating all the Rx blocks */
  447. for (j = 0; j < blk_cnt; j++) {
  448. #ifndef CONFIG_2BUFF_MODE
  449. size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
  450. #else
  451. size = SIZE_OF_BLOCK;
  452. #endif
  453. tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
  454. &tmp_p_addr);
  455. if (tmp_v_addr == NULL) {
  456. /*
  457. * In case of failure, free_shared_mem()
  458. * is called, which should free any
  459. * memory that was alloced till the
  460. * failure happened.
  461. */
  462. mac_control->rings[i].rx_blocks[j].block_virt_addr =
  463. tmp_v_addr;
  464. return -ENOMEM;
  465. }
  466. memset(tmp_v_addr, 0, size);
  467. mac_control->rings[i].rx_blocks[j].block_virt_addr =
  468. tmp_v_addr;
  469. mac_control->rings[i].rx_blocks[j].block_dma_addr =
  470. tmp_p_addr;
  471. }
  472. /* Interlinking all Rx Blocks */
  473. for (j = 0; j < blk_cnt; j++) {
  474. tmp_v_addr =
  475. mac_control->rings[i].rx_blocks[j].block_virt_addr;
  476. tmp_v_addr_next =
  477. mac_control->rings[i].rx_blocks[(j + 1) %
  478. blk_cnt].block_virt_addr;
  479. tmp_p_addr =
  480. mac_control->rings[i].rx_blocks[j].block_dma_addr;
  481. tmp_p_addr_next =
  482. mac_control->rings[i].rx_blocks[(j + 1) %
  483. blk_cnt].block_dma_addr;
  484. pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
  485. pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
  486. * marker.
  487. */
  488. #ifndef CONFIG_2BUFF_MODE
  489. pre_rxd_blk->reserved_2_pNext_RxD_block =
  490. (unsigned long) tmp_v_addr_next;
  491. #endif
  492. pre_rxd_blk->pNext_RxD_Blk_physical =
  493. (u64) tmp_p_addr_next;
  494. }
  495. }
  496. #ifdef CONFIG_2BUFF_MODE
  497. /*
  498. * Allocation of Storages for buffer addresses in 2BUFF mode
  499. * and the buffers as well.
  500. */
  501. for (i = 0; i < config->rx_ring_num; i++) {
  502. blk_cnt =
  503. config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
  504. mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
  505. GFP_KERNEL);
  506. if (!mac_control->rings[i].ba)
  507. return -ENOMEM;
  508. for (j = 0; j < blk_cnt; j++) {
  509. int k = 0;
  510. mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) *
  511. (MAX_RXDS_PER_BLOCK + 1)),
  512. GFP_KERNEL);
  513. if (!mac_control->rings[i].ba[j])
  514. return -ENOMEM;
  515. while (k != MAX_RXDS_PER_BLOCK) {
  516. ba = &mac_control->rings[i].ba[j][k];
  517. ba->ba_0_org = (void *) kmalloc
  518. (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
  519. if (!ba->ba_0_org)
  520. return -ENOMEM;
  521. tmp = (unsigned long) ba->ba_0_org;
  522. tmp += ALIGN_SIZE;
  523. tmp &= ~((unsigned long) ALIGN_SIZE);
  524. ba->ba_0 = (void *) tmp;
  525. ba->ba_1_org = (void *) kmalloc
  526. (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
  527. if (!ba->ba_1_org)
  528. return -ENOMEM;
  529. tmp = (unsigned long) ba->ba_1_org;
  530. tmp += ALIGN_SIZE;
  531. tmp &= ~((unsigned long) ALIGN_SIZE);
  532. ba->ba_1 = (void *) tmp;
  533. k++;
  534. }
  535. }
  536. }
  537. #endif
  538. /* Allocation and initialization of Statistics block */
  539. size = sizeof(StatInfo_t);
  540. mac_control->stats_mem = pci_alloc_consistent
  541. (nic->pdev, size, &mac_control->stats_mem_phy);
  542. if (!mac_control->stats_mem) {
  543. /*
  544. * In case of failure, free_shared_mem() is called, which
  545. * should free any memory that was alloced till the
  546. * failure happened.
  547. */
  548. return -ENOMEM;
  549. }
  550. mac_control->stats_mem_sz = size;
  551. tmp_v_addr = mac_control->stats_mem;
  552. mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
  553. memset(tmp_v_addr, 0, size);
  554. DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
  555. (unsigned long long) tmp_p_addr);
  556. return SUCCESS;
  557. }
  558. /**
  559. * free_shared_mem - Free the allocated Memory
  560. * @nic: Device private variable.
  561. * Description: This function is to free all memory locations allocated by
  562. * the init_shared_mem() function and return it to the kernel.
  563. */
  564. static void free_shared_mem(struct s2io_nic *nic)
  565. {
  566. int i, j, blk_cnt, size;
  567. void *tmp_v_addr;
  568. dma_addr_t tmp_p_addr;
  569. mac_info_t *mac_control;
  570. struct config_param *config;
  571. int lst_size, lst_per_page;
  572. struct net_device *dev = nic->dev;
  573. if (!nic)
  574. return;
  575. mac_control = &nic->mac_control;
  576. config = &nic->config;
  577. lst_size = (sizeof(TxD_t) * config->max_txds);
  578. lst_per_page = PAGE_SIZE / lst_size;
  579. for (i = 0; i < config->tx_fifo_num; i++) {
  580. int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
  581. lst_per_page);
  582. for (j = 0; j < page_num; j++) {
  583. int mem_blks = (j * lst_per_page);
  584. if (!mac_control->fifos[i].list_info)
  585. return;
  586. if (!mac_control->fifos[i].list_info[mem_blks].
  587. list_virt_addr)
  588. break;
  589. pci_free_consistent(nic->pdev, PAGE_SIZE,
  590. mac_control->fifos[i].
  591. list_info[mem_blks].
  592. list_virt_addr,
  593. mac_control->fifos[i].
  594. list_info[mem_blks].
  595. list_phy_addr);
  596. }
  597. /* If we got a zero DMA address during allocation,
  598. * free the page now
  599. */
  600. if (mac_control->zerodma_virt_addr) {
  601. pci_free_consistent(nic->pdev, PAGE_SIZE,
  602. mac_control->zerodma_virt_addr,
  603. (dma_addr_t)0);
  604. DBG_PRINT(INIT_DBG,
  605. "%s: Freeing TxDL with zero DMA addr. ",
  606. dev->name);
  607. DBG_PRINT(INIT_DBG, "Virtual address %p\n",
  608. mac_control->zerodma_virt_addr);
  609. }
  610. kfree(mac_control->fifos[i].list_info);
  611. }
  612. #ifndef CONFIG_2BUFF_MODE
  613. size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
  614. #else
  615. size = SIZE_OF_BLOCK;
  616. #endif
  617. for (i = 0; i < config->rx_ring_num; i++) {
  618. blk_cnt = mac_control->rings[i].block_count;
  619. for (j = 0; j < blk_cnt; j++) {
  620. tmp_v_addr = mac_control->rings[i].rx_blocks[j].
  621. block_virt_addr;
  622. tmp_p_addr = mac_control->rings[i].rx_blocks[j].
  623. block_dma_addr;
  624. if (tmp_v_addr == NULL)
  625. break;
  626. pci_free_consistent(nic->pdev, size,
  627. tmp_v_addr, tmp_p_addr);
  628. }
  629. }
  630. #ifdef CONFIG_2BUFF_MODE
  631. /* Freeing buffer storage addresses in 2BUFF mode. */
  632. for (i = 0; i < config->rx_ring_num; i++) {
  633. blk_cnt =
  634. config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
  635. for (j = 0; j < blk_cnt; j++) {
  636. int k = 0;
  637. if (!mac_control->rings[i].ba[j])
  638. continue;
  639. while (k != MAX_RXDS_PER_BLOCK) {
  640. buffAdd_t *ba = &mac_control->rings[i].ba[j][k];
  641. kfree(ba->ba_0_org);
  642. kfree(ba->ba_1_org);
  643. k++;
  644. }
  645. kfree(mac_control->rings[i].ba[j]);
  646. }
  647. kfree(mac_control->rings[i].ba);
  648. }
  649. #endif
  650. if (mac_control->stats_mem) {
  651. pci_free_consistent(nic->pdev,
  652. mac_control->stats_mem_sz,
  653. mac_control->stats_mem,
  654. mac_control->stats_mem_phy);
  655. }
  656. }
  657. /**
  658. * s2io_verify_pci_mode -
  659. */
  660. static int s2io_verify_pci_mode(nic_t *nic)
  661. {
  662. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  663. register u64 val64 = 0;
  664. int mode;
  665. val64 = readq(&bar0->pci_mode);
  666. mode = (u8)GET_PCI_MODE(val64);
  667. if ( val64 & PCI_MODE_UNKNOWN_MODE)
  668. return -1; /* Unknown PCI mode */
  669. return mode;
  670. }
  671. /**
  672. * s2io_print_pci_mode -
  673. */
  674. static int s2io_print_pci_mode(nic_t *nic)
  675. {
  676. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  677. register u64 val64 = 0;
  678. int mode;
  679. struct config_param *config = &nic->config;
  680. val64 = readq(&bar0->pci_mode);
  681. mode = (u8)GET_PCI_MODE(val64);
  682. if ( val64 & PCI_MODE_UNKNOWN_MODE)
  683. return -1; /* Unknown PCI mode */
  684. if (val64 & PCI_MODE_32_BITS) {
  685. DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
  686. } else {
  687. DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
  688. }
  689. switch(mode) {
  690. case PCI_MODE_PCI_33:
  691. DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
  692. config->bus_speed = 33;
  693. break;
  694. case PCI_MODE_PCI_66:
  695. DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
  696. config->bus_speed = 133;
  697. break;
  698. case PCI_MODE_PCIX_M1_66:
  699. DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
  700. config->bus_speed = 133; /* Herc doubles the clock rate */
  701. break;
  702. case PCI_MODE_PCIX_M1_100:
  703. DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
  704. config->bus_speed = 200;
  705. break;
  706. case PCI_MODE_PCIX_M1_133:
  707. DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
  708. config->bus_speed = 266;
  709. break;
  710. case PCI_MODE_PCIX_M2_66:
  711. DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
  712. config->bus_speed = 133;
  713. break;
  714. case PCI_MODE_PCIX_M2_100:
  715. DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
  716. config->bus_speed = 200;
  717. break;
  718. case PCI_MODE_PCIX_M2_133:
  719. DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
  720. config->bus_speed = 266;
  721. break;
  722. default:
  723. return -1; /* Unsupported bus speed */
  724. }
  725. return mode;
  726. }
  727. /**
  728. * init_nic - Initialization of hardware
  729. * @nic: device peivate variable
  730. * Description: The function sequentially configures every block
  731. * of the H/W from their reset values.
  732. * Return Value: SUCCESS on success and
  733. * '-1' on failure (endian settings incorrect).
  734. */
  735. static int init_nic(struct s2io_nic *nic)
  736. {
  737. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  738. struct net_device *dev = nic->dev;
  739. register u64 val64 = 0;
  740. void __iomem *add;
  741. u32 time;
  742. int i, j;
  743. mac_info_t *mac_control;
  744. struct config_param *config;
  745. int mdio_cnt = 0, dtx_cnt = 0;
  746. unsigned long long mem_share;
  747. int mem_size;
  748. mac_control = &nic->mac_control;
  749. config = &nic->config;
  750. /* to set the swapper controle on the card */
  751. if(s2io_set_swapper(nic)) {
  752. DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
  753. return -1;
  754. }
  755. /*
  756. * Herc requires EOI to be removed from reset before XGXS, so..
  757. */
  758. if (nic->device_type & XFRAME_II_DEVICE) {
  759. val64 = 0xA500000000ULL;
  760. writeq(val64, &bar0->sw_reset);
  761. msleep(500);
  762. val64 = readq(&bar0->sw_reset);
  763. }
  764. /* Remove XGXS from reset state */
  765. val64 = 0;
  766. writeq(val64, &bar0->sw_reset);
  767. msleep(500);
  768. val64 = readq(&bar0->sw_reset);
  769. /* Enable Receiving broadcasts */
  770. add = &bar0->mac_cfg;
  771. val64 = readq(&bar0->mac_cfg);
  772. val64 |= MAC_RMAC_BCAST_ENABLE;
  773. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  774. writel((u32) val64, add);
  775. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  776. writel((u32) (val64 >> 32), (add + 4));
  777. /* Read registers in all blocks */
  778. val64 = readq(&bar0->mac_int_mask);
  779. val64 = readq(&bar0->mc_int_mask);
  780. val64 = readq(&bar0->xgxs_int_mask);
  781. /* Set MTU */
  782. val64 = dev->mtu;
  783. writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
  784. /*
  785. * Configuring the XAUI Interface of Xena.
  786. * ***************************************
  787. * To Configure the Xena's XAUI, one has to write a series
  788. * of 64 bit values into two registers in a particular
  789. * sequence. Hence a macro 'SWITCH_SIGN' has been defined
  790. * which will be defined in the array of configuration values
  791. * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
  792. * to switch writing from one regsiter to another. We continue
  793. * writing these values until we encounter the 'END_SIGN' macro.
  794. * For example, After making a series of 21 writes into
  795. * dtx_control register the 'SWITCH_SIGN' appears and hence we
  796. * start writing into mdio_control until we encounter END_SIGN.
  797. */
  798. if (nic->device_type & XFRAME_II_DEVICE) {
  799. while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
  800. SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
  801. &bar0->dtx_control, UF);
  802. if (dtx_cnt & 0x1)
  803. msleep(1); /* Necessary!! */
  804. dtx_cnt++;
  805. }
  806. } else {
  807. while (1) {
  808. dtx_cfg:
  809. while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
  810. if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
  811. dtx_cnt++;
  812. goto mdio_cfg;
  813. }
  814. SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
  815. &bar0->dtx_control, UF);
  816. val64 = readq(&bar0->dtx_control);
  817. dtx_cnt++;
  818. }
  819. mdio_cfg:
  820. while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
  821. if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
  822. mdio_cnt++;
  823. goto dtx_cfg;
  824. }
  825. SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
  826. &bar0->mdio_control, UF);
  827. val64 = readq(&bar0->mdio_control);
  828. mdio_cnt++;
  829. }
  830. if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
  831. (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
  832. break;
  833. } else {
  834. goto dtx_cfg;
  835. }
  836. }
  837. }
  838. /* Tx DMA Initialization */
  839. val64 = 0;
  840. writeq(val64, &bar0->tx_fifo_partition_0);
  841. writeq(val64, &bar0->tx_fifo_partition_1);
  842. writeq(val64, &bar0->tx_fifo_partition_2);
  843. writeq(val64, &bar0->tx_fifo_partition_3);
  844. for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
  845. val64 |=
  846. vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
  847. 13) | vBIT(config->tx_cfg[i].fifo_priority,
  848. ((i * 32) + 5), 3);
  849. if (i == (config->tx_fifo_num - 1)) {
  850. if (i % 2 == 0)
  851. i++;
  852. }
  853. switch (i) {
  854. case 1:
  855. writeq(val64, &bar0->tx_fifo_partition_0);
  856. val64 = 0;
  857. break;
  858. case 3:
  859. writeq(val64, &bar0->tx_fifo_partition_1);
  860. val64 = 0;
  861. break;
  862. case 5:
  863. writeq(val64, &bar0->tx_fifo_partition_2);
  864. val64 = 0;
  865. break;
  866. case 7:
  867. writeq(val64, &bar0->tx_fifo_partition_3);
  868. break;
  869. }
  870. }
  871. /* Enable Tx FIFO partition 0. */
  872. val64 = readq(&bar0->tx_fifo_partition_0);
  873. val64 |= BIT(0); /* To enable the FIFO partition. */
  874. writeq(val64, &bar0->tx_fifo_partition_0);
  875. /*
  876. * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
  877. * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
  878. */
  879. if ((nic->device_type == XFRAME_I_DEVICE) &&
  880. (get_xena_rev_id(nic->pdev) < 4))
  881. writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
  882. val64 = readq(&bar0->tx_fifo_partition_0);
  883. DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
  884. &bar0->tx_fifo_partition_0, (unsigned long long) val64);
  885. /*
  886. * Initialization of Tx_PA_CONFIG register to ignore packet
  887. * integrity checking.
  888. */
  889. val64 = readq(&bar0->tx_pa_cfg);
  890. val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
  891. TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
  892. writeq(val64, &bar0->tx_pa_cfg);
  893. /* Rx DMA intialization. */
  894. val64 = 0;
  895. for (i = 0; i < config->rx_ring_num; i++) {
  896. val64 |=
  897. vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
  898. 3);
  899. }
  900. writeq(val64, &bar0->rx_queue_priority);
  901. /*
  902. * Allocating equal share of memory to all the
  903. * configured Rings.
  904. */
  905. val64 = 0;
  906. if (nic->device_type & XFRAME_II_DEVICE)
  907. mem_size = 32;
  908. else
  909. mem_size = 64;
  910. for (i = 0; i < config->rx_ring_num; i++) {
  911. switch (i) {
  912. case 0:
  913. mem_share = (mem_size / config->rx_ring_num +
  914. mem_size % config->rx_ring_num);
  915. val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
  916. continue;
  917. case 1:
  918. mem_share = (mem_size / config->rx_ring_num);
  919. val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
  920. continue;
  921. case 2:
  922. mem_share = (mem_size / config->rx_ring_num);
  923. val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
  924. continue;
  925. case 3:
  926. mem_share = (mem_size / config->rx_ring_num);
  927. val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
  928. continue;
  929. case 4:
  930. mem_share = (mem_size / config->rx_ring_num);
  931. val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
  932. continue;
  933. case 5:
  934. mem_share = (mem_size / config->rx_ring_num);
  935. val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
  936. continue;
  937. case 6:
  938. mem_share = (mem_size / config->rx_ring_num);
  939. val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
  940. continue;
  941. case 7:
  942. mem_share = (mem_size / config->rx_ring_num);
  943. val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
  944. continue;
  945. }
  946. }
  947. writeq(val64, &bar0->rx_queue_cfg);
  948. /*
  949. * Filling Tx round robin registers
  950. * as per the number of FIFOs
  951. */
  952. switch (config->tx_fifo_num) {
  953. case 1:
  954. val64 = 0x0000000000000000ULL;
  955. writeq(val64, &bar0->tx_w_round_robin_0);
  956. writeq(val64, &bar0->tx_w_round_robin_1);
  957. writeq(val64, &bar0->tx_w_round_robin_2);
  958. writeq(val64, &bar0->tx_w_round_robin_3);
  959. writeq(val64, &bar0->tx_w_round_robin_4);
  960. break;
  961. case 2:
  962. val64 = 0x0000010000010000ULL;
  963. writeq(val64, &bar0->tx_w_round_robin_0);
  964. val64 = 0x0100000100000100ULL;
  965. writeq(val64, &bar0->tx_w_round_robin_1);
  966. val64 = 0x0001000001000001ULL;
  967. writeq(val64, &bar0->tx_w_round_robin_2);
  968. val64 = 0x0000010000010000ULL;
  969. writeq(val64, &bar0->tx_w_round_robin_3);
  970. val64 = 0x0100000000000000ULL;
  971. writeq(val64, &bar0->tx_w_round_robin_4);
  972. break;
  973. case 3:
  974. val64 = 0x0001000102000001ULL;
  975. writeq(val64, &bar0->tx_w_round_robin_0);
  976. val64 = 0x0001020000010001ULL;
  977. writeq(val64, &bar0->tx_w_round_robin_1);
  978. val64 = 0x0200000100010200ULL;
  979. writeq(val64, &bar0->tx_w_round_robin_2);
  980. val64 = 0x0001000102000001ULL;
  981. writeq(val64, &bar0->tx_w_round_robin_3);
  982. val64 = 0x0001020000000000ULL;
  983. writeq(val64, &bar0->tx_w_round_robin_4);
  984. break;
  985. case 4:
  986. val64 = 0x0001020300010200ULL;
  987. writeq(val64, &bar0->tx_w_round_robin_0);
  988. val64 = 0x0100000102030001ULL;
  989. writeq(val64, &bar0->tx_w_round_robin_1);
  990. val64 = 0x0200010000010203ULL;
  991. writeq(val64, &bar0->tx_w_round_robin_2);
  992. val64 = 0x0001020001000001ULL;
  993. writeq(val64, &bar0->tx_w_round_robin_3);
  994. val64 = 0x0203000100000000ULL;
  995. writeq(val64, &bar0->tx_w_round_robin_4);
  996. break;
  997. case 5:
  998. val64 = 0x0001000203000102ULL;
  999. writeq(val64, &bar0->tx_w_round_robin_0);
  1000. val64 = 0x0001020001030004ULL;
  1001. writeq(val64, &bar0->tx_w_round_robin_1);
  1002. val64 = 0x0001000203000102ULL;
  1003. writeq(val64, &bar0->tx_w_round_robin_2);
  1004. val64 = 0x0001020001030004ULL;
  1005. writeq(val64, &bar0->tx_w_round_robin_3);
  1006. val64 = 0x0001000000000000ULL;
  1007. writeq(val64, &bar0->tx_w_round_robin_4);
  1008. break;
  1009. case 6:
  1010. val64 = 0x0001020304000102ULL;
  1011. writeq(val64, &bar0->tx_w_round_robin_0);
  1012. val64 = 0x0304050001020001ULL;
  1013. writeq(val64, &bar0->tx_w_round_robin_1);
  1014. val64 = 0x0203000100000102ULL;
  1015. writeq(val64, &bar0->tx_w_round_robin_2);
  1016. val64 = 0x0304000102030405ULL;
  1017. writeq(val64, &bar0->tx_w_round_robin_3);
  1018. val64 = 0x0001000200000000ULL;
  1019. writeq(val64, &bar0->tx_w_round_robin_4);
  1020. break;
  1021. case 7:
  1022. val64 = 0x0001020001020300ULL;
  1023. writeq(val64, &bar0->tx_w_round_robin_0);
  1024. val64 = 0x0102030400010203ULL;
  1025. writeq(val64, &bar0->tx_w_round_robin_1);
  1026. val64 = 0x0405060001020001ULL;
  1027. writeq(val64, &bar0->tx_w_round_robin_2);
  1028. val64 = 0x0304050000010200ULL;
  1029. writeq(val64, &bar0->tx_w_round_robin_3);
  1030. val64 = 0x0102030000000000ULL;
  1031. writeq(val64, &bar0->tx_w_round_robin_4);
  1032. break;
  1033. case 8:
  1034. val64 = 0x0001020300040105ULL;
  1035. writeq(val64, &bar0->tx_w_round_robin_0);
  1036. val64 = 0x0200030106000204ULL;
  1037. writeq(val64, &bar0->tx_w_round_robin_1);
  1038. val64 = 0x0103000502010007ULL;
  1039. writeq(val64, &bar0->tx_w_round_robin_2);
  1040. val64 = 0x0304010002060500ULL;
  1041. writeq(val64, &bar0->tx_w_round_robin_3);
  1042. val64 = 0x0103020400000000ULL;
  1043. writeq(val64, &bar0->tx_w_round_robin_4);
  1044. break;
  1045. }
  1046. /* Filling the Rx round robin registers as per the
  1047. * number of Rings and steering based on QoS.
  1048. */
  1049. switch (config->rx_ring_num) {
  1050. case 1:
  1051. val64 = 0x8080808080808080ULL;
  1052. writeq(val64, &bar0->rts_qos_steering);
  1053. break;
  1054. case 2:
  1055. val64 = 0x0000010000010000ULL;
  1056. writeq(val64, &bar0->rx_w_round_robin_0);
  1057. val64 = 0x0100000100000100ULL;
  1058. writeq(val64, &bar0->rx_w_round_robin_1);
  1059. val64 = 0x0001000001000001ULL;
  1060. writeq(val64, &bar0->rx_w_round_robin_2);
  1061. val64 = 0x0000010000010000ULL;
  1062. writeq(val64, &bar0->rx_w_round_robin_3);
  1063. val64 = 0x0100000000000000ULL;
  1064. writeq(val64, &bar0->rx_w_round_robin_4);
  1065. val64 = 0x8080808040404040ULL;
  1066. writeq(val64, &bar0->rts_qos_steering);
  1067. break;
  1068. case 3:
  1069. val64 = 0x0001000102000001ULL;
  1070. writeq(val64, &bar0->rx_w_round_robin_0);
  1071. val64 = 0x0001020000010001ULL;
  1072. writeq(val64, &bar0->rx_w_round_robin_1);
  1073. val64 = 0x0200000100010200ULL;
  1074. writeq(val64, &bar0->rx_w_round_robin_2);
  1075. val64 = 0x0001000102000001ULL;
  1076. writeq(val64, &bar0->rx_w_round_robin_3);
  1077. val64 = 0x0001020000000000ULL;
  1078. writeq(val64, &bar0->rx_w_round_robin_4);
  1079. val64 = 0x8080804040402020ULL;
  1080. writeq(val64, &bar0->rts_qos_steering);
  1081. break;
  1082. case 4:
  1083. val64 = 0x0001020300010200ULL;
  1084. writeq(val64, &bar0->rx_w_round_robin_0);
  1085. val64 = 0x0100000102030001ULL;
  1086. writeq(val64, &bar0->rx_w_round_robin_1);
  1087. val64 = 0x0200010000010203ULL;
  1088. writeq(val64, &bar0->rx_w_round_robin_2);
  1089. val64 = 0x0001020001000001ULL;
  1090. writeq(val64, &bar0->rx_w_round_robin_3);
  1091. val64 = 0x0203000100000000ULL;
  1092. writeq(val64, &bar0->rx_w_round_robin_4);
  1093. val64 = 0x8080404020201010ULL;
  1094. writeq(val64, &bar0->rts_qos_steering);
  1095. break;
  1096. case 5:
  1097. val64 = 0x0001000203000102ULL;
  1098. writeq(val64, &bar0->rx_w_round_robin_0);
  1099. val64 = 0x0001020001030004ULL;
  1100. writeq(val64, &bar0->rx_w_round_robin_1);
  1101. val64 = 0x0001000203000102ULL;
  1102. writeq(val64, &bar0->rx_w_round_robin_2);
  1103. val64 = 0x0001020001030004ULL;
  1104. writeq(val64, &bar0->rx_w_round_robin_3);
  1105. val64 = 0x0001000000000000ULL;
  1106. writeq(val64, &bar0->rx_w_round_robin_4);
  1107. val64 = 0x8080404020201008ULL;
  1108. writeq(val64, &bar0->rts_qos_steering);
  1109. break;
  1110. case 6:
  1111. val64 = 0x0001020304000102ULL;
  1112. writeq(val64, &bar0->rx_w_round_robin_0);
  1113. val64 = 0x0304050001020001ULL;
  1114. writeq(val64, &bar0->rx_w_round_robin_1);
  1115. val64 = 0x0203000100000102ULL;
  1116. writeq(val64, &bar0->rx_w_round_robin_2);
  1117. val64 = 0x0304000102030405ULL;
  1118. writeq(val64, &bar0->rx_w_round_robin_3);
  1119. val64 = 0x0001000200000000ULL;
  1120. writeq(val64, &bar0->rx_w_round_robin_4);
  1121. val64 = 0x8080404020100804ULL;
  1122. writeq(val64, &bar0->rts_qos_steering);
  1123. break;
  1124. case 7:
  1125. val64 = 0x0001020001020300ULL;
  1126. writeq(val64, &bar0->rx_w_round_robin_0);
  1127. val64 = 0x0102030400010203ULL;
  1128. writeq(val64, &bar0->rx_w_round_robin_1);
  1129. val64 = 0x0405060001020001ULL;
  1130. writeq(val64, &bar0->rx_w_round_robin_2);
  1131. val64 = 0x0304050000010200ULL;
  1132. writeq(val64, &bar0->rx_w_round_robin_3);
  1133. val64 = 0x0102030000000000ULL;
  1134. writeq(val64, &bar0->rx_w_round_robin_4);
  1135. val64 = 0x8080402010080402ULL;
  1136. writeq(val64, &bar0->rts_qos_steering);
  1137. break;
  1138. case 8:
  1139. val64 = 0x0001020300040105ULL;
  1140. writeq(val64, &bar0->rx_w_round_robin_0);
  1141. val64 = 0x0200030106000204ULL;
  1142. writeq(val64, &bar0->rx_w_round_robin_1);
  1143. val64 = 0x0103000502010007ULL;
  1144. writeq(val64, &bar0->rx_w_round_robin_2);
  1145. val64 = 0x0304010002060500ULL;
  1146. writeq(val64, &bar0->rx_w_round_robin_3);
  1147. val64 = 0x0103020400000000ULL;
  1148. writeq(val64, &bar0->rx_w_round_robin_4);
  1149. val64 = 0x8040201008040201ULL;
  1150. writeq(val64, &bar0->rts_qos_steering);
  1151. break;
  1152. }
  1153. /* UDP Fix */
  1154. val64 = 0;
  1155. for (i = 0; i < 8; i++)
  1156. writeq(val64, &bar0->rts_frm_len_n[i]);
  1157. /* Set the default rts frame length for the rings configured */
  1158. val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
  1159. for (i = 0 ; i < config->rx_ring_num ; i++)
  1160. writeq(val64, &bar0->rts_frm_len_n[i]);
  1161. /* Set the frame length for the configured rings
  1162. * desired by the user
  1163. */
  1164. for (i = 0; i < config->rx_ring_num; i++) {
  1165. /* If rts_frm_len[i] == 0 then it is assumed that user not
  1166. * specified frame length steering.
  1167. * If the user provides the frame length then program
  1168. * the rts_frm_len register for those values or else
  1169. * leave it as it is.
  1170. */
  1171. if (rts_frm_len[i] != 0) {
  1172. writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
  1173. &bar0->rts_frm_len_n[i]);
  1174. }
  1175. }
  1176. /* Program statistics memory */
  1177. writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
  1178. if (nic->device_type == XFRAME_II_DEVICE) {
  1179. val64 = STAT_BC(0x320);
  1180. writeq(val64, &bar0->stat_byte_cnt);
  1181. }
  1182. /*
  1183. * Initializing the sampling rate for the device to calculate the
  1184. * bandwidth utilization.
  1185. */
  1186. val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
  1187. MAC_RX_LINK_UTIL_VAL(rmac_util_period);
  1188. writeq(val64, &bar0->mac_link_util);
  1189. /*
  1190. * Initializing the Transmit and Receive Traffic Interrupt
  1191. * Scheme.
  1192. */
  1193. /*
  1194. * TTI Initialization. Default Tx timer gets us about
  1195. * 250 interrupts per sec. Continuous interrupts are enabled
  1196. * by default.
  1197. */
  1198. if (nic->device_type == XFRAME_II_DEVICE) {
  1199. int count = (nic->config.bus_speed * 125)/2;
  1200. val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
  1201. } else {
  1202. val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
  1203. }
  1204. val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
  1205. TTI_DATA1_MEM_TX_URNG_B(0x10) |
  1206. TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
  1207. if (use_continuous_tx_intrs)
  1208. val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
  1209. writeq(val64, &bar0->tti_data1_mem);
  1210. val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
  1211. TTI_DATA2_MEM_TX_UFC_B(0x20) |
  1212. TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
  1213. writeq(val64, &bar0->tti_data2_mem);
  1214. val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
  1215. writeq(val64, &bar0->tti_command_mem);
  1216. /*
  1217. * Once the operation completes, the Strobe bit of the command
  1218. * register will be reset. We poll for this particular condition
  1219. * We wait for a maximum of 500ms for the operation to complete,
  1220. * if it's not complete by then we return error.
  1221. */
  1222. time = 0;
  1223. while (TRUE) {
  1224. val64 = readq(&bar0->tti_command_mem);
  1225. if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
  1226. break;
  1227. }
  1228. if (time > 10) {
  1229. DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
  1230. dev->name);
  1231. return -1;
  1232. }
  1233. msleep(50);
  1234. time++;
  1235. }
  1236. if (nic->config.bimodal) {
  1237. int k = 0;
  1238. for (k = 0; k < config->rx_ring_num; k++) {
  1239. val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
  1240. val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
  1241. writeq(val64, &bar0->tti_command_mem);
  1242. /*
  1243. * Once the operation completes, the Strobe bit of the command
  1244. * register will be reset. We poll for this particular condition
  1245. * We wait for a maximum of 500ms for the operation to complete,
  1246. * if it's not complete by then we return error.
  1247. */
  1248. time = 0;
  1249. while (TRUE) {
  1250. val64 = readq(&bar0->tti_command_mem);
  1251. if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
  1252. break;
  1253. }
  1254. if (time > 10) {
  1255. DBG_PRINT(ERR_DBG,
  1256. "%s: TTI init Failed\n",
  1257. dev->name);
  1258. return -1;
  1259. }
  1260. time++;
  1261. msleep(50);
  1262. }
  1263. }
  1264. } else {
  1265. /* RTI Initialization */
  1266. if (nic->device_type == XFRAME_II_DEVICE) {
  1267. /*
  1268. * Programmed to generate Apprx 500 Intrs per
  1269. * second
  1270. */
  1271. int count = (nic->config.bus_speed * 125)/4;
  1272. val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
  1273. } else {
  1274. val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
  1275. }
  1276. val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
  1277. RTI_DATA1_MEM_RX_URNG_B(0x10) |
  1278. RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
  1279. writeq(val64, &bar0->rti_data1_mem);
  1280. val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
  1281. RTI_DATA2_MEM_RX_UFC_B(0x2) ;
  1282. if (nic->intr_type == MSI_X)
  1283. val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
  1284. RTI_DATA2_MEM_RX_UFC_D(0x40));
  1285. else
  1286. val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
  1287. RTI_DATA2_MEM_RX_UFC_D(0x80));
  1288. writeq(val64, &bar0->rti_data2_mem);
  1289. for (i = 0; i < config->rx_ring_num; i++) {
  1290. val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
  1291. | RTI_CMD_MEM_OFFSET(i);
  1292. writeq(val64, &bar0->rti_command_mem);
  1293. /*
  1294. * Once the operation completes, the Strobe bit of the
  1295. * command register will be reset. We poll for this
  1296. * particular condition. We wait for a maximum of 500ms
  1297. * for the operation to complete, if it's not complete
  1298. * by then we return error.
  1299. */
  1300. time = 0;
  1301. while (TRUE) {
  1302. val64 = readq(&bar0->rti_command_mem);
  1303. if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
  1304. break;
  1305. }
  1306. if (time > 10) {
  1307. DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
  1308. dev->name);
  1309. return -1;
  1310. }
  1311. time++;
  1312. msleep(50);
  1313. }
  1314. }
  1315. }
  1316. /*
  1317. * Initializing proper values as Pause threshold into all
  1318. * the 8 Queues on Rx side.
  1319. */
  1320. writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
  1321. writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
  1322. /* Disable RMAC PAD STRIPPING */
  1323. add = &bar0->mac_cfg;
  1324. val64 = readq(&bar0->mac_cfg);
  1325. val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
  1326. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1327. writel((u32) (val64), add);
  1328. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1329. writel((u32) (val64 >> 32), (add + 4));
  1330. val64 = readq(&bar0->mac_cfg);
  1331. /*
  1332. * Set the time value to be inserted in the pause frame
  1333. * generated by xena.
  1334. */
  1335. val64 = readq(&bar0->rmac_pause_cfg);
  1336. val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
  1337. val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
  1338. writeq(val64, &bar0->rmac_pause_cfg);
  1339. /*
  1340. * Set the Threshold Limit for Generating the pause frame
  1341. * If the amount of data in any Queue exceeds ratio of
  1342. * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
  1343. * pause frame is generated
  1344. */
  1345. val64 = 0;
  1346. for (i = 0; i < 4; i++) {
  1347. val64 |=
  1348. (((u64) 0xFF00 | nic->mac_control.
  1349. mc_pause_threshold_q0q3)
  1350. << (i * 2 * 8));
  1351. }
  1352. writeq(val64, &bar0->mc_pause_thresh_q0q3);
  1353. val64 = 0;
  1354. for (i = 0; i < 4; i++) {
  1355. val64 |=
  1356. (((u64) 0xFF00 | nic->mac_control.
  1357. mc_pause_threshold_q4q7)
  1358. << (i * 2 * 8));
  1359. }
  1360. writeq(val64, &bar0->mc_pause_thresh_q4q7);
  1361. /*
  1362. * TxDMA will stop Read request if the number of read split has
  1363. * exceeded the limit pointed by shared_splits
  1364. */
  1365. val64 = readq(&bar0->pic_control);
  1366. val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
  1367. writeq(val64, &bar0->pic_control);
  1368. /*
  1369. * Programming the Herc to split every write transaction
  1370. * that does not start on an ADB to reduce disconnects.
  1371. */
  1372. if (nic->device_type == XFRAME_II_DEVICE) {
  1373. val64 = WREQ_SPLIT_MASK_SET_MASK(255);
  1374. writeq(val64, &bar0->wreq_split_mask);
  1375. }
  1376. /* Setting Link stability period to 64 ms */
  1377. if (nic->device_type == XFRAME_II_DEVICE) {
  1378. val64 = MISC_LINK_STABILITY_PRD(3);
  1379. writeq(val64, &bar0->misc_control);
  1380. }
  1381. return SUCCESS;
  1382. }
  1383. #define LINK_UP_DOWN_INTERRUPT 1
  1384. #define MAC_RMAC_ERR_TIMER 2
  1385. int s2io_link_fault_indication(nic_t *nic)
  1386. {
  1387. if (nic->intr_type != INTA)
  1388. return MAC_RMAC_ERR_TIMER;
  1389. if (nic->device_type == XFRAME_II_DEVICE)
  1390. return LINK_UP_DOWN_INTERRUPT;
  1391. else
  1392. return MAC_RMAC_ERR_TIMER;
  1393. }
  1394. /**
  1395. * en_dis_able_nic_intrs - Enable or Disable the interrupts
  1396. * @nic: device private variable,
  1397. * @mask: A mask indicating which Intr block must be modified and,
  1398. * @flag: A flag indicating whether to enable or disable the Intrs.
  1399. * Description: This function will either disable or enable the interrupts
  1400. * depending on the flag argument. The mask argument can be used to
  1401. * enable/disable any Intr block.
  1402. * Return Value: NONE.
  1403. */
  1404. static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
  1405. {
  1406. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  1407. register u64 val64 = 0, temp64 = 0;
  1408. /* Top level interrupt classification */
  1409. /* PIC Interrupts */
  1410. if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
  1411. /* Enable PIC Intrs in the general intr mask register */
  1412. val64 = TXPIC_INT_M | PIC_RX_INT_M;
  1413. if (flag == ENABLE_INTRS) {
  1414. temp64 = readq(&bar0->general_int_mask);
  1415. temp64 &= ~((u64) val64);
  1416. writeq(temp64, &bar0->general_int_mask);
  1417. /*
  1418. * If Hercules adapter enable GPIO otherwise
  1419. * disabled all PCIX, Flash, MDIO, IIC and GPIO
  1420. * interrupts for now.
  1421. * TODO
  1422. */
  1423. if (s2io_link_fault_indication(nic) ==
  1424. LINK_UP_DOWN_INTERRUPT ) {
  1425. temp64 = readq(&bar0->pic_int_mask);
  1426. temp64 &= ~((u64) PIC_INT_GPIO);
  1427. writeq(temp64, &bar0->pic_int_mask);
  1428. temp64 = readq(&bar0->gpio_int_mask);
  1429. temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
  1430. writeq(temp64, &bar0->gpio_int_mask);
  1431. } else {
  1432. writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
  1433. }
  1434. /*
  1435. * No MSI Support is available presently, so TTI and
  1436. * RTI interrupts are also disabled.
  1437. */
  1438. } else if (flag == DISABLE_INTRS) {
  1439. /*
  1440. * Disable PIC Intrs in the general
  1441. * intr mask register
  1442. */
  1443. writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
  1444. temp64 = readq(&bar0->general_int_mask);
  1445. val64 |= temp64;
  1446. writeq(val64, &bar0->general_int_mask);
  1447. }
  1448. }
  1449. /* DMA Interrupts */
  1450. /* Enabling/Disabling Tx DMA interrupts */
  1451. if (mask & TX_DMA_INTR) {
  1452. /* Enable TxDMA Intrs in the general intr mask register */
  1453. val64 = TXDMA_INT_M;
  1454. if (flag == ENABLE_INTRS) {
  1455. temp64 = readq(&bar0->general_int_mask);
  1456. temp64 &= ~((u64) val64);
  1457. writeq(temp64, &bar0->general_int_mask);
  1458. /*
  1459. * Keep all interrupts other than PFC interrupt
  1460. * and PCC interrupt disabled in DMA level.
  1461. */
  1462. val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
  1463. TXDMA_PCC_INT_M);
  1464. writeq(val64, &bar0->txdma_int_mask);
  1465. /*
  1466. * Enable only the MISC error 1 interrupt in PFC block
  1467. */
  1468. val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
  1469. writeq(val64, &bar0->pfc_err_mask);
  1470. /*
  1471. * Enable only the FB_ECC error interrupt in PCC block
  1472. */
  1473. val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
  1474. writeq(val64, &bar0->pcc_err_mask);
  1475. } else if (flag == DISABLE_INTRS) {
  1476. /*
  1477. * Disable TxDMA Intrs in the general intr mask
  1478. * register
  1479. */
  1480. writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
  1481. writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
  1482. temp64 = readq(&bar0->general_int_mask);
  1483. val64 |= temp64;
  1484. writeq(val64, &bar0->general_int_mask);
  1485. }
  1486. }
  1487. /* Enabling/Disabling Rx DMA interrupts */
  1488. if (mask & RX_DMA_INTR) {
  1489. /* Enable RxDMA Intrs in the general intr mask register */
  1490. val64 = RXDMA_INT_M;
  1491. if (flag == ENABLE_INTRS) {
  1492. temp64 = readq(&bar0->general_int_mask);
  1493. temp64 &= ~((u64) val64);
  1494. writeq(temp64, &bar0->general_int_mask);
  1495. /*
  1496. * All RxDMA block interrupts are disabled for now
  1497. * TODO
  1498. */
  1499. writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
  1500. } else if (flag == DISABLE_INTRS) {
  1501. /*
  1502. * Disable RxDMA Intrs in the general intr mask
  1503. * register
  1504. */
  1505. writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
  1506. temp64 = readq(&bar0->general_int_mask);
  1507. val64 |= temp64;
  1508. writeq(val64, &bar0->general_int_mask);
  1509. }
  1510. }
  1511. /* MAC Interrupts */
  1512. /* Enabling/Disabling MAC interrupts */
  1513. if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
  1514. val64 = TXMAC_INT_M | RXMAC_INT_M;
  1515. if (flag == ENABLE_INTRS) {
  1516. temp64 = readq(&bar0->general_int_mask);
  1517. temp64 &= ~((u64) val64);
  1518. writeq(temp64, &bar0->general_int_mask);
  1519. /*
  1520. * All MAC block error interrupts are disabled for now
  1521. * TODO
  1522. */
  1523. } else if (flag == DISABLE_INTRS) {
  1524. /*
  1525. * Disable MAC Intrs in the general intr mask register
  1526. */
  1527. writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
  1528. writeq(DISABLE_ALL_INTRS,
  1529. &bar0->mac_rmac_err_mask);
  1530. temp64 = readq(&bar0->general_int_mask);
  1531. val64 |= temp64;
  1532. writeq(val64, &bar0->general_int_mask);
  1533. }
  1534. }
  1535. /* XGXS Interrupts */
  1536. if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
  1537. val64 = TXXGXS_INT_M | RXXGXS_INT_M;
  1538. if (flag == ENABLE_INTRS) {
  1539. temp64 = readq(&bar0->general_int_mask);
  1540. temp64 &= ~((u64) val64);
  1541. writeq(temp64, &bar0->general_int_mask);
  1542. /*
  1543. * All XGXS block error interrupts are disabled for now
  1544. * TODO
  1545. */
  1546. writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
  1547. } else if (flag == DISABLE_INTRS) {
  1548. /*
  1549. * Disable MC Intrs in the general intr mask register
  1550. */
  1551. writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
  1552. temp64 = readq(&bar0->general_int_mask);
  1553. val64 |= temp64;
  1554. writeq(val64, &bar0->general_int_mask);
  1555. }
  1556. }
  1557. /* Memory Controller(MC) interrupts */
  1558. if (mask & MC_INTR) {
  1559. val64 = MC_INT_M;
  1560. if (flag == ENABLE_INTRS) {
  1561. temp64 = readq(&bar0->general_int_mask);
  1562. temp64 &= ~((u64) val64);
  1563. writeq(temp64, &bar0->general_int_mask);
  1564. /*
  1565. * Enable all MC Intrs.
  1566. */
  1567. writeq(0x0, &bar0->mc_int_mask);
  1568. writeq(0x0, &bar0->mc_err_mask);
  1569. } else if (flag == DISABLE_INTRS) {
  1570. /*
  1571. * Disable MC Intrs in the general intr mask register
  1572. */
  1573. writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
  1574. temp64 = readq(&bar0->general_int_mask);
  1575. val64 |= temp64;
  1576. writeq(val64, &bar0->general_int_mask);
  1577. }
  1578. }
  1579. /* Tx traffic interrupts */
  1580. if (mask & TX_TRAFFIC_INTR) {
  1581. val64 = TXTRAFFIC_INT_M;
  1582. if (flag == ENABLE_INTRS) {
  1583. temp64 = readq(&bar0->general_int_mask);
  1584. temp64 &= ~((u64) val64);
  1585. writeq(temp64, &bar0->general_int_mask);
  1586. /*
  1587. * Enable all the Tx side interrupts
  1588. * writing 0 Enables all 64 TX interrupt levels
  1589. */
  1590. writeq(0x0, &bar0->tx_traffic_mask);
  1591. } else if (flag == DISABLE_INTRS) {
  1592. /*
  1593. * Disable Tx Traffic Intrs in the general intr mask
  1594. * register.
  1595. */
  1596. writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
  1597. temp64 = readq(&bar0->general_int_mask);
  1598. val64 |= temp64;
  1599. writeq(val64, &bar0->general_int_mask);
  1600. }
  1601. }
  1602. /* Rx traffic interrupts */
  1603. if (mask & RX_TRAFFIC_INTR) {
  1604. val64 = RXTRAFFIC_INT_M;
  1605. if (flag == ENABLE_INTRS) {
  1606. temp64 = readq(&bar0->general_int_mask);
  1607. temp64 &= ~((u64) val64);
  1608. writeq(temp64, &bar0->general_int_mask);
  1609. /* writing 0 Enables all 8 RX interrupt levels */
  1610. writeq(0x0, &bar0->rx_traffic_mask);
  1611. } else if (flag == DISABLE_INTRS) {
  1612. /*
  1613. * Disable Rx Traffic Intrs in the general intr mask
  1614. * register.
  1615. */
  1616. writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
  1617. temp64 = readq(&bar0->general_int_mask);
  1618. val64 |= temp64;
  1619. writeq(val64, &bar0->general_int_mask);
  1620. }
  1621. }
  1622. }
  1623. static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
  1624. {
  1625. int ret = 0;
  1626. if (flag == FALSE) {
  1627. if ((!herc && (rev_id >= 4)) || herc) {
  1628. if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
  1629. ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
  1630. ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
  1631. ret = 1;
  1632. }
  1633. }else {
  1634. if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
  1635. ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
  1636. ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
  1637. ret = 1;
  1638. }
  1639. }
  1640. } else {
  1641. if ((!herc && (rev_id >= 4)) || herc) {
  1642. if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
  1643. ADAPTER_STATUS_RMAC_PCC_IDLE) &&
  1644. (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
  1645. ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
  1646. ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
  1647. ret = 1;
  1648. }
  1649. } else {
  1650. if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
  1651. ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
  1652. (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
  1653. ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
  1654. ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
  1655. ret = 1;
  1656. }
  1657. }
  1658. }
  1659. return ret;
  1660. }
  1661. /**
  1662. * verify_xena_quiescence - Checks whether the H/W is ready
  1663. * @val64 : Value read from adapter status register.
  1664. * @flag : indicates if the adapter enable bit was ever written once
  1665. * before.
  1666. * Description: Returns whether the H/W is ready to go or not. Depending
  1667. * on whether adapter enable bit was written or not the comparison
  1668. * differs and the calling function passes the input argument flag to
  1669. * indicate this.
  1670. * Return: 1 If xena is quiescence
  1671. * 0 If Xena is not quiescence
  1672. */
  1673. static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
  1674. {
  1675. int ret = 0, herc;
  1676. u64 tmp64 = ~((u64) val64);
  1677. int rev_id = get_xena_rev_id(sp->pdev);
  1678. herc = (sp->device_type == XFRAME_II_DEVICE);
  1679. if (!
  1680. (tmp64 &
  1681. (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
  1682. ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
  1683. ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
  1684. ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
  1685. ADAPTER_STATUS_P_PLL_LOCK))) {
  1686. ret = check_prc_pcc_state(val64, flag, rev_id, herc);
  1687. }
  1688. return ret;
  1689. }
  1690. /**
  1691. * fix_mac_address - Fix for Mac addr problem on Alpha platforms
  1692. * @sp: Pointer to device specifc structure
  1693. * Description :
  1694. * New procedure to clear mac address reading problems on Alpha platforms
  1695. *
  1696. */
  1697. void fix_mac_address(nic_t * sp)
  1698. {
  1699. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  1700. u64 val64;
  1701. int i = 0;
  1702. while (fix_mac[i] != END_SIGN) {
  1703. writeq(fix_mac[i++], &bar0->gpio_control);
  1704. udelay(10);
  1705. val64 = readq(&bar0->gpio_control);
  1706. }
  1707. }
  1708. /**
  1709. * start_nic - Turns the device on
  1710. * @nic : device private variable.
  1711. * Description:
  1712. * This function actually turns the device on. Before this function is
  1713. * called,all Registers are configured from their reset states
  1714. * and shared memory is allocated but the NIC is still quiescent. On
  1715. * calling this function, the device interrupts are cleared and the NIC is
  1716. * literally switched on by writing into the adapter control register.
  1717. * Return Value:
  1718. * SUCCESS on success and -1 on failure.
  1719. */
  1720. static int start_nic(struct s2io_nic *nic)
  1721. {
  1722. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  1723. struct net_device *dev = nic->dev;
  1724. register u64 val64 = 0;
  1725. u16 interruptible;
  1726. u16 subid, i;
  1727. mac_info_t *mac_control;
  1728. struct config_param *config;
  1729. mac_control = &nic->mac_control;
  1730. config = &nic->config;
  1731. /* PRC Initialization and configuration */
  1732. for (i = 0; i < config->rx_ring_num; i++) {
  1733. writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
  1734. &bar0->prc_rxd0_n[i]);
  1735. val64 = readq(&bar0->prc_ctrl_n[i]);
  1736. if (nic->config.bimodal)
  1737. val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
  1738. #ifndef CONFIG_2BUFF_MODE
  1739. val64 |= PRC_CTRL_RC_ENABLED;
  1740. #else
  1741. val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
  1742. #endif
  1743. writeq(val64, &bar0->prc_ctrl_n[i]);
  1744. }
  1745. #ifdef CONFIG_2BUFF_MODE
  1746. /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
  1747. val64 = readq(&bar0->rx_pa_cfg);
  1748. val64 |= RX_PA_CFG_IGNORE_L2_ERR;
  1749. writeq(val64, &bar0->rx_pa_cfg);
  1750. #endif
  1751. /*
  1752. * Enabling MC-RLDRAM. After enabling the device, we timeout
  1753. * for around 100ms, which is approximately the time required
  1754. * for the device to be ready for operation.
  1755. */
  1756. val64 = readq(&bar0->mc_rldram_mrs);
  1757. val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
  1758. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  1759. val64 = readq(&bar0->mc_rldram_mrs);
  1760. msleep(100); /* Delay by around 100 ms. */
  1761. /* Enabling ECC Protection. */
  1762. val64 = readq(&bar0->adapter_control);
  1763. val64 &= ~ADAPTER_ECC_EN;
  1764. writeq(val64, &bar0->adapter_control);
  1765. /*
  1766. * Clearing any possible Link state change interrupts that
  1767. * could have popped up just before Enabling the card.
  1768. */
  1769. val64 = readq(&bar0->mac_rmac_err_reg);
  1770. if (val64)
  1771. writeq(val64, &bar0->mac_rmac_err_reg);
  1772. /*
  1773. * Verify if the device is ready to be enabled, if so enable
  1774. * it.
  1775. */
  1776. val64 = readq(&bar0->adapter_status);
  1777. if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
  1778. DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
  1779. DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
  1780. (unsigned long long) val64);
  1781. return FAILURE;
  1782. }
  1783. /* Enable select interrupts */
  1784. if (nic->intr_type != INTA)
  1785. en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
  1786. else {
  1787. interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
  1788. interruptible |= TX_PIC_INTR | RX_PIC_INTR;
  1789. interruptible |= TX_MAC_INTR | RX_MAC_INTR;
  1790. en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
  1791. }
  1792. /*
  1793. * With some switches, link might be already up at this point.
  1794. * Because of this weird behavior, when we enable laser,
  1795. * we may not get link. We need to handle this. We cannot
  1796. * figure out which switch is misbehaving. So we are forced to
  1797. * make a global change.
  1798. */
  1799. /* Enabling Laser. */
  1800. val64 = readq(&bar0->adapter_control);
  1801. val64 |= ADAPTER_EOI_TX_ON;
  1802. writeq(val64, &bar0->adapter_control);
  1803. /* SXE-002: Initialize link and activity LED */
  1804. subid = nic->pdev->subsystem_device;
  1805. if (((subid & 0xFF) >= 0x07) &&
  1806. (nic->device_type == XFRAME_I_DEVICE)) {
  1807. val64 = readq(&bar0->gpio_control);
  1808. val64 |= 0x0000800000000000ULL;
  1809. writeq(val64, &bar0->gpio_control);
  1810. val64 = 0x0411040400000000ULL;
  1811. writeq(val64, (void __iomem *)bar0 + 0x2700);
  1812. }
  1813. /*
  1814. * Don't see link state interrupts on certain switches, so
  1815. * directly scheduling a link state task from here.
  1816. */
  1817. schedule_work(&nic->set_link_task);
  1818. return SUCCESS;
  1819. }
  1820. /**
  1821. * free_tx_buffers - Free all queued Tx buffers
  1822. * @nic : device private variable.
  1823. * Description:
  1824. * Free all queued Tx buffers.
  1825. * Return Value: void
  1826. */
  1827. static void free_tx_buffers(struct s2io_nic *nic)
  1828. {
  1829. struct net_device *dev = nic->dev;
  1830. struct sk_buff *skb;
  1831. TxD_t *txdp;
  1832. int i, j;
  1833. mac_info_t *mac_control;
  1834. struct config_param *config;
  1835. int cnt = 0, frg_cnt;
  1836. mac_control = &nic->mac_control;
  1837. config = &nic->config;
  1838. for (i = 0; i < config->tx_fifo_num; i++) {
  1839. for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
  1840. txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
  1841. list_virt_addr;
  1842. skb =
  1843. (struct sk_buff *) ((unsigned long) txdp->
  1844. Host_Control);
  1845. if (skb == NULL) {
  1846. memset(txdp, 0, sizeof(TxD_t) *
  1847. config->max_txds);
  1848. continue;
  1849. }
  1850. frg_cnt = skb_shinfo(skb)->nr_frags;
  1851. pci_unmap_single(nic->pdev, (dma_addr_t)
  1852. txdp->Buffer_Pointer,
  1853. skb->len - skb->data_len,
  1854. PCI_DMA_TODEVICE);
  1855. if (frg_cnt) {
  1856. TxD_t *temp;
  1857. temp = txdp;
  1858. txdp++;
  1859. for (j = 0; j < frg_cnt; j++, txdp++) {
  1860. skb_frag_t *frag =
  1861. &skb_shinfo(skb)->frags[j];
  1862. pci_unmap_page(nic->pdev,
  1863. (dma_addr_t)
  1864. txdp->
  1865. Buffer_Pointer,
  1866. frag->size,
  1867. PCI_DMA_TODEVICE);
  1868. }
  1869. txdp = temp;
  1870. }
  1871. dev_kfree_skb(skb);
  1872. memset(txdp, 0, sizeof(TxD_t) * config->max_txds);
  1873. cnt++;
  1874. }
  1875. DBG_PRINT(INTR_DBG,
  1876. "%s:forcibly freeing %d skbs on FIFO%d\n",
  1877. dev->name, cnt, i);
  1878. mac_control->fifos[i].tx_curr_get_info.offset = 0;
  1879. mac_control->fifos[i].tx_curr_put_info.offset = 0;
  1880. }
  1881. }
  1882. /**
  1883. * stop_nic - To stop the nic
  1884. * @nic ; device private variable.
  1885. * Description:
  1886. * This function does exactly the opposite of what the start_nic()
  1887. * function does. This function is called to stop the device.
  1888. * Return Value:
  1889. * void.
  1890. */
  1891. static void stop_nic(struct s2io_nic *nic)
  1892. {
  1893. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  1894. register u64 val64 = 0;
  1895. u16 interruptible, i;
  1896. mac_info_t *mac_control;
  1897. struct config_param *config;
  1898. mac_control = &nic->mac_control;
  1899. config = &nic->config;
  1900. /* Disable all interrupts */
  1901. interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
  1902. interruptible |= TX_PIC_INTR | RX_PIC_INTR;
  1903. interruptible |= TX_MAC_INTR | RX_MAC_INTR;
  1904. en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
  1905. /* Disable PRCs */
  1906. for (i = 0; i < config->rx_ring_num; i++) {
  1907. val64 = readq(&bar0->prc_ctrl_n[i]);
  1908. val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
  1909. writeq(val64, &bar0->prc_ctrl_n[i]);
  1910. }
  1911. }
  1912. /**
  1913. * fill_rx_buffers - Allocates the Rx side skbs
  1914. * @nic: device private variable
  1915. * @ring_no: ring number
  1916. * Description:
  1917. * The function allocates Rx side skbs and puts the physical
  1918. * address of these buffers into the RxD buffer pointers, so that the NIC
  1919. * can DMA the received frame into these locations.
  1920. * The NIC supports 3 receive modes, viz
  1921. * 1. single buffer,
  1922. * 2. three buffer and
  1923. * 3. Five buffer modes.
  1924. * Each mode defines how many fragments the received frame will be split
  1925. * up into by the NIC. The frame is split into L3 header, L4 Header,
  1926. * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
  1927. * is split into 3 fragments. As of now only single buffer mode is
  1928. * supported.
  1929. * Return Value:
  1930. * SUCCESS on success or an appropriate -ve value on failure.
  1931. */
  1932. int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
  1933. {
  1934. struct net_device *dev = nic->dev;
  1935. struct sk_buff *skb;
  1936. RxD_t *rxdp;
  1937. int off, off1, size, block_no, block_no1;
  1938. int offset, offset1;
  1939. u32 alloc_tab = 0;
  1940. u32 alloc_cnt;
  1941. mac_info_t *mac_control;
  1942. struct config_param *config;
  1943. #ifdef CONFIG_2BUFF_MODE
  1944. RxD_t *rxdpnext;
  1945. int nextblk;
  1946. u64 tmp;
  1947. buffAdd_t *ba;
  1948. dma_addr_t rxdpphys;
  1949. #endif
  1950. #ifndef CONFIG_S2IO_NAPI
  1951. unsigned long flags;
  1952. #endif
  1953. RxD_t *first_rxdp = NULL;
  1954. mac_control = &nic->mac_control;
  1955. config = &nic->config;
  1956. alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
  1957. atomic_read(&nic->rx_bufs_left[ring_no]);
  1958. size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
  1959. HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
  1960. while (alloc_tab < alloc_cnt) {
  1961. block_no = mac_control->rings[ring_no].rx_curr_put_info.
  1962. block_index;
  1963. block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
  1964. block_index;
  1965. off = mac_control->rings[ring_no].rx_curr_put_info.offset;
  1966. off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
  1967. #ifndef CONFIG_2BUFF_MODE
  1968. offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
  1969. offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
  1970. #else
  1971. offset = block_no * (MAX_RXDS_PER_BLOCK) + off;
  1972. offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
  1973. #endif
  1974. rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
  1975. block_virt_addr + off;
  1976. if ((offset == offset1) && (rxdp->Host_Control)) {
  1977. DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
  1978. DBG_PRINT(INTR_DBG, " info equated\n");
  1979. goto end;
  1980. }
  1981. #ifndef CONFIG_2BUFF_MODE
  1982. if (rxdp->Control_1 == END_OF_BLOCK) {
  1983. mac_control->rings[ring_no].rx_curr_put_info.
  1984. block_index++;
  1985. mac_control->rings[ring_no].rx_curr_put_info.
  1986. block_index %= mac_control->rings[ring_no].block_count;
  1987. block_no = mac_control->rings[ring_no].rx_curr_put_info.
  1988. block_index;
  1989. off++;
  1990. off %= (MAX_RXDS_PER_BLOCK + 1);
  1991. mac_control->rings[ring_no].rx_curr_put_info.offset =
  1992. off;
  1993. rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
  1994. DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
  1995. dev->name, rxdp);
  1996. }
  1997. #ifndef CONFIG_S2IO_NAPI
  1998. spin_lock_irqsave(&nic->put_lock, flags);
  1999. mac_control->rings[ring_no].put_pos =
  2000. (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
  2001. spin_unlock_irqrestore(&nic->put_lock, flags);
  2002. #endif
  2003. #else
  2004. if (rxdp->Host_Control == END_OF_BLOCK) {
  2005. mac_control->rings[ring_no].rx_curr_put_info.
  2006. block_index++;
  2007. mac_control->rings[ring_no].rx_curr_put_info.block_index
  2008. %= mac_control->rings[ring_no].block_count;
  2009. block_no = mac_control->rings[ring_no].rx_curr_put_info
  2010. .block_index;
  2011. off = 0;
  2012. DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
  2013. dev->name, block_no,
  2014. (unsigned long long) rxdp->Control_1);
  2015. mac_control->rings[ring_no].rx_curr_put_info.offset =
  2016. off;
  2017. rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
  2018. block_virt_addr;
  2019. }
  2020. #ifndef CONFIG_S2IO_NAPI
  2021. spin_lock_irqsave(&nic->put_lock, flags);
  2022. mac_control->rings[ring_no].put_pos = (block_no *
  2023. (MAX_RXDS_PER_BLOCK + 1)) + off;
  2024. spin_unlock_irqrestore(&nic->put_lock, flags);
  2025. #endif
  2026. #endif
  2027. #ifndef CONFIG_2BUFF_MODE
  2028. if (rxdp->Control_1 & RXD_OWN_XENA)
  2029. #else
  2030. if (rxdp->Control_2 & BIT(0))
  2031. #endif
  2032. {
  2033. mac_control->rings[ring_no].rx_curr_put_info.
  2034. offset = off;
  2035. goto end;
  2036. }
  2037. #ifdef CONFIG_2BUFF_MODE
  2038. /*
  2039. * RxDs Spanning cache lines will be replenished only
  2040. * if the succeeding RxD is also owned by Host. It
  2041. * will always be the ((8*i)+3) and ((8*i)+6)
  2042. * descriptors for the 48 byte descriptor. The offending
  2043. * decsriptor is of-course the 3rd descriptor.
  2044. */
  2045. rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no].
  2046. block_dma_addr + (off * sizeof(RxD_t));
  2047. if (((u64) (rxdpphys)) % 128 > 80) {
  2048. rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no].
  2049. block_virt_addr + (off + 1);
  2050. if (rxdpnext->Host_Control == END_OF_BLOCK) {
  2051. nextblk = (block_no + 1) %
  2052. (mac_control->rings[ring_no].block_count);
  2053. rxdpnext = mac_control->rings[ring_no].rx_blocks
  2054. [nextblk].block_virt_addr;
  2055. }
  2056. if (rxdpnext->Control_2 & BIT(0))
  2057. goto end;
  2058. }
  2059. #endif
  2060. #ifndef CONFIG_2BUFF_MODE
  2061. skb = dev_alloc_skb(size + NET_IP_ALIGN);
  2062. #else
  2063. skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE + BUF0_LEN + 4);
  2064. #endif
  2065. if (!skb) {
  2066. DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
  2067. DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
  2068. if (first_rxdp) {
  2069. wmb();
  2070. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2071. }
  2072. return -ENOMEM;
  2073. }
  2074. #ifndef CONFIG_2BUFF_MODE
  2075. skb_reserve(skb, NET_IP_ALIGN);
  2076. memset(rxdp, 0, sizeof(RxD_t));
  2077. rxdp->Buffer0_ptr = pci_map_single
  2078. (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
  2079. rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
  2080. rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
  2081. rxdp->Host_Control = (unsigned long) (skb);
  2082. if (alloc_tab & ((1 << rxsync_frequency) - 1))
  2083. rxdp->Control_1 |= RXD_OWN_XENA;
  2084. off++;
  2085. off %= (MAX_RXDS_PER_BLOCK + 1);
  2086. mac_control->rings[ring_no].rx_curr_put_info.offset = off;
  2087. #else
  2088. ba = &mac_control->rings[ring_no].ba[block_no][off];
  2089. skb_reserve(skb, BUF0_LEN);
  2090. tmp = ((unsigned long) skb->data & ALIGN_SIZE);
  2091. if (tmp)
  2092. skb_reserve(skb, (ALIGN_SIZE + 1) - tmp);
  2093. memset(rxdp, 0, sizeof(RxD_t));
  2094. rxdp->Buffer2_ptr = pci_map_single
  2095. (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4,
  2096. PCI_DMA_FROMDEVICE);
  2097. rxdp->Buffer0_ptr =
  2098. pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
  2099. PCI_DMA_FROMDEVICE);
  2100. rxdp->Buffer1_ptr =
  2101. pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
  2102. PCI_DMA_FROMDEVICE);
  2103. rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4);
  2104. rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN);
  2105. rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
  2106. rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */
  2107. rxdp->Host_Control = (u64) ((unsigned long) (skb));
  2108. if (alloc_tab & ((1 << rxsync_frequency) - 1))
  2109. rxdp->Control_1 |= RXD_OWN_XENA;
  2110. off++;
  2111. mac_control->rings[ring_no].rx_curr_put_info.offset = off;
  2112. #endif
  2113. rxdp->Control_2 |= SET_RXD_MARKER;
  2114. if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
  2115. if (first_rxdp) {
  2116. wmb();
  2117. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2118. }
  2119. first_rxdp = rxdp;
  2120. }
  2121. atomic_inc(&nic->rx_bufs_left[ring_no]);
  2122. alloc_tab++;
  2123. }
  2124. end:
  2125. /* Transfer ownership of first descriptor to adapter just before
  2126. * exiting. Before that, use memory barrier so that ownership
  2127. * and other fields are seen by adapter correctly.
  2128. */
  2129. if (first_rxdp) {
  2130. wmb();
  2131. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2132. }
  2133. return SUCCESS;
  2134. }
  2135. /**
  2136. * free_rx_buffers - Frees all Rx buffers
  2137. * @sp: device private variable.
  2138. * Description:
  2139. * This function will free all Rx buffers allocated by host.
  2140. * Return Value:
  2141. * NONE.
  2142. */
  2143. static void free_rx_buffers(struct s2io_nic *sp)
  2144. {
  2145. struct net_device *dev = sp->dev;
  2146. int i, j, blk = 0, off, buf_cnt = 0;
  2147. RxD_t *rxdp;
  2148. struct sk_buff *skb;
  2149. mac_info_t *mac_control;
  2150. struct config_param *config;
  2151. #ifdef CONFIG_2BUFF_MODE
  2152. buffAdd_t *ba;
  2153. #endif
  2154. mac_control = &sp->mac_control;
  2155. config = &sp->config;
  2156. for (i = 0; i < config->rx_ring_num; i++) {
  2157. for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) {
  2158. off = j % (MAX_RXDS_PER_BLOCK + 1);
  2159. rxdp = mac_control->rings[i].rx_blocks[blk].
  2160. block_virt_addr + off;
  2161. #ifndef CONFIG_2BUFF_MODE
  2162. if (rxdp->Control_1 == END_OF_BLOCK) {
  2163. rxdp =
  2164. (RxD_t *) ((unsigned long) rxdp->
  2165. Control_2);
  2166. j++;
  2167. blk++;
  2168. }
  2169. #else
  2170. if (rxdp->Host_Control == END_OF_BLOCK) {
  2171. blk++;
  2172. continue;
  2173. }
  2174. #endif
  2175. if (!(rxdp->Control_1 & RXD_OWN_XENA)) {
  2176. memset(rxdp, 0, sizeof(RxD_t));
  2177. continue;
  2178. }
  2179. skb =
  2180. (struct sk_buff *) ((unsigned long) rxdp->
  2181. Host_Control);
  2182. if (skb) {
  2183. #ifndef CONFIG_2BUFF_MODE
  2184. pci_unmap_single(sp->pdev, (dma_addr_t)
  2185. rxdp->Buffer0_ptr,
  2186. dev->mtu +
  2187. HEADER_ETHERNET_II_802_3_SIZE
  2188. + HEADER_802_2_SIZE +
  2189. HEADER_SNAP_SIZE,
  2190. PCI_DMA_FROMDEVICE);
  2191. #else
  2192. ba = &mac_control->rings[i].ba[blk][off];
  2193. pci_unmap_single(sp->pdev, (dma_addr_t)
  2194. rxdp->Buffer0_ptr,
  2195. BUF0_LEN,
  2196. PCI_DMA_FROMDEVICE);
  2197. pci_unmap_single(sp->pdev, (dma_addr_t)
  2198. rxdp->Buffer1_ptr,
  2199. BUF1_LEN,
  2200. PCI_DMA_FROMDEVICE);
  2201. pci_unmap_single(sp->pdev, (dma_addr_t)
  2202. rxdp->Buffer2_ptr,
  2203. dev->mtu + BUF0_LEN + 4,
  2204. PCI_DMA_FROMDEVICE);
  2205. #endif
  2206. dev_kfree_skb(skb);
  2207. atomic_dec(&sp->rx_bufs_left[i]);
  2208. buf_cnt++;
  2209. }
  2210. memset(rxdp, 0, sizeof(RxD_t));
  2211. }
  2212. mac_control->rings[i].rx_curr_put_info.block_index = 0;
  2213. mac_control->rings[i].rx_curr_get_info.block_index = 0;
  2214. mac_control->rings[i].rx_curr_put_info.offset = 0;
  2215. mac_control->rings[i].rx_curr_get_info.offset = 0;
  2216. atomic_set(&sp->rx_bufs_left[i], 0);
  2217. DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
  2218. dev->name, buf_cnt, i);
  2219. }
  2220. }
  2221. /**
  2222. * s2io_poll - Rx interrupt handler for NAPI support
  2223. * @dev : pointer to the device structure.
  2224. * @budget : The number of packets that were budgeted to be processed
  2225. * during one pass through the 'Poll" function.
  2226. * Description:
  2227. * Comes into picture only if NAPI support has been incorporated. It does
  2228. * the same thing that rx_intr_handler does, but not in a interrupt context
  2229. * also It will process only a given number of packets.
  2230. * Return value:
  2231. * 0 on success and 1 if there are No Rx packets to be processed.
  2232. */
  2233. #if defined(CONFIG_S2IO_NAPI)
  2234. static int s2io_poll(struct net_device *dev, int *budget)
  2235. {
  2236. nic_t *nic = dev->priv;
  2237. int pkt_cnt = 0, org_pkts_to_process;
  2238. mac_info_t *mac_control;
  2239. struct config_param *config;
  2240. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  2241. u64 val64;
  2242. int i;
  2243. atomic_inc(&nic->isr_cnt);
  2244. mac_control = &nic->mac_control;
  2245. config = &nic->config;
  2246. nic->pkts_to_process = *budget;
  2247. if (nic->pkts_to_process > dev->quota)
  2248. nic->pkts_to_process = dev->quota;
  2249. org_pkts_to_process = nic->pkts_to_process;
  2250. val64 = readq(&bar0->rx_traffic_int);
  2251. writeq(val64, &bar0->rx_traffic_int);
  2252. for (i = 0; i < config->rx_ring_num; i++) {
  2253. rx_intr_handler(&mac_control->rings[i]);
  2254. pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
  2255. if (!nic->pkts_to_process) {
  2256. /* Quota for the current iteration has been met */
  2257. goto no_rx;
  2258. }
  2259. }
  2260. if (!pkt_cnt)
  2261. pkt_cnt = 1;
  2262. dev->quota -= pkt_cnt;
  2263. *budget -= pkt_cnt;
  2264. netif_rx_complete(dev);
  2265. for (i = 0; i < config->rx_ring_num; i++) {
  2266. if (fill_rx_buffers(nic, i) == -ENOMEM) {
  2267. DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
  2268. DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
  2269. break;
  2270. }
  2271. }
  2272. /* Re enable the Rx interrupts. */
  2273. en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
  2274. atomic_dec(&nic->isr_cnt);
  2275. return 0;
  2276. no_rx:
  2277. dev->quota -= pkt_cnt;
  2278. *budget -= pkt_cnt;
  2279. for (i = 0; i < config->rx_ring_num; i++) {
  2280. if (fill_rx_buffers(nic, i) == -ENOMEM) {
  2281. DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
  2282. DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
  2283. break;
  2284. }
  2285. }
  2286. atomic_dec(&nic->isr_cnt);
  2287. return 1;
  2288. }
  2289. #endif
  2290. /**
  2291. * rx_intr_handler - Rx interrupt handler
  2292. * @nic: device private variable.
  2293. * Description:
  2294. * If the interrupt is because of a received frame or if the
  2295. * receive ring contains fresh as yet un-processed frames,this function is
  2296. * called. It picks out the RxD at which place the last Rx processing had
  2297. * stopped and sends the skb to the OSM's Rx handler and then increments
  2298. * the offset.
  2299. * Return Value:
  2300. * NONE.
  2301. */
  2302. static void rx_intr_handler(ring_info_t *ring_data)
  2303. {
  2304. nic_t *nic = ring_data->nic;
  2305. struct net_device *dev = (struct net_device *) nic->dev;
  2306. int get_block, get_offset, put_block, put_offset, ring_bufs;
  2307. rx_curr_get_info_t get_info, put_info;
  2308. RxD_t *rxdp;
  2309. struct sk_buff *skb;
  2310. #ifndef CONFIG_S2IO_NAPI
  2311. int pkt_cnt = 0;
  2312. #endif
  2313. spin_lock(&nic->rx_lock);
  2314. if (atomic_read(&nic->card_state) == CARD_DOWN) {
  2315. DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
  2316. __FUNCTION__, dev->name);
  2317. spin_unlock(&nic->rx_lock);
  2318. return;
  2319. }
  2320. get_info = ring_data->rx_curr_get_info;
  2321. get_block = get_info.block_index;
  2322. put_info = ring_data->rx_curr_put_info;
  2323. put_block = put_info.block_index;
  2324. ring_bufs = get_info.ring_len+1;
  2325. rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
  2326. get_info.offset;
  2327. get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
  2328. get_info.offset;
  2329. #ifndef CONFIG_S2IO_NAPI
  2330. spin_lock(&nic->put_lock);
  2331. put_offset = ring_data->put_pos;
  2332. spin_unlock(&nic->put_lock);
  2333. #else
  2334. put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
  2335. put_info.offset;
  2336. #endif
  2337. while (RXD_IS_UP2DT(rxdp) &&
  2338. (((get_offset + 1) % ring_bufs) != put_offset)) {
  2339. skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
  2340. if (skb == NULL) {
  2341. DBG_PRINT(ERR_DBG, "%s: The skb is ",
  2342. dev->name);
  2343. DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
  2344. spin_unlock(&nic->rx_lock);
  2345. return;
  2346. }
  2347. #ifndef CONFIG_2BUFF_MODE
  2348. pci_unmap_single(nic->pdev, (dma_addr_t)
  2349. rxdp->Buffer0_ptr,
  2350. dev->mtu +
  2351. HEADER_ETHERNET_II_802_3_SIZE +
  2352. HEADER_802_2_SIZE +
  2353. HEADER_SNAP_SIZE,
  2354. PCI_DMA_FROMDEVICE);
  2355. #else
  2356. pci_unmap_single(nic->pdev, (dma_addr_t)
  2357. rxdp->Buffer0_ptr,
  2358. BUF0_LEN, PCI_DMA_FROMDEVICE);
  2359. pci_unmap_single(nic->pdev, (dma_addr_t)
  2360. rxdp->Buffer1_ptr,
  2361. BUF1_LEN, PCI_DMA_FROMDEVICE);
  2362. pci_unmap_single(nic->pdev, (dma_addr_t)
  2363. rxdp->Buffer2_ptr,
  2364. dev->mtu + BUF0_LEN + 4,
  2365. PCI_DMA_FROMDEVICE);
  2366. #endif
  2367. rx_osm_handler(ring_data, rxdp);
  2368. get_info.offset++;
  2369. ring_data->rx_curr_get_info.offset =
  2370. get_info.offset;
  2371. rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
  2372. get_info.offset;
  2373. if (get_info.offset &&
  2374. (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
  2375. get_info.offset = 0;
  2376. ring_data->rx_curr_get_info.offset
  2377. = get_info.offset;
  2378. get_block++;
  2379. get_block %= ring_data->block_count;
  2380. ring_data->rx_curr_get_info.block_index
  2381. = get_block;
  2382. rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
  2383. }
  2384. get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
  2385. get_info.offset;
  2386. #ifdef CONFIG_S2IO_NAPI
  2387. nic->pkts_to_process -= 1;
  2388. if (!nic->pkts_to_process)
  2389. break;
  2390. #else
  2391. pkt_cnt++;
  2392. if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
  2393. break;
  2394. #endif
  2395. }
  2396. spin_unlock(&nic->rx_lock);
  2397. }
  2398. /**
  2399. * tx_intr_handler - Transmit interrupt handler
  2400. * @nic : device private variable
  2401. * Description:
  2402. * If an interrupt was raised to indicate DMA complete of the
  2403. * Tx packet, this function is called. It identifies the last TxD
  2404. * whose buffer was freed and frees all skbs whose data have already
  2405. * DMA'ed into the NICs internal memory.
  2406. * Return Value:
  2407. * NONE
  2408. */
  2409. static void tx_intr_handler(fifo_info_t *fifo_data)
  2410. {
  2411. nic_t *nic = fifo_data->nic;
  2412. struct net_device *dev = (struct net_device *) nic->dev;
  2413. tx_curr_get_info_t get_info, put_info;
  2414. struct sk_buff *skb;
  2415. TxD_t *txdlp;
  2416. u16 j, frg_cnt;
  2417. get_info = fifo_data->tx_curr_get_info;
  2418. put_info = fifo_data->tx_curr_put_info;
  2419. txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
  2420. list_virt_addr;
  2421. while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
  2422. (get_info.offset != put_info.offset) &&
  2423. (txdlp->Host_Control)) {
  2424. /* Check for TxD errors */
  2425. if (txdlp->Control_1 & TXD_T_CODE) {
  2426. unsigned long long err;
  2427. err = txdlp->Control_1 & TXD_T_CODE;
  2428. if ((err >> 48) == 0xA) {
  2429. DBG_PRINT(TX_DBG, "TxD returned due \
  2430. to loss of link\n");
  2431. }
  2432. else {
  2433. DBG_PRINT(ERR_DBG, "***TxD error \
  2434. %llx\n", err);
  2435. }
  2436. }
  2437. skb = (struct sk_buff *) ((unsigned long)
  2438. txdlp->Host_Control);
  2439. if (skb == NULL) {
  2440. DBG_PRINT(ERR_DBG, "%s: Null skb ",
  2441. __FUNCTION__);
  2442. DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
  2443. return;
  2444. }
  2445. frg_cnt = skb_shinfo(skb)->nr_frags;
  2446. nic->tx_pkt_count++;
  2447. pci_unmap_single(nic->pdev, (dma_addr_t)
  2448. txdlp->Buffer_Pointer,
  2449. skb->len - skb->data_len,
  2450. PCI_DMA_TODEVICE);
  2451. if (frg_cnt) {
  2452. TxD_t *temp;
  2453. temp = txdlp;
  2454. txdlp++;
  2455. for (j = 0; j < frg_cnt; j++, txdlp++) {
  2456. skb_frag_t *frag =
  2457. &skb_shinfo(skb)->frags[j];
  2458. if (!txdlp->Buffer_Pointer)
  2459. break;
  2460. pci_unmap_page(nic->pdev,
  2461. (dma_addr_t)
  2462. txdlp->
  2463. Buffer_Pointer,
  2464. frag->size,
  2465. PCI_DMA_TODEVICE);
  2466. }
  2467. txdlp = temp;
  2468. }
  2469. memset(txdlp, 0,
  2470. (sizeof(TxD_t) * fifo_data->max_txds));
  2471. /* Updating the statistics block */
  2472. nic->stats.tx_bytes += skb->len;
  2473. dev_kfree_skb_irq(skb);
  2474. get_info.offset++;
  2475. get_info.offset %= get_info.fifo_len + 1;
  2476. txdlp = (TxD_t *) fifo_data->list_info
  2477. [get_info.offset].list_virt_addr;
  2478. fifo_data->tx_curr_get_info.offset =
  2479. get_info.offset;
  2480. }
  2481. spin_lock(&nic->tx_lock);
  2482. if (netif_queue_stopped(dev))
  2483. netif_wake_queue(dev);
  2484. spin_unlock(&nic->tx_lock);
  2485. }
  2486. /**
  2487. * alarm_intr_handler - Alarm Interrrupt handler
  2488. * @nic: device private variable
  2489. * Description: If the interrupt was neither because of Rx packet or Tx
  2490. * complete, this function is called. If the interrupt was to indicate
  2491. * a loss of link, the OSM link status handler is invoked for any other
  2492. * alarm interrupt the block that raised the interrupt is displayed
  2493. * and a H/W reset is issued.
  2494. * Return Value:
  2495. * NONE
  2496. */
  2497. static void alarm_intr_handler(struct s2io_nic *nic)
  2498. {
  2499. struct net_device *dev = (struct net_device *) nic->dev;
  2500. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  2501. register u64 val64 = 0, err_reg = 0;
  2502. /* Handling link status change error Intr */
  2503. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
  2504. err_reg = readq(&bar0->mac_rmac_err_reg);
  2505. writeq(err_reg, &bar0->mac_rmac_err_reg);
  2506. if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
  2507. schedule_work(&nic->set_link_task);
  2508. }
  2509. }
  2510. /* Handling Ecc errors */
  2511. val64 = readq(&bar0->mc_err_reg);
  2512. writeq(val64, &bar0->mc_err_reg);
  2513. if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
  2514. if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
  2515. nic->mac_control.stats_info->sw_stat.
  2516. double_ecc_errs++;
  2517. DBG_PRINT(INIT_DBG, "%s: Device indicates ",
  2518. dev->name);
  2519. DBG_PRINT(INIT_DBG, "double ECC error!!\n");
  2520. if (nic->device_type != XFRAME_II_DEVICE) {
  2521. /* Reset XframeI only if critical error */
  2522. if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
  2523. MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
  2524. netif_stop_queue(dev);
  2525. schedule_work(&nic->rst_timer_task);
  2526. }
  2527. }
  2528. } else {
  2529. nic->mac_control.stats_info->sw_stat.
  2530. single_ecc_errs++;
  2531. }
  2532. }
  2533. /* In case of a serious error, the device will be Reset. */
  2534. val64 = readq(&bar0->serr_source);
  2535. if (val64 & SERR_SOURCE_ANY) {
  2536. DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
  2537. DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
  2538. (unsigned long long)val64);
  2539. netif_stop_queue(dev);
  2540. schedule_work(&nic->rst_timer_task);
  2541. }
  2542. /*
  2543. * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
  2544. * Error occurs, the adapter will be recycled by disabling the
  2545. * adapter enable bit and enabling it again after the device
  2546. * becomes Quiescent.
  2547. */
  2548. val64 = readq(&bar0->pcc_err_reg);
  2549. writeq(val64, &bar0->pcc_err_reg);
  2550. if (val64 & PCC_FB_ECC_DB_ERR) {
  2551. u64 ac = readq(&bar0->adapter_control);
  2552. ac &= ~(ADAPTER_CNTL_EN);
  2553. writeq(ac, &bar0->adapter_control);
  2554. ac = readq(&bar0->adapter_control);
  2555. schedule_work(&nic->set_link_task);
  2556. }
  2557. /* Other type of interrupts are not being handled now, TODO */
  2558. }
  2559. /**
  2560. * wait_for_cmd_complete - waits for a command to complete.
  2561. * @sp : private member of the device structure, which is a pointer to the
  2562. * s2io_nic structure.
  2563. * Description: Function that waits for a command to Write into RMAC
  2564. * ADDR DATA registers to be completed and returns either success or
  2565. * error depending on whether the command was complete or not.
  2566. * Return value:
  2567. * SUCCESS on success and FAILURE on failure.
  2568. */
  2569. int wait_for_cmd_complete(nic_t * sp)
  2570. {
  2571. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  2572. int ret = FAILURE, cnt = 0;
  2573. u64 val64;
  2574. while (TRUE) {
  2575. val64 = readq(&bar0->rmac_addr_cmd_mem);
  2576. if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
  2577. ret = SUCCESS;
  2578. break;
  2579. }
  2580. msleep(50);
  2581. if (cnt++ > 10)
  2582. break;
  2583. }
  2584. return ret;
  2585. }
  2586. /**
  2587. * s2io_reset - Resets the card.
  2588. * @sp : private member of the device structure.
  2589. * Description: Function to Reset the card. This function then also
  2590. * restores the previously saved PCI configuration space registers as
  2591. * the card reset also resets the configuration space.
  2592. * Return value:
  2593. * void.
  2594. */
  2595. void s2io_reset(nic_t * sp)
  2596. {
  2597. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  2598. u64 val64;
  2599. u16 subid, pci_cmd;
  2600. /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
  2601. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
  2602. val64 = SW_RESET_ALL;
  2603. writeq(val64, &bar0->sw_reset);
  2604. /*
  2605. * At this stage, if the PCI write is indeed completed, the
  2606. * card is reset and so is the PCI Config space of the device.
  2607. * So a read cannot be issued at this stage on any of the
  2608. * registers to ensure the write into "sw_reset" register
  2609. * has gone through.
  2610. * Question: Is there any system call that will explicitly force
  2611. * all the write commands still pending on the bus to be pushed
  2612. * through?
  2613. * As of now I'am just giving a 250ms delay and hoping that the
  2614. * PCI write to sw_reset register is done by this time.
  2615. */
  2616. msleep(250);
  2617. /* Restore the PCI state saved during initialization. */
  2618. pci_restore_state(sp->pdev);
  2619. pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  2620. pci_cmd);
  2621. s2io_init_pci(sp);
  2622. msleep(250);
  2623. /* Set swapper to enable I/O register access */
  2624. s2io_set_swapper(sp);
  2625. /* Restore the MSIX table entries from local variables */
  2626. restore_xmsi_data(sp);
  2627. /* Clear certain PCI/PCI-X fields after reset */
  2628. if (sp->device_type == XFRAME_II_DEVICE) {
  2629. /* Clear parity err detect bit */
  2630. pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
  2631. /* Clearing PCIX Ecc status register */
  2632. pci_write_config_dword(sp->pdev, 0x68, 0x7C);
  2633. /* Clearing PCI_STATUS error reflected here */
  2634. writeq(BIT(62), &bar0->txpic_int_reg);
  2635. }
  2636. /* Reset device statistics maintained by OS */
  2637. memset(&sp->stats, 0, sizeof (struct net_device_stats));
  2638. /* SXE-002: Configure link and activity LED to turn it off */
  2639. subid = sp->pdev->subsystem_device;
  2640. if (((subid & 0xFF) >= 0x07) &&
  2641. (sp->device_type == XFRAME_I_DEVICE)) {
  2642. val64 = readq(&bar0->gpio_control);
  2643. val64 |= 0x0000800000000000ULL;
  2644. writeq(val64, &bar0->gpio_control);
  2645. val64 = 0x0411040400000000ULL;
  2646. writeq(val64, (void __iomem *)bar0 + 0x2700);
  2647. }
  2648. /*
  2649. * Clear spurious ECC interrupts that would have occured on
  2650. * XFRAME II cards after reset.
  2651. */
  2652. if (sp->device_type == XFRAME_II_DEVICE) {
  2653. val64 = readq(&bar0->pcc_err_reg);
  2654. writeq(val64, &bar0->pcc_err_reg);
  2655. }
  2656. sp->device_enabled_once = FALSE;
  2657. }
  2658. /**
  2659. * s2io_set_swapper - to set the swapper controle on the card
  2660. * @sp : private member of the device structure,
  2661. * pointer to the s2io_nic structure.
  2662. * Description: Function to set the swapper control on the card
  2663. * correctly depending on the 'endianness' of the system.
  2664. * Return value:
  2665. * SUCCESS on success and FAILURE on failure.
  2666. */
  2667. int s2io_set_swapper(nic_t * sp)
  2668. {
  2669. struct net_device *dev = sp->dev;
  2670. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  2671. u64 val64, valt, valr;
  2672. /*
  2673. * Set proper endian settings and verify the same by reading
  2674. * the PIF Feed-back register.
  2675. */
  2676. val64 = readq(&bar0->pif_rd_swapper_fb);
  2677. if (val64 != 0x0123456789ABCDEFULL) {
  2678. int i = 0;
  2679. u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
  2680. 0x8100008181000081ULL, /* FE=1, SE=0 */
  2681. 0x4200004242000042ULL, /* FE=0, SE=1 */
  2682. 0}; /* FE=0, SE=0 */
  2683. while(i<4) {
  2684. writeq(value[i], &bar0->swapper_ctrl);
  2685. val64 = readq(&bar0->pif_rd_swapper_fb);
  2686. if (val64 == 0x0123456789ABCDEFULL)
  2687. break;
  2688. i++;
  2689. }
  2690. if (i == 4) {
  2691. DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
  2692. dev->name);
  2693. DBG_PRINT(ERR_DBG, "feedback read %llx\n",
  2694. (unsigned long long) val64);
  2695. return FAILURE;
  2696. }
  2697. valr = value[i];
  2698. } else {
  2699. valr = readq(&bar0->swapper_ctrl);
  2700. }
  2701. valt = 0x0123456789ABCDEFULL;
  2702. writeq(valt, &bar0->xmsi_address);
  2703. val64 = readq(&bar0->xmsi_address);
  2704. if(val64 != valt) {
  2705. int i = 0;
  2706. u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
  2707. 0x0081810000818100ULL, /* FE=1, SE=0 */
  2708. 0x0042420000424200ULL, /* FE=0, SE=1 */
  2709. 0}; /* FE=0, SE=0 */
  2710. while(i<4) {
  2711. writeq((value[i] | valr), &bar0->swapper_ctrl);
  2712. writeq(valt, &bar0->xmsi_address);
  2713. val64 = readq(&bar0->xmsi_address);
  2714. if(val64 == valt)
  2715. break;
  2716. i++;
  2717. }
  2718. if(i == 4) {
  2719. unsigned long long x = val64;
  2720. DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
  2721. DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
  2722. return FAILURE;
  2723. }
  2724. }
  2725. val64 = readq(&bar0->swapper_ctrl);
  2726. val64 &= 0xFFFF000000000000ULL;
  2727. #ifdef __BIG_ENDIAN
  2728. /*
  2729. * The device by default set to a big endian format, so a
  2730. * big endian driver need not set anything.
  2731. */
  2732. val64 |= (SWAPPER_CTRL_TXP_FE |
  2733. SWAPPER_CTRL_TXP_SE |
  2734. SWAPPER_CTRL_TXD_R_FE |
  2735. SWAPPER_CTRL_TXD_W_FE |
  2736. SWAPPER_CTRL_TXF_R_FE |
  2737. SWAPPER_CTRL_RXD_R_FE |
  2738. SWAPPER_CTRL_RXD_W_FE |
  2739. SWAPPER_CTRL_RXF_W_FE |
  2740. SWAPPER_CTRL_XMSI_FE |
  2741. SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
  2742. if (sp->intr_type == INTA)
  2743. val64 |= SWAPPER_CTRL_XMSI_SE;
  2744. writeq(val64, &bar0->swapper_ctrl);
  2745. #else
  2746. /*
  2747. * Initially we enable all bits to make it accessible by the
  2748. * driver, then we selectively enable only those bits that
  2749. * we want to set.
  2750. */
  2751. val64 |= (SWAPPER_CTRL_TXP_FE |
  2752. SWAPPER_CTRL_TXP_SE |
  2753. SWAPPER_CTRL_TXD_R_FE |
  2754. SWAPPER_CTRL_TXD_R_SE |
  2755. SWAPPER_CTRL_TXD_W_FE |
  2756. SWAPPER_CTRL_TXD_W_SE |
  2757. SWAPPER_CTRL_TXF_R_FE |
  2758. SWAPPER_CTRL_RXD_R_FE |
  2759. SWAPPER_CTRL_RXD_R_SE |
  2760. SWAPPER_CTRL_RXD_W_FE |
  2761. SWAPPER_CTRL_RXD_W_SE |
  2762. SWAPPER_CTRL_RXF_W_FE |
  2763. SWAPPER_CTRL_XMSI_FE |
  2764. SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
  2765. if (sp->intr_type == INTA)
  2766. val64 |= SWAPPER_CTRL_XMSI_SE;
  2767. writeq(val64, &bar0->swapper_ctrl);
  2768. #endif
  2769. val64 = readq(&bar0->swapper_ctrl);
  2770. /*
  2771. * Verifying if endian settings are accurate by reading a
  2772. * feedback register.
  2773. */
  2774. val64 = readq(&bar0->pif_rd_swapper_fb);
  2775. if (val64 != 0x0123456789ABCDEFULL) {
  2776. /* Endian settings are incorrect, calls for another dekko. */
  2777. DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
  2778. dev->name);
  2779. DBG_PRINT(ERR_DBG, "feedback read %llx\n",
  2780. (unsigned long long) val64);
  2781. return FAILURE;
  2782. }
  2783. return SUCCESS;
  2784. }
  2785. int wait_for_msix_trans(nic_t *nic, int i)
  2786. {
  2787. XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
  2788. u64 val64;
  2789. int ret = 0, cnt = 0;
  2790. do {
  2791. val64 = readq(&bar0->xmsi_access);
  2792. if (!(val64 & BIT(15)))
  2793. break;
  2794. mdelay(1);
  2795. cnt++;
  2796. } while(cnt < 5);
  2797. if (cnt == 5) {
  2798. DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
  2799. ret = 1;
  2800. }
  2801. return ret;
  2802. }
  2803. void restore_xmsi_data(nic_t *nic)
  2804. {
  2805. XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
  2806. u64 val64;
  2807. int i;
  2808. for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
  2809. writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
  2810. writeq(nic->msix_info[i].data, &bar0->xmsi_data);
  2811. val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
  2812. writeq(val64, &bar0->xmsi_access);
  2813. if (wait_for_msix_trans(nic, i)) {
  2814. DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
  2815. continue;
  2816. }
  2817. }
  2818. }
  2819. void store_xmsi_data(nic_t *nic)
  2820. {
  2821. XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
  2822. u64 val64, addr, data;
  2823. int i;
  2824. /* Store and display */
  2825. for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
  2826. val64 = (BIT(15) | vBIT(i, 26, 6));
  2827. writeq(val64, &bar0->xmsi_access);
  2828. if (wait_for_msix_trans(nic, i)) {
  2829. DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
  2830. continue;
  2831. }
  2832. addr = readq(&bar0->xmsi_address);
  2833. data = readq(&bar0->xmsi_data);
  2834. if (addr && data) {
  2835. nic->msix_info[i].addr = addr;
  2836. nic->msix_info[i].data = data;
  2837. }
  2838. }
  2839. }
  2840. int s2io_enable_msi(nic_t *nic)
  2841. {
  2842. XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
  2843. u16 msi_ctrl, msg_val;
  2844. struct config_param *config = &nic->config;
  2845. struct net_device *dev = nic->dev;
  2846. u64 val64, tx_mat, rx_mat;
  2847. int i, err;
  2848. val64 = readq(&bar0->pic_control);
  2849. val64 &= ~BIT(1);
  2850. writeq(val64, &bar0->pic_control);
  2851. err = pci_enable_msi(nic->pdev);
  2852. if (err) {
  2853. DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
  2854. nic->dev->name);
  2855. return err;
  2856. }
  2857. /*
  2858. * Enable MSI and use MSI-1 in stead of the standard MSI-0
  2859. * for interrupt handling.
  2860. */
  2861. pci_read_config_word(nic->pdev, 0x4c, &msg_val);
  2862. msg_val ^= 0x1;
  2863. pci_write_config_word(nic->pdev, 0x4c, msg_val);
  2864. pci_read_config_word(nic->pdev, 0x4c, &msg_val);
  2865. pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
  2866. msi_ctrl |= 0x10;
  2867. pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
  2868. /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
  2869. tx_mat = readq(&bar0->tx_mat0_n[0]);
  2870. for (i=0; i<config->tx_fifo_num; i++) {
  2871. tx_mat |= TX_MAT_SET(i, 1);
  2872. }
  2873. writeq(tx_mat, &bar0->tx_mat0_n[0]);
  2874. rx_mat = readq(&bar0->rx_mat);
  2875. for (i=0; i<config->rx_ring_num; i++) {
  2876. rx_mat |= RX_MAT_SET(i, 1);
  2877. }
  2878. writeq(rx_mat, &bar0->rx_mat);
  2879. dev->irq = nic->pdev->irq;
  2880. return 0;
  2881. }
  2882. int s2io_enable_msi_x(nic_t *nic)
  2883. {
  2884. XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
  2885. u64 tx_mat, rx_mat;
  2886. u16 msi_control; /* Temp variable */
  2887. int ret, i, j, msix_indx = 1;
  2888. nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
  2889. GFP_KERNEL);
  2890. if (nic->entries == NULL) {
  2891. DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
  2892. return -ENOMEM;
  2893. }
  2894. memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
  2895. nic->s2io_entries =
  2896. kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
  2897. GFP_KERNEL);
  2898. if (nic->s2io_entries == NULL) {
  2899. DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
  2900. kfree(nic->entries);
  2901. return -ENOMEM;
  2902. }
  2903. memset(nic->s2io_entries, 0,
  2904. MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
  2905. for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
  2906. nic->entries[i].entry = i;
  2907. nic->s2io_entries[i].entry = i;
  2908. nic->s2io_entries[i].arg = NULL;
  2909. nic->s2io_entries[i].in_use = 0;
  2910. }
  2911. tx_mat = readq(&bar0->tx_mat0_n[0]);
  2912. for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
  2913. tx_mat |= TX_MAT_SET(i, msix_indx);
  2914. nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
  2915. nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
  2916. nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
  2917. }
  2918. writeq(tx_mat, &bar0->tx_mat0_n[0]);
  2919. if (!nic->config.bimodal) {
  2920. rx_mat = readq(&bar0->rx_mat);
  2921. for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
  2922. rx_mat |= RX_MAT_SET(j, msix_indx);
  2923. nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
  2924. nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
  2925. nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
  2926. }
  2927. writeq(rx_mat, &bar0->rx_mat);
  2928. } else {
  2929. tx_mat = readq(&bar0->tx_mat0_n[7]);
  2930. for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
  2931. tx_mat |= TX_MAT_SET(i, msix_indx);
  2932. nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
  2933. nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
  2934. nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
  2935. }
  2936. writeq(tx_mat, &bar0->tx_mat0_n[7]);
  2937. }
  2938. ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
  2939. if (ret) {
  2940. DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
  2941. kfree(nic->entries);
  2942. kfree(nic->s2io_entries);
  2943. nic->entries = NULL;
  2944. nic->s2io_entries = NULL;
  2945. return -ENOMEM;
  2946. }
  2947. /*
  2948. * To enable MSI-X, MSI also needs to be enabled, due to a bug
  2949. * in the herc NIC. (Temp change, needs to be removed later)
  2950. */
  2951. pci_read_config_word(nic->pdev, 0x42, &msi_control);
  2952. msi_control |= 0x1; /* Enable MSI */
  2953. pci_write_config_word(nic->pdev, 0x42, msi_control);
  2954. return 0;
  2955. }
  2956. /* ********************************************************* *
  2957. * Functions defined below concern the OS part of the driver *
  2958. * ********************************************************* */
  2959. /**
  2960. * s2io_open - open entry point of the driver
  2961. * @dev : pointer to the device structure.
  2962. * Description:
  2963. * This function is the open entry point of the driver. It mainly calls a
  2964. * function to allocate Rx buffers and inserts them into the buffer
  2965. * descriptors and then enables the Rx part of the NIC.
  2966. * Return value:
  2967. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  2968. * file on failure.
  2969. */
  2970. int s2io_open(struct net_device *dev)
  2971. {
  2972. nic_t *sp = dev->priv;
  2973. int err = 0;
  2974. int i;
  2975. u16 msi_control; /* Temp variable */
  2976. /*
  2977. * Make sure you have link off by default every time
  2978. * Nic is initialized
  2979. */
  2980. netif_carrier_off(dev);
  2981. sp->last_link_state = 0;
  2982. /* Initialize H/W and enable interrupts */
  2983. if (s2io_card_up(sp)) {
  2984. DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
  2985. dev->name);
  2986. err = -ENODEV;
  2987. goto hw_init_failed;
  2988. }
  2989. /* Store the values of the MSIX table in the nic_t structure */
  2990. store_xmsi_data(sp);
  2991. /* After proper initialization of H/W, register ISR */
  2992. if (sp->intr_type == MSI) {
  2993. err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
  2994. SA_SHIRQ, sp->name, dev);
  2995. if (err) {
  2996. DBG_PRINT(ERR_DBG, "%s: MSI registration \
  2997. failed\n", dev->name);
  2998. goto isr_registration_failed;
  2999. }
  3000. }
  3001. if (sp->intr_type == MSI_X) {
  3002. for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
  3003. if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
  3004. sprintf(sp->desc1, "%s:MSI-X-%d-TX",
  3005. dev->name, i);
  3006. err = request_irq(sp->entries[i].vector,
  3007. s2io_msix_fifo_handle, 0, sp->desc1,
  3008. sp->s2io_entries[i].arg);
  3009. DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1,
  3010. sp->msix_info[i].addr);
  3011. } else {
  3012. sprintf(sp->desc2, "%s:MSI-X-%d-RX",
  3013. dev->name, i);
  3014. err = request_irq(sp->entries[i].vector,
  3015. s2io_msix_ring_handle, 0, sp->desc2,
  3016. sp->s2io_entries[i].arg);
  3017. DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2,
  3018. sp->msix_info[i].addr);
  3019. }
  3020. if (err) {
  3021. DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
  3022. failed\n", dev->name, i);
  3023. DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
  3024. goto isr_registration_failed;
  3025. }
  3026. sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
  3027. }
  3028. }
  3029. if (sp->intr_type == INTA) {
  3030. err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
  3031. sp->name, dev);
  3032. if (err) {
  3033. DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
  3034. dev->name);
  3035. goto isr_registration_failed;
  3036. }
  3037. }
  3038. if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
  3039. DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
  3040. err = -ENODEV;
  3041. goto setting_mac_address_failed;
  3042. }
  3043. netif_start_queue(dev);
  3044. return 0;
  3045. setting_mac_address_failed:
  3046. if (sp->intr_type != MSI_X)
  3047. free_irq(sp->pdev->irq, dev);
  3048. isr_registration_failed:
  3049. del_timer_sync(&sp->alarm_timer);
  3050. if (sp->intr_type == MSI_X) {
  3051. if (sp->device_type == XFRAME_II_DEVICE) {
  3052. for (i=1; (sp->s2io_entries[i].in_use ==
  3053. MSIX_REGISTERED_SUCCESS); i++) {
  3054. int vector = sp->entries[i].vector;
  3055. void *arg = sp->s2io_entries[i].arg;
  3056. free_irq(vector, arg);
  3057. }
  3058. pci_disable_msix(sp->pdev);
  3059. /* Temp */
  3060. pci_read_config_word(sp->pdev, 0x42, &msi_control);
  3061. msi_control &= 0xFFFE; /* Disable MSI */
  3062. pci_write_config_word(sp->pdev, 0x42, msi_control);
  3063. }
  3064. }
  3065. else if (sp->intr_type == MSI)
  3066. pci_disable_msi(sp->pdev);
  3067. s2io_reset(sp);
  3068. hw_init_failed:
  3069. if (sp->intr_type == MSI_X) {
  3070. if (sp->entries)
  3071. kfree(sp->entries);
  3072. if (sp->s2io_entries)
  3073. kfree(sp->s2io_entries);
  3074. }
  3075. return err;
  3076. }
  3077. /**
  3078. * s2io_close -close entry point of the driver
  3079. * @dev : device pointer.
  3080. * Description:
  3081. * This is the stop entry point of the driver. It needs to undo exactly
  3082. * whatever was done by the open entry point,thus it's usually referred to
  3083. * as the close function.Among other things this function mainly stops the
  3084. * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
  3085. * Return value:
  3086. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  3087. * file on failure.
  3088. */
  3089. int s2io_close(struct net_device *dev)
  3090. {
  3091. nic_t *sp = dev->priv;
  3092. int i;
  3093. u16 msi_control;
  3094. flush_scheduled_work();
  3095. netif_stop_queue(dev);
  3096. /* Reset card, kill tasklet and free Tx and Rx buffers. */
  3097. s2io_card_down(sp);
  3098. if (sp->intr_type == MSI_X) {
  3099. if (sp->device_type == XFRAME_II_DEVICE) {
  3100. for (i=1; (sp->s2io_entries[i].in_use ==
  3101. MSIX_REGISTERED_SUCCESS); i++) {
  3102. int vector = sp->entries[i].vector;
  3103. void *arg = sp->s2io_entries[i].arg;
  3104. free_irq(vector, arg);
  3105. }
  3106. pci_read_config_word(sp->pdev, 0x42, &msi_control);
  3107. msi_control &= 0xFFFE; /* Disable MSI */
  3108. pci_write_config_word(sp->pdev, 0x42, msi_control);
  3109. pci_disable_msix(sp->pdev);
  3110. }
  3111. }
  3112. else {
  3113. free_irq(sp->pdev->irq, dev);
  3114. if (sp->intr_type == MSI)
  3115. pci_disable_msi(sp->pdev);
  3116. }
  3117. sp->device_close_flag = TRUE; /* Device is shut down. */
  3118. return 0;
  3119. }
  3120. /**
  3121. * s2io_xmit - Tx entry point of te driver
  3122. * @skb : the socket buffer containing the Tx data.
  3123. * @dev : device pointer.
  3124. * Description :
  3125. * This function is the Tx entry point of the driver. S2IO NIC supports
  3126. * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
  3127. * NOTE: when device cant queue the pkt,just the trans_start variable will
  3128. * not be upadted.
  3129. * Return value:
  3130. * 0 on success & 1 on failure.
  3131. */
  3132. int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
  3133. {
  3134. nic_t *sp = dev->priv;
  3135. u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
  3136. register u64 val64;
  3137. TxD_t *txdp;
  3138. TxFIFO_element_t __iomem *tx_fifo;
  3139. unsigned long flags;
  3140. #ifdef NETIF_F_TSO
  3141. int mss;
  3142. #endif
  3143. u16 vlan_tag = 0;
  3144. int vlan_priority = 0;
  3145. mac_info_t *mac_control;
  3146. struct config_param *config;
  3147. mac_control = &sp->mac_control;
  3148. config = &sp->config;
  3149. DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
  3150. spin_lock_irqsave(&sp->tx_lock, flags);
  3151. if (atomic_read(&sp->card_state) == CARD_DOWN) {
  3152. DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
  3153. dev->name);
  3154. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3155. dev_kfree_skb(skb);
  3156. return 0;
  3157. }
  3158. queue = 0;
  3159. /* Get Fifo number to Transmit based on vlan priority */
  3160. if (sp->vlgrp && vlan_tx_tag_present(skb)) {
  3161. vlan_tag = vlan_tx_tag_get(skb);
  3162. vlan_priority = vlan_tag >> 13;
  3163. queue = config->fifo_mapping[vlan_priority];
  3164. }
  3165. put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
  3166. get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
  3167. txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
  3168. list_virt_addr;
  3169. queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
  3170. /* Avoid "put" pointer going beyond "get" pointer */
  3171. if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
  3172. DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
  3173. netif_stop_queue(dev);
  3174. dev_kfree_skb(skb);
  3175. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3176. return 0;
  3177. }
  3178. /* A buffer with no data will be dropped */
  3179. if (!skb->len) {
  3180. DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
  3181. dev_kfree_skb(skb);
  3182. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3183. return 0;
  3184. }
  3185. #ifdef NETIF_F_TSO
  3186. mss = skb_shinfo(skb)->tso_size;
  3187. if (mss) {
  3188. txdp->Control_1 |= TXD_TCP_LSO_EN;
  3189. txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
  3190. }
  3191. #endif
  3192. frg_cnt = skb_shinfo(skb)->nr_frags;
  3193. frg_len = skb->len - skb->data_len;
  3194. txdp->Buffer_Pointer = pci_map_single
  3195. (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
  3196. txdp->Host_Control = (unsigned long) skb;
  3197. if (skb->ip_summed == CHECKSUM_HW) {
  3198. txdp->Control_2 |=
  3199. (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
  3200. TXD_TX_CKO_UDP_EN);
  3201. }
  3202. txdp->Control_2 |= config->tx_intr_type;
  3203. if (sp->vlgrp && vlan_tx_tag_present(skb)) {
  3204. txdp->Control_2 |= TXD_VLAN_ENABLE;
  3205. txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
  3206. }
  3207. txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
  3208. TXD_GATHER_CODE_FIRST);
  3209. txdp->Control_1 |= TXD_LIST_OWN_XENA;
  3210. /* For fragmented SKB. */
  3211. for (i = 0; i < frg_cnt; i++) {
  3212. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3213. /* A '0' length fragment will be ignored */
  3214. if (!frag->size)
  3215. continue;
  3216. txdp++;
  3217. txdp->Buffer_Pointer = (u64) pci_map_page
  3218. (sp->pdev, frag->page, frag->page_offset,
  3219. frag->size, PCI_DMA_TODEVICE);
  3220. txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size);
  3221. }
  3222. txdp->Control_1 |= TXD_GATHER_CODE_LAST;
  3223. tx_fifo = mac_control->tx_FIFO_start[queue];
  3224. val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
  3225. writeq(val64, &tx_fifo->TxDL_Pointer);
  3226. val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
  3227. TX_FIFO_LAST_LIST);
  3228. #ifdef NETIF_F_TSO
  3229. if (mss)
  3230. val64 |= TX_FIFO_SPECIAL_FUNC;
  3231. #endif
  3232. writeq(val64, &tx_fifo->List_Control);
  3233. mmiowb();
  3234. put_off++;
  3235. put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
  3236. mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
  3237. /* Avoid "put" pointer going beyond "get" pointer */
  3238. if (((put_off + 1) % queue_len) == get_off) {
  3239. DBG_PRINT(TX_DBG,
  3240. "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
  3241. put_off, get_off);
  3242. netif_stop_queue(dev);
  3243. }
  3244. dev->trans_start = jiffies;
  3245. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3246. return 0;
  3247. }
  3248. static void
  3249. s2io_alarm_handle(unsigned long data)
  3250. {
  3251. nic_t *sp = (nic_t *)data;
  3252. alarm_intr_handler(sp);
  3253. mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
  3254. }
  3255. static irqreturn_t
  3256. s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
  3257. {
  3258. struct net_device *dev = (struct net_device *) dev_id;
  3259. nic_t *sp = dev->priv;
  3260. int i;
  3261. int ret;
  3262. mac_info_t *mac_control;
  3263. struct config_param *config;
  3264. atomic_inc(&sp->isr_cnt);
  3265. mac_control = &sp->mac_control;
  3266. config = &sp->config;
  3267. DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
  3268. /* If Intr is because of Rx Traffic */
  3269. for (i = 0; i < config->rx_ring_num; i++)
  3270. rx_intr_handler(&mac_control->rings[i]);
  3271. /* If Intr is because of Tx Traffic */
  3272. for (i = 0; i < config->tx_fifo_num; i++)
  3273. tx_intr_handler(&mac_control->fifos[i]);
  3274. /*
  3275. * If the Rx buffer count is below the panic threshold then
  3276. * reallocate the buffers from the interrupt handler itself,
  3277. * else schedule a tasklet to reallocate the buffers.
  3278. */
  3279. for (i = 0; i < config->rx_ring_num; i++) {
  3280. int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
  3281. int level = rx_buffer_level(sp, rxb_size, i);
  3282. if ((level == PANIC) && (!TASKLET_IN_USE)) {
  3283. DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
  3284. DBG_PRINT(INTR_DBG, "PANIC levels\n");
  3285. if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
  3286. DBG_PRINT(ERR_DBG, "%s:Out of memory",
  3287. dev->name);
  3288. DBG_PRINT(ERR_DBG, " in ISR!!\n");
  3289. clear_bit(0, (&sp->tasklet_status));
  3290. atomic_dec(&sp->isr_cnt);
  3291. return IRQ_HANDLED;
  3292. }
  3293. clear_bit(0, (&sp->tasklet_status));
  3294. } else if (level == LOW) {
  3295. tasklet_schedule(&sp->task);
  3296. }
  3297. }
  3298. atomic_dec(&sp->isr_cnt);
  3299. return IRQ_HANDLED;
  3300. }
  3301. static irqreturn_t
  3302. s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
  3303. {
  3304. ring_info_t *ring = (ring_info_t *)dev_id;
  3305. nic_t *sp = ring->nic;
  3306. int rxb_size, level, rng_n;
  3307. atomic_inc(&sp->isr_cnt);
  3308. rx_intr_handler(ring);
  3309. rng_n = ring->ring_no;
  3310. rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
  3311. level = rx_buffer_level(sp, rxb_size, rng_n);
  3312. if ((level == PANIC) && (!TASKLET_IN_USE)) {
  3313. int ret;
  3314. DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
  3315. DBG_PRINT(INTR_DBG, "PANIC levels\n");
  3316. if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
  3317. DBG_PRINT(ERR_DBG, "Out of memory in %s",
  3318. __FUNCTION__);
  3319. clear_bit(0, (&sp->tasklet_status));
  3320. return IRQ_HANDLED;
  3321. }
  3322. clear_bit(0, (&sp->tasklet_status));
  3323. } else if (level == LOW) {
  3324. tasklet_schedule(&sp->task);
  3325. }
  3326. atomic_dec(&sp->isr_cnt);
  3327. return IRQ_HANDLED;
  3328. }
  3329. static irqreturn_t
  3330. s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
  3331. {
  3332. fifo_info_t *fifo = (fifo_info_t *)dev_id;
  3333. nic_t *sp = fifo->nic;
  3334. atomic_inc(&sp->isr_cnt);
  3335. tx_intr_handler(fifo);
  3336. atomic_dec(&sp->isr_cnt);
  3337. return IRQ_HANDLED;
  3338. }
  3339. static void s2io_txpic_intr_handle(nic_t *sp)
  3340. {
  3341. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3342. u64 val64;
  3343. val64 = readq(&bar0->pic_int_status);
  3344. if (val64 & PIC_INT_GPIO) {
  3345. val64 = readq(&bar0->gpio_int_reg);
  3346. if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
  3347. (val64 & GPIO_INT_REG_LINK_UP)) {
  3348. val64 |= GPIO_INT_REG_LINK_DOWN;
  3349. val64 |= GPIO_INT_REG_LINK_UP;
  3350. writeq(val64, &bar0->gpio_int_reg);
  3351. goto masking;
  3352. }
  3353. if (((sp->last_link_state == LINK_UP) &&
  3354. (val64 & GPIO_INT_REG_LINK_DOWN)) ||
  3355. ((sp->last_link_state == LINK_DOWN) &&
  3356. (val64 & GPIO_INT_REG_LINK_UP))) {
  3357. val64 = readq(&bar0->gpio_int_mask);
  3358. val64 |= GPIO_INT_MASK_LINK_DOWN;
  3359. val64 |= GPIO_INT_MASK_LINK_UP;
  3360. writeq(val64, &bar0->gpio_int_mask);
  3361. s2io_set_link((unsigned long)sp);
  3362. }
  3363. masking:
  3364. if (sp->last_link_state == LINK_UP) {
  3365. /*enable down interrupt */
  3366. val64 = readq(&bar0->gpio_int_mask);
  3367. /* unmasks link down intr */
  3368. val64 &= ~GPIO_INT_MASK_LINK_DOWN;
  3369. /* masks link up intr */
  3370. val64 |= GPIO_INT_MASK_LINK_UP;
  3371. writeq(val64, &bar0->gpio_int_mask);
  3372. } else {
  3373. /*enable UP Interrupt */
  3374. val64 = readq(&bar0->gpio_int_mask);
  3375. /* unmasks link up interrupt */
  3376. val64 &= ~GPIO_INT_MASK_LINK_UP;
  3377. /* masks link down interrupt */
  3378. val64 |= GPIO_INT_MASK_LINK_DOWN;
  3379. writeq(val64, &bar0->gpio_int_mask);
  3380. }
  3381. }
  3382. }
  3383. /**
  3384. * s2io_isr - ISR handler of the device .
  3385. * @irq: the irq of the device.
  3386. * @dev_id: a void pointer to the dev structure of the NIC.
  3387. * @pt_regs: pointer to the registers pushed on the stack.
  3388. * Description: This function is the ISR handler of the device. It
  3389. * identifies the reason for the interrupt and calls the relevant
  3390. * service routines. As a contongency measure, this ISR allocates the
  3391. * recv buffers, if their numbers are below the panic value which is
  3392. * presently set to 25% of the original number of rcv buffers allocated.
  3393. * Return value:
  3394. * IRQ_HANDLED: will be returned if IRQ was handled by this routine
  3395. * IRQ_NONE: will be returned if interrupt is not from our device
  3396. */
  3397. static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
  3398. {
  3399. struct net_device *dev = (struct net_device *) dev_id;
  3400. nic_t *sp = dev->priv;
  3401. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3402. int i;
  3403. u64 reason = 0, val64;
  3404. mac_info_t *mac_control;
  3405. struct config_param *config;
  3406. atomic_inc(&sp->isr_cnt);
  3407. mac_control = &sp->mac_control;
  3408. config = &sp->config;
  3409. /*
  3410. * Identify the cause for interrupt and call the appropriate
  3411. * interrupt handler. Causes for the interrupt could be;
  3412. * 1. Rx of packet.
  3413. * 2. Tx complete.
  3414. * 3. Link down.
  3415. * 4. Error in any functional blocks of the NIC.
  3416. */
  3417. reason = readq(&bar0->general_int_status);
  3418. if (!reason) {
  3419. /* The interrupt was not raised by Xena. */
  3420. atomic_dec(&sp->isr_cnt);
  3421. return IRQ_NONE;
  3422. }
  3423. #ifdef CONFIG_S2IO_NAPI
  3424. if (reason & GEN_INTR_RXTRAFFIC) {
  3425. if (netif_rx_schedule_prep(dev)) {
  3426. en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
  3427. DISABLE_INTRS);
  3428. __netif_rx_schedule(dev);
  3429. }
  3430. }
  3431. #else
  3432. /* If Intr is because of Rx Traffic */
  3433. if (reason & GEN_INTR_RXTRAFFIC) {
  3434. /*
  3435. * rx_traffic_int reg is an R1 register, writing all 1's
  3436. * will ensure that the actual interrupt causing bit get's
  3437. * cleared and hence a read can be avoided.
  3438. */
  3439. val64 = 0xFFFFFFFFFFFFFFFFULL;
  3440. writeq(val64, &bar0->rx_traffic_int);
  3441. for (i = 0; i < config->rx_ring_num; i++) {
  3442. rx_intr_handler(&mac_control->rings[i]);
  3443. }
  3444. }
  3445. #endif
  3446. /* If Intr is because of Tx Traffic */
  3447. if (reason & GEN_INTR_TXTRAFFIC) {
  3448. /*
  3449. * tx_traffic_int reg is an R1 register, writing all 1's
  3450. * will ensure that the actual interrupt causing bit get's
  3451. * cleared and hence a read can be avoided.
  3452. */
  3453. val64 = 0xFFFFFFFFFFFFFFFFULL;
  3454. writeq(val64, &bar0->tx_traffic_int);
  3455. for (i = 0; i < config->tx_fifo_num; i++)
  3456. tx_intr_handler(&mac_control->fifos[i]);
  3457. }
  3458. if (reason & GEN_INTR_TXPIC)
  3459. s2io_txpic_intr_handle(sp);
  3460. /*
  3461. * If the Rx buffer count is below the panic threshold then
  3462. * reallocate the buffers from the interrupt handler itself,
  3463. * else schedule a tasklet to reallocate the buffers.
  3464. */
  3465. #ifndef CONFIG_S2IO_NAPI
  3466. for (i = 0; i < config->rx_ring_num; i++) {
  3467. int ret;
  3468. int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
  3469. int level = rx_buffer_level(sp, rxb_size, i);
  3470. if ((level == PANIC) && (!TASKLET_IN_USE)) {
  3471. DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
  3472. DBG_PRINT(INTR_DBG, "PANIC levels\n");
  3473. if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
  3474. DBG_PRINT(ERR_DBG, "%s:Out of memory",
  3475. dev->name);
  3476. DBG_PRINT(ERR_DBG, " in ISR!!\n");
  3477. clear_bit(0, (&sp->tasklet_status));
  3478. atomic_dec(&sp->isr_cnt);
  3479. return IRQ_HANDLED;
  3480. }
  3481. clear_bit(0, (&sp->tasklet_status));
  3482. } else if (level == LOW) {
  3483. tasklet_schedule(&sp->task);
  3484. }
  3485. }
  3486. #endif
  3487. atomic_dec(&sp->isr_cnt);
  3488. return IRQ_HANDLED;
  3489. }
  3490. /**
  3491. * s2io_updt_stats -
  3492. */
  3493. static void s2io_updt_stats(nic_t *sp)
  3494. {
  3495. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3496. u64 val64;
  3497. int cnt = 0;
  3498. if (atomic_read(&sp->card_state) == CARD_UP) {
  3499. /* Apprx 30us on a 133 MHz bus */
  3500. val64 = SET_UPDT_CLICKS(10) |
  3501. STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
  3502. writeq(val64, &bar0->stat_cfg);
  3503. do {
  3504. udelay(100);
  3505. val64 = readq(&bar0->stat_cfg);
  3506. if (!(val64 & BIT(0)))
  3507. break;
  3508. cnt++;
  3509. if (cnt == 5)
  3510. break; /* Updt failed */
  3511. } while(1);
  3512. }
  3513. }
  3514. /**
  3515. * s2io_get_stats - Updates the device statistics structure.
  3516. * @dev : pointer to the device structure.
  3517. * Description:
  3518. * This function updates the device statistics structure in the s2io_nic
  3519. * structure and returns a pointer to the same.
  3520. * Return value:
  3521. * pointer to the updated net_device_stats structure.
  3522. */
  3523. struct net_device_stats *s2io_get_stats(struct net_device *dev)
  3524. {
  3525. nic_t *sp = dev->priv;
  3526. mac_info_t *mac_control;
  3527. struct config_param *config;
  3528. mac_control = &sp->mac_control;
  3529. config = &sp->config;
  3530. /* Configure Stats for immediate updt */
  3531. s2io_updt_stats(sp);
  3532. sp->stats.tx_packets =
  3533. le32_to_cpu(mac_control->stats_info->tmac_frms);
  3534. sp->stats.tx_errors =
  3535. le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
  3536. sp->stats.rx_errors =
  3537. le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
  3538. sp->stats.multicast =
  3539. le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
  3540. sp->stats.rx_length_errors =
  3541. le32_to_cpu(mac_control->stats_info->rmac_long_frms);
  3542. return (&sp->stats);
  3543. }
  3544. /**
  3545. * s2io_set_multicast - entry point for multicast address enable/disable.
  3546. * @dev : pointer to the device structure
  3547. * Description:
  3548. * This function is a driver entry point which gets called by the kernel
  3549. * whenever multicast addresses must be enabled/disabled. This also gets
  3550. * called to set/reset promiscuous mode. Depending on the deivce flag, we
  3551. * determine, if multicast address must be enabled or if promiscuous mode
  3552. * is to be disabled etc.
  3553. * Return value:
  3554. * void.
  3555. */
  3556. static void s2io_set_multicast(struct net_device *dev)
  3557. {
  3558. int i, j, prev_cnt;
  3559. struct dev_mc_list *mclist;
  3560. nic_t *sp = dev->priv;
  3561. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3562. u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
  3563. 0xfeffffffffffULL;
  3564. u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
  3565. void __iomem *add;
  3566. if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
  3567. /* Enable all Multicast addresses */
  3568. writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
  3569. &bar0->rmac_addr_data0_mem);
  3570. writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
  3571. &bar0->rmac_addr_data1_mem);
  3572. val64 = RMAC_ADDR_CMD_MEM_WE |
  3573. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  3574. RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
  3575. writeq(val64, &bar0->rmac_addr_cmd_mem);
  3576. /* Wait till command completes */
  3577. wait_for_cmd_complete(sp);
  3578. sp->m_cast_flg = 1;
  3579. sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
  3580. } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
  3581. /* Disable all Multicast addresses */
  3582. writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
  3583. &bar0->rmac_addr_data0_mem);
  3584. writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
  3585. &bar0->rmac_addr_data1_mem);
  3586. val64 = RMAC_ADDR_CMD_MEM_WE |
  3587. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  3588. RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
  3589. writeq(val64, &bar0->rmac_addr_cmd_mem);
  3590. /* Wait till command completes */
  3591. wait_for_cmd_complete(sp);
  3592. sp->m_cast_flg = 0;
  3593. sp->all_multi_pos = 0;
  3594. }
  3595. if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
  3596. /* Put the NIC into promiscuous mode */
  3597. add = &bar0->mac_cfg;
  3598. val64 = readq(&bar0->mac_cfg);
  3599. val64 |= MAC_CFG_RMAC_PROM_ENABLE;
  3600. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3601. writel((u32) val64, add);
  3602. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3603. writel((u32) (val64 >> 32), (add + 4));
  3604. val64 = readq(&bar0->mac_cfg);
  3605. sp->promisc_flg = 1;
  3606. DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
  3607. dev->name);
  3608. } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
  3609. /* Remove the NIC from promiscuous mode */
  3610. add = &bar0->mac_cfg;
  3611. val64 = readq(&bar0->mac_cfg);
  3612. val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
  3613. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3614. writel((u32) val64, add);
  3615. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3616. writel((u32) (val64 >> 32), (add + 4));
  3617. val64 = readq(&bar0->mac_cfg);
  3618. sp->promisc_flg = 0;
  3619. DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
  3620. dev->name);
  3621. }
  3622. /* Update individual M_CAST address list */
  3623. if ((!sp->m_cast_flg) && dev->mc_count) {
  3624. if (dev->mc_count >
  3625. (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
  3626. DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
  3627. dev->name);
  3628. DBG_PRINT(ERR_DBG, "can be added, please enable ");
  3629. DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
  3630. return;
  3631. }
  3632. prev_cnt = sp->mc_addr_count;
  3633. sp->mc_addr_count = dev->mc_count;
  3634. /* Clear out the previous list of Mc in the H/W. */
  3635. for (i = 0; i < prev_cnt; i++) {
  3636. writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
  3637. &bar0->rmac_addr_data0_mem);
  3638. writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
  3639. &bar0->rmac_addr_data1_mem);
  3640. val64 = RMAC_ADDR_CMD_MEM_WE |
  3641. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  3642. RMAC_ADDR_CMD_MEM_OFFSET
  3643. (MAC_MC_ADDR_START_OFFSET + i);
  3644. writeq(val64, &bar0->rmac_addr_cmd_mem);
  3645. /* Wait for command completes */
  3646. if (wait_for_cmd_complete(sp)) {
  3647. DBG_PRINT(ERR_DBG, "%s: Adding ",
  3648. dev->name);
  3649. DBG_PRINT(ERR_DBG, "Multicasts failed\n");
  3650. return;
  3651. }
  3652. }
  3653. /* Create the new Rx filter list and update the same in H/W. */
  3654. for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
  3655. i++, mclist = mclist->next) {
  3656. memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
  3657. ETH_ALEN);
  3658. for (j = 0; j < ETH_ALEN; j++) {
  3659. mac_addr |= mclist->dmi_addr[j];
  3660. mac_addr <<= 8;
  3661. }
  3662. mac_addr >>= 8;
  3663. writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
  3664. &bar0->rmac_addr_data0_mem);
  3665. writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
  3666. &bar0->rmac_addr_data1_mem);
  3667. val64 = RMAC_ADDR_CMD_MEM_WE |
  3668. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  3669. RMAC_ADDR_CMD_MEM_OFFSET
  3670. (i + MAC_MC_ADDR_START_OFFSET);
  3671. writeq(val64, &bar0->rmac_addr_cmd_mem);
  3672. /* Wait for command completes */
  3673. if (wait_for_cmd_complete(sp)) {
  3674. DBG_PRINT(ERR_DBG, "%s: Adding ",
  3675. dev->name);
  3676. DBG_PRINT(ERR_DBG, "Multicasts failed\n");
  3677. return;
  3678. }
  3679. }
  3680. }
  3681. }
  3682. /**
  3683. * s2io_set_mac_addr - Programs the Xframe mac address
  3684. * @dev : pointer to the device structure.
  3685. * @addr: a uchar pointer to the new mac address which is to be set.
  3686. * Description : This procedure will program the Xframe to receive
  3687. * frames with new Mac Address
  3688. * Return value: SUCCESS on success and an appropriate (-)ve integer
  3689. * as defined in errno.h file on failure.
  3690. */
  3691. int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
  3692. {
  3693. nic_t *sp = dev->priv;
  3694. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3695. register u64 val64, mac_addr = 0;
  3696. int i;
  3697. /*
  3698. * Set the new MAC address as the new unicast filter and reflect this
  3699. * change on the device address registered with the OS. It will be
  3700. * at offset 0.
  3701. */
  3702. for (i = 0; i < ETH_ALEN; i++) {
  3703. mac_addr <<= 8;
  3704. mac_addr |= addr[i];
  3705. }
  3706. writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
  3707. &bar0->rmac_addr_data0_mem);
  3708. val64 =
  3709. RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  3710. RMAC_ADDR_CMD_MEM_OFFSET(0);
  3711. writeq(val64, &bar0->rmac_addr_cmd_mem);
  3712. /* Wait till command completes */
  3713. if (wait_for_cmd_complete(sp)) {
  3714. DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
  3715. return FAILURE;
  3716. }
  3717. return SUCCESS;
  3718. }
  3719. /**
  3720. * s2io_ethtool_sset - Sets different link parameters.
  3721. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
  3722. * @info: pointer to the structure with parameters given by ethtool to set
  3723. * link information.
  3724. * Description:
  3725. * The function sets different link parameters provided by the user onto
  3726. * the NIC.
  3727. * Return value:
  3728. * 0 on success.
  3729. */
  3730. static int s2io_ethtool_sset(struct net_device *dev,
  3731. struct ethtool_cmd *info)
  3732. {
  3733. nic_t *sp = dev->priv;
  3734. if ((info->autoneg == AUTONEG_ENABLE) ||
  3735. (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
  3736. return -EINVAL;
  3737. else {
  3738. s2io_close(sp->dev);
  3739. s2io_open(sp->dev);
  3740. }
  3741. return 0;
  3742. }
  3743. /**
  3744. * s2io_ethtol_gset - Return link specific information.
  3745. * @sp : private member of the device structure, pointer to the
  3746. * s2io_nic structure.
  3747. * @info : pointer to the structure with parameters given by ethtool
  3748. * to return link information.
  3749. * Description:
  3750. * Returns link specific information like speed, duplex etc.. to ethtool.
  3751. * Return value :
  3752. * return 0 on success.
  3753. */
  3754. static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
  3755. {
  3756. nic_t *sp = dev->priv;
  3757. info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  3758. info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  3759. info->port = PORT_FIBRE;
  3760. /* info->transceiver?? TODO */
  3761. if (netif_carrier_ok(sp->dev)) {
  3762. info->speed = 10000;
  3763. info->duplex = DUPLEX_FULL;
  3764. } else {
  3765. info->speed = -1;
  3766. info->duplex = -1;
  3767. }
  3768. info->autoneg = AUTONEG_DISABLE;
  3769. return 0;
  3770. }
  3771. /**
  3772. * s2io_ethtool_gdrvinfo - Returns driver specific information.
  3773. * @sp : private member of the device structure, which is a pointer to the
  3774. * s2io_nic structure.
  3775. * @info : pointer to the structure with parameters given by ethtool to
  3776. * return driver information.
  3777. * Description:
  3778. * Returns driver specefic information like name, version etc.. to ethtool.
  3779. * Return value:
  3780. * void
  3781. */
  3782. static void s2io_ethtool_gdrvinfo(struct net_device *dev,
  3783. struct ethtool_drvinfo *info)
  3784. {
  3785. nic_t *sp = dev->priv;
  3786. strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
  3787. strncpy(info->version, s2io_driver_version, sizeof(info->version));
  3788. strncpy(info->fw_version, "", sizeof(info->fw_version));
  3789. strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
  3790. info->regdump_len = XENA_REG_SPACE;
  3791. info->eedump_len = XENA_EEPROM_SPACE;
  3792. info->testinfo_len = S2IO_TEST_LEN;
  3793. info->n_stats = S2IO_STAT_LEN;
  3794. }
  3795. /**
  3796. * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
  3797. * @sp: private member of the device structure, which is a pointer to the
  3798. * s2io_nic structure.
  3799. * @regs : pointer to the structure with parameters given by ethtool for
  3800. * dumping the registers.
  3801. * @reg_space: The input argumnet into which all the registers are dumped.
  3802. * Description:
  3803. * Dumps the entire register space of xFrame NIC into the user given
  3804. * buffer area.
  3805. * Return value :
  3806. * void .
  3807. */
  3808. static void s2io_ethtool_gregs(struct net_device *dev,
  3809. struct ethtool_regs *regs, void *space)
  3810. {
  3811. int i;
  3812. u64 reg;
  3813. u8 *reg_space = (u8 *) space;
  3814. nic_t *sp = dev->priv;
  3815. regs->len = XENA_REG_SPACE;
  3816. regs->version = sp->pdev->subsystem_device;
  3817. for (i = 0; i < regs->len; i += 8) {
  3818. reg = readq(sp->bar0 + i);
  3819. memcpy((reg_space + i), &reg, 8);
  3820. }
  3821. }
  3822. /**
  3823. * s2io_phy_id - timer function that alternates adapter LED.
  3824. * @data : address of the private member of the device structure, which
  3825. * is a pointer to the s2io_nic structure, provided as an u32.
  3826. * Description: This is actually the timer function that alternates the
  3827. * adapter LED bit of the adapter control bit to set/reset every time on
  3828. * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
  3829. * once every second.
  3830. */
  3831. static void s2io_phy_id(unsigned long data)
  3832. {
  3833. nic_t *sp = (nic_t *) data;
  3834. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3835. u64 val64 = 0;
  3836. u16 subid;
  3837. subid = sp->pdev->subsystem_device;
  3838. if ((sp->device_type == XFRAME_II_DEVICE) ||
  3839. ((subid & 0xFF) >= 0x07)) {
  3840. val64 = readq(&bar0->gpio_control);
  3841. val64 ^= GPIO_CTRL_GPIO_0;
  3842. writeq(val64, &bar0->gpio_control);
  3843. } else {
  3844. val64 = readq(&bar0->adapter_control);
  3845. val64 ^= ADAPTER_LED_ON;
  3846. writeq(val64, &bar0->adapter_control);
  3847. }
  3848. mod_timer(&sp->id_timer, jiffies + HZ / 2);
  3849. }
  3850. /**
  3851. * s2io_ethtool_idnic - To physically identify the nic on the system.
  3852. * @sp : private member of the device structure, which is a pointer to the
  3853. * s2io_nic structure.
  3854. * @id : pointer to the structure with identification parameters given by
  3855. * ethtool.
  3856. * Description: Used to physically identify the NIC on the system.
  3857. * The Link LED will blink for a time specified by the user for
  3858. * identification.
  3859. * NOTE: The Link has to be Up to be able to blink the LED. Hence
  3860. * identification is possible only if it's link is up.
  3861. * Return value:
  3862. * int , returns 0 on success
  3863. */
  3864. static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
  3865. {
  3866. u64 val64 = 0, last_gpio_ctrl_val;
  3867. nic_t *sp = dev->priv;
  3868. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3869. u16 subid;
  3870. subid = sp->pdev->subsystem_device;
  3871. last_gpio_ctrl_val = readq(&bar0->gpio_control);
  3872. if ((sp->device_type == XFRAME_I_DEVICE) &&
  3873. ((subid & 0xFF) < 0x07)) {
  3874. val64 = readq(&bar0->adapter_control);
  3875. if (!(val64 & ADAPTER_CNTL_EN)) {
  3876. printk(KERN_ERR
  3877. "Adapter Link down, cannot blink LED\n");
  3878. return -EFAULT;
  3879. }
  3880. }
  3881. if (sp->id_timer.function == NULL) {
  3882. init_timer(&sp->id_timer);
  3883. sp->id_timer.function = s2io_phy_id;
  3884. sp->id_timer.data = (unsigned long) sp;
  3885. }
  3886. mod_timer(&sp->id_timer, jiffies);
  3887. if (data)
  3888. msleep_interruptible(data * HZ);
  3889. else
  3890. msleep_interruptible(MAX_FLICKER_TIME);
  3891. del_timer_sync(&sp->id_timer);
  3892. if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
  3893. writeq(last_gpio_ctrl_val, &bar0->gpio_control);
  3894. last_gpio_ctrl_val = readq(&bar0->gpio_control);
  3895. }
  3896. return 0;
  3897. }
  3898. /**
  3899. * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
  3900. * @sp : private member of the device structure, which is a pointer to the
  3901. * s2io_nic structure.
  3902. * @ep : pointer to the structure with pause parameters given by ethtool.
  3903. * Description:
  3904. * Returns the Pause frame generation and reception capability of the NIC.
  3905. * Return value:
  3906. * void
  3907. */
  3908. static void s2io_ethtool_getpause_data(struct net_device *dev,
  3909. struct ethtool_pauseparam *ep)
  3910. {
  3911. u64 val64;
  3912. nic_t *sp = dev->priv;
  3913. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3914. val64 = readq(&bar0->rmac_pause_cfg);
  3915. if (val64 & RMAC_PAUSE_GEN_ENABLE)
  3916. ep->tx_pause = TRUE;
  3917. if (val64 & RMAC_PAUSE_RX_ENABLE)
  3918. ep->rx_pause = TRUE;
  3919. ep->autoneg = FALSE;
  3920. }
  3921. /**
  3922. * s2io_ethtool_setpause_data - set/reset pause frame generation.
  3923. * @sp : private member of the device structure, which is a pointer to the
  3924. * s2io_nic structure.
  3925. * @ep : pointer to the structure with pause parameters given by ethtool.
  3926. * Description:
  3927. * It can be used to set or reset Pause frame generation or reception
  3928. * support of the NIC.
  3929. * Return value:
  3930. * int, returns 0 on Success
  3931. */
  3932. static int s2io_ethtool_setpause_data(struct net_device *dev,
  3933. struct ethtool_pauseparam *ep)
  3934. {
  3935. u64 val64;
  3936. nic_t *sp = dev->priv;
  3937. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3938. val64 = readq(&bar0->rmac_pause_cfg);
  3939. if (ep->tx_pause)
  3940. val64 |= RMAC_PAUSE_GEN_ENABLE;
  3941. else
  3942. val64 &= ~RMAC_PAUSE_GEN_ENABLE;
  3943. if (ep->rx_pause)
  3944. val64 |= RMAC_PAUSE_RX_ENABLE;
  3945. else
  3946. val64 &= ~RMAC_PAUSE_RX_ENABLE;
  3947. writeq(val64, &bar0->rmac_pause_cfg);
  3948. return 0;
  3949. }
  3950. /**
  3951. * read_eeprom - reads 4 bytes of data from user given offset.
  3952. * @sp : private member of the device structure, which is a pointer to the
  3953. * s2io_nic structure.
  3954. * @off : offset at which the data must be written
  3955. * @data : Its an output parameter where the data read at the given
  3956. * offset is stored.
  3957. * Description:
  3958. * Will read 4 bytes of data from the user given offset and return the
  3959. * read data.
  3960. * NOTE: Will allow to read only part of the EEPROM visible through the
  3961. * I2C bus.
  3962. * Return value:
  3963. * -1 on failure and 0 on success.
  3964. */
  3965. #define S2IO_DEV_ID 5
  3966. static int read_eeprom(nic_t * sp, int off, u64 * data)
  3967. {
  3968. int ret = -1;
  3969. u32 exit_cnt = 0;
  3970. u64 val64;
  3971. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  3972. if (sp->device_type == XFRAME_I_DEVICE) {
  3973. val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
  3974. I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
  3975. I2C_CONTROL_CNTL_START;
  3976. SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
  3977. while (exit_cnt < 5) {
  3978. val64 = readq(&bar0->i2c_control);
  3979. if (I2C_CONTROL_CNTL_END(val64)) {
  3980. *data = I2C_CONTROL_GET_DATA(val64);
  3981. ret = 0;
  3982. break;
  3983. }
  3984. msleep(50);
  3985. exit_cnt++;
  3986. }
  3987. }
  3988. if (sp->device_type == XFRAME_II_DEVICE) {
  3989. val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
  3990. SPI_CONTROL_BYTECNT(0x3) |
  3991. SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
  3992. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  3993. val64 |= SPI_CONTROL_REQ;
  3994. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  3995. while (exit_cnt < 5) {
  3996. val64 = readq(&bar0->spi_control);
  3997. if (val64 & SPI_CONTROL_NACK) {
  3998. ret = 1;
  3999. break;
  4000. } else if (val64 & SPI_CONTROL_DONE) {
  4001. *data = readq(&bar0->spi_data);
  4002. *data &= 0xffffff;
  4003. ret = 0;
  4004. break;
  4005. }
  4006. msleep(50);
  4007. exit_cnt++;
  4008. }
  4009. }
  4010. return ret;
  4011. }
  4012. /**
  4013. * write_eeprom - actually writes the relevant part of the data value.
  4014. * @sp : private member of the device structure, which is a pointer to the
  4015. * s2io_nic structure.
  4016. * @off : offset at which the data must be written
  4017. * @data : The data that is to be written
  4018. * @cnt : Number of bytes of the data that are actually to be written into
  4019. * the Eeprom. (max of 3)
  4020. * Description:
  4021. * Actually writes the relevant part of the data value into the Eeprom
  4022. * through the I2C bus.
  4023. * Return value:
  4024. * 0 on success, -1 on failure.
  4025. */
  4026. static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
  4027. {
  4028. int exit_cnt = 0, ret = -1;
  4029. u64 val64;
  4030. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  4031. if (sp->device_type == XFRAME_I_DEVICE) {
  4032. val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
  4033. I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
  4034. I2C_CONTROL_CNTL_START;
  4035. SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
  4036. while (exit_cnt < 5) {
  4037. val64 = readq(&bar0->i2c_control);
  4038. if (I2C_CONTROL_CNTL_END(val64)) {
  4039. if (!(val64 & I2C_CONTROL_NACK))
  4040. ret = 0;
  4041. break;
  4042. }
  4043. msleep(50);
  4044. exit_cnt++;
  4045. }
  4046. }
  4047. if (sp->device_type == XFRAME_II_DEVICE) {
  4048. int write_cnt = (cnt == 8) ? 0 : cnt;
  4049. writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
  4050. val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
  4051. SPI_CONTROL_BYTECNT(write_cnt) |
  4052. SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
  4053. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  4054. val64 |= SPI_CONTROL_REQ;
  4055. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  4056. while (exit_cnt < 5) {
  4057. val64 = readq(&bar0->spi_control);
  4058. if (val64 & SPI_CONTROL_NACK) {
  4059. ret = 1;
  4060. break;
  4061. } else if (val64 & SPI_CONTROL_DONE) {
  4062. ret = 0;
  4063. break;
  4064. }
  4065. msleep(50);
  4066. exit_cnt++;
  4067. }
  4068. }
  4069. return ret;
  4070. }
  4071. /**
  4072. * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
  4073. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
  4074. * @eeprom : pointer to the user level structure provided by ethtool,
  4075. * containing all relevant information.
  4076. * @data_buf : user defined value to be written into Eeprom.
  4077. * Description: Reads the values stored in the Eeprom at given offset
  4078. * for a given length. Stores these values int the input argument data
  4079. * buffer 'data_buf' and returns these to the caller (ethtool.)
  4080. * Return value:
  4081. * int 0 on success
  4082. */
  4083. static int s2io_ethtool_geeprom(struct net_device *dev,
  4084. struct ethtool_eeprom *eeprom, u8 * data_buf)
  4085. {
  4086. u32 i, valid;
  4087. u64 data;
  4088. nic_t *sp = dev->priv;
  4089. eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
  4090. if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
  4091. eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
  4092. for (i = 0; i < eeprom->len; i += 4) {
  4093. if (read_eeprom(sp, (eeprom->offset + i), &data)) {
  4094. DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
  4095. return -EFAULT;
  4096. }
  4097. valid = INV(data);
  4098. memcpy((data_buf + i), &valid, 4);
  4099. }
  4100. return 0;
  4101. }
  4102. /**
  4103. * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
  4104. * @sp : private member of the device structure, which is a pointer to the
  4105. * s2io_nic structure.
  4106. * @eeprom : pointer to the user level structure provided by ethtool,
  4107. * containing all relevant information.
  4108. * @data_buf ; user defined value to be written into Eeprom.
  4109. * Description:
  4110. * Tries to write the user provided value in the Eeprom, at the offset
  4111. * given by the user.
  4112. * Return value:
  4113. * 0 on success, -EFAULT on failure.
  4114. */
  4115. static int s2io_ethtool_seeprom(struct net_device *dev,
  4116. struct ethtool_eeprom *eeprom,
  4117. u8 * data_buf)
  4118. {
  4119. int len = eeprom->len, cnt = 0;
  4120. u64 valid = 0, data;
  4121. nic_t *sp = dev->priv;
  4122. if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
  4123. DBG_PRINT(ERR_DBG,
  4124. "ETHTOOL_WRITE_EEPROM Err: Magic value ");
  4125. DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
  4126. eeprom->magic);
  4127. return -EFAULT;
  4128. }
  4129. while (len) {
  4130. data = (u32) data_buf[cnt] & 0x000000FF;
  4131. if (data) {
  4132. valid = (u32) (data << 24);
  4133. } else
  4134. valid = data;
  4135. if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
  4136. DBG_PRINT(ERR_DBG,
  4137. "ETHTOOL_WRITE_EEPROM Err: Cannot ");
  4138. DBG_PRINT(ERR_DBG,
  4139. "write into the specified offset\n");
  4140. return -EFAULT;
  4141. }
  4142. cnt++;
  4143. len--;
  4144. }
  4145. return 0;
  4146. }
  4147. /**
  4148. * s2io_register_test - reads and writes into all clock domains.
  4149. * @sp : private member of the device structure, which is a pointer to the
  4150. * s2io_nic structure.
  4151. * @data : variable that returns the result of each of the test conducted b
  4152. * by the driver.
  4153. * Description:
  4154. * Read and write into all clock domains. The NIC has 3 clock domains,
  4155. * see that registers in all the three regions are accessible.
  4156. * Return value:
  4157. * 0 on success.
  4158. */
  4159. static int s2io_register_test(nic_t * sp, uint64_t * data)
  4160. {
  4161. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  4162. u64 val64 = 0, exp_val;
  4163. int fail = 0;
  4164. val64 = readq(&bar0->pif_rd_swapper_fb);
  4165. if (val64 != 0x123456789abcdefULL) {
  4166. fail = 1;
  4167. DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
  4168. }
  4169. val64 = readq(&bar0->rmac_pause_cfg);
  4170. if (val64 != 0xc000ffff00000000ULL) {
  4171. fail = 1;
  4172. DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
  4173. }
  4174. val64 = readq(&bar0->rx_queue_cfg);
  4175. if (sp->device_type == XFRAME_II_DEVICE)
  4176. exp_val = 0x0404040404040404ULL;
  4177. else
  4178. exp_val = 0x0808080808080808ULL;
  4179. if (val64 != exp_val) {
  4180. fail = 1;
  4181. DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
  4182. }
  4183. val64 = readq(&bar0->xgxs_efifo_cfg);
  4184. if (val64 != 0x000000001923141EULL) {
  4185. fail = 1;
  4186. DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
  4187. }
  4188. val64 = 0x5A5A5A5A5A5A5A5AULL;
  4189. writeq(val64, &bar0->xmsi_data);
  4190. val64 = readq(&bar0->xmsi_data);
  4191. if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
  4192. fail = 1;
  4193. DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
  4194. }
  4195. val64 = 0xA5A5A5A5A5A5A5A5ULL;
  4196. writeq(val64, &bar0->xmsi_data);
  4197. val64 = readq(&bar0->xmsi_data);
  4198. if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
  4199. fail = 1;
  4200. DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
  4201. }
  4202. *data = fail;
  4203. return fail;
  4204. }
  4205. /**
  4206. * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
  4207. * @sp : private member of the device structure, which is a pointer to the
  4208. * s2io_nic structure.
  4209. * @data:variable that returns the result of each of the test conducted by
  4210. * the driver.
  4211. * Description:
  4212. * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
  4213. * register.
  4214. * Return value:
  4215. * 0 on success.
  4216. */
  4217. static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
  4218. {
  4219. int fail = 0;
  4220. u64 ret_data, org_4F0, org_7F0;
  4221. u8 saved_4F0 = 0, saved_7F0 = 0;
  4222. struct net_device *dev = sp->dev;
  4223. /* Test Write Error at offset 0 */
  4224. /* Note that SPI interface allows write access to all areas
  4225. * of EEPROM. Hence doing all negative testing only for Xframe I.
  4226. */
  4227. if (sp->device_type == XFRAME_I_DEVICE)
  4228. if (!write_eeprom(sp, 0, 0, 3))
  4229. fail = 1;
  4230. /* Save current values at offsets 0x4F0 and 0x7F0 */
  4231. if (!read_eeprom(sp, 0x4F0, &org_4F0))
  4232. saved_4F0 = 1;
  4233. if (!read_eeprom(sp, 0x7F0, &org_7F0))
  4234. saved_7F0 = 1;
  4235. /* Test Write at offset 4f0 */
  4236. if (write_eeprom(sp, 0x4F0, 0x012345, 3))
  4237. fail = 1;
  4238. if (read_eeprom(sp, 0x4F0, &ret_data))
  4239. fail = 1;
  4240. if (ret_data != 0x012345) {
  4241. DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
  4242. fail = 1;
  4243. }
  4244. /* Reset the EEPROM data go FFFF */
  4245. write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
  4246. /* Test Write Request Error at offset 0x7c */
  4247. if (sp->device_type == XFRAME_I_DEVICE)
  4248. if (!write_eeprom(sp, 0x07C, 0, 3))
  4249. fail = 1;
  4250. /* Test Write Request at offset 0x7f0 */
  4251. if (write_eeprom(sp, 0x7F0, 0x012345, 3))
  4252. fail = 1;
  4253. if (read_eeprom(sp, 0x7F0, &ret_data))
  4254. fail = 1;
  4255. if (ret_data != 0x012345) {
  4256. DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
  4257. fail = 1;
  4258. }
  4259. /* Reset the EEPROM data go FFFF */
  4260. write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
  4261. if (sp->device_type == XFRAME_I_DEVICE) {
  4262. /* Test Write Error at offset 0x80 */
  4263. if (!write_eeprom(sp, 0x080, 0, 3))
  4264. fail = 1;
  4265. /* Test Write Error at offset 0xfc */
  4266. if (!write_eeprom(sp, 0x0FC, 0, 3))
  4267. fail = 1;
  4268. /* Test Write Error at offset 0x100 */
  4269. if (!write_eeprom(sp, 0x100, 0, 3))
  4270. fail = 1;
  4271. /* Test Write Error at offset 4ec */
  4272. if (!write_eeprom(sp, 0x4EC, 0, 3))
  4273. fail = 1;
  4274. }
  4275. /* Restore values at offsets 0x4F0 and 0x7F0 */
  4276. if (saved_4F0)
  4277. write_eeprom(sp, 0x4F0, org_4F0, 3);
  4278. if (saved_7F0)
  4279. write_eeprom(sp, 0x7F0, org_7F0, 3);
  4280. *data = fail;
  4281. return fail;
  4282. }
  4283. /**
  4284. * s2io_bist_test - invokes the MemBist test of the card .
  4285. * @sp : private member of the device structure, which is a pointer to the
  4286. * s2io_nic structure.
  4287. * @data:variable that returns the result of each of the test conducted by
  4288. * the driver.
  4289. * Description:
  4290. * This invokes the MemBist test of the card. We give around
  4291. * 2 secs time for the Test to complete. If it's still not complete
  4292. * within this peiod, we consider that the test failed.
  4293. * Return value:
  4294. * 0 on success and -1 on failure.
  4295. */
  4296. static int s2io_bist_test(nic_t * sp, uint64_t * data)
  4297. {
  4298. u8 bist = 0;
  4299. int cnt = 0, ret = -1;
  4300. pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
  4301. bist |= PCI_BIST_START;
  4302. pci_write_config_word(sp->pdev, PCI_BIST, bist);
  4303. while (cnt < 20) {
  4304. pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
  4305. if (!(bist & PCI_BIST_START)) {
  4306. *data = (bist & PCI_BIST_CODE_MASK);
  4307. ret = 0;
  4308. break;
  4309. }
  4310. msleep(100);
  4311. cnt++;
  4312. }
  4313. return ret;
  4314. }
  4315. /**
  4316. * s2io-link_test - verifies the link state of the nic
  4317. * @sp ; private member of the device structure, which is a pointer to the
  4318. * s2io_nic structure.
  4319. * @data: variable that returns the result of each of the test conducted by
  4320. * the driver.
  4321. * Description:
  4322. * The function verifies the link state of the NIC and updates the input
  4323. * argument 'data' appropriately.
  4324. * Return value:
  4325. * 0 on success.
  4326. */
  4327. static int s2io_link_test(nic_t * sp, uint64_t * data)
  4328. {
  4329. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  4330. u64 val64;
  4331. val64 = readq(&bar0->adapter_status);
  4332. if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
  4333. *data = 1;
  4334. return 0;
  4335. }
  4336. /**
  4337. * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
  4338. * @sp - private member of the device structure, which is a pointer to the
  4339. * s2io_nic structure.
  4340. * @data - variable that returns the result of each of the test
  4341. * conducted by the driver.
  4342. * Description:
  4343. * This is one of the offline test that tests the read and write
  4344. * access to the RldRam chip on the NIC.
  4345. * Return value:
  4346. * 0 on success.
  4347. */
  4348. static int s2io_rldram_test(nic_t * sp, uint64_t * data)
  4349. {
  4350. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  4351. u64 val64;
  4352. int cnt, iteration = 0, test_fail = 0;
  4353. val64 = readq(&bar0->adapter_control);
  4354. val64 &= ~ADAPTER_ECC_EN;
  4355. writeq(val64, &bar0->adapter_control);
  4356. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4357. val64 |= MC_RLDRAM_TEST_MODE;
  4358. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  4359. val64 = readq(&bar0->mc_rldram_mrs);
  4360. val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
  4361. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  4362. val64 |= MC_RLDRAM_MRS_ENABLE;
  4363. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  4364. while (iteration < 2) {
  4365. val64 = 0x55555555aaaa0000ULL;
  4366. if (iteration == 1) {
  4367. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  4368. }
  4369. writeq(val64, &bar0->mc_rldram_test_d0);
  4370. val64 = 0xaaaa5a5555550000ULL;
  4371. if (iteration == 1) {
  4372. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  4373. }
  4374. writeq(val64, &bar0->mc_rldram_test_d1);
  4375. val64 = 0x55aaaaaaaa5a0000ULL;
  4376. if (iteration == 1) {
  4377. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  4378. }
  4379. writeq(val64, &bar0->mc_rldram_test_d2);
  4380. val64 = (u64) (0x0000003ffffe0100ULL);
  4381. writeq(val64, &bar0->mc_rldram_test_add);
  4382. val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
  4383. MC_RLDRAM_TEST_GO;
  4384. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  4385. for (cnt = 0; cnt < 5; cnt++) {
  4386. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4387. if (val64 & MC_RLDRAM_TEST_DONE)
  4388. break;
  4389. msleep(200);
  4390. }
  4391. if (cnt == 5)
  4392. break;
  4393. val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
  4394. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  4395. for (cnt = 0; cnt < 5; cnt++) {
  4396. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4397. if (val64 & MC_RLDRAM_TEST_DONE)
  4398. break;
  4399. msleep(500);
  4400. }
  4401. if (cnt == 5)
  4402. break;
  4403. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4404. if (!(val64 & MC_RLDRAM_TEST_PASS))
  4405. test_fail = 1;
  4406. iteration++;
  4407. }
  4408. *data = test_fail;
  4409. /* Bring the adapter out of test mode */
  4410. SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
  4411. return test_fail;
  4412. }
  4413. /**
  4414. * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
  4415. * @sp : private member of the device structure, which is a pointer to the
  4416. * s2io_nic structure.
  4417. * @ethtest : pointer to a ethtool command specific structure that will be
  4418. * returned to the user.
  4419. * @data : variable that returns the result of each of the test
  4420. * conducted by the driver.
  4421. * Description:
  4422. * This function conducts 6 tests ( 4 offline and 2 online) to determine
  4423. * the health of the card.
  4424. * Return value:
  4425. * void
  4426. */
  4427. static void s2io_ethtool_test(struct net_device *dev,
  4428. struct ethtool_test *ethtest,
  4429. uint64_t * data)
  4430. {
  4431. nic_t *sp = dev->priv;
  4432. int orig_state = netif_running(sp->dev);
  4433. if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
  4434. /* Offline Tests. */
  4435. if (orig_state)
  4436. s2io_close(sp->dev);
  4437. if (s2io_register_test(sp, &data[0]))
  4438. ethtest->flags |= ETH_TEST_FL_FAILED;
  4439. s2io_reset(sp);
  4440. if (s2io_rldram_test(sp, &data[3]))
  4441. ethtest->flags |= ETH_TEST_FL_FAILED;
  4442. s2io_reset(sp);
  4443. if (s2io_eeprom_test(sp, &data[1]))
  4444. ethtest->flags |= ETH_TEST_FL_FAILED;
  4445. if (s2io_bist_test(sp, &data[4]))
  4446. ethtest->flags |= ETH_TEST_FL_FAILED;
  4447. if (orig_state)
  4448. s2io_open(sp->dev);
  4449. data[2] = 0;
  4450. } else {
  4451. /* Online Tests. */
  4452. if (!orig_state) {
  4453. DBG_PRINT(ERR_DBG,
  4454. "%s: is not up, cannot run test\n",
  4455. dev->name);
  4456. data[0] = -1;
  4457. data[1] = -1;
  4458. data[2] = -1;
  4459. data[3] = -1;
  4460. data[4] = -1;
  4461. }
  4462. if (s2io_link_test(sp, &data[2]))
  4463. ethtest->flags |= ETH_TEST_FL_FAILED;
  4464. data[0] = 0;
  4465. data[1] = 0;
  4466. data[3] = 0;
  4467. data[4] = 0;
  4468. }
  4469. }
  4470. static void s2io_get_ethtool_stats(struct net_device *dev,
  4471. struct ethtool_stats *estats,
  4472. u64 * tmp_stats)
  4473. {
  4474. int i = 0;
  4475. nic_t *sp = dev->priv;
  4476. StatInfo_t *stat_info = sp->mac_control.stats_info;
  4477. s2io_updt_stats(sp);
  4478. tmp_stats[i++] =
  4479. (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
  4480. le32_to_cpu(stat_info->tmac_frms);
  4481. tmp_stats[i++] =
  4482. (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
  4483. le32_to_cpu(stat_info->tmac_data_octets);
  4484. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
  4485. tmp_stats[i++] =
  4486. (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
  4487. le32_to_cpu(stat_info->tmac_mcst_frms);
  4488. tmp_stats[i++] =
  4489. (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
  4490. le32_to_cpu(stat_info->tmac_bcst_frms);
  4491. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
  4492. tmp_stats[i++] =
  4493. (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
  4494. le32_to_cpu(stat_info->tmac_any_err_frms);
  4495. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
  4496. tmp_stats[i++] =
  4497. (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
  4498. le32_to_cpu(stat_info->tmac_vld_ip);
  4499. tmp_stats[i++] =
  4500. (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
  4501. le32_to_cpu(stat_info->tmac_drop_ip);
  4502. tmp_stats[i++] =
  4503. (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
  4504. le32_to_cpu(stat_info->tmac_icmp);
  4505. tmp_stats[i++] =
  4506. (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
  4507. le32_to_cpu(stat_info->tmac_rst_tcp);
  4508. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
  4509. tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
  4510. le32_to_cpu(stat_info->tmac_udp);
  4511. tmp_stats[i++] =
  4512. (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
  4513. le32_to_cpu(stat_info->rmac_vld_frms);
  4514. tmp_stats[i++] =
  4515. (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
  4516. le32_to_cpu(stat_info->rmac_data_octets);
  4517. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
  4518. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
  4519. tmp_stats[i++] =
  4520. (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
  4521. le32_to_cpu(stat_info->rmac_vld_mcst_frms);
  4522. tmp_stats[i++] =
  4523. (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
  4524. le32_to_cpu(stat_info->rmac_vld_bcst_frms);
  4525. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
  4526. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
  4527. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
  4528. tmp_stats[i++] =
  4529. (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
  4530. le32_to_cpu(stat_info->rmac_discarded_frms);
  4531. tmp_stats[i++] =
  4532. (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
  4533. le32_to_cpu(stat_info->rmac_usized_frms);
  4534. tmp_stats[i++] =
  4535. (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
  4536. le32_to_cpu(stat_info->rmac_osized_frms);
  4537. tmp_stats[i++] =
  4538. (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
  4539. le32_to_cpu(stat_info->rmac_frag_frms);
  4540. tmp_stats[i++] =
  4541. (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
  4542. le32_to_cpu(stat_info->rmac_jabber_frms);
  4543. tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
  4544. le32_to_cpu(stat_info->rmac_ip);
  4545. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
  4546. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
  4547. tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
  4548. le32_to_cpu(stat_info->rmac_drop_ip);
  4549. tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
  4550. le32_to_cpu(stat_info->rmac_icmp);
  4551. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
  4552. tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
  4553. le32_to_cpu(stat_info->rmac_udp);
  4554. tmp_stats[i++] =
  4555. (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
  4556. le32_to_cpu(stat_info->rmac_err_drp_udp);
  4557. tmp_stats[i++] =
  4558. (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
  4559. le32_to_cpu(stat_info->rmac_pause_cnt);
  4560. tmp_stats[i++] =
  4561. (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
  4562. le32_to_cpu(stat_info->rmac_accepted_ip);
  4563. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
  4564. tmp_stats[i++] = 0;
  4565. tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
  4566. tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
  4567. }
  4568. int s2io_ethtool_get_regs_len(struct net_device *dev)
  4569. {
  4570. return (XENA_REG_SPACE);
  4571. }
  4572. u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
  4573. {
  4574. nic_t *sp = dev->priv;
  4575. return (sp->rx_csum);
  4576. }
  4577. int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
  4578. {
  4579. nic_t *sp = dev->priv;
  4580. if (data)
  4581. sp->rx_csum = 1;
  4582. else
  4583. sp->rx_csum = 0;
  4584. return 0;
  4585. }
  4586. int s2io_get_eeprom_len(struct net_device *dev)
  4587. {
  4588. return (XENA_EEPROM_SPACE);
  4589. }
  4590. int s2io_ethtool_self_test_count(struct net_device *dev)
  4591. {
  4592. return (S2IO_TEST_LEN);
  4593. }
  4594. void s2io_ethtool_get_strings(struct net_device *dev,
  4595. u32 stringset, u8 * data)
  4596. {
  4597. switch (stringset) {
  4598. case ETH_SS_TEST:
  4599. memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
  4600. break;
  4601. case ETH_SS_STATS:
  4602. memcpy(data, &ethtool_stats_keys,
  4603. sizeof(ethtool_stats_keys));
  4604. }
  4605. }
  4606. static int s2io_ethtool_get_stats_count(struct net_device *dev)
  4607. {
  4608. return (S2IO_STAT_LEN);
  4609. }
  4610. int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
  4611. {
  4612. if (data)
  4613. dev->features |= NETIF_F_IP_CSUM;
  4614. else
  4615. dev->features &= ~NETIF_F_IP_CSUM;
  4616. return 0;
  4617. }
  4618. static struct ethtool_ops netdev_ethtool_ops = {
  4619. .get_settings = s2io_ethtool_gset,
  4620. .set_settings = s2io_ethtool_sset,
  4621. .get_drvinfo = s2io_ethtool_gdrvinfo,
  4622. .get_regs_len = s2io_ethtool_get_regs_len,
  4623. .get_regs = s2io_ethtool_gregs,
  4624. .get_link = ethtool_op_get_link,
  4625. .get_eeprom_len = s2io_get_eeprom_len,
  4626. .get_eeprom = s2io_ethtool_geeprom,
  4627. .set_eeprom = s2io_ethtool_seeprom,
  4628. .get_pauseparam = s2io_ethtool_getpause_data,
  4629. .set_pauseparam = s2io_ethtool_setpause_data,
  4630. .get_rx_csum = s2io_ethtool_get_rx_csum,
  4631. .set_rx_csum = s2io_ethtool_set_rx_csum,
  4632. .get_tx_csum = ethtool_op_get_tx_csum,
  4633. .set_tx_csum = s2io_ethtool_op_set_tx_csum,
  4634. .get_sg = ethtool_op_get_sg,
  4635. .set_sg = ethtool_op_set_sg,
  4636. #ifdef NETIF_F_TSO
  4637. .get_tso = ethtool_op_get_tso,
  4638. .set_tso = ethtool_op_set_tso,
  4639. #endif
  4640. .self_test_count = s2io_ethtool_self_test_count,
  4641. .self_test = s2io_ethtool_test,
  4642. .get_strings = s2io_ethtool_get_strings,
  4643. .phys_id = s2io_ethtool_idnic,
  4644. .get_stats_count = s2io_ethtool_get_stats_count,
  4645. .get_ethtool_stats = s2io_get_ethtool_stats
  4646. };
  4647. /**
  4648. * s2io_ioctl - Entry point for the Ioctl
  4649. * @dev : Device pointer.
  4650. * @ifr : An IOCTL specefic structure, that can contain a pointer to
  4651. * a proprietary structure used to pass information to the driver.
  4652. * @cmd : This is used to distinguish between the different commands that
  4653. * can be passed to the IOCTL functions.
  4654. * Description:
  4655. * Currently there are no special functionality supported in IOCTL, hence
  4656. * function always return EOPNOTSUPPORTED
  4657. */
  4658. int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  4659. {
  4660. return -EOPNOTSUPP;
  4661. }
  4662. /**
  4663. * s2io_change_mtu - entry point to change MTU size for the device.
  4664. * @dev : device pointer.
  4665. * @new_mtu : the new MTU size for the device.
  4666. * Description: A driver entry point to change MTU size for the device.
  4667. * Before changing the MTU the device must be stopped.
  4668. * Return value:
  4669. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  4670. * file on failure.
  4671. */
  4672. int s2io_change_mtu(struct net_device *dev, int new_mtu)
  4673. {
  4674. nic_t *sp = dev->priv;
  4675. if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
  4676. DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
  4677. dev->name);
  4678. return -EPERM;
  4679. }
  4680. dev->mtu = new_mtu;
  4681. if (netif_running(dev)) {
  4682. s2io_card_down(sp);
  4683. netif_stop_queue(dev);
  4684. if (s2io_card_up(sp)) {
  4685. DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
  4686. __FUNCTION__);
  4687. }
  4688. if (netif_queue_stopped(dev))
  4689. netif_wake_queue(dev);
  4690. } else { /* Device is down */
  4691. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  4692. u64 val64 = new_mtu;
  4693. writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
  4694. }
  4695. return 0;
  4696. }
  4697. /**
  4698. * s2io_tasklet - Bottom half of the ISR.
  4699. * @dev_adr : address of the device structure in dma_addr_t format.
  4700. * Description:
  4701. * This is the tasklet or the bottom half of the ISR. This is
  4702. * an extension of the ISR which is scheduled by the scheduler to be run
  4703. * when the load on the CPU is low. All low priority tasks of the ISR can
  4704. * be pushed into the tasklet. For now the tasklet is used only to
  4705. * replenish the Rx buffers in the Rx buffer descriptors.
  4706. * Return value:
  4707. * void.
  4708. */
  4709. static void s2io_tasklet(unsigned long dev_addr)
  4710. {
  4711. struct net_device *dev = (struct net_device *) dev_addr;
  4712. nic_t *sp = dev->priv;
  4713. int i, ret;
  4714. mac_info_t *mac_control;
  4715. struct config_param *config;
  4716. mac_control = &sp->mac_control;
  4717. config = &sp->config;
  4718. if (!TASKLET_IN_USE) {
  4719. for (i = 0; i < config->rx_ring_num; i++) {
  4720. ret = fill_rx_buffers(sp, i);
  4721. if (ret == -ENOMEM) {
  4722. DBG_PRINT(ERR_DBG, "%s: Out of ",
  4723. dev->name);
  4724. DBG_PRINT(ERR_DBG, "memory in tasklet\n");
  4725. break;
  4726. } else if (ret == -EFILL) {
  4727. DBG_PRINT(ERR_DBG,
  4728. "%s: Rx Ring %d is full\n",
  4729. dev->name, i);
  4730. break;
  4731. }
  4732. }
  4733. clear_bit(0, (&sp->tasklet_status));
  4734. }
  4735. }
  4736. /**
  4737. * s2io_set_link - Set the LInk status
  4738. * @data: long pointer to device private structue
  4739. * Description: Sets the link status for the adapter
  4740. */
  4741. static void s2io_set_link(unsigned long data)
  4742. {
  4743. nic_t *nic = (nic_t *) data;
  4744. struct net_device *dev = nic->dev;
  4745. XENA_dev_config_t __iomem *bar0 = nic->bar0;
  4746. register u64 val64;
  4747. u16 subid;
  4748. if (test_and_set_bit(0, &(nic->link_state))) {
  4749. /* The card is being reset, no point doing anything */
  4750. return;
  4751. }
  4752. subid = nic->pdev->subsystem_device;
  4753. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
  4754. /*
  4755. * Allow a small delay for the NICs self initiated
  4756. * cleanup to complete.
  4757. */
  4758. msleep(100);
  4759. }
  4760. val64 = readq(&bar0->adapter_status);
  4761. if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
  4762. if (LINK_IS_UP(val64)) {
  4763. val64 = readq(&bar0->adapter_control);
  4764. val64 |= ADAPTER_CNTL_EN;
  4765. writeq(val64, &bar0->adapter_control);
  4766. if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
  4767. subid)) {
  4768. val64 = readq(&bar0->gpio_control);
  4769. val64 |= GPIO_CTRL_GPIO_0;
  4770. writeq(val64, &bar0->gpio_control);
  4771. val64 = readq(&bar0->gpio_control);
  4772. } else {
  4773. val64 |= ADAPTER_LED_ON;
  4774. writeq(val64, &bar0->adapter_control);
  4775. }
  4776. if (s2io_link_fault_indication(nic) ==
  4777. MAC_RMAC_ERR_TIMER) {
  4778. val64 = readq(&bar0->adapter_status);
  4779. if (!LINK_IS_UP(val64)) {
  4780. DBG_PRINT(ERR_DBG, "%s:", dev->name);
  4781. DBG_PRINT(ERR_DBG, " Link down");
  4782. DBG_PRINT(ERR_DBG, "after ");
  4783. DBG_PRINT(ERR_DBG, "enabling ");
  4784. DBG_PRINT(ERR_DBG, "device \n");
  4785. }
  4786. }
  4787. if (nic->device_enabled_once == FALSE) {
  4788. nic->device_enabled_once = TRUE;
  4789. }
  4790. s2io_link(nic, LINK_UP);
  4791. } else {
  4792. if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
  4793. subid)) {
  4794. val64 = readq(&bar0->gpio_control);
  4795. val64 &= ~GPIO_CTRL_GPIO_0;
  4796. writeq(val64, &bar0->gpio_control);
  4797. val64 = readq(&bar0->gpio_control);
  4798. }
  4799. s2io_link(nic, LINK_DOWN);
  4800. }
  4801. } else { /* NIC is not Quiescent. */
  4802. DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
  4803. DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
  4804. netif_stop_queue(dev);
  4805. }
  4806. clear_bit(0, &(nic->link_state));
  4807. }
  4808. static void s2io_card_down(nic_t * sp)
  4809. {
  4810. int cnt = 0;
  4811. XENA_dev_config_t __iomem *bar0 = sp->bar0;
  4812. unsigned long flags;
  4813. register u64 val64 = 0;
  4814. del_timer_sync(&sp->alarm_timer);
  4815. /* If s2io_set_link task is executing, wait till it completes. */
  4816. while (test_and_set_bit(0, &(sp->link_state))) {
  4817. msleep(50);
  4818. }
  4819. atomic_set(&sp->card_state, CARD_DOWN);
  4820. /* disable Tx and Rx traffic on the NIC */
  4821. stop_nic(sp);
  4822. /* Kill tasklet. */
  4823. tasklet_kill(&sp->task);
  4824. /* Check if the device is Quiescent and then Reset the NIC */
  4825. do {
  4826. val64 = readq(&bar0->adapter_status);
  4827. if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
  4828. break;
  4829. }
  4830. msleep(50);
  4831. cnt++;
  4832. if (cnt == 10) {
  4833. DBG_PRINT(ERR_DBG,
  4834. "s2io_close:Device not Quiescent ");
  4835. DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
  4836. (unsigned long long) val64);
  4837. break;
  4838. }
  4839. } while (1);
  4840. s2io_reset(sp);
  4841. /* Waiting till all Interrupt handlers are complete */
  4842. cnt = 0;
  4843. do {
  4844. msleep(10);
  4845. if (!atomic_read(&sp->isr_cnt))
  4846. break;
  4847. cnt++;
  4848. } while(cnt < 5);
  4849. spin_lock_irqsave(&sp->tx_lock, flags);
  4850. /* Free all Tx buffers */
  4851. free_tx_buffers(sp);
  4852. spin_unlock_irqrestore(&sp->tx_lock, flags);
  4853. /* Free all Rx buffers */
  4854. spin_lock_irqsave(&sp->rx_lock, flags);
  4855. free_rx_buffers(sp);
  4856. spin_unlock_irqrestore(&sp->rx_lock, flags);
  4857. clear_bit(0, &(sp->link_state));
  4858. }
  4859. static int s2io_card_up(nic_t * sp)
  4860. {
  4861. int i, ret = 0;
  4862. mac_info_t *mac_control;
  4863. struct config_param *config;
  4864. struct net_device *dev = (struct net_device *) sp->dev;
  4865. /* Initialize the H/W I/O registers */
  4866. if (init_nic(sp) != 0) {
  4867. DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
  4868. dev->name);
  4869. return -ENODEV;
  4870. }
  4871. if (sp->intr_type == MSI)
  4872. ret = s2io_enable_msi(sp);
  4873. else if (sp->intr_type == MSI_X)
  4874. ret = s2io_enable_msi_x(sp);
  4875. if (ret) {
  4876. DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
  4877. sp->intr_type = INTA;
  4878. }
  4879. /*
  4880. * Initializing the Rx buffers. For now we are considering only 1
  4881. * Rx ring and initializing buffers into 30 Rx blocks
  4882. */
  4883. mac_control = &sp->mac_control;
  4884. config = &sp->config;
  4885. for (i = 0; i < config->rx_ring_num; i++) {
  4886. if ((ret = fill_rx_buffers(sp, i))) {
  4887. DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
  4888. dev->name);
  4889. s2io_reset(sp);
  4890. free_rx_buffers(sp);
  4891. return -ENOMEM;
  4892. }
  4893. DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
  4894. atomic_read(&sp->rx_bufs_left[i]));
  4895. }
  4896. /* Setting its receive mode */
  4897. s2io_set_multicast(dev);
  4898. /* Enable tasklet for the device */
  4899. tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
  4900. /* Enable Rx Traffic and interrupts on the NIC */
  4901. if (start_nic(sp)) {
  4902. DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
  4903. tasklet_kill(&sp->task);
  4904. s2io_reset(sp);
  4905. free_irq(dev->irq, dev);
  4906. free_rx_buffers(sp);
  4907. return -ENODEV;
  4908. }
  4909. S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
  4910. atomic_set(&sp->card_state, CARD_UP);
  4911. return 0;
  4912. }
  4913. /**
  4914. * s2io_restart_nic - Resets the NIC.
  4915. * @data : long pointer to the device private structure
  4916. * Description:
  4917. * This function is scheduled to be run by the s2io_tx_watchdog
  4918. * function after 0.5 secs to reset the NIC. The idea is to reduce
  4919. * the run time of the watch dog routine which is run holding a
  4920. * spin lock.
  4921. */
  4922. static void s2io_restart_nic(unsigned long data)
  4923. {
  4924. struct net_device *dev = (struct net_device *) data;
  4925. nic_t *sp = dev->priv;
  4926. s2io_card_down(sp);
  4927. if (s2io_card_up(sp)) {
  4928. DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
  4929. dev->name);
  4930. }
  4931. netif_wake_queue(dev);
  4932. DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
  4933. dev->name);
  4934. }
  4935. /**
  4936. * s2io_tx_watchdog - Watchdog for transmit side.
  4937. * @dev : Pointer to net device structure
  4938. * Description:
  4939. * This function is triggered if the Tx Queue is stopped
  4940. * for a pre-defined amount of time when the Interface is still up.
  4941. * If the Interface is jammed in such a situation, the hardware is
  4942. * reset (by s2io_close) and restarted again (by s2io_open) to
  4943. * overcome any problem that might have been caused in the hardware.
  4944. * Return value:
  4945. * void
  4946. */
  4947. static void s2io_tx_watchdog(struct net_device *dev)
  4948. {
  4949. nic_t *sp = dev->priv;
  4950. if (netif_carrier_ok(dev)) {
  4951. schedule_work(&sp->rst_timer_task);
  4952. }
  4953. }
  4954. /**
  4955. * rx_osm_handler - To perform some OS related operations on SKB.
  4956. * @sp: private member of the device structure,pointer to s2io_nic structure.
  4957. * @skb : the socket buffer pointer.
  4958. * @len : length of the packet
  4959. * @cksum : FCS checksum of the frame.
  4960. * @ring_no : the ring from which this RxD was extracted.
  4961. * Description:
  4962. * This function is called by the Tx interrupt serivce routine to perform
  4963. * some OS related operations on the SKB before passing it to the upper
  4964. * layers. It mainly checks if the checksum is OK, if so adds it to the
  4965. * SKBs cksum variable, increments the Rx packet count and passes the SKB
  4966. * to the upper layer. If the checksum is wrong, it increments the Rx
  4967. * packet error count, frees the SKB and returns error.
  4968. * Return value:
  4969. * SUCCESS on success and -1 on failure.
  4970. */
  4971. static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
  4972. {
  4973. nic_t *sp = ring_data->nic;
  4974. struct net_device *dev = (struct net_device *) sp->dev;
  4975. struct sk_buff *skb = (struct sk_buff *)
  4976. ((unsigned long) rxdp->Host_Control);
  4977. int ring_no = ring_data->ring_no;
  4978. u16 l3_csum, l4_csum;
  4979. #ifdef CONFIG_2BUFF_MODE
  4980. int buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
  4981. int buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
  4982. int get_block = ring_data->rx_curr_get_info.block_index;
  4983. int get_off = ring_data->rx_curr_get_info.offset;
  4984. buffAdd_t *ba = &ring_data->ba[get_block][get_off];
  4985. unsigned char *buff;
  4986. #else
  4987. u16 len = (u16) ((RXD_GET_BUFFER0_SIZE(rxdp->Control_2)) >> 48);;
  4988. #endif
  4989. skb->dev = dev;
  4990. if (rxdp->Control_1 & RXD_T_CODE) {
  4991. unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
  4992. DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
  4993. dev->name, err);
  4994. dev_kfree_skb(skb);
  4995. sp->stats.rx_crc_errors++;
  4996. atomic_dec(&sp->rx_bufs_left[ring_no]);
  4997. rxdp->Host_Control = 0;
  4998. return 0;
  4999. }
  5000. /* Updating statistics */
  5001. rxdp->Host_Control = 0;
  5002. sp->rx_pkt_count++;
  5003. sp->stats.rx_packets++;
  5004. #ifndef CONFIG_2BUFF_MODE
  5005. sp->stats.rx_bytes += len;
  5006. #else
  5007. sp->stats.rx_bytes += buf0_len + buf2_len;
  5008. #endif
  5009. #ifndef CONFIG_2BUFF_MODE
  5010. skb_put(skb, len);
  5011. #else
  5012. buff = skb_push(skb, buf0_len);
  5013. memcpy(buff, ba->ba_0, buf0_len);
  5014. skb_put(skb, buf2_len);
  5015. #endif
  5016. if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
  5017. (sp->rx_csum)) {
  5018. l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
  5019. l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
  5020. if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
  5021. /*
  5022. * NIC verifies if the Checksum of the received
  5023. * frame is Ok or not and accordingly returns
  5024. * a flag in the RxD.
  5025. */
  5026. skb->ip_summed = CHECKSUM_UNNECESSARY;
  5027. } else {
  5028. /*
  5029. * Packet with erroneous checksum, let the
  5030. * upper layers deal with it.
  5031. */
  5032. skb->ip_summed = CHECKSUM_NONE;
  5033. }
  5034. } else {
  5035. skb->ip_summed = CHECKSUM_NONE;
  5036. }
  5037. skb->protocol = eth_type_trans(skb, dev);
  5038. #ifdef CONFIG_S2IO_NAPI
  5039. if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
  5040. /* Queueing the vlan frame to the upper layer */
  5041. vlan_hwaccel_receive_skb(skb, sp->vlgrp,
  5042. RXD_GET_VLAN_TAG(rxdp->Control_2));
  5043. } else {
  5044. netif_receive_skb(skb);
  5045. }
  5046. #else
  5047. if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
  5048. /* Queueing the vlan frame to the upper layer */
  5049. vlan_hwaccel_rx(skb, sp->vlgrp,
  5050. RXD_GET_VLAN_TAG(rxdp->Control_2));
  5051. } else {
  5052. netif_rx(skb);
  5053. }
  5054. #endif
  5055. dev->last_rx = jiffies;
  5056. atomic_dec(&sp->rx_bufs_left[ring_no]);
  5057. return SUCCESS;
  5058. }
  5059. /**
  5060. * s2io_link - stops/starts the Tx queue.
  5061. * @sp : private member of the device structure, which is a pointer to the
  5062. * s2io_nic structure.
  5063. * @link : inidicates whether link is UP/DOWN.
  5064. * Description:
  5065. * This function stops/starts the Tx queue depending on whether the link
  5066. * status of the NIC is is down or up. This is called by the Alarm
  5067. * interrupt handler whenever a link change interrupt comes up.
  5068. * Return value:
  5069. * void.
  5070. */
  5071. void s2io_link(nic_t * sp, int link)
  5072. {
  5073. struct net_device *dev = (struct net_device *) sp->dev;
  5074. if (link != sp->last_link_state) {
  5075. if (link == LINK_DOWN) {
  5076. DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
  5077. netif_carrier_off(dev);
  5078. } else {
  5079. DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
  5080. netif_carrier_on(dev);
  5081. }
  5082. }
  5083. sp->last_link_state = link;
  5084. }
  5085. /**
  5086. * get_xena_rev_id - to identify revision ID of xena.
  5087. * @pdev : PCI Dev structure
  5088. * Description:
  5089. * Function to identify the Revision ID of xena.
  5090. * Return value:
  5091. * returns the revision ID of the device.
  5092. */
  5093. int get_xena_rev_id(struct pci_dev *pdev)
  5094. {
  5095. u8 id = 0;
  5096. int ret;
  5097. ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
  5098. return id;
  5099. }
  5100. /**
  5101. * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
  5102. * @sp : private member of the device structure, which is a pointer to the
  5103. * s2io_nic structure.
  5104. * Description:
  5105. * This function initializes a few of the PCI and PCI-X configuration registers
  5106. * with recommended values.
  5107. * Return value:
  5108. * void
  5109. */
  5110. static void s2io_init_pci(nic_t * sp)
  5111. {
  5112. u16 pci_cmd = 0, pcix_cmd = 0;
  5113. /* Enable Data Parity Error Recovery in PCI-X command register. */
  5114. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  5115. &(pcix_cmd));
  5116. pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  5117. (pcix_cmd | 1));
  5118. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  5119. &(pcix_cmd));
  5120. /* Set the PErr Response bit in PCI command register. */
  5121. pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
  5122. pci_write_config_word(sp->pdev, PCI_COMMAND,
  5123. (pci_cmd | PCI_COMMAND_PARITY));
  5124. pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
  5125. /* Forcibly disabling relaxed ordering capability of the card. */
  5126. pcix_cmd &= 0xfffd;
  5127. pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  5128. pcix_cmd);
  5129. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  5130. &(pcix_cmd));
  5131. }
  5132. MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
  5133. MODULE_LICENSE("GPL");
  5134. MODULE_VERSION(DRV_VERSION);
  5135. module_param(tx_fifo_num, int, 0);
  5136. module_param(rx_ring_num, int, 0);
  5137. module_param_array(tx_fifo_len, uint, NULL, 0);
  5138. module_param_array(rx_ring_sz, uint, NULL, 0);
  5139. module_param_array(rts_frm_len, uint, NULL, 0);
  5140. module_param(use_continuous_tx_intrs, int, 1);
  5141. module_param(rmac_pause_time, int, 0);
  5142. module_param(mc_pause_threshold_q0q3, int, 0);
  5143. module_param(mc_pause_threshold_q4q7, int, 0);
  5144. module_param(shared_splits, int, 0);
  5145. module_param(tmac_util_period, int, 0);
  5146. module_param(rmac_util_period, int, 0);
  5147. module_param(bimodal, bool, 0);
  5148. #ifndef CONFIG_S2IO_NAPI
  5149. module_param(indicate_max_pkts, int, 0);
  5150. #endif
  5151. module_param(rxsync_frequency, int, 0);
  5152. module_param(intr_type, int, 0);
  5153. /**
  5154. * s2io_init_nic - Initialization of the adapter .
  5155. * @pdev : structure containing the PCI related information of the device.
  5156. * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
  5157. * Description:
  5158. * The function initializes an adapter identified by the pci_dec structure.
  5159. * All OS related initialization including memory and device structure and
  5160. * initlaization of the device private variable is done. Also the swapper
  5161. * control register is initialized to enable read and write into the I/O
  5162. * registers of the device.
  5163. * Return value:
  5164. * returns 0 on success and negative on failure.
  5165. */
  5166. static int __devinit
  5167. s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
  5168. {
  5169. nic_t *sp;
  5170. struct net_device *dev;
  5171. int i, j, ret;
  5172. int dma_flag = FALSE;
  5173. u32 mac_up, mac_down;
  5174. u64 val64 = 0, tmp64 = 0;
  5175. XENA_dev_config_t __iomem *bar0 = NULL;
  5176. u16 subid;
  5177. mac_info_t *mac_control;
  5178. struct config_param *config;
  5179. int mode;
  5180. u8 dev_intr_type = intr_type;
  5181. #ifdef CONFIG_S2IO_NAPI
  5182. if (dev_intr_type != INTA) {
  5183. DBG_PRINT(ERR_DBG, "NAPI cannot be enabled when MSI/MSI-X \
  5184. is enabled. Defaulting to INTA\n");
  5185. dev_intr_type = INTA;
  5186. }
  5187. else
  5188. DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
  5189. #endif
  5190. if ((ret = pci_enable_device(pdev))) {
  5191. DBG_PRINT(ERR_DBG,
  5192. "s2io_init_nic: pci_enable_device failed\n");
  5193. return ret;
  5194. }
  5195. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  5196. DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
  5197. dma_flag = TRUE;
  5198. if (pci_set_consistent_dma_mask
  5199. (pdev, DMA_64BIT_MASK)) {
  5200. DBG_PRINT(ERR_DBG,
  5201. "Unable to obtain 64bit DMA for \
  5202. consistent allocations\n");
  5203. pci_disable_device(pdev);
  5204. return -ENOMEM;
  5205. }
  5206. } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  5207. DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
  5208. } else {
  5209. pci_disable_device(pdev);
  5210. return -ENOMEM;
  5211. }
  5212. if ((dev_intr_type == MSI_X) &&
  5213. ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
  5214. (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
  5215. DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. \
  5216. Defaulting to INTA\n");
  5217. dev_intr_type = INTA;
  5218. }
  5219. if (dev_intr_type != MSI_X) {
  5220. if (pci_request_regions(pdev, s2io_driver_name)) {
  5221. DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
  5222. pci_disable_device(pdev);
  5223. return -ENODEV;
  5224. }
  5225. }
  5226. else {
  5227. if (!(request_mem_region(pci_resource_start(pdev, 0),
  5228. pci_resource_len(pdev, 0), s2io_driver_name))) {
  5229. DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
  5230. pci_disable_device(pdev);
  5231. return -ENODEV;
  5232. }
  5233. if (!(request_mem_region(pci_resource_start(pdev, 2),
  5234. pci_resource_len(pdev, 2), s2io_driver_name))) {
  5235. DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
  5236. release_mem_region(pci_resource_start(pdev, 0),
  5237. pci_resource_len(pdev, 0));
  5238. pci_disable_device(pdev);
  5239. return -ENODEV;
  5240. }
  5241. }
  5242. dev = alloc_etherdev(sizeof(nic_t));
  5243. if (dev == NULL) {
  5244. DBG_PRINT(ERR_DBG, "Device allocation failed\n");
  5245. pci_disable_device(pdev);
  5246. pci_release_regions(pdev);
  5247. return -ENODEV;
  5248. }
  5249. pci_set_master(pdev);
  5250. pci_set_drvdata(pdev, dev);
  5251. SET_MODULE_OWNER(dev);
  5252. SET_NETDEV_DEV(dev, &pdev->dev);
  5253. /* Private member variable initialized to s2io NIC structure */
  5254. sp = dev->priv;
  5255. memset(sp, 0, sizeof(nic_t));
  5256. sp->dev = dev;
  5257. sp->pdev = pdev;
  5258. sp->high_dma_flag = dma_flag;
  5259. sp->device_enabled_once = FALSE;
  5260. sp->intr_type = dev_intr_type;
  5261. if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
  5262. (pdev->device == PCI_DEVICE_ID_HERC_UNI))
  5263. sp->device_type = XFRAME_II_DEVICE;
  5264. else
  5265. sp->device_type = XFRAME_I_DEVICE;
  5266. /* Initialize some PCI/PCI-X fields of the NIC. */
  5267. s2io_init_pci(sp);
  5268. /*
  5269. * Setting the device configuration parameters.
  5270. * Most of these parameters can be specified by the user during
  5271. * module insertion as they are module loadable parameters. If
  5272. * these parameters are not not specified during load time, they
  5273. * are initialized with default values.
  5274. */
  5275. mac_control = &sp->mac_control;
  5276. config = &sp->config;
  5277. /* Tx side parameters. */
  5278. if (tx_fifo_len[0] == 0)
  5279. tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
  5280. config->tx_fifo_num = tx_fifo_num;
  5281. for (i = 0; i < MAX_TX_FIFOS; i++) {
  5282. config->tx_cfg[i].fifo_len = tx_fifo_len[i];
  5283. config->tx_cfg[i].fifo_priority = i;
  5284. }
  5285. /* mapping the QoS priority to the configured fifos */
  5286. for (i = 0; i < MAX_TX_FIFOS; i++)
  5287. config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
  5288. config->tx_intr_type = TXD_INT_TYPE_UTILZ;
  5289. for (i = 0; i < config->tx_fifo_num; i++) {
  5290. config->tx_cfg[i].f_no_snoop =
  5291. (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
  5292. if (config->tx_cfg[i].fifo_len < 65) {
  5293. config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
  5294. break;
  5295. }
  5296. }
  5297. config->max_txds = MAX_SKB_FRAGS + 1;
  5298. /* Rx side parameters. */
  5299. if (rx_ring_sz[0] == 0)
  5300. rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
  5301. config->rx_ring_num = rx_ring_num;
  5302. for (i = 0; i < MAX_RX_RINGS; i++) {
  5303. config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
  5304. (MAX_RXDS_PER_BLOCK + 1);
  5305. config->rx_cfg[i].ring_priority = i;
  5306. }
  5307. for (i = 0; i < rx_ring_num; i++) {
  5308. config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
  5309. config->rx_cfg[i].f_no_snoop =
  5310. (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
  5311. }
  5312. /* Setting Mac Control parameters */
  5313. mac_control->rmac_pause_time = rmac_pause_time;
  5314. mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
  5315. mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
  5316. /* Initialize Ring buffer parameters. */
  5317. for (i = 0; i < config->rx_ring_num; i++)
  5318. atomic_set(&sp->rx_bufs_left[i], 0);
  5319. /* Initialize the number of ISRs currently running */
  5320. atomic_set(&sp->isr_cnt, 0);
  5321. /* initialize the shared memory used by the NIC and the host */
  5322. if (init_shared_mem(sp)) {
  5323. DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
  5324. __FUNCTION__);
  5325. ret = -ENOMEM;
  5326. goto mem_alloc_failed;
  5327. }
  5328. sp->bar0 = ioremap(pci_resource_start(pdev, 0),
  5329. pci_resource_len(pdev, 0));
  5330. if (!sp->bar0) {
  5331. DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
  5332. dev->name);
  5333. ret = -ENOMEM;
  5334. goto bar0_remap_failed;
  5335. }
  5336. sp->bar1 = ioremap(pci_resource_start(pdev, 2),
  5337. pci_resource_len(pdev, 2));
  5338. if (!sp->bar1) {
  5339. DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
  5340. dev->name);
  5341. ret = -ENOMEM;
  5342. goto bar1_remap_failed;
  5343. }
  5344. dev->irq = pdev->irq;
  5345. dev->base_addr = (unsigned long) sp->bar0;
  5346. /* Initializing the BAR1 address as the start of the FIFO pointer. */
  5347. for (j = 0; j < MAX_TX_FIFOS; j++) {
  5348. mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
  5349. (sp->bar1 + (j * 0x00020000));
  5350. }
  5351. /* Driver entry points */
  5352. dev->open = &s2io_open;
  5353. dev->stop = &s2io_close;
  5354. dev->hard_start_xmit = &s2io_xmit;
  5355. dev->get_stats = &s2io_get_stats;
  5356. dev->set_multicast_list = &s2io_set_multicast;
  5357. dev->do_ioctl = &s2io_ioctl;
  5358. dev->change_mtu = &s2io_change_mtu;
  5359. SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
  5360. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  5361. dev->vlan_rx_register = s2io_vlan_rx_register;
  5362. dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
  5363. /*
  5364. * will use eth_mac_addr() for dev->set_mac_address
  5365. * mac address will be set every time dev->open() is called
  5366. */
  5367. #if defined(CONFIG_S2IO_NAPI)
  5368. dev->poll = s2io_poll;
  5369. dev->weight = 32;
  5370. #endif
  5371. dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  5372. if (sp->high_dma_flag == TRUE)
  5373. dev->features |= NETIF_F_HIGHDMA;
  5374. #ifdef NETIF_F_TSO
  5375. dev->features |= NETIF_F_TSO;
  5376. #endif
  5377. dev->tx_timeout = &s2io_tx_watchdog;
  5378. dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
  5379. INIT_WORK(&sp->rst_timer_task,
  5380. (void (*)(void *)) s2io_restart_nic, dev);
  5381. INIT_WORK(&sp->set_link_task,
  5382. (void (*)(void *)) s2io_set_link, sp);
  5383. pci_save_state(sp->pdev);
  5384. /* Setting swapper control on the NIC, for proper reset operation */
  5385. if (s2io_set_swapper(sp)) {
  5386. DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
  5387. dev->name);
  5388. ret = -EAGAIN;
  5389. goto set_swap_failed;
  5390. }
  5391. /* Verify if the Herc works on the slot its placed into */
  5392. if (sp->device_type & XFRAME_II_DEVICE) {
  5393. mode = s2io_verify_pci_mode(sp);
  5394. if (mode < 0) {
  5395. DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
  5396. DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
  5397. ret = -EBADSLT;
  5398. goto set_swap_failed;
  5399. }
  5400. }
  5401. /* Not needed for Herc */
  5402. if (sp->device_type & XFRAME_I_DEVICE) {
  5403. /*
  5404. * Fix for all "FFs" MAC address problems observed on
  5405. * Alpha platforms
  5406. */
  5407. fix_mac_address(sp);
  5408. s2io_reset(sp);
  5409. }
  5410. /*
  5411. * MAC address initialization.
  5412. * For now only one mac address will be read and used.
  5413. */
  5414. bar0 = sp->bar0;
  5415. val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  5416. RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
  5417. writeq(val64, &bar0->rmac_addr_cmd_mem);
  5418. wait_for_cmd_complete(sp);
  5419. tmp64 = readq(&bar0->rmac_addr_data0_mem);
  5420. mac_down = (u32) tmp64;
  5421. mac_up = (u32) (tmp64 >> 32);
  5422. memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
  5423. sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
  5424. sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
  5425. sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
  5426. sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
  5427. sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
  5428. sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
  5429. /* Set the factory defined MAC address initially */
  5430. dev->addr_len = ETH_ALEN;
  5431. memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
  5432. /*
  5433. * Initialize the tasklet status and link state flags
  5434. * and the card state parameter
  5435. */
  5436. atomic_set(&(sp->card_state), 0);
  5437. sp->tasklet_status = 0;
  5438. sp->link_state = 0;
  5439. /* Initialize spinlocks */
  5440. spin_lock_init(&sp->tx_lock);
  5441. #ifndef CONFIG_S2IO_NAPI
  5442. spin_lock_init(&sp->put_lock);
  5443. #endif
  5444. spin_lock_init(&sp->rx_lock);
  5445. /*
  5446. * SXE-002: Configure link and activity LED to init state
  5447. * on driver load.
  5448. */
  5449. subid = sp->pdev->subsystem_device;
  5450. if ((subid & 0xFF) >= 0x07) {
  5451. val64 = readq(&bar0->gpio_control);
  5452. val64 |= 0x0000800000000000ULL;
  5453. writeq(val64, &bar0->gpio_control);
  5454. val64 = 0x0411040400000000ULL;
  5455. writeq(val64, (void __iomem *) bar0 + 0x2700);
  5456. val64 = readq(&bar0->gpio_control);
  5457. }
  5458. sp->rx_csum = 1; /* Rx chksum verify enabled by default */
  5459. if (register_netdev(dev)) {
  5460. DBG_PRINT(ERR_DBG, "Device registration failed\n");
  5461. ret = -ENODEV;
  5462. goto register_failed;
  5463. }
  5464. if (sp->device_type & XFRAME_II_DEVICE) {
  5465. DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
  5466. dev->name);
  5467. DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
  5468. get_xena_rev_id(sp->pdev),
  5469. s2io_driver_version);
  5470. #ifdef CONFIG_2BUFF_MODE
  5471. DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
  5472. #endif
  5473. switch(sp->intr_type) {
  5474. case INTA:
  5475. DBG_PRINT(ERR_DBG, ", Intr type INTA");
  5476. break;
  5477. case MSI:
  5478. DBG_PRINT(ERR_DBG, ", Intr type MSI");
  5479. break;
  5480. case MSI_X:
  5481. DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
  5482. break;
  5483. }
  5484. DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
  5485. DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
  5486. sp->def_mac_addr[0].mac_addr[0],
  5487. sp->def_mac_addr[0].mac_addr[1],
  5488. sp->def_mac_addr[0].mac_addr[2],
  5489. sp->def_mac_addr[0].mac_addr[3],
  5490. sp->def_mac_addr[0].mac_addr[4],
  5491. sp->def_mac_addr[0].mac_addr[5]);
  5492. mode = s2io_print_pci_mode(sp);
  5493. if (mode < 0) {
  5494. DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
  5495. ret = -EBADSLT;
  5496. goto set_swap_failed;
  5497. }
  5498. } else {
  5499. DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
  5500. dev->name);
  5501. DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
  5502. get_xena_rev_id(sp->pdev),
  5503. s2io_driver_version);
  5504. #ifdef CONFIG_2BUFF_MODE
  5505. DBG_PRINT(ERR_DBG, ", Buffer mode %d",2);
  5506. #endif
  5507. switch(sp->intr_type) {
  5508. case INTA:
  5509. DBG_PRINT(ERR_DBG, ", Intr type INTA");
  5510. break;
  5511. case MSI:
  5512. DBG_PRINT(ERR_DBG, ", Intr type MSI");
  5513. break;
  5514. case MSI_X:
  5515. DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
  5516. break;
  5517. }
  5518. DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
  5519. DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
  5520. sp->def_mac_addr[0].mac_addr[0],
  5521. sp->def_mac_addr[0].mac_addr[1],
  5522. sp->def_mac_addr[0].mac_addr[2],
  5523. sp->def_mac_addr[0].mac_addr[3],
  5524. sp->def_mac_addr[0].mac_addr[4],
  5525. sp->def_mac_addr[0].mac_addr[5]);
  5526. }
  5527. /* Initialize device name */
  5528. strcpy(sp->name, dev->name);
  5529. if (sp->device_type & XFRAME_II_DEVICE)
  5530. strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
  5531. else
  5532. strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
  5533. /* Initialize bimodal Interrupts */
  5534. sp->config.bimodal = bimodal;
  5535. if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
  5536. sp->config.bimodal = 0;
  5537. DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
  5538. dev->name);
  5539. }
  5540. /*
  5541. * Make Link state as off at this point, when the Link change
  5542. * interrupt comes the state will be automatically changed to
  5543. * the right state.
  5544. */
  5545. netif_carrier_off(dev);
  5546. return 0;
  5547. register_failed:
  5548. set_swap_failed:
  5549. iounmap(sp->bar1);
  5550. bar1_remap_failed:
  5551. iounmap(sp->bar0);
  5552. bar0_remap_failed:
  5553. mem_alloc_failed:
  5554. free_shared_mem(sp);
  5555. pci_disable_device(pdev);
  5556. if (dev_intr_type != MSI_X)
  5557. pci_release_regions(pdev);
  5558. else {
  5559. release_mem_region(pci_resource_start(pdev, 0),
  5560. pci_resource_len(pdev, 0));
  5561. release_mem_region(pci_resource_start(pdev, 2),
  5562. pci_resource_len(pdev, 2));
  5563. }
  5564. pci_set_drvdata(pdev, NULL);
  5565. free_netdev(dev);
  5566. return ret;
  5567. }
  5568. /**
  5569. * s2io_rem_nic - Free the PCI device
  5570. * @pdev: structure containing the PCI related information of the device.
  5571. * Description: This function is called by the Pci subsystem to release a
  5572. * PCI device and free up all resource held up by the device. This could
  5573. * be in response to a Hot plug event or when the driver is to be removed
  5574. * from memory.
  5575. */
  5576. static void __devexit s2io_rem_nic(struct pci_dev *pdev)
  5577. {
  5578. struct net_device *dev =
  5579. (struct net_device *) pci_get_drvdata(pdev);
  5580. nic_t *sp;
  5581. if (dev == NULL) {
  5582. DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
  5583. return;
  5584. }
  5585. sp = dev->priv;
  5586. unregister_netdev(dev);
  5587. free_shared_mem(sp);
  5588. iounmap(sp->bar0);
  5589. iounmap(sp->bar1);
  5590. pci_disable_device(pdev);
  5591. if (sp->intr_type != MSI_X)
  5592. pci_release_regions(pdev);
  5593. else {
  5594. release_mem_region(pci_resource_start(pdev, 0),
  5595. pci_resource_len(pdev, 0));
  5596. release_mem_region(pci_resource_start(pdev, 2),
  5597. pci_resource_len(pdev, 2));
  5598. }
  5599. pci_set_drvdata(pdev, NULL);
  5600. free_netdev(dev);
  5601. }
  5602. /**
  5603. * s2io_starter - Entry point for the driver
  5604. * Description: This function is the entry point for the driver. It verifies
  5605. * the module loadable parameters and initializes PCI configuration space.
  5606. */
  5607. int __init s2io_starter(void)
  5608. {
  5609. return pci_module_init(&s2io_driver);
  5610. }
  5611. /**
  5612. * s2io_closer - Cleanup routine for the driver
  5613. * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
  5614. */
  5615. void s2io_closer(void)
  5616. {
  5617. pci_unregister_driver(&s2io_driver);
  5618. DBG_PRINT(INIT_DBG, "cleanup done\n");
  5619. }
  5620. module_init(s2io_starter);
  5621. module_exit(s2io_closer);