s3c2410_wdt.c 13 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@redhat.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. * Changelog:
  26. * 05-Oct-2004 BJD Added semaphore init to stop crashes on open
  27. * Fixed tmr_count / wdt_count confusion
  28. * Added configurable debug
  29. *
  30. * 11-Jan-2005 BJD Fixed divide-by-2 in timeout code
  31. *
  32. * 25-Jan-2005 DA Added suspend/resume support
  33. * Replaced reboot notifier with .shutdown method
  34. *
  35. * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
  36. */
  37. #include <linux/module.h>
  38. #include <linux/moduleparam.h>
  39. #include <linux/types.h>
  40. #include <linux/timer.h>
  41. #include <linux/miscdevice.h>
  42. #include <linux/watchdog.h>
  43. #include <linux/fs.h>
  44. #include <linux/init.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/clk.h>
  48. #include <linux/uaccess.h>
  49. #include <linux/io.h>
  50. #include <mach/map.h>
  51. #undef S3C_VA_WATCHDOG
  52. #define S3C_VA_WATCHDOG (0)
  53. #include <asm/plat-s3c/regs-watchdog.h>
  54. #define PFX "s3c2410-wdt: "
  55. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  56. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  57. static int nowayout = WATCHDOG_NOWAYOUT;
  58. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  59. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  60. static int soft_noboot;
  61. static int debug;
  62. module_param(tmr_margin, int, 0);
  63. module_param(tmr_atboot, int, 0);
  64. module_param(nowayout, int, 0);
  65. module_param(soft_noboot, int, 0);
  66. module_param(debug, int, 0);
  67. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
  68. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  69. MODULE_PARM_DESC(tmr_atboot,
  70. "Watchdog is started at boot time if set to 1, default="
  71. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  72. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  73. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  74. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default depends on ONLY_TESTING)");
  75. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
  76. typedef enum close_state {
  77. CLOSE_STATE_NOT,
  78. CLOSE_STATE_ALLOW = 0x4021
  79. } close_state_t;
  80. static unsigned long open_lock;
  81. static struct device *wdt_dev; /* platform device attached to */
  82. static struct resource *wdt_mem;
  83. static struct resource *wdt_irq;
  84. static struct clk *wdt_clock;
  85. static void __iomem *wdt_base;
  86. static unsigned int wdt_count;
  87. static close_state_t allow_close;
  88. static DEFINE_SPINLOCK(wdt_lock);
  89. /* watchdog control routines */
  90. #define DBG(msg...) do { \
  91. if (debug) \
  92. printk(KERN_INFO msg); \
  93. } while (0)
  94. /* functions */
  95. static void s3c2410wdt_keepalive(void)
  96. {
  97. spin_lock(&wdt_lock);
  98. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  99. spin_unlock(&wdt_lock);
  100. }
  101. static void __s3c2410wdt_stop(void)
  102. {
  103. unsigned long wtcon;
  104. wtcon = readl(wdt_base + S3C2410_WTCON);
  105. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  106. writel(wtcon, wdt_base + S3C2410_WTCON);
  107. }
  108. static void s3c2410wdt_stop(void)
  109. {
  110. spin_lock(&wdt_lock);
  111. __s3c2410wdt_stop();
  112. spin_unlock(&wdt_lock);
  113. }
  114. static void s3c2410wdt_start(void)
  115. {
  116. unsigned long wtcon;
  117. spin_lock(&wdt_lock);
  118. __s3c2410wdt_stop();
  119. wtcon = readl(wdt_base + S3C2410_WTCON);
  120. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  121. if (soft_noboot) {
  122. wtcon |= S3C2410_WTCON_INTEN;
  123. wtcon &= ~S3C2410_WTCON_RSTEN;
  124. } else {
  125. wtcon &= ~S3C2410_WTCON_INTEN;
  126. wtcon |= S3C2410_WTCON_RSTEN;
  127. }
  128. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  129. __func__, wdt_count, wtcon);
  130. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  131. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  132. writel(wtcon, wdt_base + S3C2410_WTCON);
  133. spin_unlock(&wdt_lock);
  134. }
  135. static int s3c2410wdt_set_heartbeat(int timeout)
  136. {
  137. unsigned int freq = clk_get_rate(wdt_clock);
  138. unsigned int count;
  139. unsigned int divisor = 1;
  140. unsigned long wtcon;
  141. if (timeout < 1)
  142. return -EINVAL;
  143. freq /= 128;
  144. count = timeout * freq;
  145. DBG("%s: count=%d, timeout=%d, freq=%d\n",
  146. __func__, count, timeout, freq);
  147. /* if the count is bigger than the watchdog register,
  148. then work out what we need to do (and if) we can
  149. actually make this value
  150. */
  151. if (count >= 0x10000) {
  152. for (divisor = 1; divisor <= 0x100; divisor++) {
  153. if ((count / divisor) < 0x10000)
  154. break;
  155. }
  156. if ((count / divisor) >= 0x10000) {
  157. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  158. return -EINVAL;
  159. }
  160. }
  161. tmr_margin = timeout;
  162. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  163. __func__, timeout, divisor, count, count/divisor);
  164. count /= divisor;
  165. wdt_count = count;
  166. /* update the pre-scaler */
  167. wtcon = readl(wdt_base + S3C2410_WTCON);
  168. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  169. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  170. writel(count, wdt_base + S3C2410_WTDAT);
  171. writel(wtcon, wdt_base + S3C2410_WTCON);
  172. return 0;
  173. }
  174. /*
  175. * /dev/watchdog handling
  176. */
  177. static int s3c2410wdt_open(struct inode *inode, struct file *file)
  178. {
  179. if (test_and_set_bit(0, &open_lock))
  180. return -EBUSY;
  181. if (nowayout)
  182. __module_get(THIS_MODULE);
  183. allow_close = CLOSE_STATE_NOT;
  184. /* start the timer */
  185. s3c2410wdt_start();
  186. return nonseekable_open(inode, file);
  187. }
  188. static int s3c2410wdt_release(struct inode *inode, struct file *file)
  189. {
  190. /*
  191. * Shut off the timer.
  192. * Lock it in if it's a module and we set nowayout
  193. */
  194. if (allow_close == CLOSE_STATE_ALLOW)
  195. s3c2410wdt_stop();
  196. else {
  197. dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
  198. s3c2410wdt_keepalive();
  199. }
  200. allow_close = CLOSE_STATE_NOT;
  201. clear_bit(0, &open_lock);
  202. return 0;
  203. }
  204. static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
  205. size_t len, loff_t *ppos)
  206. {
  207. /*
  208. * Refresh the timer.
  209. */
  210. if (len) {
  211. if (!nowayout) {
  212. size_t i;
  213. /* In case it was set long ago */
  214. allow_close = CLOSE_STATE_NOT;
  215. for (i = 0; i != len; i++) {
  216. char c;
  217. if (get_user(c, data + i))
  218. return -EFAULT;
  219. if (c == 'V')
  220. allow_close = CLOSE_STATE_ALLOW;
  221. }
  222. }
  223. s3c2410wdt_keepalive();
  224. }
  225. return len;
  226. }
  227. #define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE
  228. static const struct watchdog_info s3c2410_wdt_ident = {
  229. .options = OPTIONS,
  230. .firmware_version = 0,
  231. .identity = "S3C2410 Watchdog",
  232. };
  233. static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
  234. unsigned long arg)
  235. {
  236. void __user *argp = (void __user *)arg;
  237. int __user *p = argp;
  238. int new_margin;
  239. switch (cmd) {
  240. case WDIOC_GETSUPPORT:
  241. return copy_to_user(argp, &s3c2410_wdt_ident,
  242. sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
  243. case WDIOC_GETSTATUS:
  244. case WDIOC_GETBOOTSTATUS:
  245. return put_user(0, p);
  246. case WDIOC_KEEPALIVE:
  247. s3c2410wdt_keepalive();
  248. return 0;
  249. case WDIOC_SETTIMEOUT:
  250. if (get_user(new_margin, p))
  251. return -EFAULT;
  252. if (s3c2410wdt_set_heartbeat(new_margin))
  253. return -EINVAL;
  254. s3c2410wdt_keepalive();
  255. return put_user(tmr_margin, p);
  256. case WDIOC_GETTIMEOUT:
  257. return put_user(tmr_margin, p);
  258. default:
  259. return -ENOTTY;
  260. }
  261. }
  262. /* kernel interface */
  263. static const struct file_operations s3c2410wdt_fops = {
  264. .owner = THIS_MODULE,
  265. .llseek = no_llseek,
  266. .write = s3c2410wdt_write,
  267. .unlocked_ioctl = s3c2410wdt_ioctl,
  268. .open = s3c2410wdt_open,
  269. .release = s3c2410wdt_release,
  270. };
  271. static struct miscdevice s3c2410wdt_miscdev = {
  272. .minor = WATCHDOG_MINOR,
  273. .name = "watchdog",
  274. .fops = &s3c2410wdt_fops,
  275. };
  276. /* interrupt handler code */
  277. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  278. {
  279. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  280. s3c2410wdt_keepalive();
  281. return IRQ_HANDLED;
  282. }
  283. /* device interface */
  284. static int s3c2410wdt_probe(struct platform_device *pdev)
  285. {
  286. struct resource *res;
  287. struct device *dev;
  288. unsigned int wtcon;
  289. int started = 0;
  290. int ret;
  291. int size;
  292. DBG("%s: probe=%p\n", __func__, pdev);
  293. dev = &pdev->dev;
  294. wdt_dev = &pdev->dev;
  295. /* get the memory region for the watchdog timer */
  296. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  297. if (res == NULL) {
  298. dev_err(dev, "no memory resource specified\n");
  299. return -ENOENT;
  300. }
  301. size = (res->end-res->start)+1;
  302. wdt_mem = request_mem_region(res->start, size, pdev->name);
  303. if (wdt_mem == NULL) {
  304. dev_err(dev, "failed to get memory region\n");
  305. ret = -ENOENT;
  306. goto err_req;
  307. }
  308. wdt_base = ioremap(res->start, size);
  309. if (wdt_base == NULL) {
  310. dev_err(dev, "failed to ioremap() region\n");
  311. ret = -EINVAL;
  312. goto err_req;
  313. }
  314. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  315. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  316. if (wdt_irq == NULL) {
  317. dev_err(dev, "no irq resource specified\n");
  318. ret = -ENOENT;
  319. goto err_map;
  320. }
  321. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  322. if (ret != 0) {
  323. dev_err(dev, "failed to install irq (%d)\n", ret);
  324. goto err_map;
  325. }
  326. wdt_clock = clk_get(&pdev->dev, "watchdog");
  327. if (IS_ERR(wdt_clock)) {
  328. dev_err(dev, "failed to find watchdog clock source\n");
  329. ret = PTR_ERR(wdt_clock);
  330. goto err_irq;
  331. }
  332. clk_enable(wdt_clock);
  333. /* see if we can actually set the requested timer margin, and if
  334. * not, try the default value */
  335. if (s3c2410wdt_set_heartbeat(tmr_margin)) {
  336. started = s3c2410wdt_set_heartbeat(
  337. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  338. if (started == 0)
  339. dev_info(dev,
  340. "tmr_margin value out of range, default %d used\n",
  341. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  342. else
  343. dev_info(dev, "default timer value is out of range, cannot start\n");
  344. }
  345. ret = misc_register(&s3c2410wdt_miscdev);
  346. if (ret) {
  347. dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
  348. WATCHDOG_MINOR, ret);
  349. goto err_clk;
  350. }
  351. if (tmr_atboot && started == 0) {
  352. dev_info(dev, "starting watchdog timer\n");
  353. s3c2410wdt_start();
  354. } else if (!tmr_atboot) {
  355. /* if we're not enabling the watchdog, then ensure it is
  356. * disabled if it has been left running from the bootloader
  357. * or other source */
  358. s3c2410wdt_stop();
  359. }
  360. /* print out a statement of readiness */
  361. wtcon = readl(wdt_base + S3C2410_WTCON);
  362. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  363. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  364. (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
  365. (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
  366. return 0;
  367. err_clk:
  368. clk_disable(wdt_clock);
  369. clk_put(wdt_clock);
  370. err_irq:
  371. free_irq(wdt_irq->start, pdev);
  372. err_map:
  373. iounmap(wdt_base);
  374. err_req:
  375. release_resource(wdt_mem);
  376. kfree(wdt_mem);
  377. return ret;
  378. }
  379. static int s3c2410wdt_remove(struct platform_device *dev)
  380. {
  381. release_resource(wdt_mem);
  382. kfree(wdt_mem);
  383. wdt_mem = NULL;
  384. free_irq(wdt_irq->start, dev);
  385. wdt_irq = NULL;
  386. clk_disable(wdt_clock);
  387. clk_put(wdt_clock);
  388. wdt_clock = NULL;
  389. iounmap(wdt_base);
  390. misc_deregister(&s3c2410wdt_miscdev);
  391. return 0;
  392. }
  393. static void s3c2410wdt_shutdown(struct platform_device *dev)
  394. {
  395. s3c2410wdt_stop();
  396. }
  397. #ifdef CONFIG_PM
  398. static unsigned long wtcon_save;
  399. static unsigned long wtdat_save;
  400. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  401. {
  402. /* Save watchdog state, and turn it off. */
  403. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  404. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  405. /* Note that WTCNT doesn't need to be saved. */
  406. s3c2410wdt_stop();
  407. return 0;
  408. }
  409. static int s3c2410wdt_resume(struct platform_device *dev)
  410. {
  411. /* Restore watchdog state. */
  412. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  413. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  414. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  415. printk(KERN_INFO PFX "watchdog %sabled\n",
  416. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  417. return 0;
  418. }
  419. #else
  420. #define s3c2410wdt_suspend NULL
  421. #define s3c2410wdt_resume NULL
  422. #endif /* CONFIG_PM */
  423. static struct platform_driver s3c2410wdt_driver = {
  424. .probe = s3c2410wdt_probe,
  425. .remove = s3c2410wdt_remove,
  426. .shutdown = s3c2410wdt_shutdown,
  427. .suspend = s3c2410wdt_suspend,
  428. .resume = s3c2410wdt_resume,
  429. .driver = {
  430. .owner = THIS_MODULE,
  431. .name = "s3c2410-wdt",
  432. },
  433. };
  434. static char banner[] __initdata =
  435. KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  436. static int __init watchdog_init(void)
  437. {
  438. printk(banner);
  439. return platform_driver_register(&s3c2410wdt_driver);
  440. }
  441. static void __exit watchdog_exit(void)
  442. {
  443. platform_driver_unregister(&s3c2410wdt_driver);
  444. }
  445. module_init(watchdog_init);
  446. module_exit(watchdog_exit);
  447. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  448. "Dimitry Andric <dimitry.andric@tomtom.com>");
  449. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  450. MODULE_LICENSE("GPL");
  451. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  452. MODULE_ALIAS("platform:s3c2410-wdt");