main.c 27 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/ssb/ssb.h>
  14. #include <linux/ssb/ssb_regs.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/pci.h>
  17. #include <pcmcia/cs_types.h>
  18. #include <pcmcia/cs.h>
  19. #include <pcmcia/cistpl.h>
  20. #include <pcmcia/ds.h>
  21. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  22. MODULE_LICENSE("GPL");
  23. /* Temporary list of yet-to-be-attached buses */
  24. static LIST_HEAD(attach_queue);
  25. /* List if running buses */
  26. static LIST_HEAD(buses);
  27. /* Software ID counter */
  28. static unsigned int next_busnumber;
  29. /* buses_mutes locks the two buslists and the next_busnumber.
  30. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  31. static DEFINE_MUTEX(buses_mutex);
  32. /* There are differences in the codeflow, if the bus is
  33. * initialized from early boot, as various needed services
  34. * are not available early. This is a mechanism to delay
  35. * these initializations to after early boot has finished.
  36. * It's also used to avoid mutex locking, as that's not
  37. * available and needed early. */
  38. static bool ssb_is_early_boot = 1;
  39. static void ssb_buses_lock(void);
  40. static void ssb_buses_unlock(void);
  41. #ifdef CONFIG_SSB_PCIHOST
  42. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  43. {
  44. struct ssb_bus *bus;
  45. ssb_buses_lock();
  46. list_for_each_entry(bus, &buses, list) {
  47. if (bus->bustype == SSB_BUSTYPE_PCI &&
  48. bus->host_pci == pdev)
  49. goto found;
  50. }
  51. bus = NULL;
  52. found:
  53. ssb_buses_unlock();
  54. return bus;
  55. }
  56. #endif /* CONFIG_SSB_PCIHOST */
  57. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  58. {
  59. if (dev)
  60. get_device(dev->dev);
  61. return dev;
  62. }
  63. static void ssb_device_put(struct ssb_device *dev)
  64. {
  65. if (dev)
  66. put_device(dev->dev);
  67. }
  68. static int ssb_bus_resume(struct ssb_bus *bus)
  69. {
  70. int err;
  71. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  72. err = ssb_pcmcia_init(bus);
  73. if (err) {
  74. /* No need to disable XTAL, as we don't have one on PCMCIA. */
  75. return err;
  76. }
  77. ssb_chipco_resume(&bus->chipco);
  78. return 0;
  79. }
  80. static int ssb_device_resume(struct device *dev)
  81. {
  82. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  83. struct ssb_driver *ssb_drv;
  84. struct ssb_bus *bus;
  85. int err = 0;
  86. bus = ssb_dev->bus;
  87. if (bus->suspend_cnt == bus->nr_devices) {
  88. err = ssb_bus_resume(bus);
  89. if (err)
  90. return err;
  91. }
  92. bus->suspend_cnt--;
  93. if (dev->driver) {
  94. ssb_drv = drv_to_ssb_drv(dev->driver);
  95. if (ssb_drv && ssb_drv->resume)
  96. err = ssb_drv->resume(ssb_dev);
  97. if (err)
  98. goto out;
  99. }
  100. out:
  101. return err;
  102. }
  103. static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
  104. {
  105. ssb_chipco_suspend(&bus->chipco, state);
  106. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  107. /* Reset HW state information in memory, so that HW is
  108. * completely reinitialized on resume. */
  109. bus->mapped_device = NULL;
  110. #ifdef CONFIG_SSB_DRIVER_PCICORE
  111. bus->pcicore.setup_done = 0;
  112. #endif
  113. #ifdef CONFIG_SSB_DEBUG
  114. bus->powered_up = 0;
  115. #endif
  116. }
  117. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  118. {
  119. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  120. struct ssb_driver *ssb_drv;
  121. struct ssb_bus *bus;
  122. int err = 0;
  123. if (dev->driver) {
  124. ssb_drv = drv_to_ssb_drv(dev->driver);
  125. if (ssb_drv && ssb_drv->suspend)
  126. err = ssb_drv->suspend(ssb_dev, state);
  127. if (err)
  128. goto out;
  129. }
  130. bus = ssb_dev->bus;
  131. bus->suspend_cnt++;
  132. if (bus->suspend_cnt == bus->nr_devices) {
  133. /* All devices suspended. Shutdown the bus. */
  134. ssb_bus_suspend(bus, state);
  135. }
  136. out:
  137. return err;
  138. }
  139. #ifdef CONFIG_SSB_PCIHOST
  140. int ssb_devices_freeze(struct ssb_bus *bus)
  141. {
  142. struct ssb_device *dev;
  143. struct ssb_driver *drv;
  144. int err = 0;
  145. int i;
  146. pm_message_t state = PMSG_FREEZE;
  147. /* First check that we are capable to freeze all devices. */
  148. for (i = 0; i < bus->nr_devices; i++) {
  149. dev = &(bus->devices[i]);
  150. if (!dev->dev ||
  151. !dev->dev->driver ||
  152. !device_is_registered(dev->dev))
  153. continue;
  154. drv = drv_to_ssb_drv(dev->dev->driver);
  155. if (!drv)
  156. continue;
  157. if (!drv->suspend) {
  158. /* Nope, can't suspend this one. */
  159. return -EOPNOTSUPP;
  160. }
  161. }
  162. /* Now suspend all devices */
  163. for (i = 0; i < bus->nr_devices; i++) {
  164. dev = &(bus->devices[i]);
  165. if (!dev->dev ||
  166. !dev->dev->driver ||
  167. !device_is_registered(dev->dev))
  168. continue;
  169. drv = drv_to_ssb_drv(dev->dev->driver);
  170. if (!drv)
  171. continue;
  172. err = drv->suspend(dev, state);
  173. if (err) {
  174. ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
  175. dev->dev->bus_id);
  176. goto err_unwind;
  177. }
  178. }
  179. return 0;
  180. err_unwind:
  181. for (i--; i >= 0; i--) {
  182. dev = &(bus->devices[i]);
  183. if (!dev->dev ||
  184. !dev->dev->driver ||
  185. !device_is_registered(dev->dev))
  186. continue;
  187. drv = drv_to_ssb_drv(dev->dev->driver);
  188. if (!drv)
  189. continue;
  190. if (drv->resume)
  191. drv->resume(dev);
  192. }
  193. return err;
  194. }
  195. int ssb_devices_thaw(struct ssb_bus *bus)
  196. {
  197. struct ssb_device *dev;
  198. struct ssb_driver *drv;
  199. int err;
  200. int i;
  201. for (i = 0; i < bus->nr_devices; i++) {
  202. dev = &(bus->devices[i]);
  203. if (!dev->dev ||
  204. !dev->dev->driver ||
  205. !device_is_registered(dev->dev))
  206. continue;
  207. drv = drv_to_ssb_drv(dev->dev->driver);
  208. if (!drv)
  209. continue;
  210. if (SSB_WARN_ON(!drv->resume))
  211. continue;
  212. err = drv->resume(dev);
  213. if (err) {
  214. ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
  215. dev->dev->bus_id);
  216. }
  217. }
  218. return 0;
  219. }
  220. #endif /* CONFIG_SSB_PCIHOST */
  221. static void ssb_device_shutdown(struct device *dev)
  222. {
  223. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  224. struct ssb_driver *ssb_drv;
  225. if (!dev->driver)
  226. return;
  227. ssb_drv = drv_to_ssb_drv(dev->driver);
  228. if (ssb_drv && ssb_drv->shutdown)
  229. ssb_drv->shutdown(ssb_dev);
  230. }
  231. static int ssb_device_remove(struct device *dev)
  232. {
  233. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  234. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  235. if (ssb_drv && ssb_drv->remove)
  236. ssb_drv->remove(ssb_dev);
  237. ssb_device_put(ssb_dev);
  238. return 0;
  239. }
  240. static int ssb_device_probe(struct device *dev)
  241. {
  242. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  243. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  244. int err = 0;
  245. ssb_device_get(ssb_dev);
  246. if (ssb_drv && ssb_drv->probe)
  247. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  248. if (err)
  249. ssb_device_put(ssb_dev);
  250. return err;
  251. }
  252. static int ssb_match_devid(const struct ssb_device_id *tabid,
  253. const struct ssb_device_id *devid)
  254. {
  255. if ((tabid->vendor != devid->vendor) &&
  256. tabid->vendor != SSB_ANY_VENDOR)
  257. return 0;
  258. if ((tabid->coreid != devid->coreid) &&
  259. tabid->coreid != SSB_ANY_ID)
  260. return 0;
  261. if ((tabid->revision != devid->revision) &&
  262. tabid->revision != SSB_ANY_REV)
  263. return 0;
  264. return 1;
  265. }
  266. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  267. {
  268. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  269. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  270. const struct ssb_device_id *id;
  271. for (id = ssb_drv->id_table;
  272. id->vendor || id->coreid || id->revision;
  273. id++) {
  274. if (ssb_match_devid(id, &ssb_dev->id))
  275. return 1; /* found */
  276. }
  277. return 0;
  278. }
  279. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  280. {
  281. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  282. if (!dev)
  283. return -ENODEV;
  284. return add_uevent_var(env,
  285. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  286. ssb_dev->id.vendor, ssb_dev->id.coreid,
  287. ssb_dev->id.revision);
  288. }
  289. static struct bus_type ssb_bustype = {
  290. .name = "ssb",
  291. .match = ssb_bus_match,
  292. .probe = ssb_device_probe,
  293. .remove = ssb_device_remove,
  294. .shutdown = ssb_device_shutdown,
  295. .suspend = ssb_device_suspend,
  296. .resume = ssb_device_resume,
  297. .uevent = ssb_device_uevent,
  298. };
  299. static void ssb_buses_lock(void)
  300. {
  301. /* See the comment at the ssb_is_early_boot definition */
  302. if (!ssb_is_early_boot)
  303. mutex_lock(&buses_mutex);
  304. }
  305. static void ssb_buses_unlock(void)
  306. {
  307. /* See the comment at the ssb_is_early_boot definition */
  308. if (!ssb_is_early_boot)
  309. mutex_unlock(&buses_mutex);
  310. }
  311. static void ssb_devices_unregister(struct ssb_bus *bus)
  312. {
  313. struct ssb_device *sdev;
  314. int i;
  315. for (i = bus->nr_devices - 1; i >= 0; i--) {
  316. sdev = &(bus->devices[i]);
  317. if (sdev->dev)
  318. device_unregister(sdev->dev);
  319. }
  320. }
  321. void ssb_bus_unregister(struct ssb_bus *bus)
  322. {
  323. ssb_buses_lock();
  324. ssb_devices_unregister(bus);
  325. list_del(&bus->list);
  326. ssb_buses_unlock();
  327. /* ssb_pcmcia_exit(bus); */
  328. ssb_pci_exit(bus);
  329. ssb_iounmap(bus);
  330. }
  331. EXPORT_SYMBOL(ssb_bus_unregister);
  332. static void ssb_release_dev(struct device *dev)
  333. {
  334. struct __ssb_dev_wrapper *devwrap;
  335. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  336. kfree(devwrap);
  337. }
  338. static int ssb_devices_register(struct ssb_bus *bus)
  339. {
  340. struct ssb_device *sdev;
  341. struct device *dev;
  342. struct __ssb_dev_wrapper *devwrap;
  343. int i, err = 0;
  344. int dev_idx = 0;
  345. for (i = 0; i < bus->nr_devices; i++) {
  346. sdev = &(bus->devices[i]);
  347. /* We don't register SSB-system devices to the kernel,
  348. * as the drivers for them are built into SSB. */
  349. switch (sdev->id.coreid) {
  350. case SSB_DEV_CHIPCOMMON:
  351. case SSB_DEV_PCI:
  352. case SSB_DEV_PCIE:
  353. case SSB_DEV_PCMCIA:
  354. case SSB_DEV_MIPS:
  355. case SSB_DEV_MIPS_3302:
  356. case SSB_DEV_EXTIF:
  357. continue;
  358. }
  359. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  360. if (!devwrap) {
  361. ssb_printk(KERN_ERR PFX
  362. "Could not allocate device\n");
  363. err = -ENOMEM;
  364. goto error;
  365. }
  366. dev = &devwrap->dev;
  367. devwrap->sdev = sdev;
  368. dev->release = ssb_release_dev;
  369. dev->bus = &ssb_bustype;
  370. snprintf(dev->bus_id, sizeof(dev->bus_id),
  371. "ssb%u:%d", bus->busnumber, dev_idx);
  372. switch (bus->bustype) {
  373. case SSB_BUSTYPE_PCI:
  374. #ifdef CONFIG_SSB_PCIHOST
  375. sdev->irq = bus->host_pci->irq;
  376. dev->parent = &bus->host_pci->dev;
  377. #endif
  378. break;
  379. case SSB_BUSTYPE_PCMCIA:
  380. #ifdef CONFIG_SSB_PCMCIAHOST
  381. sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
  382. dev->parent = &bus->host_pcmcia->dev;
  383. #endif
  384. break;
  385. case SSB_BUSTYPE_SSB:
  386. break;
  387. }
  388. sdev->dev = dev;
  389. err = device_register(dev);
  390. if (err) {
  391. ssb_printk(KERN_ERR PFX
  392. "Could not register %s\n",
  393. dev->bus_id);
  394. /* Set dev to NULL to not unregister
  395. * dev on error unwinding. */
  396. sdev->dev = NULL;
  397. kfree(devwrap);
  398. goto error;
  399. }
  400. dev_idx++;
  401. }
  402. return 0;
  403. error:
  404. /* Unwind the already registered devices. */
  405. ssb_devices_unregister(bus);
  406. return err;
  407. }
  408. /* Needs ssb_buses_lock() */
  409. static int ssb_attach_queued_buses(void)
  410. {
  411. struct ssb_bus *bus, *n;
  412. int err = 0;
  413. int drop_them_all = 0;
  414. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  415. if (drop_them_all) {
  416. list_del(&bus->list);
  417. continue;
  418. }
  419. /* Can't init the PCIcore in ssb_bus_register(), as that
  420. * is too early in boot for embedded systems
  421. * (no udelay() available). So do it here in attach stage.
  422. */
  423. err = ssb_bus_powerup(bus, 0);
  424. if (err)
  425. goto error;
  426. ssb_pcicore_init(&bus->pcicore);
  427. ssb_bus_may_powerdown(bus);
  428. err = ssb_devices_register(bus);
  429. error:
  430. if (err) {
  431. drop_them_all = 1;
  432. list_del(&bus->list);
  433. continue;
  434. }
  435. list_move_tail(&bus->list, &buses);
  436. }
  437. return err;
  438. }
  439. static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
  440. {
  441. struct ssb_bus *bus = dev->bus;
  442. offset += dev->core_index * SSB_CORE_SIZE;
  443. return readw(bus->mmio + offset);
  444. }
  445. static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
  446. {
  447. struct ssb_bus *bus = dev->bus;
  448. offset += dev->core_index * SSB_CORE_SIZE;
  449. return readl(bus->mmio + offset);
  450. }
  451. static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  452. {
  453. struct ssb_bus *bus = dev->bus;
  454. offset += dev->core_index * SSB_CORE_SIZE;
  455. writew(value, bus->mmio + offset);
  456. }
  457. static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  458. {
  459. struct ssb_bus *bus = dev->bus;
  460. offset += dev->core_index * SSB_CORE_SIZE;
  461. writel(value, bus->mmio + offset);
  462. }
  463. /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
  464. static const struct ssb_bus_ops ssb_ssb_ops = {
  465. .read16 = ssb_ssb_read16,
  466. .read32 = ssb_ssb_read32,
  467. .write16 = ssb_ssb_write16,
  468. .write32 = ssb_ssb_write32,
  469. };
  470. static int ssb_fetch_invariants(struct ssb_bus *bus,
  471. ssb_invariants_func_t get_invariants)
  472. {
  473. struct ssb_init_invariants iv;
  474. int err;
  475. memset(&iv, 0, sizeof(iv));
  476. err = get_invariants(bus, &iv);
  477. if (err)
  478. goto out;
  479. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  480. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  481. bus->has_cardbus_slot = iv.has_cardbus_slot;
  482. out:
  483. return err;
  484. }
  485. static int ssb_bus_register(struct ssb_bus *bus,
  486. ssb_invariants_func_t get_invariants,
  487. unsigned long baseaddr)
  488. {
  489. int err;
  490. spin_lock_init(&bus->bar_lock);
  491. INIT_LIST_HEAD(&bus->list);
  492. #ifdef CONFIG_SSB_EMBEDDED
  493. spin_lock_init(&bus->gpio_lock);
  494. #endif
  495. /* Powerup the bus */
  496. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  497. if (err)
  498. goto out;
  499. ssb_buses_lock();
  500. bus->busnumber = next_busnumber;
  501. /* Scan for devices (cores) */
  502. err = ssb_bus_scan(bus, baseaddr);
  503. if (err)
  504. goto err_disable_xtal;
  505. /* Init PCI-host device (if any) */
  506. err = ssb_pci_init(bus);
  507. if (err)
  508. goto err_unmap;
  509. /* Init PCMCIA-host device (if any) */
  510. err = ssb_pcmcia_init(bus);
  511. if (err)
  512. goto err_pci_exit;
  513. /* Initialize basic system devices (if available) */
  514. err = ssb_bus_powerup(bus, 0);
  515. if (err)
  516. goto err_pcmcia_exit;
  517. ssb_chipcommon_init(&bus->chipco);
  518. ssb_mipscore_init(&bus->mipscore);
  519. err = ssb_fetch_invariants(bus, get_invariants);
  520. if (err) {
  521. ssb_bus_may_powerdown(bus);
  522. goto err_pcmcia_exit;
  523. }
  524. ssb_bus_may_powerdown(bus);
  525. /* Queue it for attach.
  526. * See the comment at the ssb_is_early_boot definition. */
  527. list_add_tail(&bus->list, &attach_queue);
  528. if (!ssb_is_early_boot) {
  529. /* This is not early boot, so we must attach the bus now */
  530. err = ssb_attach_queued_buses();
  531. if (err)
  532. goto err_dequeue;
  533. }
  534. next_busnumber++;
  535. ssb_buses_unlock();
  536. out:
  537. return err;
  538. err_dequeue:
  539. list_del(&bus->list);
  540. err_pcmcia_exit:
  541. /* ssb_pcmcia_exit(bus); */
  542. err_pci_exit:
  543. ssb_pci_exit(bus);
  544. err_unmap:
  545. ssb_iounmap(bus);
  546. err_disable_xtal:
  547. ssb_buses_unlock();
  548. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  549. return err;
  550. }
  551. #ifdef CONFIG_SSB_PCIHOST
  552. int ssb_bus_pcibus_register(struct ssb_bus *bus,
  553. struct pci_dev *host_pci)
  554. {
  555. int err;
  556. bus->bustype = SSB_BUSTYPE_PCI;
  557. bus->host_pci = host_pci;
  558. bus->ops = &ssb_pci_ops;
  559. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  560. if (!err) {
  561. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  562. "PCI device %s\n", host_pci->dev.bus_id);
  563. }
  564. return err;
  565. }
  566. EXPORT_SYMBOL(ssb_bus_pcibus_register);
  567. #endif /* CONFIG_SSB_PCIHOST */
  568. #ifdef CONFIG_SSB_PCMCIAHOST
  569. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  570. struct pcmcia_device *pcmcia_dev,
  571. unsigned long baseaddr)
  572. {
  573. int err;
  574. bus->bustype = SSB_BUSTYPE_PCMCIA;
  575. bus->host_pcmcia = pcmcia_dev;
  576. bus->ops = &ssb_pcmcia_ops;
  577. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  578. if (!err) {
  579. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  580. "PCMCIA device %s\n", pcmcia_dev->devname);
  581. }
  582. return err;
  583. }
  584. EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
  585. #endif /* CONFIG_SSB_PCMCIAHOST */
  586. int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  587. unsigned long baseaddr,
  588. ssb_invariants_func_t get_invariants)
  589. {
  590. int err;
  591. bus->bustype = SSB_BUSTYPE_SSB;
  592. bus->ops = &ssb_ssb_ops;
  593. err = ssb_bus_register(bus, get_invariants, baseaddr);
  594. if (!err) {
  595. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
  596. "address 0x%08lX\n", baseaddr);
  597. }
  598. return err;
  599. }
  600. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  601. {
  602. drv->drv.name = drv->name;
  603. drv->drv.bus = &ssb_bustype;
  604. drv->drv.owner = owner;
  605. return driver_register(&drv->drv);
  606. }
  607. EXPORT_SYMBOL(__ssb_driver_register);
  608. void ssb_driver_unregister(struct ssb_driver *drv)
  609. {
  610. driver_unregister(&drv->drv);
  611. }
  612. EXPORT_SYMBOL(ssb_driver_unregister);
  613. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  614. {
  615. struct ssb_bus *bus = dev->bus;
  616. struct ssb_device *ent;
  617. int i;
  618. for (i = 0; i < bus->nr_devices; i++) {
  619. ent = &(bus->devices[i]);
  620. if (ent->id.vendor != dev->id.vendor)
  621. continue;
  622. if (ent->id.coreid != dev->id.coreid)
  623. continue;
  624. ent->devtypedata = data;
  625. }
  626. }
  627. EXPORT_SYMBOL(ssb_set_devtypedata);
  628. static u32 clkfactor_f6_resolve(u32 v)
  629. {
  630. /* map the magic values */
  631. switch (v) {
  632. case SSB_CHIPCO_CLK_F6_2:
  633. return 2;
  634. case SSB_CHIPCO_CLK_F6_3:
  635. return 3;
  636. case SSB_CHIPCO_CLK_F6_4:
  637. return 4;
  638. case SSB_CHIPCO_CLK_F6_5:
  639. return 5;
  640. case SSB_CHIPCO_CLK_F6_6:
  641. return 6;
  642. case SSB_CHIPCO_CLK_F6_7:
  643. return 7;
  644. }
  645. return 0;
  646. }
  647. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  648. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  649. {
  650. u32 n1, n2, clock, m1, m2, m3, mc;
  651. n1 = (n & SSB_CHIPCO_CLK_N1);
  652. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  653. switch (plltype) {
  654. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  655. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  656. return SSB_CHIPCO_CLK_T6_M0;
  657. return SSB_CHIPCO_CLK_T6_M1;
  658. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  659. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  660. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  661. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  662. n1 = clkfactor_f6_resolve(n1);
  663. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  664. break;
  665. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  666. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  667. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  668. SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  669. SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  670. break;
  671. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  672. return 100000000;
  673. default:
  674. SSB_WARN_ON(1);
  675. }
  676. switch (plltype) {
  677. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  678. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  679. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  680. break;
  681. default:
  682. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  683. }
  684. if (!clock)
  685. return 0;
  686. m1 = (m & SSB_CHIPCO_CLK_M1);
  687. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  688. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  689. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  690. switch (plltype) {
  691. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  692. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  693. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  694. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  695. m1 = clkfactor_f6_resolve(m1);
  696. if ((plltype == SSB_PLLTYPE_1) ||
  697. (plltype == SSB_PLLTYPE_3))
  698. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  699. else
  700. m2 = clkfactor_f6_resolve(m2);
  701. m3 = clkfactor_f6_resolve(m3);
  702. switch (mc) {
  703. case SSB_CHIPCO_CLK_MC_BYPASS:
  704. return clock;
  705. case SSB_CHIPCO_CLK_MC_M1:
  706. return (clock / m1);
  707. case SSB_CHIPCO_CLK_MC_M1M2:
  708. return (clock / (m1 * m2));
  709. case SSB_CHIPCO_CLK_MC_M1M2M3:
  710. return (clock / (m1 * m2 * m3));
  711. case SSB_CHIPCO_CLK_MC_M1M3:
  712. return (clock / (m1 * m3));
  713. }
  714. return 0;
  715. case SSB_PLLTYPE_2:
  716. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  717. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  718. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  719. SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  720. SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  721. SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  722. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  723. clock /= m1;
  724. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  725. clock /= m2;
  726. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  727. clock /= m3;
  728. return clock;
  729. default:
  730. SSB_WARN_ON(1);
  731. }
  732. return 0;
  733. }
  734. /* Get the current speed the backplane is running at */
  735. u32 ssb_clockspeed(struct ssb_bus *bus)
  736. {
  737. u32 rate;
  738. u32 plltype;
  739. u32 clkctl_n, clkctl_m;
  740. if (ssb_extif_available(&bus->extif))
  741. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  742. &clkctl_n, &clkctl_m);
  743. else if (bus->chipco.dev)
  744. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  745. &clkctl_n, &clkctl_m);
  746. else
  747. return 0;
  748. if (bus->chip_id == 0x5365) {
  749. rate = 100000000;
  750. } else {
  751. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  752. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  753. rate /= 2;
  754. }
  755. return rate;
  756. }
  757. EXPORT_SYMBOL(ssb_clockspeed);
  758. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  759. {
  760. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  761. /* The REJECT bit changed position in TMSLOW between
  762. * Backplane revisions. */
  763. switch (rev) {
  764. case SSB_IDLOW_SSBREV_22:
  765. return SSB_TMSLOW_REJECT_22;
  766. case SSB_IDLOW_SSBREV_23:
  767. return SSB_TMSLOW_REJECT_23;
  768. case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
  769. case SSB_IDLOW_SSBREV_25: /* same here */
  770. case SSB_IDLOW_SSBREV_26: /* same here */
  771. case SSB_IDLOW_SSBREV_27: /* same here */
  772. return SSB_TMSLOW_REJECT_23; /* this is a guess */
  773. default:
  774. printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  775. WARN_ON(1);
  776. }
  777. return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
  778. }
  779. int ssb_device_is_enabled(struct ssb_device *dev)
  780. {
  781. u32 val;
  782. u32 reject;
  783. reject = ssb_tmslow_reject_bitmask(dev);
  784. val = ssb_read32(dev, SSB_TMSLOW);
  785. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  786. return (val == SSB_TMSLOW_CLOCK);
  787. }
  788. EXPORT_SYMBOL(ssb_device_is_enabled);
  789. static void ssb_flush_tmslow(struct ssb_device *dev)
  790. {
  791. /* Make _really_ sure the device has finished the TMSLOW
  792. * register write transaction, as we risk running into
  793. * a machine check exception otherwise.
  794. * Do this by reading the register back to commit the
  795. * PCI write and delay an additional usec for the device
  796. * to react to the change. */
  797. ssb_read32(dev, SSB_TMSLOW);
  798. udelay(1);
  799. }
  800. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  801. {
  802. u32 val;
  803. ssb_device_disable(dev, core_specific_flags);
  804. ssb_write32(dev, SSB_TMSLOW,
  805. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  806. SSB_TMSLOW_FGC | core_specific_flags);
  807. ssb_flush_tmslow(dev);
  808. /* Clear SERR if set. This is a hw bug workaround. */
  809. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  810. ssb_write32(dev, SSB_TMSHIGH, 0);
  811. val = ssb_read32(dev, SSB_IMSTATE);
  812. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  813. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  814. ssb_write32(dev, SSB_IMSTATE, val);
  815. }
  816. ssb_write32(dev, SSB_TMSLOW,
  817. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  818. core_specific_flags);
  819. ssb_flush_tmslow(dev);
  820. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  821. core_specific_flags);
  822. ssb_flush_tmslow(dev);
  823. }
  824. EXPORT_SYMBOL(ssb_device_enable);
  825. /* Wait for a bit in a register to get set or unset.
  826. * timeout is in units of ten-microseconds */
  827. static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
  828. int timeout, int set)
  829. {
  830. int i;
  831. u32 val;
  832. for (i = 0; i < timeout; i++) {
  833. val = ssb_read32(dev, reg);
  834. if (set) {
  835. if (val & bitmask)
  836. return 0;
  837. } else {
  838. if (!(val & bitmask))
  839. return 0;
  840. }
  841. udelay(10);
  842. }
  843. printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
  844. "register %04X to %s.\n",
  845. bitmask, reg, (set ? "set" : "clear"));
  846. return -ETIMEDOUT;
  847. }
  848. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  849. {
  850. u32 reject;
  851. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  852. return;
  853. reject = ssb_tmslow_reject_bitmask(dev);
  854. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  855. ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
  856. ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  857. ssb_write32(dev, SSB_TMSLOW,
  858. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  859. reject | SSB_TMSLOW_RESET |
  860. core_specific_flags);
  861. ssb_flush_tmslow(dev);
  862. ssb_write32(dev, SSB_TMSLOW,
  863. reject | SSB_TMSLOW_RESET |
  864. core_specific_flags);
  865. ssb_flush_tmslow(dev);
  866. }
  867. EXPORT_SYMBOL(ssb_device_disable);
  868. u32 ssb_dma_translation(struct ssb_device *dev)
  869. {
  870. switch (dev->bus->bustype) {
  871. case SSB_BUSTYPE_SSB:
  872. return 0;
  873. case SSB_BUSTYPE_PCI:
  874. case SSB_BUSTYPE_PCMCIA:
  875. return SSB_PCI_DMA;
  876. }
  877. return 0;
  878. }
  879. EXPORT_SYMBOL(ssb_dma_translation);
  880. int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
  881. {
  882. struct device *dev = ssb_dev->dev;
  883. #ifdef CONFIG_SSB_PCIHOST
  884. if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
  885. !dma_supported(dev, mask))
  886. return -EIO;
  887. #endif
  888. dev->coherent_dma_mask = mask;
  889. dev->dma_mask = &dev->coherent_dma_mask;
  890. return 0;
  891. }
  892. EXPORT_SYMBOL(ssb_dma_set_mask);
  893. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  894. {
  895. struct ssb_chipcommon *cc;
  896. int err = 0;
  897. /* On buses where more than one core may be working
  898. * at a time, we must not powerdown stuff if there are
  899. * still cores that may want to run. */
  900. if (bus->bustype == SSB_BUSTYPE_SSB)
  901. goto out;
  902. cc = &bus->chipco;
  903. if (!cc->dev)
  904. goto out;
  905. if (cc->dev->id.revision < 5)
  906. goto out;
  907. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  908. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  909. if (err)
  910. goto error;
  911. out:
  912. #ifdef CONFIG_SSB_DEBUG
  913. bus->powered_up = 0;
  914. #endif
  915. return err;
  916. error:
  917. ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
  918. goto out;
  919. }
  920. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  921. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  922. {
  923. struct ssb_chipcommon *cc;
  924. int err;
  925. enum ssb_clkmode mode;
  926. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  927. if (err)
  928. goto error;
  929. cc = &bus->chipco;
  930. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  931. ssb_chipco_set_clockmode(cc, mode);
  932. #ifdef CONFIG_SSB_DEBUG
  933. bus->powered_up = 1;
  934. #endif
  935. return 0;
  936. error:
  937. ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
  938. return err;
  939. }
  940. EXPORT_SYMBOL(ssb_bus_powerup);
  941. u32 ssb_admatch_base(u32 adm)
  942. {
  943. u32 base = 0;
  944. switch (adm & SSB_ADM_TYPE) {
  945. case SSB_ADM_TYPE0:
  946. base = (adm & SSB_ADM_BASE0);
  947. break;
  948. case SSB_ADM_TYPE1:
  949. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  950. base = (adm & SSB_ADM_BASE1);
  951. break;
  952. case SSB_ADM_TYPE2:
  953. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  954. base = (adm & SSB_ADM_BASE2);
  955. break;
  956. default:
  957. SSB_WARN_ON(1);
  958. }
  959. return base;
  960. }
  961. EXPORT_SYMBOL(ssb_admatch_base);
  962. u32 ssb_admatch_size(u32 adm)
  963. {
  964. u32 size = 0;
  965. switch (adm & SSB_ADM_TYPE) {
  966. case SSB_ADM_TYPE0:
  967. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  968. break;
  969. case SSB_ADM_TYPE1:
  970. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  971. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  972. break;
  973. case SSB_ADM_TYPE2:
  974. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  975. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  976. break;
  977. default:
  978. SSB_WARN_ON(1);
  979. }
  980. size = (1 << (size + 1));
  981. return size;
  982. }
  983. EXPORT_SYMBOL(ssb_admatch_size);
  984. static int __init ssb_modinit(void)
  985. {
  986. int err;
  987. /* See the comment at the ssb_is_early_boot definition */
  988. ssb_is_early_boot = 0;
  989. err = bus_register(&ssb_bustype);
  990. if (err)
  991. return err;
  992. /* Maybe we already registered some buses at early boot.
  993. * Check for this and attach them
  994. */
  995. ssb_buses_lock();
  996. err = ssb_attach_queued_buses();
  997. ssb_buses_unlock();
  998. if (err)
  999. bus_unregister(&ssb_bustype);
  1000. err = b43_pci_ssb_bridge_init();
  1001. if (err) {
  1002. ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
  1003. "initialization failed");
  1004. /* don't fail SSB init because of this */
  1005. err = 0;
  1006. }
  1007. return err;
  1008. }
  1009. /* ssb must be initialized after PCI but before the ssb drivers.
  1010. * That means we must use some initcall between subsys_initcall
  1011. * and device_initcall. */
  1012. fs_initcall(ssb_modinit);
  1013. static void __exit ssb_modexit(void)
  1014. {
  1015. b43_pci_ssb_bridge_exit();
  1016. bus_unregister(&ssb_bustype);
  1017. }
  1018. module_exit(ssb_modexit)