twl4030.c 69 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. struct snd_soc_codec codec;
  120. unsigned int codec_powered;
  121. unsigned int apll_enabled;
  122. struct snd_pcm_substream *master_substream;
  123. struct snd_pcm_substream *slave_substream;
  124. unsigned int configured;
  125. unsigned int rate;
  126. unsigned int sample_bits;
  127. unsigned int channels;
  128. unsigned int sysclk;
  129. /* Headset output state handling */
  130. unsigned int hsl_enabled;
  131. unsigned int hsr_enabled;
  132. };
  133. /*
  134. * read twl4030 register cache
  135. */
  136. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  137. unsigned int reg)
  138. {
  139. u8 *cache = codec->reg_cache;
  140. if (reg >= TWL4030_CACHEREGNUM)
  141. return -EIO;
  142. return cache[reg];
  143. }
  144. /*
  145. * write twl4030 register cache
  146. */
  147. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  148. u8 reg, u8 value)
  149. {
  150. u8 *cache = codec->reg_cache;
  151. if (reg >= TWL4030_CACHEREGNUM)
  152. return;
  153. cache[reg] = value;
  154. }
  155. /*
  156. * write to the twl4030 register space
  157. */
  158. static int twl4030_write(struct snd_soc_codec *codec,
  159. unsigned int reg, unsigned int value)
  160. {
  161. twl4030_write_reg_cache(codec, reg, value);
  162. if (likely(reg < TWL4030_REG_SW_SHADOW))
  163. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  164. reg);
  165. else
  166. return 0;
  167. }
  168. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  169. {
  170. struct twl4030_priv *twl4030 = codec->private_data;
  171. int mode;
  172. if (enable == twl4030->codec_powered)
  173. return;
  174. if (enable)
  175. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  176. else
  177. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  178. if (mode >= 0) {
  179. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  180. twl4030->codec_powered = enable;
  181. }
  182. /* REVISIT: this delay is present in TI sample drivers */
  183. /* but there seems to be no TRM requirement for it */
  184. udelay(10);
  185. }
  186. static void twl4030_init_chip(struct snd_soc_codec *codec)
  187. {
  188. u8 *cache = codec->reg_cache;
  189. int i;
  190. /* clear CODECPDZ prior to setting register defaults */
  191. twl4030_codec_enable(codec, 0);
  192. /* set all audio section registers to reasonable defaults */
  193. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  194. twl4030_write(codec, i, cache[i]);
  195. }
  196. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  197. {
  198. struct twl4030_priv *twl4030 = codec->private_data;
  199. int status;
  200. if (enable == twl4030->apll_enabled)
  201. return;
  202. if (enable)
  203. /* Enable PLL */
  204. status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
  205. else
  206. /* Disable PLL */
  207. status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
  208. if (status >= 0)
  209. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  210. twl4030->apll_enabled = enable;
  211. }
  212. static void twl4030_power_up(struct snd_soc_codec *codec)
  213. {
  214. struct twl4030_priv *twl4030 = codec->private_data;
  215. u8 anamicl, regmisc1, byte;
  216. int i = 0;
  217. if (twl4030->codec_powered)
  218. return;
  219. /* set CODECPDZ to turn on codec */
  220. twl4030_codec_enable(codec, 1);
  221. /* initiate offset cancellation */
  222. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  223. twl4030_write(codec, TWL4030_REG_ANAMICL,
  224. anamicl | TWL4030_CNCL_OFFSET_START);
  225. /* wait for offset cancellation to complete */
  226. do {
  227. /* this takes a little while, so don't slam i2c */
  228. udelay(2000);
  229. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  230. TWL4030_REG_ANAMICL);
  231. } while ((i++ < 100) &&
  232. ((byte & TWL4030_CNCL_OFFSET_START) ==
  233. TWL4030_CNCL_OFFSET_START));
  234. /* Make sure that the reg_cache has the same value as the HW */
  235. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  236. /* anti-pop when changing analog gain */
  237. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  238. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  239. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  240. /* toggle CODECPDZ as per TRM */
  241. twl4030_codec_enable(codec, 0);
  242. twl4030_codec_enable(codec, 1);
  243. }
  244. /*
  245. * Unconditional power down
  246. */
  247. static void twl4030_power_down(struct snd_soc_codec *codec)
  248. {
  249. /* power down */
  250. twl4030_codec_enable(codec, 0);
  251. }
  252. /* Earpiece */
  253. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  254. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  255. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  256. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  257. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  258. };
  259. /* PreDrive Left */
  260. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  261. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  262. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  263. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  264. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  265. };
  266. /* PreDrive Right */
  267. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  268. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  269. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  270. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  271. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  272. };
  273. /* Headset Left */
  274. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  275. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  276. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  277. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  278. };
  279. /* Headset Right */
  280. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  281. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  282. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  283. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  284. };
  285. /* Carkit Left */
  286. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  287. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  288. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  289. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  290. };
  291. /* Carkit Right */
  292. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  293. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  294. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  295. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  296. };
  297. /* Handsfree Left */
  298. static const char *twl4030_handsfreel_texts[] =
  299. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  300. static const struct soc_enum twl4030_handsfreel_enum =
  301. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  302. ARRAY_SIZE(twl4030_handsfreel_texts),
  303. twl4030_handsfreel_texts);
  304. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  305. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  306. /* Handsfree Left virtual mute */
  307. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  308. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  309. /* Handsfree Right */
  310. static const char *twl4030_handsfreer_texts[] =
  311. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  312. static const struct soc_enum twl4030_handsfreer_enum =
  313. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  314. ARRAY_SIZE(twl4030_handsfreer_texts),
  315. twl4030_handsfreer_texts);
  316. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  317. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  318. /* Handsfree Right virtual mute */
  319. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  320. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  321. /* Vibra */
  322. /* Vibra audio path selection */
  323. static const char *twl4030_vibra_texts[] =
  324. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  325. static const struct soc_enum twl4030_vibra_enum =
  326. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  327. ARRAY_SIZE(twl4030_vibra_texts),
  328. twl4030_vibra_texts);
  329. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  330. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  331. /* Vibra path selection: local vibrator (PWM) or audio driven */
  332. static const char *twl4030_vibrapath_texts[] =
  333. {"Local vibrator", "Audio"};
  334. static const struct soc_enum twl4030_vibrapath_enum =
  335. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  336. ARRAY_SIZE(twl4030_vibrapath_texts),
  337. twl4030_vibrapath_texts);
  338. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  339. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  340. /* Left analog microphone selection */
  341. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  342. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  343. TWL4030_REG_ANAMICL, 0, 1, 0),
  344. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  345. TWL4030_REG_ANAMICL, 1, 1, 0),
  346. SOC_DAPM_SINGLE("AUXL Capture Switch",
  347. TWL4030_REG_ANAMICL, 2, 1, 0),
  348. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  349. TWL4030_REG_ANAMICL, 3, 1, 0),
  350. };
  351. /* Right analog microphone selection */
  352. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  353. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  354. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  355. };
  356. /* TX1 L/R Analog/Digital microphone selection */
  357. static const char *twl4030_micpathtx1_texts[] =
  358. {"Analog", "Digimic0"};
  359. static const struct soc_enum twl4030_micpathtx1_enum =
  360. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  361. ARRAY_SIZE(twl4030_micpathtx1_texts),
  362. twl4030_micpathtx1_texts);
  363. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  364. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  365. /* TX2 L/R Analog/Digital microphone selection */
  366. static const char *twl4030_micpathtx2_texts[] =
  367. {"Analog", "Digimic1"};
  368. static const struct soc_enum twl4030_micpathtx2_enum =
  369. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  370. ARRAY_SIZE(twl4030_micpathtx2_texts),
  371. twl4030_micpathtx2_texts);
  372. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  373. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  374. /* Analog bypass for AudioR1 */
  375. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  376. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  377. /* Analog bypass for AudioL1 */
  378. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  379. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  380. /* Analog bypass for AudioR2 */
  381. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  382. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  383. /* Analog bypass for AudioL2 */
  384. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  385. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  386. /* Analog bypass for Voice */
  387. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  388. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  389. /* Digital bypass gain, 0 mutes the bypass */
  390. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  391. TLV_DB_RANGE_HEAD(2),
  392. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  393. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  394. };
  395. /* Digital bypass left (TX1L -> RX2L) */
  396. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  397. SOC_DAPM_SINGLE_TLV("Volume",
  398. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  399. twl4030_dapm_dbypass_tlv);
  400. /* Digital bypass right (TX1R -> RX2R) */
  401. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  402. SOC_DAPM_SINGLE_TLV("Volume",
  403. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  404. twl4030_dapm_dbypass_tlv);
  405. /*
  406. * Voice Sidetone GAIN volume control:
  407. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  408. */
  409. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  410. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  411. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  412. SOC_DAPM_SINGLE_TLV("Volume",
  413. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  414. twl4030_dapm_dbypassv_tlv);
  415. static int micpath_event(struct snd_soc_dapm_widget *w,
  416. struct snd_kcontrol *kcontrol, int event)
  417. {
  418. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  419. unsigned char adcmicsel, micbias_ctl;
  420. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  421. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  422. /* Prepare the bits for the given TX path:
  423. * shift_l == 0: TX1 microphone path
  424. * shift_l == 2: TX2 microphone path */
  425. if (e->shift_l) {
  426. /* TX2 microphone path */
  427. if (adcmicsel & TWL4030_TX2IN_SEL)
  428. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  429. else
  430. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  431. } else {
  432. /* TX1 microphone path */
  433. if (adcmicsel & TWL4030_TX1IN_SEL)
  434. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  435. else
  436. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  437. }
  438. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  439. return 0;
  440. }
  441. /*
  442. * Output PGA builder:
  443. * Handle the muting and unmuting of the given output (turning off the
  444. * amplifier associated with the output pin)
  445. * On mute bypass the reg_cache and mute the volume
  446. * On unmute: restore the register content
  447. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  448. */
  449. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  450. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  451. struct snd_kcontrol *kcontrol, int event) \
  452. { \
  453. u8 reg_val; \
  454. \
  455. switch (event) { \
  456. case SND_SOC_DAPM_POST_PMU: \
  457. twl4030_write(w->codec, reg, \
  458. twl4030_read_reg_cache(w->codec, reg)); \
  459. break; \
  460. case SND_SOC_DAPM_POST_PMD: \
  461. reg_val = twl4030_read_reg_cache(w->codec, reg); \
  462. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  463. reg_val & (~mask), \
  464. reg); \
  465. break; \
  466. } \
  467. return 0; \
  468. }
  469. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  470. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  471. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  472. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  473. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  474. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  475. {
  476. unsigned char hs_ctl;
  477. hs_ctl = twl4030_read_reg_cache(codec, reg);
  478. if (ramp) {
  479. /* HF ramp-up */
  480. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  481. twl4030_write(codec, reg, hs_ctl);
  482. udelay(10);
  483. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  484. twl4030_write(codec, reg, hs_ctl);
  485. udelay(40);
  486. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  487. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  488. twl4030_write(codec, reg, hs_ctl);
  489. } else {
  490. /* HF ramp-down */
  491. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  492. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  493. twl4030_write(codec, reg, hs_ctl);
  494. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  495. twl4030_write(codec, reg, hs_ctl);
  496. udelay(40);
  497. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  498. twl4030_write(codec, reg, hs_ctl);
  499. }
  500. }
  501. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  502. struct snd_kcontrol *kcontrol, int event)
  503. {
  504. switch (event) {
  505. case SND_SOC_DAPM_POST_PMU:
  506. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  507. break;
  508. case SND_SOC_DAPM_POST_PMD:
  509. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  510. break;
  511. }
  512. return 0;
  513. }
  514. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  515. struct snd_kcontrol *kcontrol, int event)
  516. {
  517. switch (event) {
  518. case SND_SOC_DAPM_POST_PMU:
  519. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  520. break;
  521. case SND_SOC_DAPM_POST_PMD:
  522. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  523. break;
  524. }
  525. return 0;
  526. }
  527. static int vibramux_event(struct snd_soc_dapm_widget *w,
  528. struct snd_kcontrol *kcontrol, int event)
  529. {
  530. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  531. return 0;
  532. }
  533. static int apll_event(struct snd_soc_dapm_widget *w,
  534. struct snd_kcontrol *kcontrol, int event)
  535. {
  536. switch (event) {
  537. case SND_SOC_DAPM_PRE_PMU:
  538. twl4030_apll_enable(w->codec, 1);
  539. break;
  540. case SND_SOC_DAPM_POST_PMD:
  541. twl4030_apll_enable(w->codec, 0);
  542. break;
  543. }
  544. return 0;
  545. }
  546. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  547. {
  548. struct snd_soc_device *socdev = codec->socdev;
  549. struct twl4030_setup_data *setup = socdev->codec_data;
  550. unsigned char hs_gain, hs_pop;
  551. struct twl4030_priv *twl4030 = codec->private_data;
  552. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  553. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  554. 8388608, 16777216, 33554432, 67108864};
  555. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  556. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  557. /* Enable external mute control, this dramatically reduces
  558. * the pop-noise */
  559. if (setup && setup->hs_extmute) {
  560. if (setup->set_hs_extmute) {
  561. setup->set_hs_extmute(1);
  562. } else {
  563. hs_pop |= TWL4030_EXTMUTE;
  564. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  565. }
  566. }
  567. if (ramp) {
  568. /* Headset ramp-up according to the TRM */
  569. hs_pop |= TWL4030_VMID_EN;
  570. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  571. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  572. hs_pop |= TWL4030_RAMP_EN;
  573. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  574. /* Wait ramp delay time + 1, so the VMID can settle */
  575. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  576. twl4030->sysclk) + 1);
  577. } else {
  578. /* Headset ramp-down _not_ according to
  579. * the TRM, but in a way that it is working */
  580. hs_pop &= ~TWL4030_RAMP_EN;
  581. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  582. /* Wait ramp delay time + 1, so the VMID can settle */
  583. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  584. twl4030->sysclk) + 1);
  585. /* Bypass the reg_cache to mute the headset */
  586. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  587. hs_gain & (~0x0f),
  588. TWL4030_REG_HS_GAIN_SET);
  589. hs_pop &= ~TWL4030_VMID_EN;
  590. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  591. }
  592. /* Disable external mute */
  593. if (setup && setup->hs_extmute) {
  594. if (setup->set_hs_extmute) {
  595. setup->set_hs_extmute(0);
  596. } else {
  597. hs_pop &= ~TWL4030_EXTMUTE;
  598. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  599. }
  600. }
  601. }
  602. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  603. struct snd_kcontrol *kcontrol, int event)
  604. {
  605. struct twl4030_priv *twl4030 = w->codec->private_data;
  606. switch (event) {
  607. case SND_SOC_DAPM_POST_PMU:
  608. /* Do the ramp-up only once */
  609. if (!twl4030->hsr_enabled)
  610. headset_ramp(w->codec, 1);
  611. twl4030->hsl_enabled = 1;
  612. break;
  613. case SND_SOC_DAPM_POST_PMD:
  614. /* Do the ramp-down only if both headsetL/R is disabled */
  615. if (!twl4030->hsr_enabled)
  616. headset_ramp(w->codec, 0);
  617. twl4030->hsl_enabled = 0;
  618. break;
  619. }
  620. return 0;
  621. }
  622. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  623. struct snd_kcontrol *kcontrol, int event)
  624. {
  625. struct twl4030_priv *twl4030 = w->codec->private_data;
  626. switch (event) {
  627. case SND_SOC_DAPM_POST_PMU:
  628. /* Do the ramp-up only once */
  629. if (!twl4030->hsl_enabled)
  630. headset_ramp(w->codec, 1);
  631. twl4030->hsr_enabled = 1;
  632. break;
  633. case SND_SOC_DAPM_POST_PMD:
  634. /* Do the ramp-down only if both headsetL/R is disabled */
  635. if (!twl4030->hsl_enabled)
  636. headset_ramp(w->codec, 0);
  637. twl4030->hsr_enabled = 0;
  638. break;
  639. }
  640. return 0;
  641. }
  642. /*
  643. * Some of the gain controls in TWL (mostly those which are associated with
  644. * the outputs) are implemented in an interesting way:
  645. * 0x0 : Power down (mute)
  646. * 0x1 : 6dB
  647. * 0x2 : 0 dB
  648. * 0x3 : -6 dB
  649. * Inverting not going to help with these.
  650. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  651. */
  652. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  653. xinvert, tlv_array) \
  654. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  655. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  656. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  657. .tlv.p = (tlv_array), \
  658. .info = snd_soc_info_volsw, \
  659. .get = snd_soc_get_volsw_twl4030, \
  660. .put = snd_soc_put_volsw_twl4030, \
  661. .private_value = (unsigned long)&(struct soc_mixer_control) \
  662. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  663. .max = xmax, .invert = xinvert} }
  664. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  665. xinvert, tlv_array) \
  666. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  667. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  668. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  669. .tlv.p = (tlv_array), \
  670. .info = snd_soc_info_volsw_2r, \
  671. .get = snd_soc_get_volsw_r2_twl4030,\
  672. .put = snd_soc_put_volsw_r2_twl4030, \
  673. .private_value = (unsigned long)&(struct soc_mixer_control) \
  674. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  675. .rshift = xshift, .max = xmax, .invert = xinvert} }
  676. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  677. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  678. xinvert, tlv_array)
  679. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  680. struct snd_ctl_elem_value *ucontrol)
  681. {
  682. struct soc_mixer_control *mc =
  683. (struct soc_mixer_control *)kcontrol->private_value;
  684. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  685. unsigned int reg = mc->reg;
  686. unsigned int shift = mc->shift;
  687. unsigned int rshift = mc->rshift;
  688. int max = mc->max;
  689. int mask = (1 << fls(max)) - 1;
  690. ucontrol->value.integer.value[0] =
  691. (snd_soc_read(codec, reg) >> shift) & mask;
  692. if (ucontrol->value.integer.value[0])
  693. ucontrol->value.integer.value[0] =
  694. max + 1 - ucontrol->value.integer.value[0];
  695. if (shift != rshift) {
  696. ucontrol->value.integer.value[1] =
  697. (snd_soc_read(codec, reg) >> rshift) & mask;
  698. if (ucontrol->value.integer.value[1])
  699. ucontrol->value.integer.value[1] =
  700. max + 1 - ucontrol->value.integer.value[1];
  701. }
  702. return 0;
  703. }
  704. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  705. struct snd_ctl_elem_value *ucontrol)
  706. {
  707. struct soc_mixer_control *mc =
  708. (struct soc_mixer_control *)kcontrol->private_value;
  709. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  710. unsigned int reg = mc->reg;
  711. unsigned int shift = mc->shift;
  712. unsigned int rshift = mc->rshift;
  713. int max = mc->max;
  714. int mask = (1 << fls(max)) - 1;
  715. unsigned short val, val2, val_mask;
  716. val = (ucontrol->value.integer.value[0] & mask);
  717. val_mask = mask << shift;
  718. if (val)
  719. val = max + 1 - val;
  720. val = val << shift;
  721. if (shift != rshift) {
  722. val2 = (ucontrol->value.integer.value[1] & mask);
  723. val_mask |= mask << rshift;
  724. if (val2)
  725. val2 = max + 1 - val2;
  726. val |= val2 << rshift;
  727. }
  728. return snd_soc_update_bits(codec, reg, val_mask, val);
  729. }
  730. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  731. struct snd_ctl_elem_value *ucontrol)
  732. {
  733. struct soc_mixer_control *mc =
  734. (struct soc_mixer_control *)kcontrol->private_value;
  735. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  736. unsigned int reg = mc->reg;
  737. unsigned int reg2 = mc->rreg;
  738. unsigned int shift = mc->shift;
  739. int max = mc->max;
  740. int mask = (1<<fls(max))-1;
  741. ucontrol->value.integer.value[0] =
  742. (snd_soc_read(codec, reg) >> shift) & mask;
  743. ucontrol->value.integer.value[1] =
  744. (snd_soc_read(codec, reg2) >> shift) & mask;
  745. if (ucontrol->value.integer.value[0])
  746. ucontrol->value.integer.value[0] =
  747. max + 1 - ucontrol->value.integer.value[0];
  748. if (ucontrol->value.integer.value[1])
  749. ucontrol->value.integer.value[1] =
  750. max + 1 - ucontrol->value.integer.value[1];
  751. return 0;
  752. }
  753. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  754. struct snd_ctl_elem_value *ucontrol)
  755. {
  756. struct soc_mixer_control *mc =
  757. (struct soc_mixer_control *)kcontrol->private_value;
  758. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  759. unsigned int reg = mc->reg;
  760. unsigned int reg2 = mc->rreg;
  761. unsigned int shift = mc->shift;
  762. int max = mc->max;
  763. int mask = (1 << fls(max)) - 1;
  764. int err;
  765. unsigned short val, val2, val_mask;
  766. val_mask = mask << shift;
  767. val = (ucontrol->value.integer.value[0] & mask);
  768. val2 = (ucontrol->value.integer.value[1] & mask);
  769. if (val)
  770. val = max + 1 - val;
  771. if (val2)
  772. val2 = max + 1 - val2;
  773. val = val << shift;
  774. val2 = val2 << shift;
  775. err = snd_soc_update_bits(codec, reg, val_mask, val);
  776. if (err < 0)
  777. return err;
  778. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  779. return err;
  780. }
  781. /* Codec operation modes */
  782. static const char *twl4030_op_modes_texts[] = {
  783. "Option 2 (voice/audio)", "Option 1 (audio)"
  784. };
  785. static const struct soc_enum twl4030_op_modes_enum =
  786. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  787. ARRAY_SIZE(twl4030_op_modes_texts),
  788. twl4030_op_modes_texts);
  789. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  790. struct snd_ctl_elem_value *ucontrol)
  791. {
  792. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  793. struct twl4030_priv *twl4030 = codec->private_data;
  794. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  795. unsigned short val;
  796. unsigned short mask, bitmask;
  797. if (twl4030->configured) {
  798. printk(KERN_ERR "twl4030 operation mode cannot be "
  799. "changed on-the-fly\n");
  800. return -EBUSY;
  801. }
  802. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  803. ;
  804. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  805. return -EINVAL;
  806. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  807. mask = (bitmask - 1) << e->shift_l;
  808. if (e->shift_l != e->shift_r) {
  809. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  810. return -EINVAL;
  811. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  812. mask |= (bitmask - 1) << e->shift_r;
  813. }
  814. return snd_soc_update_bits(codec, e->reg, mask, val);
  815. }
  816. /*
  817. * FGAIN volume control:
  818. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  819. */
  820. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  821. /*
  822. * CGAIN volume control:
  823. * 0 dB to 12 dB in 6 dB steps
  824. * value 2 and 3 means 12 dB
  825. */
  826. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  827. /*
  828. * Voice Downlink GAIN volume control:
  829. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  830. */
  831. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  832. /*
  833. * Analog playback gain
  834. * -24 dB to 12 dB in 2 dB steps
  835. */
  836. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  837. /*
  838. * Gain controls tied to outputs
  839. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  840. */
  841. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  842. /*
  843. * Gain control for earpiece amplifier
  844. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  845. */
  846. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  847. /*
  848. * Capture gain after the ADCs
  849. * from 0 dB to 31 dB in 1 dB steps
  850. */
  851. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  852. /*
  853. * Gain control for input amplifiers
  854. * 0 dB to 30 dB in 6 dB steps
  855. */
  856. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  857. /* AVADC clock priority */
  858. static const char *twl4030_avadc_clk_priority_texts[] = {
  859. "Voice high priority", "HiFi high priority"
  860. };
  861. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  862. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  863. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  864. twl4030_avadc_clk_priority_texts);
  865. static const char *twl4030_rampdelay_texts[] = {
  866. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  867. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  868. "3495/2581/1748 ms"
  869. };
  870. static const struct soc_enum twl4030_rampdelay_enum =
  871. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  872. ARRAY_SIZE(twl4030_rampdelay_texts),
  873. twl4030_rampdelay_texts);
  874. /* Vibra H-bridge direction mode */
  875. static const char *twl4030_vibradirmode_texts[] = {
  876. "Vibra H-bridge direction", "Audio data MSB",
  877. };
  878. static const struct soc_enum twl4030_vibradirmode_enum =
  879. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  880. ARRAY_SIZE(twl4030_vibradirmode_texts),
  881. twl4030_vibradirmode_texts);
  882. /* Vibra H-bridge direction */
  883. static const char *twl4030_vibradir_texts[] = {
  884. "Positive polarity", "Negative polarity",
  885. };
  886. static const struct soc_enum twl4030_vibradir_enum =
  887. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  888. ARRAY_SIZE(twl4030_vibradir_texts),
  889. twl4030_vibradir_texts);
  890. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  891. /* Codec operation mode control */
  892. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  893. snd_soc_get_enum_double,
  894. snd_soc_put_twl4030_opmode_enum_double),
  895. /* Common playback gain controls */
  896. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  897. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  898. 0, 0x3f, 0, digital_fine_tlv),
  899. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  900. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  901. 0, 0x3f, 0, digital_fine_tlv),
  902. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  903. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  904. 6, 0x2, 0, digital_coarse_tlv),
  905. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  906. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  907. 6, 0x2, 0, digital_coarse_tlv),
  908. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  909. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  910. 3, 0x12, 1, analog_tlv),
  911. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  912. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  913. 3, 0x12, 1, analog_tlv),
  914. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  915. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  916. 1, 1, 0),
  917. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  918. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  919. 1, 1, 0),
  920. /* Common voice downlink gain controls */
  921. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  922. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  923. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  924. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  925. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  926. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  927. /* Separate output gain controls */
  928. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  929. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  930. 4, 3, 0, output_tvl),
  931. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  932. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  933. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  934. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  935. 4, 3, 0, output_tvl),
  936. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  937. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  938. /* Common capture gain controls */
  939. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  940. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  941. 0, 0x1f, 0, digital_capture_tlv),
  942. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  943. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  944. 0, 0x1f, 0, digital_capture_tlv),
  945. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  946. 0, 3, 5, 0, input_gain_tlv),
  947. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  948. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  949. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  950. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  951. };
  952. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  953. /* Left channel inputs */
  954. SND_SOC_DAPM_INPUT("MAINMIC"),
  955. SND_SOC_DAPM_INPUT("HSMIC"),
  956. SND_SOC_DAPM_INPUT("AUXL"),
  957. SND_SOC_DAPM_INPUT("CARKITMIC"),
  958. /* Right channel inputs */
  959. SND_SOC_DAPM_INPUT("SUBMIC"),
  960. SND_SOC_DAPM_INPUT("AUXR"),
  961. /* Digital microphones (Stereo) */
  962. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  963. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  964. /* Outputs */
  965. SND_SOC_DAPM_OUTPUT("OUTL"),
  966. SND_SOC_DAPM_OUTPUT("OUTR"),
  967. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  968. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  969. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  970. SND_SOC_DAPM_OUTPUT("HSOL"),
  971. SND_SOC_DAPM_OUTPUT("HSOR"),
  972. SND_SOC_DAPM_OUTPUT("CARKITL"),
  973. SND_SOC_DAPM_OUTPUT("CARKITR"),
  974. SND_SOC_DAPM_OUTPUT("HFL"),
  975. SND_SOC_DAPM_OUTPUT("HFR"),
  976. SND_SOC_DAPM_OUTPUT("VIBRA"),
  977. /* DACs */
  978. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  979. SND_SOC_NOPM, 0, 0),
  980. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  981. SND_SOC_NOPM, 0, 0),
  982. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  983. SND_SOC_NOPM, 0, 0),
  984. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  985. SND_SOC_NOPM, 0, 0),
  986. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  987. SND_SOC_NOPM, 0, 0),
  988. /* Analog bypasses */
  989. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  990. &twl4030_dapm_abypassr1_control),
  991. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  992. &twl4030_dapm_abypassl1_control),
  993. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  994. &twl4030_dapm_abypassr2_control),
  995. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  996. &twl4030_dapm_abypassl2_control),
  997. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  998. &twl4030_dapm_abypassv_control),
  999. /* Master analog loopback switch */
  1000. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1001. NULL, 0),
  1002. /* Digital bypasses */
  1003. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1004. &twl4030_dapm_dbypassl_control),
  1005. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1006. &twl4030_dapm_dbypassr_control),
  1007. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1008. &twl4030_dapm_dbypassv_control),
  1009. /* Digital mixers, power control for the physical DACs */
  1010. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1011. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1012. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1013. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1014. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1015. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1016. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1017. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1018. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1019. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1020. /* Analog mixers, power control for the physical PGAs */
  1021. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1022. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1023. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1024. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1025. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1026. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1027. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1028. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1029. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1030. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1031. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1032. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1033. /* Output MIXER controls */
  1034. /* Earpiece */
  1035. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1036. &twl4030_dapm_earpiece_controls[0],
  1037. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1038. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1039. 0, 0, NULL, 0, earpiecepga_event,
  1040. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1041. /* PreDrivL/R */
  1042. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1043. &twl4030_dapm_predrivel_controls[0],
  1044. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1045. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1046. 0, 0, NULL, 0, predrivelpga_event,
  1047. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1048. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1049. &twl4030_dapm_predriver_controls[0],
  1050. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1051. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1052. 0, 0, NULL, 0, predriverpga_event,
  1053. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1054. /* HeadsetL/R */
  1055. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1056. &twl4030_dapm_hsol_controls[0],
  1057. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1058. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1059. 0, 0, NULL, 0, headsetlpga_event,
  1060. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1061. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1062. &twl4030_dapm_hsor_controls[0],
  1063. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1064. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1065. 0, 0, NULL, 0, headsetrpga_event,
  1066. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1067. /* CarkitL/R */
  1068. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1069. &twl4030_dapm_carkitl_controls[0],
  1070. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1071. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1072. 0, 0, NULL, 0, carkitlpga_event,
  1073. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1074. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1075. &twl4030_dapm_carkitr_controls[0],
  1076. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1077. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1078. 0, 0, NULL, 0, carkitrpga_event,
  1079. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1080. /* Output MUX controls */
  1081. /* HandsfreeL/R */
  1082. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1083. &twl4030_dapm_handsfreel_control),
  1084. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1085. &twl4030_dapm_handsfreelmute_control),
  1086. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1087. 0, 0, NULL, 0, handsfreelpga_event,
  1088. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1089. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1090. &twl4030_dapm_handsfreer_control),
  1091. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1092. &twl4030_dapm_handsfreermute_control),
  1093. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1094. 0, 0, NULL, 0, handsfreerpga_event,
  1095. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1096. /* Vibra */
  1097. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1098. &twl4030_dapm_vibra_control, vibramux_event,
  1099. SND_SOC_DAPM_PRE_PMU),
  1100. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1101. &twl4030_dapm_vibrapath_control),
  1102. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1103. capture */
  1104. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1105. SND_SOC_NOPM, 0, 0),
  1106. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1107. SND_SOC_NOPM, 0, 0),
  1108. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1109. SND_SOC_NOPM, 0, 0),
  1110. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1111. SND_SOC_NOPM, 0, 0),
  1112. /* Analog/Digital mic path selection.
  1113. TX1 Left/Right: either analog Left/Right or Digimic0
  1114. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1115. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1116. &twl4030_dapm_micpathtx1_control, micpath_event,
  1117. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1118. SND_SOC_DAPM_POST_REG),
  1119. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1120. &twl4030_dapm_micpathtx2_control, micpath_event,
  1121. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1122. SND_SOC_DAPM_POST_REG),
  1123. /* Analog input mixers for the capture amplifiers */
  1124. SND_SOC_DAPM_MIXER("Analog Left",
  1125. TWL4030_REG_ANAMICL, 4, 0,
  1126. &twl4030_dapm_analoglmic_controls[0],
  1127. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1128. SND_SOC_DAPM_MIXER("Analog Right",
  1129. TWL4030_REG_ANAMICR, 4, 0,
  1130. &twl4030_dapm_analogrmic_controls[0],
  1131. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1132. SND_SOC_DAPM_PGA("ADC Physical Left",
  1133. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1134. SND_SOC_DAPM_PGA("ADC Physical Right",
  1135. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1136. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1137. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1138. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1139. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1140. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1141. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1142. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1143. };
  1144. static const struct snd_soc_dapm_route intercon[] = {
  1145. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1146. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1147. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1148. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1149. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1150. /* Supply for the digital part (APLL) */
  1151. {"Digital R1 Playback Mixer", NULL, "APLL Enable"},
  1152. {"Digital L1 Playback Mixer", NULL, "APLL Enable"},
  1153. {"Digital R2 Playback Mixer", NULL, "APLL Enable"},
  1154. {"Digital L2 Playback Mixer", NULL, "APLL Enable"},
  1155. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1156. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1157. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1158. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1159. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1160. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1161. /* Internal playback routings */
  1162. /* Earpiece */
  1163. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1164. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1165. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1166. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1167. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1168. /* PreDrivL */
  1169. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1170. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1171. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1172. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1173. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1174. /* PreDrivR */
  1175. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1176. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1177. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1178. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1179. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1180. /* HeadsetL */
  1181. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1182. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1183. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1184. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1185. /* HeadsetR */
  1186. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1187. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1188. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1189. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1190. /* CarkitL */
  1191. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1192. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1193. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1194. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1195. /* CarkitR */
  1196. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1197. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1198. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1199. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1200. /* HandsfreeL */
  1201. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1202. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1203. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1204. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1205. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1206. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1207. /* HandsfreeR */
  1208. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1209. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1210. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1211. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1212. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1213. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1214. /* Vibra */
  1215. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1216. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1217. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1218. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1219. /* outputs */
  1220. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1221. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1222. {"EARPIECE", NULL, "Earpiece PGA"},
  1223. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1224. {"PREDRIVER", NULL, "PredriveR PGA"},
  1225. {"HSOL", NULL, "HeadsetL PGA"},
  1226. {"HSOR", NULL, "HeadsetR PGA"},
  1227. {"CARKITL", NULL, "CarkitL PGA"},
  1228. {"CARKITR", NULL, "CarkitR PGA"},
  1229. {"HFL", NULL, "HandsfreeL PGA"},
  1230. {"HFR", NULL, "HandsfreeR PGA"},
  1231. {"Vibra Route", "Audio", "Vibra Mux"},
  1232. {"VIBRA", NULL, "Vibra Route"},
  1233. /* Capture path */
  1234. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1235. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1236. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1237. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1238. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1239. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1240. {"ADC Physical Left", NULL, "Analog Left"},
  1241. {"ADC Physical Right", NULL, "Analog Right"},
  1242. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1243. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1244. /* TX1 Left capture path */
  1245. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1246. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1247. /* TX1 Right capture path */
  1248. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1249. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1250. /* TX2 Left capture path */
  1251. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1252. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1253. /* TX2 Right capture path */
  1254. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1255. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1256. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1257. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1258. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1259. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1260. {"ADC Virtual Left1", NULL, "APLL Enable"},
  1261. {"ADC Virtual Right1", NULL, "APLL Enable"},
  1262. {"ADC Virtual Left2", NULL, "APLL Enable"},
  1263. {"ADC Virtual Right2", NULL, "APLL Enable"},
  1264. /* Analog bypass routes */
  1265. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1266. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1267. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1268. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1269. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1270. /* Supply for the Analog loopbacks */
  1271. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1272. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1273. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1274. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1275. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1276. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1277. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1278. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1279. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1280. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1281. /* Digital bypass routes */
  1282. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1283. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1284. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1285. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1286. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1287. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1288. };
  1289. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1290. {
  1291. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1292. ARRAY_SIZE(twl4030_dapm_widgets));
  1293. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1294. snd_soc_dapm_new_widgets(codec);
  1295. return 0;
  1296. }
  1297. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1298. enum snd_soc_bias_level level)
  1299. {
  1300. switch (level) {
  1301. case SND_SOC_BIAS_ON:
  1302. break;
  1303. case SND_SOC_BIAS_PREPARE:
  1304. break;
  1305. case SND_SOC_BIAS_STANDBY:
  1306. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1307. twl4030_power_up(codec);
  1308. break;
  1309. case SND_SOC_BIAS_OFF:
  1310. twl4030_power_down(codec);
  1311. break;
  1312. }
  1313. codec->bias_level = level;
  1314. return 0;
  1315. }
  1316. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1317. struct snd_pcm_substream *mst_substream)
  1318. {
  1319. struct snd_pcm_substream *slv_substream;
  1320. /* Pick the stream, which need to be constrained */
  1321. if (mst_substream == twl4030->master_substream)
  1322. slv_substream = twl4030->slave_substream;
  1323. else if (mst_substream == twl4030->slave_substream)
  1324. slv_substream = twl4030->master_substream;
  1325. else /* This should not happen.. */
  1326. return;
  1327. /* Set the constraints according to the already configured stream */
  1328. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1329. SNDRV_PCM_HW_PARAM_RATE,
  1330. twl4030->rate,
  1331. twl4030->rate);
  1332. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1333. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1334. twl4030->sample_bits,
  1335. twl4030->sample_bits);
  1336. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1337. SNDRV_PCM_HW_PARAM_CHANNELS,
  1338. twl4030->channels,
  1339. twl4030->channels);
  1340. }
  1341. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1342. * capture has to be enabled/disabled. */
  1343. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1344. int enable)
  1345. {
  1346. u8 reg, mask;
  1347. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1348. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1349. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1350. else
  1351. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1352. if (enable)
  1353. reg |= mask;
  1354. else
  1355. reg &= ~mask;
  1356. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1357. }
  1358. static int twl4030_startup(struct snd_pcm_substream *substream,
  1359. struct snd_soc_dai *dai)
  1360. {
  1361. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1362. struct snd_soc_device *socdev = rtd->socdev;
  1363. struct snd_soc_codec *codec = socdev->card->codec;
  1364. struct twl4030_priv *twl4030 = codec->private_data;
  1365. if (twl4030->master_substream) {
  1366. twl4030->slave_substream = substream;
  1367. /* The DAI has one configuration for playback and capture, so
  1368. * if the DAI has been already configured then constrain this
  1369. * substream to match it. */
  1370. if (twl4030->configured)
  1371. twl4030_constraints(twl4030, twl4030->master_substream);
  1372. } else {
  1373. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1374. TWL4030_OPTION_1)) {
  1375. /* In option2 4 channel is not supported, set the
  1376. * constraint for the first stream for channels, the
  1377. * second stream will 'inherit' this cosntraint */
  1378. snd_pcm_hw_constraint_minmax(substream->runtime,
  1379. SNDRV_PCM_HW_PARAM_CHANNELS,
  1380. 2, 2);
  1381. }
  1382. twl4030->master_substream = substream;
  1383. }
  1384. return 0;
  1385. }
  1386. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1387. struct snd_soc_dai *dai)
  1388. {
  1389. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1390. struct snd_soc_device *socdev = rtd->socdev;
  1391. struct snd_soc_codec *codec = socdev->card->codec;
  1392. struct twl4030_priv *twl4030 = codec->private_data;
  1393. if (twl4030->master_substream == substream)
  1394. twl4030->master_substream = twl4030->slave_substream;
  1395. twl4030->slave_substream = NULL;
  1396. /* If all streams are closed, or the remaining stream has not yet
  1397. * been configured than set the DAI as not configured. */
  1398. if (!twl4030->master_substream)
  1399. twl4030->configured = 0;
  1400. else if (!twl4030->master_substream->runtime->channels)
  1401. twl4030->configured = 0;
  1402. /* If the closing substream had 4 channel, do the necessary cleanup */
  1403. if (substream->runtime->channels == 4)
  1404. twl4030_tdm_enable(codec, substream->stream, 0);
  1405. }
  1406. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1407. struct snd_pcm_hw_params *params,
  1408. struct snd_soc_dai *dai)
  1409. {
  1410. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1411. struct snd_soc_device *socdev = rtd->socdev;
  1412. struct snd_soc_codec *codec = socdev->card->codec;
  1413. struct twl4030_priv *twl4030 = codec->private_data;
  1414. u8 mode, old_mode, format, old_format;
  1415. /* If the substream has 4 channel, do the necessary setup */
  1416. if (params_channels(params) == 4) {
  1417. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1418. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1419. /* Safety check: are we in the correct operating mode and
  1420. * the interface is in TDM mode? */
  1421. if ((mode & TWL4030_OPTION_1) &&
  1422. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1423. twl4030_tdm_enable(codec, substream->stream, 1);
  1424. else
  1425. return -EINVAL;
  1426. }
  1427. if (twl4030->configured)
  1428. /* Ignoring hw_params for already configured DAI */
  1429. return 0;
  1430. /* bit rate */
  1431. old_mode = twl4030_read_reg_cache(codec,
  1432. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1433. mode = old_mode & ~TWL4030_APLL_RATE;
  1434. switch (params_rate(params)) {
  1435. case 8000:
  1436. mode |= TWL4030_APLL_RATE_8000;
  1437. break;
  1438. case 11025:
  1439. mode |= TWL4030_APLL_RATE_11025;
  1440. break;
  1441. case 12000:
  1442. mode |= TWL4030_APLL_RATE_12000;
  1443. break;
  1444. case 16000:
  1445. mode |= TWL4030_APLL_RATE_16000;
  1446. break;
  1447. case 22050:
  1448. mode |= TWL4030_APLL_RATE_22050;
  1449. break;
  1450. case 24000:
  1451. mode |= TWL4030_APLL_RATE_24000;
  1452. break;
  1453. case 32000:
  1454. mode |= TWL4030_APLL_RATE_32000;
  1455. break;
  1456. case 44100:
  1457. mode |= TWL4030_APLL_RATE_44100;
  1458. break;
  1459. case 48000:
  1460. mode |= TWL4030_APLL_RATE_48000;
  1461. break;
  1462. case 96000:
  1463. mode |= TWL4030_APLL_RATE_96000;
  1464. break;
  1465. default:
  1466. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1467. params_rate(params));
  1468. return -EINVAL;
  1469. }
  1470. if (mode != old_mode) {
  1471. /* change rate and set CODECPDZ */
  1472. twl4030_codec_enable(codec, 0);
  1473. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1474. twl4030_codec_enable(codec, 1);
  1475. }
  1476. /* sample size */
  1477. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1478. format = old_format;
  1479. format &= ~TWL4030_DATA_WIDTH;
  1480. switch (params_format(params)) {
  1481. case SNDRV_PCM_FORMAT_S16_LE:
  1482. format |= TWL4030_DATA_WIDTH_16S_16W;
  1483. break;
  1484. case SNDRV_PCM_FORMAT_S24_LE:
  1485. format |= TWL4030_DATA_WIDTH_32S_24W;
  1486. break;
  1487. default:
  1488. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1489. params_format(params));
  1490. return -EINVAL;
  1491. }
  1492. if (format != old_format) {
  1493. /* clear CODECPDZ before changing format (codec requirement) */
  1494. twl4030_codec_enable(codec, 0);
  1495. /* change format */
  1496. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1497. /* set CODECPDZ afterwards */
  1498. twl4030_codec_enable(codec, 1);
  1499. }
  1500. /* Store the important parameters for the DAI configuration and set
  1501. * the DAI as configured */
  1502. twl4030->configured = 1;
  1503. twl4030->rate = params_rate(params);
  1504. twl4030->sample_bits = hw_param_interval(params,
  1505. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1506. twl4030->channels = params_channels(params);
  1507. /* If both playback and capture streams are open, and one of them
  1508. * is setting the hw parameters right now (since we are here), set
  1509. * constraints to the other stream to match the current one. */
  1510. if (twl4030->slave_substream)
  1511. twl4030_constraints(twl4030, substream);
  1512. return 0;
  1513. }
  1514. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1515. int clk_id, unsigned int freq, int dir)
  1516. {
  1517. struct snd_soc_codec *codec = codec_dai->codec;
  1518. struct twl4030_priv *twl4030 = codec->private_data;
  1519. u8 apll_ctrl;
  1520. apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  1521. apll_ctrl &= ~TWL4030_APLL_INFREQ;
  1522. switch (freq) {
  1523. case 19200000:
  1524. apll_ctrl |= TWL4030_APLL_INFREQ_19200KHZ;
  1525. twl4030->sysclk = 19200;
  1526. break;
  1527. case 26000000:
  1528. apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
  1529. twl4030->sysclk = 26000;
  1530. break;
  1531. case 38400000:
  1532. apll_ctrl |= TWL4030_APLL_INFREQ_38400KHZ;
  1533. twl4030->sysclk = 38400;
  1534. break;
  1535. default:
  1536. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1537. freq);
  1538. return -EINVAL;
  1539. }
  1540. twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
  1541. return 0;
  1542. }
  1543. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1544. unsigned int fmt)
  1545. {
  1546. struct snd_soc_codec *codec = codec_dai->codec;
  1547. u8 old_format, format;
  1548. /* get format */
  1549. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1550. format = old_format;
  1551. /* set master/slave audio interface */
  1552. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1553. case SND_SOC_DAIFMT_CBM_CFM:
  1554. format &= ~(TWL4030_AIF_SLAVE_EN);
  1555. format &= ~(TWL4030_CLK256FS_EN);
  1556. break;
  1557. case SND_SOC_DAIFMT_CBS_CFS:
  1558. format |= TWL4030_AIF_SLAVE_EN;
  1559. format |= TWL4030_CLK256FS_EN;
  1560. break;
  1561. default:
  1562. return -EINVAL;
  1563. }
  1564. /* interface format */
  1565. format &= ~TWL4030_AIF_FORMAT;
  1566. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1567. case SND_SOC_DAIFMT_I2S:
  1568. format |= TWL4030_AIF_FORMAT_CODEC;
  1569. break;
  1570. case SND_SOC_DAIFMT_DSP_A:
  1571. format |= TWL4030_AIF_FORMAT_TDM;
  1572. break;
  1573. default:
  1574. return -EINVAL;
  1575. }
  1576. if (format != old_format) {
  1577. /* clear CODECPDZ before changing format (codec requirement) */
  1578. twl4030_codec_enable(codec, 0);
  1579. /* change format */
  1580. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1581. /* set CODECPDZ afterwards */
  1582. twl4030_codec_enable(codec, 1);
  1583. }
  1584. return 0;
  1585. }
  1586. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1587. {
  1588. struct snd_soc_codec *codec = dai->codec;
  1589. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1590. if (tristate)
  1591. reg |= TWL4030_AIF_TRI_EN;
  1592. else
  1593. reg &= ~TWL4030_AIF_TRI_EN;
  1594. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1595. }
  1596. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1597. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1598. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1599. int enable)
  1600. {
  1601. u8 reg, mask;
  1602. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1603. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1604. mask = TWL4030_ARXL1_VRX_EN;
  1605. else
  1606. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1607. if (enable)
  1608. reg |= mask;
  1609. else
  1610. reg &= ~mask;
  1611. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1612. }
  1613. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1614. struct snd_soc_dai *dai)
  1615. {
  1616. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1617. struct snd_soc_device *socdev = rtd->socdev;
  1618. struct snd_soc_codec *codec = socdev->card->codec;
  1619. u8 infreq;
  1620. u8 mode;
  1621. /* If the system master clock is not 26MHz, the voice PCM interface is
  1622. * not avilable.
  1623. */
  1624. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1625. & TWL4030_APLL_INFREQ;
  1626. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1627. printk(KERN_ERR "TWL4030 voice startup: "
  1628. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1629. return -EINVAL;
  1630. }
  1631. /* If the codec mode is not option2, the voice PCM interface is not
  1632. * avilable.
  1633. */
  1634. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1635. & TWL4030_OPT_MODE;
  1636. if (mode != TWL4030_OPTION_2) {
  1637. printk(KERN_ERR "TWL4030 voice startup: "
  1638. "the codec mode is not option2\n");
  1639. return -EINVAL;
  1640. }
  1641. return 0;
  1642. }
  1643. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1644. struct snd_soc_dai *dai)
  1645. {
  1646. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1647. struct snd_soc_device *socdev = rtd->socdev;
  1648. struct snd_soc_codec *codec = socdev->card->codec;
  1649. /* Enable voice digital filters */
  1650. twl4030_voice_enable(codec, substream->stream, 0);
  1651. }
  1652. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1653. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1654. {
  1655. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1656. struct snd_soc_device *socdev = rtd->socdev;
  1657. struct snd_soc_codec *codec = socdev->card->codec;
  1658. u8 old_mode, mode;
  1659. /* Enable voice digital filters */
  1660. twl4030_voice_enable(codec, substream->stream, 1);
  1661. /* bit rate */
  1662. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1663. & ~(TWL4030_CODECPDZ);
  1664. mode = old_mode;
  1665. switch (params_rate(params)) {
  1666. case 8000:
  1667. mode &= ~(TWL4030_SEL_16K);
  1668. break;
  1669. case 16000:
  1670. mode |= TWL4030_SEL_16K;
  1671. break;
  1672. default:
  1673. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1674. params_rate(params));
  1675. return -EINVAL;
  1676. }
  1677. if (mode != old_mode) {
  1678. /* change rate and set CODECPDZ */
  1679. twl4030_codec_enable(codec, 0);
  1680. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1681. twl4030_codec_enable(codec, 1);
  1682. }
  1683. return 0;
  1684. }
  1685. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1686. int clk_id, unsigned int freq, int dir)
  1687. {
  1688. struct snd_soc_codec *codec = codec_dai->codec;
  1689. u8 apll_ctrl;
  1690. apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  1691. apll_ctrl &= ~TWL4030_APLL_INFREQ;
  1692. switch (freq) {
  1693. case 26000000:
  1694. apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
  1695. break;
  1696. default:
  1697. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1698. freq);
  1699. return -EINVAL;
  1700. }
  1701. twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
  1702. return 0;
  1703. }
  1704. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1705. unsigned int fmt)
  1706. {
  1707. struct snd_soc_codec *codec = codec_dai->codec;
  1708. u8 old_format, format;
  1709. /* get format */
  1710. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1711. format = old_format;
  1712. /* set master/slave audio interface */
  1713. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1714. case SND_SOC_DAIFMT_CBM_CFM:
  1715. format &= ~(TWL4030_VIF_SLAVE_EN);
  1716. break;
  1717. case SND_SOC_DAIFMT_CBS_CFS:
  1718. format |= TWL4030_VIF_SLAVE_EN;
  1719. break;
  1720. default:
  1721. return -EINVAL;
  1722. }
  1723. /* clock inversion */
  1724. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1725. case SND_SOC_DAIFMT_IB_NF:
  1726. format &= ~(TWL4030_VIF_FORMAT);
  1727. break;
  1728. case SND_SOC_DAIFMT_NB_IF:
  1729. format |= TWL4030_VIF_FORMAT;
  1730. break;
  1731. default:
  1732. return -EINVAL;
  1733. }
  1734. if (format != old_format) {
  1735. /* change format and set CODECPDZ */
  1736. twl4030_codec_enable(codec, 0);
  1737. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1738. twl4030_codec_enable(codec, 1);
  1739. }
  1740. return 0;
  1741. }
  1742. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1743. {
  1744. struct snd_soc_codec *codec = dai->codec;
  1745. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1746. if (tristate)
  1747. reg |= TWL4030_VIF_TRI_EN;
  1748. else
  1749. reg &= ~TWL4030_VIF_TRI_EN;
  1750. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1751. }
  1752. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1753. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1754. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1755. .startup = twl4030_startup,
  1756. .shutdown = twl4030_shutdown,
  1757. .hw_params = twl4030_hw_params,
  1758. .set_sysclk = twl4030_set_dai_sysclk,
  1759. .set_fmt = twl4030_set_dai_fmt,
  1760. .set_tristate = twl4030_set_tristate,
  1761. };
  1762. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1763. .startup = twl4030_voice_startup,
  1764. .shutdown = twl4030_voice_shutdown,
  1765. .hw_params = twl4030_voice_hw_params,
  1766. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1767. .set_fmt = twl4030_voice_set_dai_fmt,
  1768. .set_tristate = twl4030_voice_set_tristate,
  1769. };
  1770. struct snd_soc_dai twl4030_dai[] = {
  1771. {
  1772. .name = "twl4030",
  1773. .playback = {
  1774. .stream_name = "HiFi Playback",
  1775. .channels_min = 2,
  1776. .channels_max = 4,
  1777. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1778. .formats = TWL4030_FORMATS,},
  1779. .capture = {
  1780. .stream_name = "Capture",
  1781. .channels_min = 2,
  1782. .channels_max = 4,
  1783. .rates = TWL4030_RATES,
  1784. .formats = TWL4030_FORMATS,},
  1785. .ops = &twl4030_dai_ops,
  1786. },
  1787. {
  1788. .name = "twl4030 Voice",
  1789. .playback = {
  1790. .stream_name = "Voice Playback",
  1791. .channels_min = 1,
  1792. .channels_max = 1,
  1793. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1794. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1795. .capture = {
  1796. .stream_name = "Capture",
  1797. .channels_min = 1,
  1798. .channels_max = 2,
  1799. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1800. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1801. .ops = &twl4030_dai_voice_ops,
  1802. },
  1803. };
  1804. EXPORT_SYMBOL_GPL(twl4030_dai);
  1805. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1806. {
  1807. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1808. struct snd_soc_codec *codec = socdev->card->codec;
  1809. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1810. return 0;
  1811. }
  1812. static int twl4030_soc_resume(struct platform_device *pdev)
  1813. {
  1814. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1815. struct snd_soc_codec *codec = socdev->card->codec;
  1816. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1817. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1818. return 0;
  1819. }
  1820. static struct snd_soc_codec *twl4030_codec;
  1821. static int twl4030_soc_probe(struct platform_device *pdev)
  1822. {
  1823. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1824. struct twl4030_setup_data *setup = socdev->codec_data;
  1825. struct snd_soc_codec *codec;
  1826. struct twl4030_priv *twl4030;
  1827. int ret;
  1828. BUG_ON(!twl4030_codec);
  1829. codec = twl4030_codec;
  1830. twl4030 = codec->private_data;
  1831. socdev->card->codec = codec;
  1832. /* Configuration for headset ramp delay from setup data */
  1833. if (setup) {
  1834. unsigned char hs_pop;
  1835. if (setup->sysclk)
  1836. twl4030->sysclk = setup->sysclk;
  1837. else
  1838. twl4030->sysclk = 26000;
  1839. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1840. hs_pop &= ~TWL4030_RAMP_DELAY;
  1841. hs_pop |= (setup->ramp_delay_value << 2);
  1842. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1843. } else {
  1844. twl4030->sysclk = 26000;
  1845. }
  1846. /* register pcms */
  1847. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1848. if (ret < 0) {
  1849. dev_err(&pdev->dev, "failed to create pcms\n");
  1850. return ret;
  1851. }
  1852. snd_soc_add_controls(codec, twl4030_snd_controls,
  1853. ARRAY_SIZE(twl4030_snd_controls));
  1854. twl4030_add_widgets(codec);
  1855. ret = snd_soc_init_card(socdev);
  1856. if (ret < 0) {
  1857. dev_err(&pdev->dev, "failed to register card\n");
  1858. goto card_err;
  1859. }
  1860. return 0;
  1861. card_err:
  1862. snd_soc_free_pcms(socdev);
  1863. snd_soc_dapm_free(socdev);
  1864. return ret;
  1865. }
  1866. static int twl4030_soc_remove(struct platform_device *pdev)
  1867. {
  1868. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1869. struct snd_soc_codec *codec = socdev->card->codec;
  1870. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1871. snd_soc_free_pcms(socdev);
  1872. snd_soc_dapm_free(socdev);
  1873. kfree(codec->private_data);
  1874. kfree(codec);
  1875. return 0;
  1876. }
  1877. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1878. {
  1879. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1880. struct snd_soc_codec *codec;
  1881. struct twl4030_priv *twl4030;
  1882. int ret;
  1883. if (!pdata || !(pdata->audio_mclk == 19200000 ||
  1884. pdata->audio_mclk == 26000000 ||
  1885. pdata->audio_mclk == 38400000)) {
  1886. dev_err(&pdev->dev, "Invalid platform_data\n");
  1887. return -EINVAL;
  1888. }
  1889. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1890. if (twl4030 == NULL) {
  1891. dev_err(&pdev->dev, "Can not allocate memroy\n");
  1892. return -ENOMEM;
  1893. }
  1894. codec = &twl4030->codec;
  1895. codec->private_data = twl4030;
  1896. codec->dev = &pdev->dev;
  1897. twl4030_dai[0].dev = &pdev->dev;
  1898. twl4030_dai[1].dev = &pdev->dev;
  1899. mutex_init(&codec->mutex);
  1900. INIT_LIST_HEAD(&codec->dapm_widgets);
  1901. INIT_LIST_HEAD(&codec->dapm_paths);
  1902. codec->name = "twl4030";
  1903. codec->owner = THIS_MODULE;
  1904. codec->read = twl4030_read_reg_cache;
  1905. codec->write = twl4030_write;
  1906. codec->set_bias_level = twl4030_set_bias_level;
  1907. codec->dai = twl4030_dai;
  1908. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1909. codec->reg_cache_size = sizeof(twl4030_reg);
  1910. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1911. GFP_KERNEL);
  1912. if (codec->reg_cache == NULL) {
  1913. ret = -ENOMEM;
  1914. goto error_cache;
  1915. }
  1916. platform_set_drvdata(pdev, twl4030);
  1917. twl4030_codec = codec;
  1918. /* Set the defaults, and power up the codec */
  1919. twl4030_init_chip(codec);
  1920. codec->bias_level = SND_SOC_BIAS_OFF;
  1921. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1922. ret = snd_soc_register_codec(codec);
  1923. if (ret != 0) {
  1924. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  1925. goto error_codec;
  1926. }
  1927. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1928. if (ret != 0) {
  1929. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  1930. snd_soc_unregister_codec(codec);
  1931. goto error_codec;
  1932. }
  1933. return 0;
  1934. error_codec:
  1935. twl4030_power_down(codec);
  1936. kfree(codec->reg_cache);
  1937. error_cache:
  1938. kfree(twl4030);
  1939. return ret;
  1940. }
  1941. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  1942. {
  1943. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  1944. kfree(twl4030);
  1945. twl4030_codec = NULL;
  1946. return 0;
  1947. }
  1948. MODULE_ALIAS("platform:twl4030_codec_audio");
  1949. static struct platform_driver twl4030_codec_driver = {
  1950. .probe = twl4030_codec_probe,
  1951. .remove = __devexit_p(twl4030_codec_remove),
  1952. .driver = {
  1953. .name = "twl4030_codec_audio",
  1954. .owner = THIS_MODULE,
  1955. },
  1956. };
  1957. static int __init twl4030_modinit(void)
  1958. {
  1959. return platform_driver_register(&twl4030_codec_driver);
  1960. }
  1961. module_init(twl4030_modinit);
  1962. static void __exit twl4030_exit(void)
  1963. {
  1964. platform_driver_unregister(&twl4030_codec_driver);
  1965. }
  1966. module_exit(twl4030_exit);
  1967. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1968. .probe = twl4030_soc_probe,
  1969. .remove = twl4030_soc_remove,
  1970. .suspend = twl4030_soc_suspend,
  1971. .resume = twl4030_soc_resume,
  1972. };
  1973. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1974. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1975. MODULE_AUTHOR("Steve Sakoman");
  1976. MODULE_LICENSE("GPL");