m54xxacr.h 2.5 KB

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  1. /*
  2. * Bit definitions for the MCF54xx ACR and CACR registers.
  3. */
  4. #ifndef m54xxacr_h
  5. #define m54xxacr_h
  6. /*
  7. * Define the Cache register flags.
  8. */
  9. #define CACR_DEC 0x80000000 /* Enable data cache */
  10. #define CACR_DWP 0x40000000 /* Data write protection */
  11. #define CACR_DESB 0x20000000 /* Enable data store buffer */
  12. #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
  13. #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
  14. #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
  15. #define CACR_DDCM_CP 0x02000000 /* Copyback cache */
  16. #define CACR_DDCM_P 0x04000000 /* No cache, precise */
  17. #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
  18. #define CACR_DCINVA 0x01000000 /* Invalidate data cache */
  19. #define CACR_BEC 0x00080000 /* Enable branch cache */
  20. #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
  21. #define CACR_IEC 0x00008000 /* Enable instruction cache */
  22. #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
  23. #define CACR_IDPI 0x00001000 /* Disable CPUSHL */
  24. #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
  25. #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
  26. #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
  27. #define ACR_BASE_POS 24 /* Address Base */
  28. #define ACR_MASK_POS 16 /* Address Mask */
  29. #define ACR_ENABLE 0x00008000 /* Enable address */
  30. #define ACR_USER 0x00000000 /* User mode access only */
  31. #define ACR_SUPER 0x00002000 /* Supervisor mode only */
  32. #define ACR_ANY 0x00004000 /* Match any access mode */
  33. #define ACR_CM_WT 0x00000000 /* Write through mode */
  34. #define ACR_CM_CP 0x00000020 /* Copyback mode */
  35. #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
  36. #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
  37. #define ACR_CM 0x00000060 /* Cache mode mask */
  38. #define ACR_WPROTECT 0x00000004 /* Write protect */
  39. #ifndef __ASSEMBLY__
  40. static inline void __m54xx_flush_cache_all(void)
  41. {
  42. /*
  43. * Use cpushl to push and invalidate all cache lines.
  44. * Gas doesn't seem to know how to generate the ColdFire
  45. * cpushl instruction... Oh well, bit stuff it for now.
  46. */
  47. __asm__ __volatile__ (
  48. "nop\n\t"
  49. "clrl %%d0\n\t"
  50. "1:\n\t"
  51. "movel %%d0,%%a0\n\t"
  52. "2:\n\t"
  53. ".word 0xf468\n\t"
  54. "addl #0x10,%%a0\n\t"
  55. "cmpl #0x00000800,%%a0\n\t"
  56. "blt 2b\n\t"
  57. "addql #1,%%d0\n\t"
  58. "cmpil #4,%%d0\n\t"
  59. "bne 1b\n\t"
  60. "movel #0xb6088500,%%d0\n\t"
  61. "movec %%d0,%%CACR\n\t"
  62. : : : "d0", "a0" );
  63. }
  64. #define __flush_cache_all() __m54xx_flush_cache_all()
  65. #endif /* __ASSEMBLY__ */
  66. #endif /* m54xxacr_h */