ql4_mbx.c 48 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine issue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. uint32_t dev_state;
  33. /* Make sure that pointers are valid */
  34. if (!mbx_cmd || !mbx_sts) {
  35. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  36. "pointer\n", ha->host_no, __func__));
  37. return status;
  38. }
  39. if (is_qla8022(ha)) {
  40. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  41. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  42. "prematurely completing mbx cmd as firmware "
  43. "recovery detected\n", ha->host_no, __func__));
  44. return status;
  45. }
  46. /* Do not send any mbx cmd if h/w is in failed state*/
  47. qla4_8xxx_idc_lock(ha);
  48. dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  49. qla4_8xxx_idc_unlock(ha);
  50. if (dev_state == QLA82XX_DEV_FAILED) {
  51. ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
  52. "failed state, do not send any mailbox commands\n",
  53. ha->host_no, __func__);
  54. return status;
  55. }
  56. }
  57. if ((is_aer_supported(ha)) &&
  58. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  59. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  60. "timeout MBX Exiting.\n", ha->host_no, __func__));
  61. return status;
  62. }
  63. /* Mailbox code active */
  64. wait_count = MBOX_TOV * 100;
  65. while (wait_count--) {
  66. mutex_lock(&ha->mbox_sem);
  67. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  68. set_bit(AF_MBOX_COMMAND, &ha->flags);
  69. mutex_unlock(&ha->mbox_sem);
  70. break;
  71. }
  72. mutex_unlock(&ha->mbox_sem);
  73. if (!wait_count) {
  74. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  75. ha->host_no, __func__));
  76. return status;
  77. }
  78. msleep(10);
  79. }
  80. spin_lock_irqsave(&ha->hardware_lock, flags);
  81. ha->mbox_status_count = outCount;
  82. for (i = 0; i < outCount; i++)
  83. ha->mbox_status[i] = 0;
  84. if (is_qla8022(ha)) {
  85. /* Load all mailbox registers, except mailbox 0. */
  86. DEBUG5(
  87. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  88. for (i = 0; i < inCount; i++)
  89. printk("mb%d=%04x ", i, mbx_cmd[i]);
  90. printk("\n"));
  91. for (i = 1; i < inCount; i++)
  92. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  93. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  94. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  95. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  96. } else {
  97. /* Load all mailbox registers, except mailbox 0. */
  98. for (i = 1; i < inCount; i++)
  99. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  100. /* Wakeup firmware */
  101. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  102. readl(&ha->reg->mailbox[0]);
  103. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  104. readl(&ha->reg->ctrl_status);
  105. }
  106. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  107. /* Wait for completion */
  108. /*
  109. * If we don't want status, don't wait for the mailbox command to
  110. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  111. * you must poll the inbound Interrupt Mask for completion.
  112. */
  113. if (outCount == 0) {
  114. status = QLA_SUCCESS;
  115. goto mbox_exit;
  116. }
  117. /*
  118. * Wait for completion: Poll or completion queue
  119. */
  120. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  121. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  122. test_bit(AF_ONLINE, &ha->flags) &&
  123. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  124. /* Do not poll for completion. Use completion queue */
  125. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  127. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  128. } else {
  129. /* Poll for command to complete */
  130. wait_count = jiffies + MBOX_TOV * HZ;
  131. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  132. if (time_after_eq(jiffies, wait_count))
  133. break;
  134. /*
  135. * Service the interrupt.
  136. * The ISR will save the mailbox status registers
  137. * to a temporary storage location in the adapter
  138. * structure.
  139. */
  140. spin_lock_irqsave(&ha->hardware_lock, flags);
  141. if (is_qla8022(ha)) {
  142. intr_status =
  143. readl(&ha->qla4_8xxx_reg->host_int);
  144. if (intr_status & ISRX_82XX_RISC_INT) {
  145. ha->mbox_status_count = outCount;
  146. intr_status =
  147. readl(&ha->qla4_8xxx_reg->host_status);
  148. ha->isp_ops->interrupt_service_routine(
  149. ha, intr_status);
  150. if (test_bit(AF_INTERRUPTS_ON,
  151. &ha->flags) &&
  152. test_bit(AF_INTx_ENABLED,
  153. &ha->flags))
  154. qla4_8xxx_wr_32(ha,
  155. ha->nx_legacy_intr.tgt_mask_reg,
  156. 0xfbff);
  157. }
  158. } else {
  159. intr_status = readl(&ha->reg->ctrl_status);
  160. if (intr_status & INTR_PENDING) {
  161. /*
  162. * Service the interrupt.
  163. * The ISR will save the mailbox status
  164. * registers to a temporary storage
  165. * location in the adapter structure.
  166. */
  167. ha->mbox_status_count = outCount;
  168. ha->isp_ops->interrupt_service_routine(
  169. ha, intr_status);
  170. }
  171. }
  172. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  173. msleep(10);
  174. }
  175. }
  176. /* Check for mailbox timeout. */
  177. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  178. if (is_qla8022(ha) &&
  179. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  180. DEBUG2(ql4_printk(KERN_INFO, ha,
  181. "scsi%ld: %s: prematurely completing mbx cmd as "
  182. "firmware recovery detected\n",
  183. ha->host_no, __func__));
  184. goto mbox_exit;
  185. }
  186. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  187. " Scheduling Adapter Reset\n", ha->host_no,
  188. mbx_cmd[0]));
  189. ha->mailbox_timeout_count++;
  190. mbx_sts[0] = (-1);
  191. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  192. goto mbox_exit;
  193. }
  194. /*
  195. * Copy the mailbox out registers to the caller's mailbox in/out
  196. * structure.
  197. */
  198. spin_lock_irqsave(&ha->hardware_lock, flags);
  199. for (i = 0; i < outCount; i++)
  200. mbx_sts[i] = ha->mbox_status[i];
  201. /* Set return status and error flags (if applicable). */
  202. switch (ha->mbox_status[0]) {
  203. case MBOX_STS_COMMAND_COMPLETE:
  204. status = QLA_SUCCESS;
  205. break;
  206. case MBOX_STS_INTERMEDIATE_COMPLETION:
  207. status = QLA_SUCCESS;
  208. break;
  209. case MBOX_STS_BUSY:
  210. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  211. ha->host_no, __func__, mbx_cmd[0]));
  212. ha->mailbox_timeout_count++;
  213. break;
  214. default:
  215. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  216. "sts = %08X ****\n", ha->host_no, __func__,
  217. mbx_cmd[0], mbx_sts[0]));
  218. break;
  219. }
  220. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  221. mbox_exit:
  222. mutex_lock(&ha->mbox_sem);
  223. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  224. mutex_unlock(&ha->mbox_sem);
  225. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  226. return status;
  227. }
  228. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  229. {
  230. set_bit(AF_FW_RECOVERY, &ha->flags);
  231. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  232. ha->host_no, __func__);
  233. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  234. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  235. complete(&ha->mbx_intr_comp);
  236. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  237. "recovery, doing premature completion of "
  238. "mbx cmd\n", ha->host_no, __func__);
  239. } else {
  240. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  241. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  242. "recovery, doing premature completion of "
  243. "polling mbx cmd\n", ha->host_no, __func__);
  244. }
  245. }
  246. }
  247. static uint8_t
  248. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  249. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  250. {
  251. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  252. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  253. if (is_qla8022(ha))
  254. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  255. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  256. mbox_cmd[1] = 0;
  257. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  258. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  259. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  260. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  261. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  262. QLA_SUCCESS) {
  263. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  264. "MBOX_CMD_INITIALIZE_FIRMWARE"
  265. " failed w/ status %04X\n",
  266. ha->host_no, __func__, mbox_sts[0]));
  267. return QLA_ERROR;
  268. }
  269. return QLA_SUCCESS;
  270. }
  271. uint8_t
  272. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  273. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  274. {
  275. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  276. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  277. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  278. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  279. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  280. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  281. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  282. QLA_SUCCESS) {
  283. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  284. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  285. " failed w/ status %04X\n",
  286. ha->host_no, __func__, mbox_sts[0]));
  287. return QLA_ERROR;
  288. }
  289. return QLA_SUCCESS;
  290. }
  291. static void
  292. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  293. struct addr_ctrl_blk *init_fw_cb)
  294. {
  295. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  296. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  297. ha->ip_config.ipv4_addr_state =
  298. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  299. if (ha->acb_version == ACB_SUPPORTED) {
  300. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  301. ha->ip_config.ipv6_addl_options =
  302. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  303. }
  304. /* Save IPv4 Address Info */
  305. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  306. min(sizeof(ha->ip_config.ip_address),
  307. sizeof(init_fw_cb->ipv4_addr)));
  308. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  309. min(sizeof(ha->ip_config.subnet_mask),
  310. sizeof(init_fw_cb->ipv4_subnet)));
  311. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  312. min(sizeof(ha->ip_config.gateway),
  313. sizeof(init_fw_cb->ipv4_gw_addr)));
  314. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  315. if (is_ipv6_enabled(ha)) {
  316. /* Save IPv6 Address */
  317. ha->ip_config.ipv6_link_local_state =
  318. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  319. ha->ip_config.ipv6_addr0_state =
  320. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  321. ha->ip_config.ipv6_addr1_state =
  322. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  323. ha->ip_config.ipv6_default_router_state =
  324. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  325. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  326. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  327. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  328. init_fw_cb->ipv6_if_id,
  329. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  330. sizeof(init_fw_cb->ipv6_if_id)));
  331. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  332. min(sizeof(ha->ip_config.ipv6_addr0),
  333. sizeof(init_fw_cb->ipv6_addr0)));
  334. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  335. min(sizeof(ha->ip_config.ipv6_addr1),
  336. sizeof(init_fw_cb->ipv6_addr1)));
  337. memcpy(&ha->ip_config.ipv6_default_router_addr,
  338. init_fw_cb->ipv6_dflt_rtr_addr,
  339. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  340. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  341. ha->ip_config.ipv6_vlan_tag =
  342. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  343. }
  344. }
  345. uint8_t
  346. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  347. uint32_t *mbox_cmd,
  348. uint32_t *mbox_sts,
  349. struct addr_ctrl_blk *init_fw_cb,
  350. dma_addr_t init_fw_cb_dma)
  351. {
  352. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  353. != QLA_SUCCESS) {
  354. DEBUG2(printk(KERN_WARNING
  355. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  356. ha->host_no, __func__));
  357. return QLA_ERROR;
  358. }
  359. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  360. /* Save some info in adapter structure. */
  361. ha->acb_version = init_fw_cb->acb_version;
  362. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  363. ha->heartbeat_interval = init_fw_cb->hb_interval;
  364. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  365. min(sizeof(ha->name_string),
  366. sizeof(init_fw_cb->iscsi_name)));
  367. /*memcpy(ha->alias, init_fw_cb->Alias,
  368. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  369. qla4xxx_update_local_ip(ha, init_fw_cb);
  370. return QLA_SUCCESS;
  371. }
  372. /**
  373. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  374. * @ha: Pointer to host adapter structure.
  375. **/
  376. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  377. {
  378. struct addr_ctrl_blk *init_fw_cb;
  379. dma_addr_t init_fw_cb_dma;
  380. uint32_t mbox_cmd[MBOX_REG_COUNT];
  381. uint32_t mbox_sts[MBOX_REG_COUNT];
  382. int status = QLA_ERROR;
  383. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  384. sizeof(struct addr_ctrl_blk),
  385. &init_fw_cb_dma, GFP_KERNEL);
  386. if (init_fw_cb == NULL) {
  387. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  388. ha->host_no, __func__));
  389. goto exit_init_fw_cb_no_free;
  390. }
  391. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  392. /* Get Initialize Firmware Control Block. */
  393. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  394. memset(&mbox_sts, 0, sizeof(mbox_sts));
  395. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  396. QLA_SUCCESS) {
  397. dma_free_coherent(&ha->pdev->dev,
  398. sizeof(struct addr_ctrl_blk),
  399. init_fw_cb, init_fw_cb_dma);
  400. goto exit_init_fw_cb;
  401. }
  402. /* Initialize request and response queues. */
  403. qla4xxx_init_rings(ha);
  404. /* Fill in the request and response queue information. */
  405. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  406. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  407. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  408. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  409. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  410. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  411. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  412. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  413. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  414. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  415. /* Set up required options. */
  416. init_fw_cb->fw_options |=
  417. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  418. FWOPT_INITIATOR_MODE);
  419. if (is_qla8022(ha))
  420. init_fw_cb->fw_options |=
  421. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  422. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  423. init_fw_cb->add_fw_options = 0;
  424. init_fw_cb->add_fw_options |=
  425. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  426. init_fw_cb->add_fw_options |=
  427. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  428. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  429. != QLA_SUCCESS) {
  430. DEBUG2(printk(KERN_WARNING
  431. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  432. ha->host_no, __func__));
  433. goto exit_init_fw_cb;
  434. }
  435. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  436. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  437. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  438. ha->host_no, __func__));
  439. goto exit_init_fw_cb;
  440. }
  441. status = QLA_SUCCESS;
  442. exit_init_fw_cb:
  443. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  444. init_fw_cb, init_fw_cb_dma);
  445. exit_init_fw_cb_no_free:
  446. return status;
  447. }
  448. /**
  449. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  450. * @ha: Pointer to host adapter structure.
  451. **/
  452. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  453. {
  454. struct addr_ctrl_blk *init_fw_cb;
  455. dma_addr_t init_fw_cb_dma;
  456. uint32_t mbox_cmd[MBOX_REG_COUNT];
  457. uint32_t mbox_sts[MBOX_REG_COUNT];
  458. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  459. sizeof(struct addr_ctrl_blk),
  460. &init_fw_cb_dma, GFP_KERNEL);
  461. if (init_fw_cb == NULL) {
  462. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  463. __func__);
  464. return QLA_ERROR;
  465. }
  466. /* Get Initialize Firmware Control Block. */
  467. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  468. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  469. QLA_SUCCESS) {
  470. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  471. ha->host_no, __func__));
  472. dma_free_coherent(&ha->pdev->dev,
  473. sizeof(struct addr_ctrl_blk),
  474. init_fw_cb, init_fw_cb_dma);
  475. return QLA_ERROR;
  476. }
  477. /* Save IP Address. */
  478. qla4xxx_update_local_ip(ha, init_fw_cb);
  479. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  480. init_fw_cb, init_fw_cb_dma);
  481. return QLA_SUCCESS;
  482. }
  483. /**
  484. * qla4xxx_get_firmware_state - gets firmware state of HBA
  485. * @ha: Pointer to host adapter structure.
  486. **/
  487. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  488. {
  489. uint32_t mbox_cmd[MBOX_REG_COUNT];
  490. uint32_t mbox_sts[MBOX_REG_COUNT];
  491. /* Get firmware version */
  492. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  493. memset(&mbox_sts, 0, sizeof(mbox_sts));
  494. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  495. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  496. QLA_SUCCESS) {
  497. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  498. "status %04X\n", ha->host_no, __func__,
  499. mbox_sts[0]));
  500. return QLA_ERROR;
  501. }
  502. ha->firmware_state = mbox_sts[1];
  503. ha->board_id = mbox_sts[2];
  504. ha->addl_fw_state = mbox_sts[3];
  505. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  506. ha->host_no, __func__, ha->firmware_state);)
  507. return QLA_SUCCESS;
  508. }
  509. /**
  510. * qla4xxx_get_firmware_status - retrieves firmware status
  511. * @ha: Pointer to host adapter structure.
  512. **/
  513. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  514. {
  515. uint32_t mbox_cmd[MBOX_REG_COUNT];
  516. uint32_t mbox_sts[MBOX_REG_COUNT];
  517. /* Get firmware version */
  518. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  519. memset(&mbox_sts, 0, sizeof(mbox_sts));
  520. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  521. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  522. QLA_SUCCESS) {
  523. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  524. "status %04X\n", ha->host_no, __func__,
  525. mbox_sts[0]));
  526. return QLA_ERROR;
  527. }
  528. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  529. ha->host_no, mbox_sts[2]);
  530. return QLA_SUCCESS;
  531. }
  532. /**
  533. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  534. * @ha: Pointer to host adapter structure.
  535. * @fw_ddb_index: Firmware's device database index
  536. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  537. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  538. * @next_ddb_index: Pointer to next valid device database index
  539. * @fw_ddb_device_state: Pointer to device state
  540. **/
  541. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  542. uint16_t fw_ddb_index,
  543. struct dev_db_entry *fw_ddb_entry,
  544. dma_addr_t fw_ddb_entry_dma,
  545. uint32_t *num_valid_ddb_entries,
  546. uint32_t *next_ddb_index,
  547. uint32_t *fw_ddb_device_state,
  548. uint32_t *conn_err_detail,
  549. uint16_t *tcp_source_port_num,
  550. uint16_t *connection_id)
  551. {
  552. int status = QLA_ERROR;
  553. uint16_t options;
  554. uint32_t mbox_cmd[MBOX_REG_COUNT];
  555. uint32_t mbox_sts[MBOX_REG_COUNT];
  556. /* Make sure the device index is valid */
  557. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  558. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  559. ha->host_no, __func__, fw_ddb_index));
  560. goto exit_get_fwddb;
  561. }
  562. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  563. memset(&mbox_sts, 0, sizeof(mbox_sts));
  564. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  565. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  566. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  567. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  568. mbox_cmd[4] = sizeof(struct dev_db_entry);
  569. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  570. QLA_ERROR) {
  571. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  572. " with status 0x%04X\n", ha->host_no, __func__,
  573. mbox_sts[0]));
  574. goto exit_get_fwddb;
  575. }
  576. if (fw_ddb_index != mbox_sts[1]) {
  577. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  578. ha->host_no, __func__, fw_ddb_index,
  579. mbox_sts[1]));
  580. goto exit_get_fwddb;
  581. }
  582. if (fw_ddb_entry) {
  583. options = le16_to_cpu(fw_ddb_entry->options);
  584. if (options & DDB_OPT_IPV6_DEVICE) {
  585. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  586. "Next %d State %04x ConnErr %08x %pI6 "
  587. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  588. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  589. mbox_sts[4], mbox_sts[5],
  590. fw_ddb_entry->ip_addr,
  591. le16_to_cpu(fw_ddb_entry->port),
  592. fw_ddb_entry->iscsi_name);
  593. } else {
  594. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  595. "Next %d State %04x ConnErr %08x %pI4 "
  596. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  597. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  598. mbox_sts[4], mbox_sts[5],
  599. fw_ddb_entry->ip_addr,
  600. le16_to_cpu(fw_ddb_entry->port),
  601. fw_ddb_entry->iscsi_name);
  602. }
  603. }
  604. if (num_valid_ddb_entries)
  605. *num_valid_ddb_entries = mbox_sts[2];
  606. if (next_ddb_index)
  607. *next_ddb_index = mbox_sts[3];
  608. if (fw_ddb_device_state)
  609. *fw_ddb_device_state = mbox_sts[4];
  610. /*
  611. * RA: This mailbox has been changed to pass connection error and
  612. * details. Its true for ISP4010 as per Version E - Not sure when it
  613. * was changed. Get the time2wait from the fw_dd_entry field :
  614. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  615. * struct.
  616. */
  617. if (conn_err_detail)
  618. *conn_err_detail = mbox_sts[5];
  619. if (tcp_source_port_num)
  620. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  621. if (connection_id)
  622. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  623. status = QLA_SUCCESS;
  624. exit_get_fwddb:
  625. return status;
  626. }
  627. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  628. {
  629. uint32_t mbox_cmd[MBOX_REG_COUNT];
  630. uint32_t mbox_sts[MBOX_REG_COUNT];
  631. int status;
  632. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  633. memset(&mbox_sts, 0, sizeof(mbox_sts));
  634. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  635. mbox_cmd[1] = fw_ddb_index;
  636. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  637. &mbox_sts[0]);
  638. DEBUG2(ql4_printk(KERN_INFO, ha,
  639. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  640. __func__, status, mbox_sts[0], mbox_sts[1]));
  641. return status;
  642. }
  643. /**
  644. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  645. * @ha: Pointer to host adapter structure.
  646. * @fw_ddb_index: Firmware's device database index
  647. * @fw_ddb_entry_dma: dma address of ddb entry
  648. * @mbx_sts: mailbox 0 to be returned or NULL
  649. *
  650. * This routine initializes or updates the adapter's device database
  651. * entry for the specified device.
  652. **/
  653. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  654. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  655. {
  656. uint32_t mbox_cmd[MBOX_REG_COUNT];
  657. uint32_t mbox_sts[MBOX_REG_COUNT];
  658. int status;
  659. /* Do not wait for completion. The firmware will send us an
  660. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  661. */
  662. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  663. memset(&mbox_sts, 0, sizeof(mbox_sts));
  664. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  665. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  666. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  667. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  668. mbox_cmd[4] = sizeof(struct dev_db_entry);
  669. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  670. &mbox_sts[0]);
  671. if (mbx_sts)
  672. *mbx_sts = mbox_sts[0];
  673. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  674. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  675. return status;
  676. }
  677. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  678. struct ddb_entry *ddb_entry, int options)
  679. {
  680. int status;
  681. uint32_t mbox_cmd[MBOX_REG_COUNT];
  682. uint32_t mbox_sts[MBOX_REG_COUNT];
  683. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  684. memset(&mbox_sts, 0, sizeof(mbox_sts));
  685. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  686. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  687. mbox_cmd[3] = options;
  688. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  689. &mbox_sts[0]);
  690. if (status != QLA_SUCCESS) {
  691. DEBUG2(ql4_printk(KERN_INFO, ha,
  692. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  693. "failed sts %04X %04X", __func__,
  694. mbox_sts[0], mbox_sts[1]));
  695. }
  696. return status;
  697. }
  698. /**
  699. * qla4xxx_get_crash_record - retrieves crash record.
  700. * @ha: Pointer to host adapter structure.
  701. *
  702. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  703. **/
  704. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  705. {
  706. uint32_t mbox_cmd[MBOX_REG_COUNT];
  707. uint32_t mbox_sts[MBOX_REG_COUNT];
  708. struct crash_record *crash_record = NULL;
  709. dma_addr_t crash_record_dma = 0;
  710. uint32_t crash_record_size = 0;
  711. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  712. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  713. /* Get size of crash record. */
  714. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  715. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  716. QLA_SUCCESS) {
  717. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  718. ha->host_no, __func__));
  719. goto exit_get_crash_record;
  720. }
  721. crash_record_size = mbox_sts[4];
  722. if (crash_record_size == 0) {
  723. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  724. ha->host_no, __func__));
  725. goto exit_get_crash_record;
  726. }
  727. /* Alloc Memory for Crash Record. */
  728. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  729. &crash_record_dma, GFP_KERNEL);
  730. if (crash_record == NULL)
  731. goto exit_get_crash_record;
  732. /* Get Crash Record. */
  733. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  734. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  735. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  736. mbox_cmd[2] = LSDW(crash_record_dma);
  737. mbox_cmd[3] = MSDW(crash_record_dma);
  738. mbox_cmd[4] = crash_record_size;
  739. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  740. QLA_SUCCESS)
  741. goto exit_get_crash_record;
  742. /* Dump Crash Record. */
  743. exit_get_crash_record:
  744. if (crash_record)
  745. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  746. crash_record, crash_record_dma);
  747. }
  748. /**
  749. * qla4xxx_get_conn_event_log - retrieves connection event log
  750. * @ha: Pointer to host adapter structure.
  751. **/
  752. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  753. {
  754. uint32_t mbox_cmd[MBOX_REG_COUNT];
  755. uint32_t mbox_sts[MBOX_REG_COUNT];
  756. struct conn_event_log_entry *event_log = NULL;
  757. dma_addr_t event_log_dma = 0;
  758. uint32_t event_log_size = 0;
  759. uint32_t num_valid_entries;
  760. uint32_t oldest_entry = 0;
  761. uint32_t max_event_log_entries;
  762. uint8_t i;
  763. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  764. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  765. /* Get size of crash record. */
  766. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  767. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  768. QLA_SUCCESS)
  769. goto exit_get_event_log;
  770. event_log_size = mbox_sts[4];
  771. if (event_log_size == 0)
  772. goto exit_get_event_log;
  773. /* Alloc Memory for Crash Record. */
  774. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  775. &event_log_dma, GFP_KERNEL);
  776. if (event_log == NULL)
  777. goto exit_get_event_log;
  778. /* Get Crash Record. */
  779. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  780. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  781. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  782. mbox_cmd[2] = LSDW(event_log_dma);
  783. mbox_cmd[3] = MSDW(event_log_dma);
  784. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  785. QLA_SUCCESS) {
  786. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  787. "log!\n", ha->host_no, __func__));
  788. goto exit_get_event_log;
  789. }
  790. /* Dump Event Log. */
  791. num_valid_entries = mbox_sts[1];
  792. max_event_log_entries = event_log_size /
  793. sizeof(struct conn_event_log_entry);
  794. if (num_valid_entries > max_event_log_entries)
  795. oldest_entry = num_valid_entries % max_event_log_entries;
  796. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  797. ha->host_no, num_valid_entries));
  798. if (ql4xextended_error_logging == 3) {
  799. if (oldest_entry == 0) {
  800. /* Circular Buffer has not wrapped around */
  801. for (i=0; i < num_valid_entries; i++) {
  802. qla4xxx_dump_buffer((uint8_t *)event_log+
  803. (i*sizeof(*event_log)),
  804. sizeof(*event_log));
  805. }
  806. }
  807. else {
  808. /* Circular Buffer has wrapped around -
  809. * display accordingly*/
  810. for (i=oldest_entry; i < max_event_log_entries; i++) {
  811. qla4xxx_dump_buffer((uint8_t *)event_log+
  812. (i*sizeof(*event_log)),
  813. sizeof(*event_log));
  814. }
  815. for (i=0; i < oldest_entry; i++) {
  816. qla4xxx_dump_buffer((uint8_t *)event_log+
  817. (i*sizeof(*event_log)),
  818. sizeof(*event_log));
  819. }
  820. }
  821. }
  822. exit_get_event_log:
  823. if (event_log)
  824. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  825. event_log_dma);
  826. }
  827. /**
  828. * qla4xxx_abort_task - issues Abort Task
  829. * @ha: Pointer to host adapter structure.
  830. * @srb: Pointer to srb entry
  831. *
  832. * This routine performs a LUN RESET on the specified target/lun.
  833. * The caller must ensure that the ddb_entry and lun_entry pointers
  834. * are valid before calling this routine.
  835. **/
  836. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  837. {
  838. uint32_t mbox_cmd[MBOX_REG_COUNT];
  839. uint32_t mbox_sts[MBOX_REG_COUNT];
  840. struct scsi_cmnd *cmd = srb->cmd;
  841. int status = QLA_SUCCESS;
  842. unsigned long flags = 0;
  843. uint32_t index;
  844. /*
  845. * Send abort task command to ISP, so that the ISP will return
  846. * request with ABORT status
  847. */
  848. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  849. memset(&mbox_sts, 0, sizeof(mbox_sts));
  850. spin_lock_irqsave(&ha->hardware_lock, flags);
  851. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  852. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  853. /* Firmware already posted completion on response queue */
  854. if (index == MAX_SRBS)
  855. return status;
  856. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  857. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  858. mbox_cmd[2] = index;
  859. /* Immediate Command Enable */
  860. mbox_cmd[5] = 0x01;
  861. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  862. &mbox_sts[0]);
  863. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  864. status = QLA_ERROR;
  865. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  866. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  867. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  868. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  869. }
  870. return status;
  871. }
  872. /**
  873. * qla4xxx_reset_lun - issues LUN Reset
  874. * @ha: Pointer to host adapter structure.
  875. * @ddb_entry: Pointer to device database entry
  876. * @lun: lun number
  877. *
  878. * This routine performs a LUN RESET on the specified target/lun.
  879. * The caller must ensure that the ddb_entry and lun_entry pointers
  880. * are valid before calling this routine.
  881. **/
  882. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  883. int lun)
  884. {
  885. uint32_t mbox_cmd[MBOX_REG_COUNT];
  886. uint32_t mbox_sts[MBOX_REG_COUNT];
  887. int status = QLA_SUCCESS;
  888. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  889. ddb_entry->fw_ddb_index, lun));
  890. /*
  891. * Send lun reset command to ISP, so that the ISP will return all
  892. * outstanding requests with RESET status
  893. */
  894. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  895. memset(&mbox_sts, 0, sizeof(mbox_sts));
  896. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  897. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  898. mbox_cmd[2] = lun << 8;
  899. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  900. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  901. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  902. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  903. status = QLA_ERROR;
  904. return status;
  905. }
  906. /**
  907. * qla4xxx_reset_target - issues target Reset
  908. * @ha: Pointer to host adapter structure.
  909. * @db_entry: Pointer to device database entry
  910. * @un_entry: Pointer to lun entry structure
  911. *
  912. * This routine performs a TARGET RESET on the specified target.
  913. * The caller must ensure that the ddb_entry pointers
  914. * are valid before calling this routine.
  915. **/
  916. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  917. struct ddb_entry *ddb_entry)
  918. {
  919. uint32_t mbox_cmd[MBOX_REG_COUNT];
  920. uint32_t mbox_sts[MBOX_REG_COUNT];
  921. int status = QLA_SUCCESS;
  922. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  923. ddb_entry->fw_ddb_index));
  924. /*
  925. * Send target reset command to ISP, so that the ISP will return all
  926. * outstanding requests with RESET status
  927. */
  928. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  929. memset(&mbox_sts, 0, sizeof(mbox_sts));
  930. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  931. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  932. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  933. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  934. &mbox_sts[0]);
  935. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  936. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  937. status = QLA_ERROR;
  938. return status;
  939. }
  940. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  941. uint32_t offset, uint32_t len)
  942. {
  943. uint32_t mbox_cmd[MBOX_REG_COUNT];
  944. uint32_t mbox_sts[MBOX_REG_COUNT];
  945. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  946. memset(&mbox_sts, 0, sizeof(mbox_sts));
  947. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  948. mbox_cmd[1] = LSDW(dma_addr);
  949. mbox_cmd[2] = MSDW(dma_addr);
  950. mbox_cmd[3] = offset;
  951. mbox_cmd[4] = len;
  952. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  953. QLA_SUCCESS) {
  954. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  955. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  956. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  957. return QLA_ERROR;
  958. }
  959. return QLA_SUCCESS;
  960. }
  961. /**
  962. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  963. * @ha: Pointer to host adapter structure.
  964. *
  965. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  966. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  967. * those mailboxes, if unused.
  968. **/
  969. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  970. {
  971. struct about_fw_info *about_fw = NULL;
  972. dma_addr_t about_fw_dma;
  973. uint32_t mbox_cmd[MBOX_REG_COUNT];
  974. uint32_t mbox_sts[MBOX_REG_COUNT];
  975. int status = QLA_ERROR;
  976. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  977. sizeof(struct about_fw_info),
  978. &about_fw_dma, GFP_KERNEL);
  979. if (!about_fw) {
  980. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  981. "for about_fw\n", __func__));
  982. return status;
  983. }
  984. memset(about_fw, 0, sizeof(struct about_fw_info));
  985. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  986. memset(&mbox_sts, 0, sizeof(mbox_sts));
  987. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  988. mbox_cmd[2] = LSDW(about_fw_dma);
  989. mbox_cmd[3] = MSDW(about_fw_dma);
  990. mbox_cmd[4] = sizeof(struct about_fw_info);
  991. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  992. &mbox_cmd[0], &mbox_sts[0]);
  993. if (status != QLA_SUCCESS) {
  994. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  995. "failed w/ status %04X\n", __func__,
  996. mbox_sts[0]));
  997. goto exit_about_fw;
  998. }
  999. /* Save version information. */
  1000. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  1001. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  1002. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  1003. ha->build_number = le16_to_cpu(about_fw->fw_build);
  1004. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1005. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1006. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  1007. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1008. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1009. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  1010. status = QLA_SUCCESS;
  1011. exit_about_fw:
  1012. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1013. about_fw, about_fw_dma);
  1014. return status;
  1015. }
  1016. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1017. dma_addr_t dma_addr)
  1018. {
  1019. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1020. uint32_t mbox_sts[MBOX_REG_COUNT];
  1021. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1022. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1023. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1024. mbox_cmd[1] = options;
  1025. mbox_cmd[2] = LSDW(dma_addr);
  1026. mbox_cmd[3] = MSDW(dma_addr);
  1027. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1028. QLA_SUCCESS) {
  1029. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1030. ha->host_no, __func__, mbox_sts[0]));
  1031. return QLA_ERROR;
  1032. }
  1033. return QLA_SUCCESS;
  1034. }
  1035. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1036. uint32_t *mbx_sts)
  1037. {
  1038. int status;
  1039. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1040. uint32_t mbox_sts[MBOX_REG_COUNT];
  1041. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1042. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1043. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1044. mbox_cmd[1] = ddb_index;
  1045. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1046. &mbox_sts[0]);
  1047. if (status != QLA_SUCCESS) {
  1048. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1049. __func__, mbox_sts[0]));
  1050. }
  1051. *mbx_sts = mbox_sts[0];
  1052. return status;
  1053. }
  1054. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  1055. {
  1056. struct dev_db_entry *fw_ddb_entry;
  1057. dma_addr_t fw_ddb_entry_dma;
  1058. uint32_t ddb_index;
  1059. uint32_t mbx_sts;
  1060. uint32_t options = 0;
  1061. int ret_val = QLA_SUCCESS;
  1062. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  1063. sizeof(*fw_ddb_entry),
  1064. &fw_ddb_entry_dma, GFP_KERNEL);
  1065. if (!fw_ddb_entry) {
  1066. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  1067. ha->host_no, __func__));
  1068. ret_val = QLA_ERROR;
  1069. goto exit_send_tgts_no_free;
  1070. }
  1071. ret_val = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1072. if (ret_val != QLA_SUCCESS)
  1073. goto exit_send_tgts;
  1074. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index, &mbx_sts);
  1075. if (ret_val != QLA_SUCCESS)
  1076. goto exit_send_tgts;
  1077. memset(fw_ddb_entry->iscsi_alias, 0,
  1078. sizeof(fw_ddb_entry->iscsi_alias));
  1079. memset(fw_ddb_entry->iscsi_name, 0,
  1080. sizeof(fw_ddb_entry->iscsi_name));
  1081. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1082. memset(fw_ddb_entry->tgt_addr, 0,
  1083. sizeof(fw_ddb_entry->tgt_addr));
  1084. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1085. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1086. fw_ddb_entry->ip_addr[0] = *ip;
  1087. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1088. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1089. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1090. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma, NULL);
  1091. exit_send_tgts:
  1092. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1093. fw_ddb_entry, fw_ddb_entry_dma);
  1094. exit_send_tgts_no_free:
  1095. return ret_val;
  1096. }
  1097. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1098. {
  1099. int status;
  1100. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1101. uint32_t mbox_sts[MBOX_REG_COUNT];
  1102. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1103. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1104. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1105. mbox_cmd[1] = ddb_index;
  1106. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1107. &mbox_sts[0]);
  1108. if (status != QLA_SUCCESS) {
  1109. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1110. __func__, mbox_sts[0]));
  1111. }
  1112. return status;
  1113. }
  1114. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1115. uint32_t offset, uint32_t length, uint32_t options)
  1116. {
  1117. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1118. uint32_t mbox_sts[MBOX_REG_COUNT];
  1119. int status = QLA_SUCCESS;
  1120. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1121. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1122. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1123. mbox_cmd[1] = LSDW(dma_addr);
  1124. mbox_cmd[2] = MSDW(dma_addr);
  1125. mbox_cmd[3] = offset;
  1126. mbox_cmd[4] = length;
  1127. mbox_cmd[5] = options;
  1128. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1129. if (status != QLA_SUCCESS) {
  1130. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1131. "failed w/ status %04X, mbx1 %04X\n",
  1132. __func__, mbox_sts[0], mbox_sts[1]));
  1133. }
  1134. return status;
  1135. }
  1136. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1137. char *password, uint16_t idx, int bidi)
  1138. {
  1139. int ret = 0;
  1140. int rval = QLA_ERROR;
  1141. uint32_t offset = 0;
  1142. struct ql4_chap_table *chap_table;
  1143. dma_addr_t chap_dma;
  1144. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1145. if (chap_table == NULL) {
  1146. ret = -ENOMEM;
  1147. goto exit_set_chap;
  1148. }
  1149. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1150. if (bidi)
  1151. chap_table->flags |= BIT_6; /* peer */
  1152. else
  1153. chap_table->flags |= BIT_7; /* local */
  1154. chap_table->secret_len = strlen(password);
  1155. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1156. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1157. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1158. offset = 0x06000000 | (idx * sizeof(struct ql4_chap_table));
  1159. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1160. sizeof(struct ql4_chap_table),
  1161. FLASH_OPT_RMW_COMMIT);
  1162. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1163. if (rval != QLA_SUCCESS)
  1164. ret = -EINVAL;
  1165. exit_set_chap:
  1166. return ret;
  1167. }
  1168. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1169. uint16_t fw_ddb_index,
  1170. uint16_t connection_id,
  1171. uint16_t option)
  1172. {
  1173. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1174. uint32_t mbox_sts[MBOX_REG_COUNT];
  1175. int status = QLA_SUCCESS;
  1176. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1177. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1178. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1179. mbox_cmd[1] = fw_ddb_index;
  1180. mbox_cmd[2] = connection_id;
  1181. mbox_cmd[3] = option;
  1182. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1183. if (status != QLA_SUCCESS) {
  1184. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1185. "option %04x failed w/ status %04X %04X\n",
  1186. __func__, option, mbox_sts[0], mbox_sts[1]));
  1187. }
  1188. return status;
  1189. }
  1190. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1191. {
  1192. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1193. uint32_t mbox_sts[MBOX_REG_COUNT];
  1194. int status = QLA_SUCCESS;
  1195. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1196. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1197. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1198. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1199. if (status != QLA_SUCCESS) {
  1200. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1201. "failed w/ status %04X %04X %04X", __func__,
  1202. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1203. }
  1204. return status;
  1205. }
  1206. int qla4xxx_get_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1207. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1208. {
  1209. int status = QLA_SUCCESS;
  1210. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1211. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1212. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1213. mbox_cmd[1] = 0; /* Primary ACB */
  1214. mbox_cmd[2] = LSDW(acb_dma);
  1215. mbox_cmd[3] = MSDW(acb_dma);
  1216. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1217. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1218. if (status != QLA_SUCCESS) {
  1219. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1220. "failed w/ status %04X\n", __func__,
  1221. mbox_sts[0]));
  1222. }
  1223. return status;
  1224. }
  1225. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1226. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1227. {
  1228. int status = QLA_SUCCESS;
  1229. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1230. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1231. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1232. mbox_cmd[1] = 0; /* Primary ACB */
  1233. mbox_cmd[2] = LSDW(acb_dma);
  1234. mbox_cmd[3] = MSDW(acb_dma);
  1235. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1236. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1237. if (status != QLA_SUCCESS) {
  1238. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1239. "failed w/ status %04X\n", __func__,
  1240. mbox_sts[0]));
  1241. }
  1242. return status;
  1243. }
  1244. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1245. struct ddb_entry *ddb_entry,
  1246. struct iscsi_cls_conn *cls_conn,
  1247. uint32_t *mbx_sts)
  1248. {
  1249. struct dev_db_entry *fw_ddb_entry;
  1250. struct iscsi_conn *conn;
  1251. struct iscsi_session *sess;
  1252. struct qla_conn *qla_conn;
  1253. struct sockaddr *dst_addr;
  1254. dma_addr_t fw_ddb_entry_dma;
  1255. int status = QLA_SUCCESS;
  1256. int rval = 0;
  1257. struct sockaddr_in *addr;
  1258. struct sockaddr_in6 *addr6;
  1259. char *ip;
  1260. uint16_t iscsi_opts = 0;
  1261. uint32_t options = 0;
  1262. uint16_t idx;
  1263. int max_chap_entries = 0;
  1264. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1265. &fw_ddb_entry_dma, GFP_KERNEL);
  1266. if (!fw_ddb_entry) {
  1267. DEBUG2(ql4_printk(KERN_ERR, ha,
  1268. "%s: Unable to allocate dma buffer.\n",
  1269. __func__));
  1270. rval = -ENOMEM;
  1271. goto exit_set_param_no_free;
  1272. }
  1273. conn = cls_conn->dd_data;
  1274. qla_conn = conn->dd_data;
  1275. sess = conn->session;
  1276. dst_addr = &qla_conn->qla_ep->dst_addr;
  1277. if (dst_addr->sa_family == AF_INET6)
  1278. options |= IPV6_DEFAULT_DDB_ENTRY;
  1279. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1280. if (status == QLA_ERROR) {
  1281. rval = -EINVAL;
  1282. goto exit_set_param;
  1283. }
  1284. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1285. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1286. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1287. if (sess->targetname != NULL) {
  1288. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1289. min(strlen(sess->targetname),
  1290. sizeof(fw_ddb_entry->iscsi_name)));
  1291. }
  1292. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1293. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1294. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1295. if (dst_addr->sa_family == AF_INET) {
  1296. addr = (struct sockaddr_in *)dst_addr;
  1297. ip = (char *)&addr->sin_addr;
  1298. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1299. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1300. DEBUG2(ql4_printk(KERN_INFO, ha,
  1301. "%s: Destination Address [%pI4]: index [%d]\n",
  1302. __func__, fw_ddb_entry->ip_addr,
  1303. ddb_entry->fw_ddb_index));
  1304. } else if (dst_addr->sa_family == AF_INET6) {
  1305. addr6 = (struct sockaddr_in6 *)dst_addr;
  1306. ip = (char *)&addr6->sin6_addr;
  1307. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1308. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1309. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1310. DEBUG2(ql4_printk(KERN_INFO, ha,
  1311. "%s: Destination Address [%pI6]: index [%d]\n",
  1312. __func__, fw_ddb_entry->ip_addr,
  1313. ddb_entry->fw_ddb_index));
  1314. } else {
  1315. ql4_printk(KERN_ERR, ha,
  1316. "%s: Failed to get IP Address\n",
  1317. __func__);
  1318. rval = -EINVAL;
  1319. goto exit_set_param;
  1320. }
  1321. if (is_qla8022(ha))
  1322. max_chap_entries = MAX_CHAP_ENTRIES_82XX;
  1323. else
  1324. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1325. /* CHAP */
  1326. if (sess->username != NULL && sess->password != NULL) {
  1327. if (strlen(sess->username) && strlen(sess->password)) {
  1328. iscsi_opts |= BIT_7;
  1329. idx = ddb_entry->fw_ddb_index * 2;
  1330. if (idx > max_chap_entries) {
  1331. ql4_printk(KERN_ERR, ha,
  1332. "%s: Invalid ddb or chap index\n",
  1333. __func__);
  1334. rval = -EINVAL;
  1335. goto exit_set_param;
  1336. }
  1337. rval = qla4xxx_set_chap(ha, sess->username,
  1338. sess->password, idx, 0);
  1339. if (rval)
  1340. goto exit_set_param;
  1341. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1342. }
  1343. }
  1344. if (sess->username_in != NULL && sess->password_in != NULL) {
  1345. /* Check if BIDI CHAP */
  1346. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1347. iscsi_opts |= BIT_4;
  1348. idx = (ddb_entry->fw_ddb_index * 2) + 1;
  1349. if (idx > max_chap_entries) {
  1350. ql4_printk(KERN_ERR, ha,
  1351. "%s: Invalid ddb or bidi chap "
  1352. "index\n", __func__);
  1353. rval = -EINVAL;
  1354. goto exit_set_param;
  1355. }
  1356. rval = qla4xxx_set_chap(ha, sess->username_in,
  1357. sess->password_in, idx, 0);
  1358. if (rval)
  1359. goto exit_set_param;
  1360. }
  1361. }
  1362. if (sess->initial_r2t_en)
  1363. iscsi_opts |= BIT_10;
  1364. if (sess->imm_data_en)
  1365. iscsi_opts |= BIT_11;
  1366. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1367. if (conn->max_recv_dlength)
  1368. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1369. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1370. if (sess->max_r2t)
  1371. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1372. if (sess->first_burst)
  1373. fw_ddb_entry->iscsi_first_burst_len =
  1374. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1375. if (sess->max_burst)
  1376. fw_ddb_entry->iscsi_max_burst_len =
  1377. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1378. if (sess->time2wait)
  1379. fw_ddb_entry->iscsi_def_time2wait =
  1380. cpu_to_le16(sess->time2wait);
  1381. if (sess->time2retain)
  1382. fw_ddb_entry->iscsi_def_time2retain =
  1383. cpu_to_le16(sess->time2retain);
  1384. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1385. fw_ddb_entry_dma, mbx_sts);
  1386. if (status != QLA_SUCCESS)
  1387. rval = -EINVAL;
  1388. exit_set_param:
  1389. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1390. fw_ddb_entry, fw_ddb_entry_dma);
  1391. exit_set_param_no_free:
  1392. return rval;
  1393. }
  1394. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1395. uint16_t stats_size, dma_addr_t stats_dma)
  1396. {
  1397. int status = QLA_SUCCESS;
  1398. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1399. uint32_t mbox_sts[MBOX_REG_COUNT];
  1400. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1401. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1402. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1403. mbox_cmd[1] = fw_ddb_index;
  1404. mbox_cmd[2] = LSDW(stats_dma);
  1405. mbox_cmd[3] = MSDW(stats_dma);
  1406. mbox_cmd[4] = stats_size;
  1407. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1408. if (status != QLA_SUCCESS) {
  1409. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1410. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1411. "failed w/ status %04X\n", __func__,
  1412. mbox_sts[0]));
  1413. }
  1414. return status;
  1415. }