qlcnic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2009 - QLogic Corporation.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called "COPYING".
  22. *
  23. */
  24. #include <linux/netdevice.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include "qlcnic.h"
  28. struct crb_addr_pair {
  29. u32 addr;
  30. u32 data;
  31. };
  32. #define QLCNIC_MAX_CRB_XFORM 60
  33. static unsigned int crb_addr_xform[QLCNIC_MAX_CRB_XFORM];
  34. #define crb_addr_transform(name) \
  35. (crb_addr_xform[QLCNIC_HW_PX_MAP_CRB_##name] = \
  36. QLCNIC_HW_CRB_HUB_AGT_ADR_##name << 20)
  37. #define QLCNIC_ADDR_ERROR (0xffffffff)
  38. static void
  39. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  40. struct qlcnic_host_rds_ring *rds_ring);
  41. static void crb_addr_transform_setup(void)
  42. {
  43. crb_addr_transform(XDMA);
  44. crb_addr_transform(TIMR);
  45. crb_addr_transform(SRE);
  46. crb_addr_transform(SQN3);
  47. crb_addr_transform(SQN2);
  48. crb_addr_transform(SQN1);
  49. crb_addr_transform(SQN0);
  50. crb_addr_transform(SQS3);
  51. crb_addr_transform(SQS2);
  52. crb_addr_transform(SQS1);
  53. crb_addr_transform(SQS0);
  54. crb_addr_transform(RPMX7);
  55. crb_addr_transform(RPMX6);
  56. crb_addr_transform(RPMX5);
  57. crb_addr_transform(RPMX4);
  58. crb_addr_transform(RPMX3);
  59. crb_addr_transform(RPMX2);
  60. crb_addr_transform(RPMX1);
  61. crb_addr_transform(RPMX0);
  62. crb_addr_transform(ROMUSB);
  63. crb_addr_transform(SN);
  64. crb_addr_transform(QMN);
  65. crb_addr_transform(QMS);
  66. crb_addr_transform(PGNI);
  67. crb_addr_transform(PGND);
  68. crb_addr_transform(PGN3);
  69. crb_addr_transform(PGN2);
  70. crb_addr_transform(PGN1);
  71. crb_addr_transform(PGN0);
  72. crb_addr_transform(PGSI);
  73. crb_addr_transform(PGSD);
  74. crb_addr_transform(PGS3);
  75. crb_addr_transform(PGS2);
  76. crb_addr_transform(PGS1);
  77. crb_addr_transform(PGS0);
  78. crb_addr_transform(PS);
  79. crb_addr_transform(PH);
  80. crb_addr_transform(NIU);
  81. crb_addr_transform(I2Q);
  82. crb_addr_transform(EG);
  83. crb_addr_transform(MN);
  84. crb_addr_transform(MS);
  85. crb_addr_transform(CAS2);
  86. crb_addr_transform(CAS1);
  87. crb_addr_transform(CAS0);
  88. crb_addr_transform(CAM);
  89. crb_addr_transform(C2C1);
  90. crb_addr_transform(C2C0);
  91. crb_addr_transform(SMB);
  92. crb_addr_transform(OCM0);
  93. crb_addr_transform(I2C0);
  94. }
  95. void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter)
  96. {
  97. struct qlcnic_recv_context *recv_ctx;
  98. struct qlcnic_host_rds_ring *rds_ring;
  99. struct qlcnic_rx_buffer *rx_buf;
  100. int i, ring;
  101. recv_ctx = &adapter->recv_ctx;
  102. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  103. rds_ring = &recv_ctx->rds_rings[ring];
  104. for (i = 0; i < rds_ring->num_desc; ++i) {
  105. rx_buf = &(rds_ring->rx_buf_arr[i]);
  106. if (rx_buf->state == QLCNIC_BUFFER_FREE)
  107. continue;
  108. pci_unmap_single(adapter->pdev,
  109. rx_buf->dma,
  110. rds_ring->dma_size,
  111. PCI_DMA_FROMDEVICE);
  112. if (rx_buf->skb != NULL)
  113. dev_kfree_skb_any(rx_buf->skb);
  114. }
  115. }
  116. }
  117. void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter)
  118. {
  119. struct qlcnic_cmd_buffer *cmd_buf;
  120. struct qlcnic_skb_frag *buffrag;
  121. int i, j;
  122. struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
  123. cmd_buf = tx_ring->cmd_buf_arr;
  124. for (i = 0; i < tx_ring->num_desc; i++) {
  125. buffrag = cmd_buf->frag_array;
  126. if (buffrag->dma) {
  127. pci_unmap_single(adapter->pdev, buffrag->dma,
  128. buffrag->length, PCI_DMA_TODEVICE);
  129. buffrag->dma = 0ULL;
  130. }
  131. for (j = 0; j < cmd_buf->frag_count; j++) {
  132. buffrag++;
  133. if (buffrag->dma) {
  134. pci_unmap_page(adapter->pdev, buffrag->dma,
  135. buffrag->length,
  136. PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. }
  140. if (cmd_buf->skb) {
  141. dev_kfree_skb_any(cmd_buf->skb);
  142. cmd_buf->skb = NULL;
  143. }
  144. cmd_buf++;
  145. }
  146. }
  147. void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter)
  148. {
  149. struct qlcnic_recv_context *recv_ctx;
  150. struct qlcnic_host_rds_ring *rds_ring;
  151. struct qlcnic_host_tx_ring *tx_ring;
  152. int ring;
  153. recv_ctx = &adapter->recv_ctx;
  154. if (recv_ctx->rds_rings == NULL)
  155. goto skip_rds;
  156. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  157. rds_ring = &recv_ctx->rds_rings[ring];
  158. vfree(rds_ring->rx_buf_arr);
  159. rds_ring->rx_buf_arr = NULL;
  160. }
  161. kfree(recv_ctx->rds_rings);
  162. skip_rds:
  163. if (adapter->tx_ring == NULL)
  164. return;
  165. tx_ring = adapter->tx_ring;
  166. vfree(tx_ring->cmd_buf_arr);
  167. kfree(adapter->tx_ring);
  168. }
  169. int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
  170. {
  171. struct qlcnic_recv_context *recv_ctx;
  172. struct qlcnic_host_rds_ring *rds_ring;
  173. struct qlcnic_host_sds_ring *sds_ring;
  174. struct qlcnic_host_tx_ring *tx_ring;
  175. struct qlcnic_rx_buffer *rx_buf;
  176. int ring, i, size;
  177. struct qlcnic_cmd_buffer *cmd_buf_arr;
  178. struct net_device *netdev = adapter->netdev;
  179. size = sizeof(struct qlcnic_host_tx_ring);
  180. tx_ring = kzalloc(size, GFP_KERNEL);
  181. if (tx_ring == NULL) {
  182. dev_err(&netdev->dev, "failed to allocate tx ring struct\n");
  183. return -ENOMEM;
  184. }
  185. adapter->tx_ring = tx_ring;
  186. tx_ring->num_desc = adapter->num_txd;
  187. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  188. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  189. if (cmd_buf_arr == NULL) {
  190. dev_err(&netdev->dev, "failed to allocate cmd buffer ring\n");
  191. return -ENOMEM;
  192. }
  193. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  194. tx_ring->cmd_buf_arr = cmd_buf_arr;
  195. recv_ctx = &adapter->recv_ctx;
  196. size = adapter->max_rds_rings * sizeof(struct qlcnic_host_rds_ring);
  197. rds_ring = kzalloc(size, GFP_KERNEL);
  198. if (rds_ring == NULL) {
  199. dev_err(&netdev->dev, "failed to allocate rds ring struct\n");
  200. return -ENOMEM;
  201. }
  202. recv_ctx->rds_rings = rds_ring;
  203. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  204. rds_ring = &recv_ctx->rds_rings[ring];
  205. switch (ring) {
  206. case RCV_RING_NORMAL:
  207. rds_ring->num_desc = adapter->num_rxd;
  208. rds_ring->dma_size = QLCNIC_P3_RX_BUF_MAX_LEN;
  209. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  210. break;
  211. case RCV_RING_JUMBO:
  212. rds_ring->num_desc = adapter->num_jumbo_rxd;
  213. rds_ring->dma_size =
  214. QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN;
  215. if (adapter->capabilities & QLCNIC_FW_CAPABILITY_HW_LRO)
  216. rds_ring->dma_size += QLCNIC_LRO_BUFFER_EXTRA;
  217. rds_ring->skb_size =
  218. rds_ring->dma_size + NET_IP_ALIGN;
  219. break;
  220. }
  221. rds_ring->rx_buf_arr = (struct qlcnic_rx_buffer *)
  222. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  223. if (rds_ring->rx_buf_arr == NULL) {
  224. dev_err(&netdev->dev, "Failed to allocate "
  225. "rx buffer ring %d\n", ring);
  226. goto err_out;
  227. }
  228. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  229. INIT_LIST_HEAD(&rds_ring->free_list);
  230. /*
  231. * Now go through all of them, set reference handles
  232. * and put them in the queues.
  233. */
  234. rx_buf = rds_ring->rx_buf_arr;
  235. for (i = 0; i < rds_ring->num_desc; i++) {
  236. list_add_tail(&rx_buf->list,
  237. &rds_ring->free_list);
  238. rx_buf->ref_handle = i;
  239. rx_buf->state = QLCNIC_BUFFER_FREE;
  240. rx_buf++;
  241. }
  242. spin_lock_init(&rds_ring->lock);
  243. }
  244. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  245. sds_ring = &recv_ctx->sds_rings[ring];
  246. sds_ring->irq = adapter->msix_entries[ring].vector;
  247. sds_ring->adapter = adapter;
  248. sds_ring->num_desc = adapter->num_rxd;
  249. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  250. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  251. }
  252. return 0;
  253. err_out:
  254. qlcnic_free_sw_resources(adapter);
  255. return -ENOMEM;
  256. }
  257. /*
  258. * Utility to translate from internal Phantom CRB address
  259. * to external PCI CRB address.
  260. */
  261. static u32 qlcnic_decode_crb_addr(u32 addr)
  262. {
  263. int i;
  264. u32 base_addr, offset, pci_base;
  265. crb_addr_transform_setup();
  266. pci_base = QLCNIC_ADDR_ERROR;
  267. base_addr = addr & 0xfff00000;
  268. offset = addr & 0x000fffff;
  269. for (i = 0; i < QLCNIC_MAX_CRB_XFORM; i++) {
  270. if (crb_addr_xform[i] == base_addr) {
  271. pci_base = i << 20;
  272. break;
  273. }
  274. }
  275. if (pci_base == QLCNIC_ADDR_ERROR)
  276. return pci_base;
  277. else
  278. return pci_base + offset;
  279. }
  280. #define QLCNIC_MAX_ROM_WAIT_USEC 100
  281. static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter)
  282. {
  283. long timeout = 0;
  284. long done = 0;
  285. cond_resched();
  286. while (done == 0) {
  287. done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS);
  288. done &= 2;
  289. if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) {
  290. dev_err(&adapter->pdev->dev,
  291. "Timeout reached waiting for rom done");
  292. return -EIO;
  293. }
  294. udelay(1);
  295. }
  296. return 0;
  297. }
  298. static int do_rom_fast_read(struct qlcnic_adapter *adapter,
  299. int addr, int *valp)
  300. {
  301. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr);
  302. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  303. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3);
  304. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  305. if (qlcnic_wait_rom_done(adapter)) {
  306. dev_err(&adapter->pdev->dev, "Error waiting for rom done\n");
  307. return -EIO;
  308. }
  309. /* reset abyte_cnt and dummy_byte_cnt */
  310. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 0);
  311. udelay(10);
  312. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  313. *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA);
  314. return 0;
  315. }
  316. static int do_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  317. u8 *bytes, size_t size)
  318. {
  319. int addridx;
  320. int ret = 0;
  321. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  322. int v;
  323. ret = do_rom_fast_read(adapter, addridx, &v);
  324. if (ret != 0)
  325. break;
  326. *(__le32 *)bytes = cpu_to_le32(v);
  327. bytes += 4;
  328. }
  329. return ret;
  330. }
  331. int
  332. qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  333. u8 *bytes, size_t size)
  334. {
  335. int ret;
  336. ret = qlcnic_rom_lock(adapter);
  337. if (ret < 0)
  338. return ret;
  339. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  340. qlcnic_rom_unlock(adapter);
  341. return ret;
  342. }
  343. int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp)
  344. {
  345. int ret;
  346. if (qlcnic_rom_lock(adapter) != 0)
  347. return -EIO;
  348. ret = do_rom_fast_read(adapter, addr, valp);
  349. qlcnic_rom_unlock(adapter);
  350. return ret;
  351. }
  352. int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
  353. {
  354. int addr, val;
  355. int i, n, init_delay;
  356. struct crb_addr_pair *buf;
  357. unsigned offset;
  358. u32 off;
  359. struct pci_dev *pdev = adapter->pdev;
  360. /* resetall */
  361. qlcnic_rom_lock(adapter);
  362. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xffffffff);
  363. qlcnic_rom_unlock(adapter);
  364. if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
  365. qlcnic_rom_fast_read(adapter, 4, &n) != 0) {
  366. dev_err(&pdev->dev, "ERROR Reading crb_init area: val:%x\n", n);
  367. return -EIO;
  368. }
  369. offset = n & 0xffffU;
  370. n = (n >> 16) & 0xffffU;
  371. if (n >= 1024) {
  372. dev_err(&pdev->dev, "QLOGIC card flash not initialized.\n");
  373. return -EIO;
  374. }
  375. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  376. if (buf == NULL) {
  377. dev_err(&pdev->dev, "Unable to calloc memory for rom read.\n");
  378. return -ENOMEM;
  379. }
  380. for (i = 0; i < n; i++) {
  381. if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  382. qlcnic_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  383. kfree(buf);
  384. return -EIO;
  385. }
  386. buf[i].addr = addr;
  387. buf[i].data = val;
  388. }
  389. for (i = 0; i < n; i++) {
  390. off = qlcnic_decode_crb_addr(buf[i].addr);
  391. if (off == QLCNIC_ADDR_ERROR) {
  392. dev_err(&pdev->dev, "CRB init value out of range %x\n",
  393. buf[i].addr);
  394. continue;
  395. }
  396. off += QLCNIC_PCI_CRBSPACE;
  397. if (off & 1)
  398. continue;
  399. /* skipping cold reboot MAGIC */
  400. if (off == QLCNIC_CAM_RAM(0x1fc))
  401. continue;
  402. if (off == (QLCNIC_CRB_I2C0 + 0x1c))
  403. continue;
  404. if (off == (ROMUSB_GLB + 0xbc)) /* do not reset PCI */
  405. continue;
  406. if (off == (ROMUSB_GLB + 0xa8))
  407. continue;
  408. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  409. continue;
  410. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  411. continue;
  412. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  413. continue;
  414. if ((off & 0x0ff00000) == QLCNIC_CRB_DDR_NET)
  415. continue;
  416. /* skip the function enable register */
  417. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION))
  418. continue;
  419. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION2))
  420. continue;
  421. if ((off & 0x0ff00000) == QLCNIC_CRB_SMB)
  422. continue;
  423. init_delay = 1;
  424. /* After writing this register, HW needs time for CRB */
  425. /* to quiet down (else crb_window returns 0xffffffff) */
  426. if (off == QLCNIC_ROMUSB_GLB_SW_RESET)
  427. init_delay = 1000;
  428. QLCWR32(adapter, off, buf[i].data);
  429. msleep(init_delay);
  430. }
  431. kfree(buf);
  432. /* p2dn replyCount */
  433. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0xec, 0x1e);
  434. /* disable_peg_cache 0 & 1*/
  435. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0x4c, 8);
  436. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_I + 0x4c, 8);
  437. /* peg_clr_all */
  438. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x8, 0);
  439. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0xc, 0);
  440. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x8, 0);
  441. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0xc, 0);
  442. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x8, 0);
  443. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0xc, 0);
  444. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x8, 0);
  445. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
  446. return 0;
  447. }
  448. int
  449. qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
  450. int timeo;
  451. u32 val;
  452. val = QLCRD32(adapter, QLCNIC_CRB_DEV_PARTITION_INFO);
  453. val = (val >> (adapter->portnum * 4)) & 0xf;
  454. if ((val & 0x3) != 1) {
  455. dev_err(&adapter->pdev->dev, "Not an Ethernet NIC func=%u\n",
  456. val);
  457. return -EIO;
  458. }
  459. adapter->physical_port = (val >> 2);
  460. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DEV_INIT_TIMEOUT, &timeo))
  461. timeo = 30;
  462. adapter->dev_init_timeo = timeo;
  463. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DRV_RESET_TIMEOUT, &timeo))
  464. timeo = 10;
  465. adapter->reset_ack_timeo = timeo;
  466. return 0;
  467. }
  468. static int
  469. qlcnic_has_mn(struct qlcnic_adapter *adapter)
  470. {
  471. u32 capability, flashed_ver;
  472. capability = 0;
  473. qlcnic_rom_fast_read(adapter,
  474. QLCNIC_FW_VERSION_OFFSET, (int *)&flashed_ver);
  475. flashed_ver = QLCNIC_DECODE_VERSION(flashed_ver);
  476. capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY);
  477. if (capability & QLCNIC_PEG_TUNE_MN_PRESENT)
  478. return 1;
  479. return 0;
  480. }
  481. static
  482. struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section)
  483. {
  484. u32 i;
  485. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  486. __le32 entries = cpu_to_le32(directory->num_entries);
  487. for (i = 0; i < entries; i++) {
  488. __le32 offs = cpu_to_le32(directory->findex) +
  489. (i * cpu_to_le32(directory->entry_size));
  490. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  491. if (tab_type == section)
  492. return (struct uni_table_desc *) &unirom[offs];
  493. }
  494. return NULL;
  495. }
  496. #define FILEHEADER_SIZE (14 * 4)
  497. static int
  498. qlcnic_validate_header(struct qlcnic_adapter *adapter)
  499. {
  500. const u8 *unirom = adapter->fw->data;
  501. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  502. __le32 fw_file_size = adapter->fw->size;
  503. __le32 entries;
  504. __le32 entry_size;
  505. __le32 tab_size;
  506. if (fw_file_size < FILEHEADER_SIZE)
  507. return -EINVAL;
  508. entries = cpu_to_le32(directory->num_entries);
  509. entry_size = cpu_to_le32(directory->entry_size);
  510. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  511. if (fw_file_size < tab_size)
  512. return -EINVAL;
  513. return 0;
  514. }
  515. static int
  516. qlcnic_validate_bootld(struct qlcnic_adapter *adapter)
  517. {
  518. struct uni_table_desc *tab_desc;
  519. struct uni_data_desc *descr;
  520. const u8 *unirom = adapter->fw->data;
  521. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  522. QLCNIC_UNI_BOOTLD_IDX_OFF));
  523. __le32 offs;
  524. __le32 tab_size;
  525. __le32 data_size;
  526. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD);
  527. if (!tab_desc)
  528. return -EINVAL;
  529. tab_size = cpu_to_le32(tab_desc->findex) +
  530. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  531. if (adapter->fw->size < tab_size)
  532. return -EINVAL;
  533. offs = cpu_to_le32(tab_desc->findex) +
  534. (cpu_to_le32(tab_desc->entry_size) * (idx));
  535. descr = (struct uni_data_desc *)&unirom[offs];
  536. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  537. if (adapter->fw->size < data_size)
  538. return -EINVAL;
  539. return 0;
  540. }
  541. static int
  542. qlcnic_validate_fw(struct qlcnic_adapter *adapter)
  543. {
  544. struct uni_table_desc *tab_desc;
  545. struct uni_data_desc *descr;
  546. const u8 *unirom = adapter->fw->data;
  547. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  548. QLCNIC_UNI_FIRMWARE_IDX_OFF));
  549. __le32 offs;
  550. __le32 tab_size;
  551. __le32 data_size;
  552. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW);
  553. if (!tab_desc)
  554. return -EINVAL;
  555. tab_size = cpu_to_le32(tab_desc->findex) +
  556. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  557. if (adapter->fw->size < tab_size)
  558. return -EINVAL;
  559. offs = cpu_to_le32(tab_desc->findex) +
  560. (cpu_to_le32(tab_desc->entry_size) * (idx));
  561. descr = (struct uni_data_desc *)&unirom[offs];
  562. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  563. if (adapter->fw->size < data_size)
  564. return -EINVAL;
  565. return 0;
  566. }
  567. static int
  568. qlcnic_validate_product_offs(struct qlcnic_adapter *adapter)
  569. {
  570. struct uni_table_desc *ptab_descr;
  571. const u8 *unirom = adapter->fw->data;
  572. int mn_present = qlcnic_has_mn(adapter);
  573. __le32 entries;
  574. __le32 entry_size;
  575. __le32 tab_size;
  576. u32 i;
  577. ptab_descr = qlcnic_get_table_desc(unirom,
  578. QLCNIC_UNI_DIR_SECT_PRODUCT_TBL);
  579. if (!ptab_descr)
  580. return -EINVAL;
  581. entries = cpu_to_le32(ptab_descr->num_entries);
  582. entry_size = cpu_to_le32(ptab_descr->entry_size);
  583. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  584. if (adapter->fw->size < tab_size)
  585. return -EINVAL;
  586. nomn:
  587. for (i = 0; i < entries; i++) {
  588. __le32 flags, file_chiprev, offs;
  589. u8 chiprev = adapter->ahw.revision_id;
  590. u32 flagbit;
  591. offs = cpu_to_le32(ptab_descr->findex) +
  592. (i * cpu_to_le32(ptab_descr->entry_size));
  593. flags = cpu_to_le32(*((int *)&unirom[offs] +
  594. QLCNIC_UNI_FLAGS_OFF));
  595. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  596. QLCNIC_UNI_CHIP_REV_OFF));
  597. flagbit = mn_present ? 1 : 2;
  598. if ((chiprev == file_chiprev) &&
  599. ((1ULL << flagbit) & flags)) {
  600. adapter->file_prd_off = offs;
  601. return 0;
  602. }
  603. }
  604. if (mn_present) {
  605. mn_present = 0;
  606. goto nomn;
  607. }
  608. return -EINVAL;
  609. }
  610. static int
  611. qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter)
  612. {
  613. if (qlcnic_validate_header(adapter)) {
  614. dev_err(&adapter->pdev->dev,
  615. "unified image: header validation failed\n");
  616. return -EINVAL;
  617. }
  618. if (qlcnic_validate_product_offs(adapter)) {
  619. dev_err(&adapter->pdev->dev,
  620. "unified image: product validation failed\n");
  621. return -EINVAL;
  622. }
  623. if (qlcnic_validate_bootld(adapter)) {
  624. dev_err(&adapter->pdev->dev,
  625. "unified image: bootld validation failed\n");
  626. return -EINVAL;
  627. }
  628. if (qlcnic_validate_fw(adapter)) {
  629. dev_err(&adapter->pdev->dev,
  630. "unified image: firmware validation failed\n");
  631. return -EINVAL;
  632. }
  633. return 0;
  634. }
  635. static
  636. struct uni_data_desc *qlcnic_get_data_desc(struct qlcnic_adapter *adapter,
  637. u32 section, u32 idx_offset)
  638. {
  639. const u8 *unirom = adapter->fw->data;
  640. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  641. idx_offset));
  642. struct uni_table_desc *tab_desc;
  643. __le32 offs;
  644. tab_desc = qlcnic_get_table_desc(unirom, section);
  645. if (tab_desc == NULL)
  646. return NULL;
  647. offs = cpu_to_le32(tab_desc->findex) +
  648. (cpu_to_le32(tab_desc->entry_size) * idx);
  649. return (struct uni_data_desc *)&unirom[offs];
  650. }
  651. static u8 *
  652. qlcnic_get_bootld_offs(struct qlcnic_adapter *adapter)
  653. {
  654. u32 offs = QLCNIC_BOOTLD_START;
  655. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  656. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  657. QLCNIC_UNI_DIR_SECT_BOOTLD,
  658. QLCNIC_UNI_BOOTLD_IDX_OFF))->findex);
  659. return (u8 *)&adapter->fw->data[offs];
  660. }
  661. static u8 *
  662. qlcnic_get_fw_offs(struct qlcnic_adapter *adapter)
  663. {
  664. u32 offs = QLCNIC_IMAGE_START;
  665. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  666. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  667. QLCNIC_UNI_DIR_SECT_FW,
  668. QLCNIC_UNI_FIRMWARE_IDX_OFF))->findex);
  669. return (u8 *)&adapter->fw->data[offs];
  670. }
  671. static __le32
  672. qlcnic_get_fw_size(struct qlcnic_adapter *adapter)
  673. {
  674. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  675. return cpu_to_le32((qlcnic_get_data_desc(adapter,
  676. QLCNIC_UNI_DIR_SECT_FW,
  677. QLCNIC_UNI_FIRMWARE_IDX_OFF))->size);
  678. else
  679. return cpu_to_le32(
  680. *(u32 *)&adapter->fw->data[QLCNIC_FW_SIZE_OFFSET]);
  681. }
  682. static __le32
  683. qlcnic_get_fw_version(struct qlcnic_adapter *adapter)
  684. {
  685. struct uni_data_desc *fw_data_desc;
  686. const struct firmware *fw = adapter->fw;
  687. __le32 major, minor, sub;
  688. const u8 *ver_str;
  689. int i, ret;
  690. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  691. return cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_VERSION_OFFSET]);
  692. fw_data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
  693. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  694. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  695. cpu_to_le32(fw_data_desc->size) - 17;
  696. for (i = 0; i < 12; i++) {
  697. if (!strncmp(&ver_str[i], "REV=", 4)) {
  698. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  699. &major, &minor, &sub);
  700. if (ret != 3)
  701. return 0;
  702. else
  703. return major + (minor << 8) + (sub << 16);
  704. }
  705. }
  706. return 0;
  707. }
  708. static __le32
  709. qlcnic_get_bios_version(struct qlcnic_adapter *adapter)
  710. {
  711. const struct firmware *fw = adapter->fw;
  712. __le32 bios_ver, prd_off = adapter->file_prd_off;
  713. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  714. return cpu_to_le32(
  715. *(u32 *)&fw->data[QLCNIC_BIOS_VERSION_OFFSET]);
  716. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  717. + QLCNIC_UNI_BIOS_VERSION_OFF));
  718. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24);
  719. }
  720. int
  721. qlcnic_need_fw_reset(struct qlcnic_adapter *adapter)
  722. {
  723. u32 count, old_count;
  724. u32 val, version, major, minor, build;
  725. int i, timeout;
  726. if (adapter->need_fw_reset)
  727. return 1;
  728. /* last attempt had failed */
  729. if (QLCRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  730. return 1;
  731. old_count = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  732. for (i = 0; i < 10; i++) {
  733. timeout = msleep_interruptible(200);
  734. if (timeout) {
  735. QLCWR32(adapter, CRB_CMDPEG_STATE,
  736. PHAN_INITIALIZE_FAILED);
  737. return -EINTR;
  738. }
  739. count = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  740. if (count != old_count)
  741. break;
  742. }
  743. /* firmware is dead */
  744. if (count == old_count)
  745. return 1;
  746. /* check if we have got newer or different file firmware */
  747. if (adapter->fw) {
  748. val = qlcnic_get_fw_version(adapter);
  749. version = QLCNIC_DECODE_VERSION(val);
  750. major = QLCRD32(adapter, QLCNIC_FW_VERSION_MAJOR);
  751. minor = QLCRD32(adapter, QLCNIC_FW_VERSION_MINOR);
  752. build = QLCRD32(adapter, QLCNIC_FW_VERSION_SUB);
  753. if (version > QLCNIC_VERSION_CODE(major, minor, build))
  754. return 1;
  755. }
  756. return 0;
  757. }
  758. static const char *fw_name[] = {
  759. QLCNIC_UNIFIED_ROMIMAGE_NAME,
  760. QLCNIC_FLASH_ROMIMAGE_NAME,
  761. };
  762. int
  763. qlcnic_load_firmware(struct qlcnic_adapter *adapter)
  764. {
  765. u64 *ptr64;
  766. u32 i, flashaddr, size;
  767. const struct firmware *fw = adapter->fw;
  768. struct pci_dev *pdev = adapter->pdev;
  769. dev_info(&pdev->dev, "loading firmware from %s\n",
  770. fw_name[adapter->fw_type]);
  771. if (fw) {
  772. __le64 data;
  773. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  774. ptr64 = (u64 *)qlcnic_get_bootld_offs(adapter);
  775. flashaddr = QLCNIC_BOOTLD_START;
  776. for (i = 0; i < size; i++) {
  777. data = cpu_to_le64(ptr64[i]);
  778. if (qlcnic_pci_mem_write_2M(adapter, flashaddr, data))
  779. return -EIO;
  780. flashaddr += 8;
  781. }
  782. size = (__force u32)qlcnic_get_fw_size(adapter) / 8;
  783. ptr64 = (u64 *)qlcnic_get_fw_offs(adapter);
  784. flashaddr = QLCNIC_IMAGE_START;
  785. for (i = 0; i < size; i++) {
  786. data = cpu_to_le64(ptr64[i]);
  787. if (qlcnic_pci_mem_write_2M(adapter,
  788. flashaddr, data))
  789. return -EIO;
  790. flashaddr += 8;
  791. }
  792. size = (__force u32)qlcnic_get_fw_size(adapter) % 8;
  793. if (size) {
  794. data = cpu_to_le64(ptr64[i]);
  795. if (qlcnic_pci_mem_write_2M(adapter,
  796. flashaddr, data))
  797. return -EIO;
  798. }
  799. } else {
  800. u64 data;
  801. u32 hi, lo;
  802. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  803. flashaddr = QLCNIC_BOOTLD_START;
  804. for (i = 0; i < size; i++) {
  805. if (qlcnic_rom_fast_read(adapter,
  806. flashaddr, (int *)&lo) != 0)
  807. return -EIO;
  808. if (qlcnic_rom_fast_read(adapter,
  809. flashaddr + 4, (int *)&hi) != 0)
  810. return -EIO;
  811. data = (((u64)hi << 32) | lo);
  812. if (qlcnic_pci_mem_write_2M(adapter,
  813. flashaddr, data))
  814. return -EIO;
  815. flashaddr += 8;
  816. }
  817. }
  818. msleep(1);
  819. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
  820. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
  821. return 0;
  822. }
  823. static int
  824. qlcnic_validate_firmware(struct qlcnic_adapter *adapter)
  825. {
  826. __le32 val;
  827. u32 ver, min_ver, bios, min_size;
  828. struct pci_dev *pdev = adapter->pdev;
  829. const struct firmware *fw = adapter->fw;
  830. u8 fw_type = adapter->fw_type;
  831. if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) {
  832. if (qlcnic_validate_unified_romimage(adapter))
  833. return -EINVAL;
  834. min_size = QLCNIC_UNI_FW_MIN_SIZE;
  835. } else {
  836. val = cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]);
  837. if ((__force u32)val != QLCNIC_BDINFO_MAGIC)
  838. return -EINVAL;
  839. min_size = QLCNIC_FW_MIN_SIZE;
  840. }
  841. if (fw->size < min_size)
  842. return -EINVAL;
  843. val = qlcnic_get_fw_version(adapter);
  844. min_ver = QLCNIC_VERSION_CODE(4, 0, 216);
  845. ver = QLCNIC_DECODE_VERSION(val);
  846. if ((_major(ver) > _QLCNIC_LINUX_MAJOR) || (ver < min_ver)) {
  847. dev_err(&pdev->dev,
  848. "%s: firmware version %d.%d.%d unsupported\n",
  849. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  850. return -EINVAL;
  851. }
  852. val = qlcnic_get_bios_version(adapter);
  853. qlcnic_rom_fast_read(adapter, QLCNIC_BIOS_VERSION_OFFSET, (int *)&bios);
  854. if ((__force u32)val != bios) {
  855. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  856. fw_name[fw_type]);
  857. return -EINVAL;
  858. }
  859. /* check if flashed firmware is newer */
  860. if (qlcnic_rom_fast_read(adapter,
  861. QLCNIC_FW_VERSION_OFFSET, (int *)&val))
  862. return -EIO;
  863. val = QLCNIC_DECODE_VERSION(val);
  864. if (val > ver) {
  865. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  866. fw_name[fw_type]);
  867. return -EINVAL;
  868. }
  869. QLCWR32(adapter, QLCNIC_CAM_RAM(0x1fc), QLCNIC_BDINFO_MAGIC);
  870. return 0;
  871. }
  872. static void
  873. qlcnic_get_next_fwtype(struct qlcnic_adapter *adapter)
  874. {
  875. u8 fw_type;
  876. switch (adapter->fw_type) {
  877. case QLCNIC_UNKNOWN_ROMIMAGE:
  878. fw_type = QLCNIC_UNIFIED_ROMIMAGE;
  879. break;
  880. case QLCNIC_UNIFIED_ROMIMAGE:
  881. default:
  882. fw_type = QLCNIC_FLASH_ROMIMAGE;
  883. break;
  884. }
  885. adapter->fw_type = fw_type;
  886. }
  887. void qlcnic_request_firmware(struct qlcnic_adapter *adapter)
  888. {
  889. struct pci_dev *pdev = adapter->pdev;
  890. int rc;
  891. adapter->fw_type = QLCNIC_UNKNOWN_ROMIMAGE;
  892. next:
  893. qlcnic_get_next_fwtype(adapter);
  894. if (adapter->fw_type == QLCNIC_FLASH_ROMIMAGE) {
  895. adapter->fw = NULL;
  896. } else {
  897. rc = request_firmware(&adapter->fw,
  898. fw_name[adapter->fw_type], &pdev->dev);
  899. if (rc != 0)
  900. goto next;
  901. rc = qlcnic_validate_firmware(adapter);
  902. if (rc != 0) {
  903. release_firmware(adapter->fw);
  904. msleep(1);
  905. goto next;
  906. }
  907. }
  908. }
  909. void
  910. qlcnic_release_firmware(struct qlcnic_adapter *adapter)
  911. {
  912. if (adapter->fw)
  913. release_firmware(adapter->fw);
  914. adapter->fw = NULL;
  915. }
  916. int qlcnic_phantom_init(struct qlcnic_adapter *adapter)
  917. {
  918. u32 val;
  919. int retries = 60;
  920. do {
  921. val = QLCRD32(adapter, CRB_CMDPEG_STATE);
  922. switch (val) {
  923. case PHAN_INITIALIZE_COMPLETE:
  924. case PHAN_INITIALIZE_ACK:
  925. return 0;
  926. case PHAN_INITIALIZE_FAILED:
  927. goto out_err;
  928. default:
  929. break;
  930. }
  931. msleep(500);
  932. } while (--retries);
  933. QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  934. out_err:
  935. dev_err(&adapter->pdev->dev, "firmware init failed\n");
  936. return -EIO;
  937. }
  938. static int
  939. qlcnic_receive_peg_ready(struct qlcnic_adapter *adapter)
  940. {
  941. u32 val;
  942. int retries = 2000;
  943. do {
  944. val = QLCRD32(adapter, CRB_RCVPEG_STATE);
  945. if (val == PHAN_PEG_RCV_INITIALIZED)
  946. return 0;
  947. msleep(10);
  948. } while (--retries);
  949. if (!retries) {
  950. dev_err(&adapter->pdev->dev, "Receive Peg initialization not "
  951. "complete, state: 0x%x.\n", val);
  952. return -EIO;
  953. }
  954. return 0;
  955. }
  956. int qlcnic_init_firmware(struct qlcnic_adapter *adapter)
  957. {
  958. int err;
  959. err = qlcnic_receive_peg_ready(adapter);
  960. if (err)
  961. return err;
  962. QLCWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  963. QLCWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  964. QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  965. return err;
  966. }
  967. static void
  968. qlcnic_handle_linkevent(struct qlcnic_adapter *adapter,
  969. struct qlcnic_fw_msg *msg)
  970. {
  971. u32 cable_OUI;
  972. u16 cable_len;
  973. u16 link_speed;
  974. u8 link_status, module, duplex, autoneg;
  975. struct net_device *netdev = adapter->netdev;
  976. adapter->has_link_events = 1;
  977. cable_OUI = msg->body[1] & 0xffffffff;
  978. cable_len = (msg->body[1] >> 32) & 0xffff;
  979. link_speed = (msg->body[1] >> 48) & 0xffff;
  980. link_status = msg->body[2] & 0xff;
  981. duplex = (msg->body[2] >> 16) & 0xff;
  982. autoneg = (msg->body[2] >> 24) & 0xff;
  983. module = (msg->body[2] >> 8) & 0xff;
  984. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE)
  985. dev_info(&netdev->dev, "unsupported cable: OUI 0x%x, "
  986. "length %d\n", cable_OUI, cable_len);
  987. else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN)
  988. dev_info(&netdev->dev, "unsupported cable length %d\n",
  989. cable_len);
  990. qlcnic_advert_link_change(adapter, link_status);
  991. if (duplex == LINKEVENT_FULL_DUPLEX)
  992. adapter->link_duplex = DUPLEX_FULL;
  993. else
  994. adapter->link_duplex = DUPLEX_HALF;
  995. adapter->module_type = module;
  996. adapter->link_autoneg = autoneg;
  997. adapter->link_speed = link_speed;
  998. }
  999. static void
  1000. qlcnic_handle_fw_message(int desc_cnt, int index,
  1001. struct qlcnic_host_sds_ring *sds_ring)
  1002. {
  1003. struct qlcnic_fw_msg msg;
  1004. struct status_desc *desc;
  1005. int i = 0, opcode;
  1006. while (desc_cnt > 0 && i < 8) {
  1007. desc = &sds_ring->desc_head[index];
  1008. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1009. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1010. index = get_next_index(index, sds_ring->num_desc);
  1011. desc_cnt--;
  1012. }
  1013. opcode = qlcnic_get_nic_msg_opcode(msg.body[0]);
  1014. switch (opcode) {
  1015. case QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1016. qlcnic_handle_linkevent(sds_ring->adapter, &msg);
  1017. break;
  1018. default:
  1019. break;
  1020. }
  1021. }
  1022. static int
  1023. qlcnic_alloc_rx_skb(struct qlcnic_adapter *adapter,
  1024. struct qlcnic_host_rds_ring *rds_ring,
  1025. struct qlcnic_rx_buffer *buffer)
  1026. {
  1027. struct sk_buff *skb;
  1028. dma_addr_t dma;
  1029. struct pci_dev *pdev = adapter->pdev;
  1030. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1031. if (!buffer->skb) {
  1032. adapter->stats.skb_alloc_failure++;
  1033. return -ENOMEM;
  1034. }
  1035. skb = buffer->skb;
  1036. skb_reserve(skb, 2);
  1037. dma = pci_map_single(pdev, skb->data,
  1038. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1039. if (pci_dma_mapping_error(pdev, dma)) {
  1040. adapter->stats.rx_dma_map_error++;
  1041. dev_kfree_skb_any(skb);
  1042. buffer->skb = NULL;
  1043. return -ENOMEM;
  1044. }
  1045. buffer->skb = skb;
  1046. buffer->dma = dma;
  1047. buffer->state = QLCNIC_BUFFER_BUSY;
  1048. return 0;
  1049. }
  1050. static struct sk_buff *qlcnic_process_rxbuf(struct qlcnic_adapter *adapter,
  1051. struct qlcnic_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1052. {
  1053. struct qlcnic_rx_buffer *buffer;
  1054. struct sk_buff *skb;
  1055. buffer = &rds_ring->rx_buf_arr[index];
  1056. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1057. PCI_DMA_FROMDEVICE);
  1058. skb = buffer->skb;
  1059. if (!skb) {
  1060. adapter->stats.null_skb++;
  1061. goto no_skb;
  1062. }
  1063. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1064. adapter->stats.csummed++;
  1065. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1066. } else {
  1067. skb->ip_summed = CHECKSUM_NONE;
  1068. }
  1069. skb->dev = adapter->netdev;
  1070. buffer->skb = NULL;
  1071. no_skb:
  1072. buffer->state = QLCNIC_BUFFER_FREE;
  1073. return skb;
  1074. }
  1075. static struct qlcnic_rx_buffer *
  1076. qlcnic_process_rcv(struct qlcnic_adapter *adapter,
  1077. struct qlcnic_host_sds_ring *sds_ring,
  1078. int ring, u64 sts_data0)
  1079. {
  1080. struct net_device *netdev = adapter->netdev;
  1081. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1082. struct qlcnic_rx_buffer *buffer;
  1083. struct sk_buff *skb;
  1084. struct qlcnic_host_rds_ring *rds_ring;
  1085. int index, length, cksum, pkt_offset;
  1086. if (unlikely(ring >= adapter->max_rds_rings))
  1087. return NULL;
  1088. rds_ring = &recv_ctx->rds_rings[ring];
  1089. index = qlcnic_get_sts_refhandle(sts_data0);
  1090. if (unlikely(index >= rds_ring->num_desc))
  1091. return NULL;
  1092. buffer = &rds_ring->rx_buf_arr[index];
  1093. length = qlcnic_get_sts_totallength(sts_data0);
  1094. cksum = qlcnic_get_sts_status(sts_data0);
  1095. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1096. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1097. if (!skb)
  1098. return buffer;
  1099. if (length > rds_ring->skb_size)
  1100. skb_put(skb, rds_ring->skb_size);
  1101. else
  1102. skb_put(skb, length);
  1103. if (pkt_offset)
  1104. skb_pull(skb, pkt_offset);
  1105. skb->truesize = skb->len + sizeof(struct sk_buff);
  1106. skb->protocol = eth_type_trans(skb, netdev);
  1107. napi_gro_receive(&sds_ring->napi, skb);
  1108. adapter->stats.rx_pkts++;
  1109. adapter->stats.rxbytes += length;
  1110. return buffer;
  1111. }
  1112. #define QLC_TCP_HDR_SIZE 20
  1113. #define QLC_TCP_TS_OPTION_SIZE 12
  1114. #define QLC_TCP_TS_HDR_SIZE (QLC_TCP_HDR_SIZE + QLC_TCP_TS_OPTION_SIZE)
  1115. static struct qlcnic_rx_buffer *
  1116. qlcnic_process_lro(struct qlcnic_adapter *adapter,
  1117. struct qlcnic_host_sds_ring *sds_ring,
  1118. int ring, u64 sts_data0, u64 sts_data1)
  1119. {
  1120. struct net_device *netdev = adapter->netdev;
  1121. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1122. struct qlcnic_rx_buffer *buffer;
  1123. struct sk_buff *skb;
  1124. struct qlcnic_host_rds_ring *rds_ring;
  1125. struct iphdr *iph;
  1126. struct tcphdr *th;
  1127. bool push, timestamp;
  1128. int l2_hdr_offset, l4_hdr_offset;
  1129. int index;
  1130. u16 lro_length, length, data_offset;
  1131. u32 seq_number;
  1132. if (unlikely(ring > adapter->max_rds_rings))
  1133. return NULL;
  1134. rds_ring = &recv_ctx->rds_rings[ring];
  1135. index = qlcnic_get_lro_sts_refhandle(sts_data0);
  1136. if (unlikely(index > rds_ring->num_desc))
  1137. return NULL;
  1138. buffer = &rds_ring->rx_buf_arr[index];
  1139. timestamp = qlcnic_get_lro_sts_timestamp(sts_data0);
  1140. lro_length = qlcnic_get_lro_sts_length(sts_data0);
  1141. l2_hdr_offset = qlcnic_get_lro_sts_l2_hdr_offset(sts_data0);
  1142. l4_hdr_offset = qlcnic_get_lro_sts_l4_hdr_offset(sts_data0);
  1143. push = qlcnic_get_lro_sts_push_flag(sts_data0);
  1144. seq_number = qlcnic_get_lro_sts_seq_number(sts_data1);
  1145. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1146. if (!skb)
  1147. return buffer;
  1148. if (timestamp)
  1149. data_offset = l4_hdr_offset + QLC_TCP_TS_HDR_SIZE;
  1150. else
  1151. data_offset = l4_hdr_offset + QLC_TCP_HDR_SIZE;
  1152. skb_put(skb, lro_length + data_offset);
  1153. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1154. skb_pull(skb, l2_hdr_offset);
  1155. skb->protocol = eth_type_trans(skb, netdev);
  1156. iph = (struct iphdr *)skb->data;
  1157. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1158. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1159. iph->tot_len = htons(length);
  1160. iph->check = 0;
  1161. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1162. th->psh = push;
  1163. th->seq = htonl(seq_number);
  1164. length = skb->len;
  1165. netif_receive_skb(skb);
  1166. adapter->stats.lro_pkts++;
  1167. adapter->stats.lrobytes += length;
  1168. return buffer;
  1169. }
  1170. int
  1171. qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max)
  1172. {
  1173. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1174. struct list_head *cur;
  1175. struct status_desc *desc;
  1176. struct qlcnic_rx_buffer *rxbuf;
  1177. u64 sts_data0, sts_data1;
  1178. int count = 0;
  1179. int opcode, ring, desc_cnt;
  1180. u32 consumer = sds_ring->consumer;
  1181. while (count < max) {
  1182. desc = &sds_ring->desc_head[consumer];
  1183. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1184. if (!(sts_data0 & STATUS_OWNER_HOST))
  1185. break;
  1186. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1187. opcode = qlcnic_get_sts_opcode(sts_data0);
  1188. switch (opcode) {
  1189. case QLCNIC_RXPKT_DESC:
  1190. case QLCNIC_OLD_RXPKT_DESC:
  1191. case QLCNIC_SYN_OFFLOAD:
  1192. ring = qlcnic_get_sts_type(sts_data0);
  1193. rxbuf = qlcnic_process_rcv(adapter, sds_ring,
  1194. ring, sts_data0);
  1195. break;
  1196. case QLCNIC_LRO_DESC:
  1197. ring = qlcnic_get_lro_sts_type(sts_data0);
  1198. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1199. rxbuf = qlcnic_process_lro(adapter, sds_ring,
  1200. ring, sts_data0, sts_data1);
  1201. break;
  1202. case QLCNIC_RESPONSE_DESC:
  1203. qlcnic_handle_fw_message(desc_cnt, consumer, sds_ring);
  1204. default:
  1205. goto skip;
  1206. }
  1207. WARN_ON(desc_cnt > 1);
  1208. if (rxbuf)
  1209. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1210. else
  1211. adapter->stats.null_rxbuf++;
  1212. skip:
  1213. for (; desc_cnt > 0; desc_cnt--) {
  1214. desc = &sds_ring->desc_head[consumer];
  1215. desc->status_desc_data[0] =
  1216. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1217. consumer = get_next_index(consumer, sds_ring->num_desc);
  1218. }
  1219. count++;
  1220. }
  1221. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1222. struct qlcnic_host_rds_ring *rds_ring =
  1223. &adapter->recv_ctx.rds_rings[ring];
  1224. if (!list_empty(&sds_ring->free_list[ring])) {
  1225. list_for_each(cur, &sds_ring->free_list[ring]) {
  1226. rxbuf = list_entry(cur,
  1227. struct qlcnic_rx_buffer, list);
  1228. qlcnic_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1229. }
  1230. spin_lock(&rds_ring->lock);
  1231. list_splice_tail_init(&sds_ring->free_list[ring],
  1232. &rds_ring->free_list);
  1233. spin_unlock(&rds_ring->lock);
  1234. }
  1235. qlcnic_post_rx_buffers_nodb(adapter, rds_ring);
  1236. }
  1237. if (count) {
  1238. sds_ring->consumer = consumer;
  1239. writel(consumer, sds_ring->crb_sts_consumer);
  1240. }
  1241. return count;
  1242. }
  1243. void
  1244. qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
  1245. struct qlcnic_host_rds_ring *rds_ring)
  1246. {
  1247. struct rcv_desc *pdesc;
  1248. struct qlcnic_rx_buffer *buffer;
  1249. int producer, count = 0;
  1250. struct list_head *head;
  1251. spin_lock(&rds_ring->lock);
  1252. producer = rds_ring->producer;
  1253. head = &rds_ring->free_list;
  1254. while (!list_empty(head)) {
  1255. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1256. if (!buffer->skb) {
  1257. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1258. break;
  1259. }
  1260. count++;
  1261. list_del(&buffer->list);
  1262. /* make a rcv descriptor */
  1263. pdesc = &rds_ring->desc_head[producer];
  1264. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1265. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1266. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1267. producer = get_next_index(producer, rds_ring->num_desc);
  1268. }
  1269. if (count) {
  1270. rds_ring->producer = producer;
  1271. writel((producer-1) & (rds_ring->num_desc-1),
  1272. rds_ring->crb_rcv_producer);
  1273. }
  1274. spin_unlock(&rds_ring->lock);
  1275. }
  1276. static void
  1277. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  1278. struct qlcnic_host_rds_ring *rds_ring)
  1279. {
  1280. struct rcv_desc *pdesc;
  1281. struct qlcnic_rx_buffer *buffer;
  1282. int producer, count = 0;
  1283. struct list_head *head;
  1284. if (!spin_trylock(&rds_ring->lock))
  1285. return;
  1286. producer = rds_ring->producer;
  1287. head = &rds_ring->free_list;
  1288. while (!list_empty(head)) {
  1289. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1290. if (!buffer->skb) {
  1291. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1292. break;
  1293. }
  1294. count++;
  1295. list_del(&buffer->list);
  1296. /* make a rcv descriptor */
  1297. pdesc = &rds_ring->desc_head[producer];
  1298. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1299. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1300. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1301. producer = get_next_index(producer, rds_ring->num_desc);
  1302. }
  1303. if (count) {
  1304. rds_ring->producer = producer;
  1305. writel((producer - 1) & (rds_ring->num_desc - 1),
  1306. rds_ring->crb_rcv_producer);
  1307. }
  1308. spin_unlock(&rds_ring->lock);
  1309. }
  1310. static struct qlcnic_rx_buffer *
  1311. qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter,
  1312. struct qlcnic_host_sds_ring *sds_ring,
  1313. int ring, u64 sts_data0)
  1314. {
  1315. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1316. struct qlcnic_rx_buffer *buffer;
  1317. struct sk_buff *skb;
  1318. struct qlcnic_host_rds_ring *rds_ring;
  1319. int index, length, cksum, pkt_offset;
  1320. if (unlikely(ring >= adapter->max_rds_rings))
  1321. return NULL;
  1322. rds_ring = &recv_ctx->rds_rings[ring];
  1323. index = qlcnic_get_sts_refhandle(sts_data0);
  1324. if (unlikely(index >= rds_ring->num_desc))
  1325. return NULL;
  1326. buffer = &rds_ring->rx_buf_arr[index];
  1327. length = qlcnic_get_sts_totallength(sts_data0);
  1328. cksum = qlcnic_get_sts_status(sts_data0);
  1329. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1330. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1331. if (!skb)
  1332. return buffer;
  1333. skb_put(skb, rds_ring->skb_size);
  1334. if (pkt_offset)
  1335. skb_pull(skb, pkt_offset);
  1336. skb->truesize = skb->len + sizeof(struct sk_buff);
  1337. if (!qlcnic_check_loopback_buff(skb->data))
  1338. adapter->diag_cnt++;
  1339. dev_kfree_skb_any(skb);
  1340. adapter->stats.rx_pkts++;
  1341. adapter->stats.rxbytes += length;
  1342. return buffer;
  1343. }
  1344. void
  1345. qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
  1346. {
  1347. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1348. struct status_desc *desc;
  1349. struct qlcnic_rx_buffer *rxbuf;
  1350. u64 sts_data0;
  1351. int opcode, ring, desc_cnt;
  1352. u32 consumer = sds_ring->consumer;
  1353. desc = &sds_ring->desc_head[consumer];
  1354. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1355. if (!(sts_data0 & STATUS_OWNER_HOST))
  1356. return;
  1357. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1358. opcode = qlcnic_get_sts_opcode(sts_data0);
  1359. ring = qlcnic_get_sts_type(sts_data0);
  1360. rxbuf = qlcnic_process_rcv_diag(adapter, sds_ring,
  1361. ring, sts_data0);
  1362. desc->status_desc_data[0] = cpu_to_le64(STATUS_OWNER_PHANTOM);
  1363. consumer = get_next_index(consumer, sds_ring->num_desc);
  1364. sds_ring->consumer = consumer;
  1365. writel(consumer, sds_ring->crb_sts_consumer);
  1366. }