debug.c 4.6 KB

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  1. /*
  2. * Copyright (c) 2004-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "core.h"
  17. #include "debug.h"
  18. int ath6kl_printk(const char *level, const char *fmt, ...)
  19. {
  20. struct va_format vaf;
  21. va_list args;
  22. int rtn;
  23. va_start(args, fmt);
  24. vaf.fmt = fmt;
  25. vaf.va = &args;
  26. rtn = printk("%sath6kl: %pV", level, &vaf);
  27. va_end(args);
  28. return rtn;
  29. }
  30. #ifdef CONFIG_ATH6KL_DEBUG
  31. void ath6kl_dump_registers(struct ath6kl_device *dev,
  32. struct ath6kl_irq_proc_registers *irq_proc_reg,
  33. struct ath6kl_irq_enable_reg *irq_enable_reg)
  34. {
  35. ath6kl_dbg(ATH6KL_DBG_ANY, ("<------- Register Table -------->\n"));
  36. if (irq_proc_reg != NULL) {
  37. ath6kl_dbg(ATH6KL_DBG_ANY,
  38. "Host Int status: 0x%x\n",
  39. irq_proc_reg->host_int_status);
  40. ath6kl_dbg(ATH6KL_DBG_ANY,
  41. "CPU Int status: 0x%x\n",
  42. irq_proc_reg->cpu_int_status);
  43. ath6kl_dbg(ATH6KL_DBG_ANY,
  44. "Error Int status: 0x%x\n",
  45. irq_proc_reg->error_int_status);
  46. ath6kl_dbg(ATH6KL_DBG_ANY,
  47. "Counter Int status: 0x%x\n",
  48. irq_proc_reg->counter_int_status);
  49. ath6kl_dbg(ATH6KL_DBG_ANY,
  50. "Mbox Frame: 0x%x\n",
  51. irq_proc_reg->mbox_frame);
  52. ath6kl_dbg(ATH6KL_DBG_ANY,
  53. "Rx Lookahead Valid: 0x%x\n",
  54. irq_proc_reg->rx_lkahd_valid);
  55. ath6kl_dbg(ATH6KL_DBG_ANY,
  56. "Rx Lookahead 0: 0x%x\n",
  57. irq_proc_reg->rx_lkahd[0]);
  58. ath6kl_dbg(ATH6KL_DBG_ANY,
  59. "Rx Lookahead 1: 0x%x\n",
  60. irq_proc_reg->rx_lkahd[1]);
  61. if (dev->ar->mbox_info.gmbox_addr != 0) {
  62. /*
  63. * If the target supports GMBOX hardware, dump some
  64. * additional state.
  65. */
  66. ath6kl_dbg(ATH6KL_DBG_ANY,
  67. "GMBOX Host Int status 2: 0x%x\n",
  68. irq_proc_reg->host_int_status2);
  69. ath6kl_dbg(ATH6KL_DBG_ANY,
  70. "GMBOX RX Avail: 0x%x\n",
  71. irq_proc_reg->gmbox_rx_avail);
  72. ath6kl_dbg(ATH6KL_DBG_ANY,
  73. "GMBOX lookahead alias 0: 0x%x\n",
  74. irq_proc_reg->rx_gmbox_lkahd_alias[0]);
  75. ath6kl_dbg(ATH6KL_DBG_ANY,
  76. "GMBOX lookahead alias 1: 0x%x\n",
  77. irq_proc_reg->rx_gmbox_lkahd_alias[1]);
  78. }
  79. }
  80. if (irq_enable_reg != NULL) {
  81. ath6kl_dbg(ATH6KL_DBG_ANY,
  82. "Int status Enable: 0x%x\n",
  83. irq_enable_reg->int_status_en);
  84. ath6kl_dbg(ATH6KL_DBG_ANY, "Counter Int status Enable: 0x%x\n",
  85. irq_enable_reg->cntr_int_status_en);
  86. }
  87. ath6kl_dbg(ATH6KL_DBG_ANY, "<------------------------------->\n");
  88. }
  89. static void dump_cred_dist(struct htc_endpoint_credit_dist *ep_dist)
  90. {
  91. ath6kl_dbg(ATH6KL_DBG_ANY,
  92. "--- endpoint: %d svc_id: 0x%X ---\n",
  93. ep_dist->endpoint, ep_dist->svc_id);
  94. ath6kl_dbg(ATH6KL_DBG_ANY, " dist_flags : 0x%X\n",
  95. ep_dist->dist_flags);
  96. ath6kl_dbg(ATH6KL_DBG_ANY, " cred_norm : %d\n",
  97. ep_dist->cred_norm);
  98. ath6kl_dbg(ATH6KL_DBG_ANY, " cred_min : %d\n",
  99. ep_dist->cred_min);
  100. ath6kl_dbg(ATH6KL_DBG_ANY, " credits : %d\n",
  101. ep_dist->credits);
  102. ath6kl_dbg(ATH6KL_DBG_ANY, " cred_assngd : %d\n",
  103. ep_dist->cred_assngd);
  104. ath6kl_dbg(ATH6KL_DBG_ANY, " seek_cred : %d\n",
  105. ep_dist->seek_cred);
  106. ath6kl_dbg(ATH6KL_DBG_ANY, " cred_sz : %d\n",
  107. ep_dist->cred_sz);
  108. ath6kl_dbg(ATH6KL_DBG_ANY, " cred_per_msg : %d\n",
  109. ep_dist->cred_per_msg);
  110. ath6kl_dbg(ATH6KL_DBG_ANY, " cred_to_dist : %d\n",
  111. ep_dist->cred_to_dist);
  112. ath6kl_dbg(ATH6KL_DBG_ANY, " txq_depth : %d\n",
  113. get_queue_depth(&((struct htc_endpoint *)
  114. ep_dist->htc_rsvd)->txq));
  115. ath6kl_dbg(ATH6KL_DBG_ANY,
  116. "----------------------------------\n");
  117. }
  118. void dump_cred_dist_stats(struct htc_target *target)
  119. {
  120. struct htc_endpoint_credit_dist *ep_list;
  121. if (!AR_DBG_LVL_CHECK(ATH6KL_DBG_TRC))
  122. return;
  123. list_for_each_entry(ep_list, &target->cred_dist_list, list)
  124. dump_cred_dist(ep_list);
  125. ath6kl_dbg(ATH6KL_DBG_HTC_SEND, "ctxt:%p dist:%p\n",
  126. target->cred_dist_cntxt, NULL);
  127. ath6kl_dbg(ATH6KL_DBG_TRC, "credit distribution, total : %d, free : %d\n",
  128. target->cred_dist_cntxt->total_avail_credits,
  129. target->cred_dist_cntxt->cur_free_credits);
  130. }
  131. #endif