cx23885-dvb.c 26 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "tda10048.h"
  39. #include "tuner-xc2028.h"
  40. #include "tuner-simple.h"
  41. #include "dib7000p.h"
  42. #include "dibx000_common.h"
  43. #include "zl10353.h"
  44. #include "stv0900.h"
  45. #include "stv0900_reg.h"
  46. #include "stv6110.h"
  47. #include "lnbh24.h"
  48. #include "cx24116.h"
  49. #include "cimax2.h"
  50. #include "lgs8gxx.h"
  51. #include "netup-eeprom.h"
  52. #include "netup-init.h"
  53. #include "lgdt3305.h"
  54. static unsigned int debug;
  55. #define dprintk(level, fmt, arg...)\
  56. do { if (debug >= level)\
  57. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  58. } while (0)
  59. /* ------------------------------------------------------------------ */
  60. static unsigned int alt_tuner;
  61. module_param(alt_tuner, int, 0644);
  62. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  63. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  64. /* ------------------------------------------------------------------ */
  65. static int dvb_buf_setup(struct videobuf_queue *q,
  66. unsigned int *count, unsigned int *size)
  67. {
  68. struct cx23885_tsport *port = q->priv_data;
  69. port->ts_packet_size = 188 * 4;
  70. port->ts_packet_count = 32;
  71. *size = port->ts_packet_size * port->ts_packet_count;
  72. *count = 32;
  73. return 0;
  74. }
  75. static int dvb_buf_prepare(struct videobuf_queue *q,
  76. struct videobuf_buffer *vb, enum v4l2_field field)
  77. {
  78. struct cx23885_tsport *port = q->priv_data;
  79. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  80. }
  81. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  82. {
  83. struct cx23885_tsport *port = q->priv_data;
  84. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  85. }
  86. static void dvb_buf_release(struct videobuf_queue *q,
  87. struct videobuf_buffer *vb)
  88. {
  89. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  90. }
  91. static struct videobuf_queue_ops dvb_qops = {
  92. .buf_setup = dvb_buf_setup,
  93. .buf_prepare = dvb_buf_prepare,
  94. .buf_queue = dvb_buf_queue,
  95. .buf_release = dvb_buf_release,
  96. };
  97. static struct s5h1409_config hauppauge_generic_config = {
  98. .demod_address = 0x32 >> 1,
  99. .output_mode = S5H1409_SERIAL_OUTPUT,
  100. .gpio = S5H1409_GPIO_ON,
  101. .qam_if = 44000,
  102. .inversion = S5H1409_INVERSION_OFF,
  103. .status_mode = S5H1409_DEMODLOCKING,
  104. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  105. };
  106. static struct tda10048_config hauppauge_hvr1200_config = {
  107. .demod_address = 0x10 >> 1,
  108. .output_mode = TDA10048_SERIAL_OUTPUT,
  109. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  110. .inversion = TDA10048_INVERSION_ON,
  111. .dtv6_if_freq_khz = TDA10048_IF_3300,
  112. .dtv7_if_freq_khz = TDA10048_IF_3800,
  113. .dtv8_if_freq_khz = TDA10048_IF_4300,
  114. .clk_freq_khz = TDA10048_CLK_16000,
  115. };
  116. static struct tda10048_config hauppauge_hvr1210_config = {
  117. .demod_address = 0x10 >> 1,
  118. .output_mode = TDA10048_SERIAL_OUTPUT,
  119. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  120. .inversion = TDA10048_INVERSION_ON,
  121. .dtv6_if_freq_khz = TDA10048_IF_3300,
  122. .dtv7_if_freq_khz = TDA10048_IF_3500,
  123. .dtv8_if_freq_khz = TDA10048_IF_4000,
  124. .clk_freq_khz = TDA10048_CLK_16000,
  125. };
  126. static struct s5h1409_config hauppauge_ezqam_config = {
  127. .demod_address = 0x32 >> 1,
  128. .output_mode = S5H1409_SERIAL_OUTPUT,
  129. .gpio = S5H1409_GPIO_OFF,
  130. .qam_if = 4000,
  131. .inversion = S5H1409_INVERSION_ON,
  132. .status_mode = S5H1409_DEMODLOCKING,
  133. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  134. };
  135. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  136. .demod_address = 0x32 >> 1,
  137. .output_mode = S5H1409_SERIAL_OUTPUT,
  138. .gpio = S5H1409_GPIO_OFF,
  139. .qam_if = 44000,
  140. .inversion = S5H1409_INVERSION_OFF,
  141. .status_mode = S5H1409_DEMODLOCKING,
  142. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  143. };
  144. static struct s5h1409_config hauppauge_hvr1500_config = {
  145. .demod_address = 0x32 >> 1,
  146. .output_mode = S5H1409_SERIAL_OUTPUT,
  147. .gpio = S5H1409_GPIO_OFF,
  148. .inversion = S5H1409_INVERSION_OFF,
  149. .status_mode = S5H1409_DEMODLOCKING,
  150. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  151. };
  152. static struct mt2131_config hauppauge_generic_tunerconfig = {
  153. 0x61
  154. };
  155. static struct lgdt330x_config fusionhdtv_5_express = {
  156. .demod_address = 0x0e,
  157. .demod_chip = LGDT3303,
  158. .serial_mpeg = 0x40,
  159. };
  160. static struct s5h1409_config hauppauge_hvr1500q_config = {
  161. .demod_address = 0x32 >> 1,
  162. .output_mode = S5H1409_SERIAL_OUTPUT,
  163. .gpio = S5H1409_GPIO_ON,
  164. .qam_if = 44000,
  165. .inversion = S5H1409_INVERSION_OFF,
  166. .status_mode = S5H1409_DEMODLOCKING,
  167. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  168. };
  169. static struct s5h1409_config dvico_s5h1409_config = {
  170. .demod_address = 0x32 >> 1,
  171. .output_mode = S5H1409_SERIAL_OUTPUT,
  172. .gpio = S5H1409_GPIO_ON,
  173. .qam_if = 44000,
  174. .inversion = S5H1409_INVERSION_OFF,
  175. .status_mode = S5H1409_DEMODLOCKING,
  176. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  177. };
  178. static struct s5h1411_config dvico_s5h1411_config = {
  179. .output_mode = S5H1411_SERIAL_OUTPUT,
  180. .gpio = S5H1411_GPIO_ON,
  181. .qam_if = S5H1411_IF_44000,
  182. .vsb_if = S5H1411_IF_44000,
  183. .inversion = S5H1411_INVERSION_OFF,
  184. .status_mode = S5H1411_DEMODLOCKING,
  185. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  186. };
  187. static struct s5h1411_config hcw_s5h1411_config = {
  188. .output_mode = S5H1411_SERIAL_OUTPUT,
  189. .gpio = S5H1411_GPIO_OFF,
  190. .vsb_if = S5H1411_IF_44000,
  191. .qam_if = S5H1411_IF_4000,
  192. .inversion = S5H1411_INVERSION_ON,
  193. .status_mode = S5H1411_DEMODLOCKING,
  194. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  197. .i2c_address = 0x61,
  198. .if_khz = 5380,
  199. };
  200. static struct xc5000_config dvico_xc5000_tunerconfig = {
  201. .i2c_address = 0x64,
  202. .if_khz = 5380,
  203. };
  204. static struct tda829x_config tda829x_no_probe = {
  205. .probe_tuner = TDA829X_DONT_PROBE,
  206. };
  207. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  208. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  209. .if_lvl = 6, .rfagc_top = 0x37 },
  210. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  211. .if_lvl = 6, .rfagc_top = 0x37 },
  212. };
  213. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  214. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  215. .if_lvl = 1, .rfagc_top = 0x37, },
  216. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  217. .if_lvl = 1, .rfagc_top = 0x37, },
  218. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  219. .if_lvl = 1, .rfagc_top = 0x37, },
  220. };
  221. static struct tda18271_config hauppauge_tda18271_config = {
  222. .std_map = &hauppauge_tda18271_std_map,
  223. .gate = TDA18271_GATE_ANALOG,
  224. };
  225. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  226. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  227. .gate = TDA18271_GATE_ANALOG,
  228. };
  229. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  230. .gate = TDA18271_GATE_DIGITAL,
  231. };
  232. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  233. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  234. .if_lvl = 1, .rfagc_top = 0x58 },
  235. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  236. .if_lvl = 1, .rfagc_top = 0x58 },
  237. };
  238. static struct tda18271_config hauppauge_hvr127x_config = {
  239. .std_map = &hauppauge_hvr127x_std_map,
  240. };
  241. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  242. .i2c_addr = 0x0e,
  243. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  244. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  245. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  246. .deny_i2c_rptr = 1,
  247. .spectral_inversion = 1,
  248. .qam_if_khz = 4000,
  249. .vsb_if_khz = 3250,
  250. };
  251. static struct dibx000_agc_config xc3028_agc_config = {
  252. BAND_VHF | BAND_UHF, /* band_caps */
  253. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  254. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  255. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  256. * P_agc_nb_est=2, P_agc_write=0
  257. */
  258. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  259. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  260. 712, /* inv_gain */
  261. 21, /* time_stabiliz */
  262. 0, /* alpha_level */
  263. 118, /* thlock */
  264. 0, /* wbd_inv */
  265. 2867, /* wbd_ref */
  266. 0, /* wbd_sel */
  267. 2, /* wbd_alpha */
  268. 0, /* agc1_max */
  269. 0, /* agc1_min */
  270. 39718, /* agc2_max */
  271. 9930, /* agc2_min */
  272. 0, /* agc1_pt1 */
  273. 0, /* agc1_pt2 */
  274. 0, /* agc1_pt3 */
  275. 0, /* agc1_slope1 */
  276. 0, /* agc1_slope2 */
  277. 0, /* agc2_pt1 */
  278. 128, /* agc2_pt2 */
  279. 29, /* agc2_slope1 */
  280. 29, /* agc2_slope2 */
  281. 17, /* alpha_mant */
  282. 27, /* alpha_exp */
  283. 23, /* beta_mant */
  284. 51, /* beta_exp */
  285. 1, /* perform_agc_softsplit */
  286. };
  287. /* PLL Configuration for COFDM BW_MHz = 8.000000
  288. * With external clock = 30.000000 */
  289. static struct dibx000_bandwidth_config xc3028_bw_config = {
  290. 60000, /* internal */
  291. 30000, /* sampling */
  292. 1, /* pll_cfg: prediv */
  293. 8, /* pll_cfg: ratio */
  294. 3, /* pll_cfg: range */
  295. 1, /* pll_cfg: reset */
  296. 0, /* pll_cfg: bypass */
  297. 0, /* misc: refdiv */
  298. 0, /* misc: bypclk_div */
  299. 1, /* misc: IO_CLK_en_core */
  300. 1, /* misc: ADClkSrc */
  301. 0, /* misc: modulo */
  302. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  303. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  304. 20452225, /* timf */
  305. 30000000 /* xtal_hz */
  306. };
  307. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  308. .output_mpeg2_in_188_bytes = 1,
  309. .hostbus_diversity = 1,
  310. .tuner_is_baseband = 0,
  311. .update_lna = NULL,
  312. .agc_config_count = 1,
  313. .agc = &xc3028_agc_config,
  314. .bw = &xc3028_bw_config,
  315. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  316. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  317. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  318. .pwm_freq_div = 0,
  319. .agc_control = NULL,
  320. .spur_protect = 0,
  321. .output_mode = OUTMODE_MPEG2_SERIAL,
  322. };
  323. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  324. .demod_address = 0x0f,
  325. .if2 = 45600,
  326. .no_tuner = 1,
  327. .disable_i2c_gate_ctrl = 1,
  328. };
  329. static struct stv0900_reg stv0900_ts_regs[] = {
  330. { R0900_TSGENERAL, 0x00 },
  331. { R0900_P1_TSSPEED, 0x40 },
  332. { R0900_P2_TSSPEED, 0x40 },
  333. { R0900_P1_TSCFGM, 0xc0 },
  334. { R0900_P2_TSCFGM, 0xc0 },
  335. { R0900_P1_TSCFGH, 0xe0 },
  336. { R0900_P2_TSCFGH, 0xe0 },
  337. { R0900_P1_TSCFGL, 0x20 },
  338. { R0900_P2_TSCFGL, 0x20 },
  339. { 0xffff, 0xff }, /* terminate */
  340. };
  341. static struct stv0900_config netup_stv0900_config = {
  342. .demod_address = 0x68,
  343. .xtal = 27000000,
  344. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  345. .diseqc_mode = 2,/* 2/3 PWM */
  346. .ts_config_regs = stv0900_ts_regs,
  347. .tun1_maddress = 0,/* 0x60 */
  348. .tun2_maddress = 3,/* 0x63 */
  349. .tun1_adc = 1,/* 1 Vpp */
  350. .tun2_adc = 1,/* 1 Vpp */
  351. };
  352. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  353. .i2c_address = 0x60,
  354. .mclk = 27000000,
  355. .iq_wiring = 0,
  356. };
  357. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  358. .i2c_address = 0x63,
  359. .mclk = 27000000,
  360. .iq_wiring = 1,
  361. };
  362. static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  363. {
  364. struct cx23885_tsport *port = fe->dvb->priv;
  365. struct cx23885_dev *dev = port->dev;
  366. if (voltage == SEC_VOLTAGE_18)
  367. cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
  368. else if (voltage == SEC_VOLTAGE_13)
  369. cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
  370. else
  371. cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
  372. return 0;
  373. }
  374. static struct cx24116_config tbs_cx24116_config = {
  375. .demod_address = 0x05,
  376. };
  377. static struct cx24116_config tevii_cx24116_config = {
  378. .demod_address = 0x55,
  379. };
  380. static struct cx24116_config dvbworld_cx24116_config = {
  381. .demod_address = 0x05,
  382. };
  383. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  384. .prod = LGS8GXX_PROD_LGS8GL5,
  385. .demod_address = 0x19,
  386. .serial_ts = 0,
  387. .ts_clk_pol = 1,
  388. .ts_clk_gated = 1,
  389. .if_clk_freq = 30400, /* 30.4 MHz */
  390. .if_freq = 5380, /* 5.38 MHz */
  391. .if_neg_center = 1,
  392. .ext_adc = 0,
  393. .adc_signed = 0,
  394. .if_neg_edge = 0,
  395. };
  396. static struct xc5000_config mygica_x8506_xc5000_config = {
  397. .i2c_address = 0x61,
  398. .if_khz = 5380,
  399. };
  400. static int dvb_register(struct cx23885_tsport *port)
  401. {
  402. struct cx23885_dev *dev = port->dev;
  403. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  404. struct videobuf_dvb_frontend *fe0;
  405. int ret;
  406. /* Get the first frontend */
  407. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  408. if (!fe0)
  409. return -EINVAL;
  410. /* init struct videobuf_dvb */
  411. fe0->dvb.name = dev->name;
  412. /* init frontend */
  413. switch (dev->board) {
  414. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  415. i2c_bus = &dev->i2c_bus[0];
  416. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  417. &hauppauge_generic_config,
  418. &i2c_bus->i2c_adap);
  419. if (fe0->dvb.frontend != NULL) {
  420. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  421. &i2c_bus->i2c_adap,
  422. &hauppauge_generic_tunerconfig, 0);
  423. }
  424. break;
  425. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  426. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  427. i2c_bus = &dev->i2c_bus[0];
  428. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  429. &hauppauge_lgdt3305_config,
  430. &i2c_bus->i2c_adap);
  431. if (fe0->dvb.frontend != NULL) {
  432. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  433. 0x60, &dev->i2c_bus[1].i2c_adap,
  434. &hauppauge_hvr127x_config);
  435. }
  436. break;
  437. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  438. i2c_bus = &dev->i2c_bus[0];
  439. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  440. &hcw_s5h1411_config,
  441. &i2c_bus->i2c_adap);
  442. if (fe0->dvb.frontend != NULL) {
  443. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  444. 0x60, &dev->i2c_bus[1].i2c_adap,
  445. &hauppauge_tda18271_config);
  446. }
  447. break;
  448. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  449. i2c_bus = &dev->i2c_bus[0];
  450. switch (alt_tuner) {
  451. case 1:
  452. fe0->dvb.frontend =
  453. dvb_attach(s5h1409_attach,
  454. &hauppauge_ezqam_config,
  455. &i2c_bus->i2c_adap);
  456. if (fe0->dvb.frontend != NULL) {
  457. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  458. &dev->i2c_bus[1].i2c_adap, 0x42,
  459. &tda829x_no_probe);
  460. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  461. 0x60, &dev->i2c_bus[1].i2c_adap,
  462. &hauppauge_tda18271_config);
  463. }
  464. break;
  465. case 0:
  466. default:
  467. fe0->dvb.frontend =
  468. dvb_attach(s5h1409_attach,
  469. &hauppauge_generic_config,
  470. &i2c_bus->i2c_adap);
  471. if (fe0->dvb.frontend != NULL)
  472. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  473. &i2c_bus->i2c_adap,
  474. &hauppauge_generic_tunerconfig, 0);
  475. break;
  476. }
  477. break;
  478. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  479. i2c_bus = &dev->i2c_bus[0];
  480. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  481. &hauppauge_hvr1800lp_config,
  482. &i2c_bus->i2c_adap);
  483. if (fe0->dvb.frontend != NULL) {
  484. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  485. &i2c_bus->i2c_adap,
  486. &hauppauge_generic_tunerconfig, 0);
  487. }
  488. break;
  489. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  490. i2c_bus = &dev->i2c_bus[0];
  491. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  492. &fusionhdtv_5_express,
  493. &i2c_bus->i2c_adap);
  494. if (fe0->dvb.frontend != NULL) {
  495. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  496. &i2c_bus->i2c_adap, 0x61,
  497. TUNER_LG_TDVS_H06XF);
  498. }
  499. break;
  500. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  501. i2c_bus = &dev->i2c_bus[1];
  502. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  503. &hauppauge_hvr1500q_config,
  504. &dev->i2c_bus[0].i2c_adap);
  505. if (fe0->dvb.frontend != NULL)
  506. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  507. &i2c_bus->i2c_adap,
  508. &hauppauge_hvr1500q_tunerconfig);
  509. break;
  510. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  511. i2c_bus = &dev->i2c_bus[1];
  512. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  513. &hauppauge_hvr1500_config,
  514. &dev->i2c_bus[0].i2c_adap);
  515. if (fe0->dvb.frontend != NULL) {
  516. struct dvb_frontend *fe;
  517. struct xc2028_config cfg = {
  518. .i2c_adap = &i2c_bus->i2c_adap,
  519. .i2c_addr = 0x61,
  520. };
  521. static struct xc2028_ctrl ctl = {
  522. .fname = XC2028_DEFAULT_FIRMWARE,
  523. .max_len = 64,
  524. .demod = XC3028_FE_OREN538,
  525. };
  526. fe = dvb_attach(xc2028_attach,
  527. fe0->dvb.frontend, &cfg);
  528. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  529. fe->ops.tuner_ops.set_config(fe, &ctl);
  530. }
  531. break;
  532. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  533. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  534. i2c_bus = &dev->i2c_bus[0];
  535. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  536. &hauppauge_hvr1200_config,
  537. &i2c_bus->i2c_adap);
  538. if (fe0->dvb.frontend != NULL) {
  539. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  540. &dev->i2c_bus[1].i2c_adap, 0x42,
  541. &tda829x_no_probe);
  542. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  543. 0x60, &dev->i2c_bus[1].i2c_adap,
  544. &hauppauge_hvr1200_tuner_config);
  545. }
  546. break;
  547. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  548. i2c_bus = &dev->i2c_bus[0];
  549. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  550. &hauppauge_hvr1210_config,
  551. &i2c_bus->i2c_adap);
  552. if (fe0->dvb.frontend != NULL) {
  553. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  554. 0x60, &dev->i2c_bus[1].i2c_adap,
  555. &hauppauge_hvr1210_tuner_config);
  556. }
  557. break;
  558. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  559. i2c_bus = &dev->i2c_bus[0];
  560. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  561. &i2c_bus->i2c_adap,
  562. 0x12, &hauppauge_hvr1400_dib7000_config);
  563. if (fe0->dvb.frontend != NULL) {
  564. struct dvb_frontend *fe;
  565. struct xc2028_config cfg = {
  566. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  567. .i2c_addr = 0x64,
  568. };
  569. static struct xc2028_ctrl ctl = {
  570. .fname = XC3028L_DEFAULT_FIRMWARE,
  571. .max_len = 64,
  572. .demod = 5000,
  573. /* This is true for all demods with
  574. v36 firmware? */
  575. .type = XC2028_D2633,
  576. };
  577. fe = dvb_attach(xc2028_attach,
  578. fe0->dvb.frontend, &cfg);
  579. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  580. fe->ops.tuner_ops.set_config(fe, &ctl);
  581. }
  582. break;
  583. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  584. i2c_bus = &dev->i2c_bus[port->nr - 1];
  585. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  586. &dvico_s5h1409_config,
  587. &i2c_bus->i2c_adap);
  588. if (fe0->dvb.frontend == NULL)
  589. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  590. &dvico_s5h1411_config,
  591. &i2c_bus->i2c_adap);
  592. if (fe0->dvb.frontend != NULL)
  593. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  594. &i2c_bus->i2c_adap,
  595. &dvico_xc5000_tunerconfig);
  596. break;
  597. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  598. i2c_bus = &dev->i2c_bus[port->nr - 1];
  599. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  600. &dvico_fusionhdtv_xc3028,
  601. &i2c_bus->i2c_adap);
  602. if (fe0->dvb.frontend != NULL) {
  603. struct dvb_frontend *fe;
  604. struct xc2028_config cfg = {
  605. .i2c_adap = &i2c_bus->i2c_adap,
  606. .i2c_addr = 0x61,
  607. };
  608. static struct xc2028_ctrl ctl = {
  609. .fname = XC2028_DEFAULT_FIRMWARE,
  610. .max_len = 64,
  611. .demod = XC3028_FE_ZARLINK456,
  612. };
  613. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  614. &cfg);
  615. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  616. fe->ops.tuner_ops.set_config(fe, &ctl);
  617. }
  618. break;
  619. }
  620. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  621. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  622. i2c_bus = &dev->i2c_bus[0];
  623. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  624. &dvico_fusionhdtv_xc3028,
  625. &i2c_bus->i2c_adap);
  626. if (fe0->dvb.frontend != NULL) {
  627. struct dvb_frontend *fe;
  628. struct xc2028_config cfg = {
  629. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  630. .i2c_addr = 0x61,
  631. };
  632. static struct xc2028_ctrl ctl = {
  633. .fname = XC2028_DEFAULT_FIRMWARE,
  634. .max_len = 64,
  635. .demod = XC3028_FE_ZARLINK456,
  636. };
  637. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  638. &cfg);
  639. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  640. fe->ops.tuner_ops.set_config(fe, &ctl);
  641. }
  642. break;
  643. case CX23885_BOARD_TBS_6920:
  644. i2c_bus = &dev->i2c_bus[0];
  645. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  646. &tbs_cx24116_config,
  647. &i2c_bus->i2c_adap);
  648. if (fe0->dvb.frontend != NULL)
  649. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  650. break;
  651. case CX23885_BOARD_TEVII_S470:
  652. i2c_bus = &dev->i2c_bus[1];
  653. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  654. &tevii_cx24116_config,
  655. &i2c_bus->i2c_adap);
  656. if (fe0->dvb.frontend != NULL)
  657. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  658. break;
  659. case CX23885_BOARD_DVBWORLD_2005:
  660. i2c_bus = &dev->i2c_bus[1];
  661. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  662. &dvbworld_cx24116_config,
  663. &i2c_bus->i2c_adap);
  664. break;
  665. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  666. i2c_bus = &dev->i2c_bus[0];
  667. switch (port->nr) {
  668. /* port B */
  669. case 1:
  670. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  671. &netup_stv0900_config,
  672. &i2c_bus->i2c_adap, 0);
  673. if (fe0->dvb.frontend != NULL) {
  674. if (dvb_attach(stv6110_attach,
  675. fe0->dvb.frontend,
  676. &netup_stv6110_tunerconfig_a,
  677. &i2c_bus->i2c_adap)) {
  678. if (!dvb_attach(lnbh24_attach,
  679. fe0->dvb.frontend,
  680. &i2c_bus->i2c_adap,
  681. LNBH24_PCL,
  682. LNBH24_TTX, 0x09))
  683. printk(KERN_ERR
  684. "No LNBH24 found!\n");
  685. }
  686. }
  687. break;
  688. /* port C */
  689. case 2:
  690. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  691. &netup_stv0900_config,
  692. &i2c_bus->i2c_adap, 1);
  693. if (fe0->dvb.frontend != NULL) {
  694. if (dvb_attach(stv6110_attach,
  695. fe0->dvb.frontend,
  696. &netup_stv6110_tunerconfig_b,
  697. &i2c_bus->i2c_adap)) {
  698. if (!dvb_attach(lnbh24_attach,
  699. fe0->dvb.frontend,
  700. &i2c_bus->i2c_adap,
  701. LNBH24_PCL,
  702. LNBH24_TTX, 0x0a))
  703. printk(KERN_ERR
  704. "No LNBH24 found!\n");
  705. }
  706. }
  707. break;
  708. }
  709. break;
  710. case CX23885_BOARD_MYGICA_X8506:
  711. i2c_bus = &dev->i2c_bus[0];
  712. i2c_bus2 = &dev->i2c_bus[1];
  713. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  714. &mygica_x8506_lgs8gl5_config,
  715. &i2c_bus->i2c_adap);
  716. if (fe0->dvb.frontend != NULL) {
  717. dvb_attach(xc5000_attach,
  718. fe0->dvb.frontend,
  719. &i2c_bus2->i2c_adap,
  720. &mygica_x8506_xc5000_config);
  721. }
  722. break;
  723. default:
  724. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  725. " isn't supported yet\n",
  726. dev->name);
  727. break;
  728. }
  729. if (NULL == fe0->dvb.frontend) {
  730. printk(KERN_ERR "%s: frontend initialization failed\n",
  731. dev->name);
  732. return -1;
  733. }
  734. /* define general-purpose callback pointer */
  735. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  736. /* Put the analog decoder in standby to keep it quiet */
  737. call_all(dev, tuner, s_standby);
  738. if (fe0->dvb.frontend->ops.analog_ops.standby)
  739. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  740. /* register everything */
  741. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  742. &dev->pci->dev, adapter_nr, 0);
  743. /* init CI & MAC */
  744. switch (dev->board) {
  745. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  746. static struct netup_card_info cinfo;
  747. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  748. memcpy(port->frontends.adapter.proposed_mac,
  749. cinfo.port[port->nr - 1].mac, 6);
  750. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  751. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  752. port->nr,
  753. port->frontends.adapter.proposed_mac[0],
  754. port->frontends.adapter.proposed_mac[1],
  755. port->frontends.adapter.proposed_mac[2],
  756. port->frontends.adapter.proposed_mac[3],
  757. port->frontends.adapter.proposed_mac[4],
  758. port->frontends.adapter.proposed_mac[5]);
  759. netup_ci_init(port);
  760. break;
  761. }
  762. }
  763. return ret;
  764. }
  765. int cx23885_dvb_register(struct cx23885_tsport *port)
  766. {
  767. struct videobuf_dvb_frontend *fe0;
  768. struct cx23885_dev *dev = port->dev;
  769. int err, i;
  770. /* Here we need to allocate the correct number of frontends,
  771. * as reflected in the cards struct. The reality is that currrently
  772. * no cx23885 boards support this - yet. But, if we don't modify this
  773. * code then the second frontend would never be allocated (later)
  774. * and fail with error before the attach in dvb_register().
  775. * Without these changes we risk an OOPS later. The changes here
  776. * are for safety, and should provide a good foundation for the
  777. * future addition of any multi-frontend cx23885 based boards.
  778. */
  779. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  780. port->num_frontends);
  781. for (i = 1; i <= port->num_frontends; i++) {
  782. if (videobuf_dvb_alloc_frontend(
  783. &port->frontends, i) == NULL) {
  784. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  785. return -ENOMEM;
  786. }
  787. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  788. if (!fe0)
  789. err = -EINVAL;
  790. dprintk(1, "%s\n", __func__);
  791. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  792. dev->board,
  793. dev->name,
  794. dev->pci_bus,
  795. dev->pci_slot);
  796. err = -ENODEV;
  797. /* dvb stuff */
  798. /* We have to init the queue for each frontend on a port. */
  799. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  800. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  801. &dev->pci->dev, &port->slock,
  802. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  803. sizeof(struct cx23885_buffer), port);
  804. }
  805. err = dvb_register(port);
  806. if (err != 0)
  807. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  808. __func__, err);
  809. return err;
  810. }
  811. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  812. {
  813. struct videobuf_dvb_frontend *fe0;
  814. /* FIXME: in an error condition where the we have
  815. * an expected number of frontends (attach problem)
  816. * then this might not clean up correctly, if 1
  817. * is invalid.
  818. * This comment only applies to future boards IF they
  819. * implement MFE support.
  820. */
  821. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  822. if (fe0->dvb.frontend)
  823. videobuf_dvb_unregister_bus(&port->frontends);
  824. switch (port->dev->board) {
  825. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  826. netup_ci_exit(port);
  827. break;
  828. }
  829. return 0;
  830. }