m25p80.c 24 KB

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  1. /*
  2. * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
  3. *
  4. * Author: Mike Lavender, mike@steroidmicros.com
  5. *
  6. * Copyright (c) 2005, Intec Automation Inc.
  7. *
  8. * Some parts are based on lart.c by Abraham Van Der Merwe
  9. *
  10. * Cleaned up and generalized based on mtd_dataflash.c
  11. *
  12. * This code is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. */
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/device.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/mutex.h>
  22. #include <linux/math64.h>
  23. #include <linux/mod_devicetable.h>
  24. #include <linux/mtd/mtd.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <linux/spi/spi.h>
  27. #include <linux/spi/flash.h>
  28. #define FLASH_PAGESIZE 256
  29. /* Flash opcodes. */
  30. #define OPCODE_WREN 0x06 /* Write enable */
  31. #define OPCODE_RDSR 0x05 /* Read status register */
  32. #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
  33. #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
  34. #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
  35. #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
  36. #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
  37. #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
  38. #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
  39. #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
  40. #define OPCODE_RDID 0x9f /* Read JEDEC ID */
  41. /* Used for SST flashes only. */
  42. #define OPCODE_BP 0x02 /* Byte program */
  43. #define OPCODE_WRDI 0x04 /* Write disable */
  44. #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
  45. /* Status Register bits. */
  46. #define SR_WIP 1 /* Write in progress */
  47. #define SR_WEL 2 /* Write enable latch */
  48. /* meaning of other SR_* bits may differ between vendors */
  49. #define SR_BP0 4 /* Block protect 0 */
  50. #define SR_BP1 8 /* Block protect 1 */
  51. #define SR_BP2 0x10 /* Block protect 2 */
  52. #define SR_SRWD 0x80 /* SR write protect */
  53. /* Define max times to check status register before we give up. */
  54. #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
  55. #define CMD_SIZE 4
  56. #ifdef CONFIG_M25PXX_USE_FAST_READ
  57. #define OPCODE_READ OPCODE_FAST_READ
  58. #define FAST_READ_DUMMY_BYTE 1
  59. #else
  60. #define OPCODE_READ OPCODE_NORM_READ
  61. #define FAST_READ_DUMMY_BYTE 0
  62. #endif
  63. /****************************************************************************/
  64. struct m25p {
  65. struct spi_device *spi;
  66. struct mutex lock;
  67. struct mtd_info mtd;
  68. unsigned partitioned:1;
  69. u8 erase_opcode;
  70. u8 *command;
  71. };
  72. static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
  73. {
  74. return container_of(mtd, struct m25p, mtd);
  75. }
  76. /****************************************************************************/
  77. /*
  78. * Internal helper functions
  79. */
  80. /*
  81. * Read the status register, returning its value in the location
  82. * Return the status register value.
  83. * Returns negative if error occurred.
  84. */
  85. static int read_sr(struct m25p *flash)
  86. {
  87. ssize_t retval;
  88. u8 code = OPCODE_RDSR;
  89. u8 val;
  90. retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
  91. if (retval < 0) {
  92. dev_err(&flash->spi->dev, "error %d reading SR\n",
  93. (int) retval);
  94. return retval;
  95. }
  96. return val;
  97. }
  98. /*
  99. * Write status register 1 byte
  100. * Returns negative if error occurred.
  101. */
  102. static int write_sr(struct m25p *flash, u8 val)
  103. {
  104. flash->command[0] = OPCODE_WRSR;
  105. flash->command[1] = val;
  106. return spi_write(flash->spi, flash->command, 2);
  107. }
  108. /*
  109. * Set write enable latch with Write Enable command.
  110. * Returns negative if error occurred.
  111. */
  112. static inline int write_enable(struct m25p *flash)
  113. {
  114. u8 code = OPCODE_WREN;
  115. return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
  116. }
  117. /*
  118. * Send write disble instruction to the chip.
  119. */
  120. static inline int write_disable(struct m25p *flash)
  121. {
  122. u8 code = OPCODE_WRDI;
  123. return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
  124. }
  125. /*
  126. * Service routine to read status register until ready, or timeout occurs.
  127. * Returns non-zero if error.
  128. */
  129. static int wait_till_ready(struct m25p *flash)
  130. {
  131. unsigned long deadline;
  132. int sr;
  133. deadline = jiffies + MAX_READY_WAIT_JIFFIES;
  134. do {
  135. if ((sr = read_sr(flash)) < 0)
  136. break;
  137. else if (!(sr & SR_WIP))
  138. return 0;
  139. cond_resched();
  140. } while (!time_after_eq(jiffies, deadline));
  141. return 1;
  142. }
  143. /*
  144. * Erase the whole flash memory
  145. *
  146. * Returns 0 if successful, non-zero otherwise.
  147. */
  148. static int erase_chip(struct m25p *flash)
  149. {
  150. DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %lldKiB\n",
  151. dev_name(&flash->spi->dev), __func__,
  152. (long long)(flash->mtd.size >> 10));
  153. /* Wait until finished previous write command. */
  154. if (wait_till_ready(flash))
  155. return 1;
  156. /* Send write enable, then erase commands. */
  157. write_enable(flash);
  158. /* Set up command buffer. */
  159. flash->command[0] = OPCODE_CHIP_ERASE;
  160. spi_write(flash->spi, flash->command, 1);
  161. return 0;
  162. }
  163. /*
  164. * Erase one sector of flash memory at offset ``offset'' which is any
  165. * address within the sector which should be erased.
  166. *
  167. * Returns 0 if successful, non-zero otherwise.
  168. */
  169. static int erase_sector(struct m25p *flash, u32 offset)
  170. {
  171. DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n",
  172. dev_name(&flash->spi->dev), __func__,
  173. flash->mtd.erasesize / 1024, offset);
  174. /* Wait until finished previous write command. */
  175. if (wait_till_ready(flash))
  176. return 1;
  177. /* Send write enable, then erase commands. */
  178. write_enable(flash);
  179. /* Set up command buffer. */
  180. flash->command[0] = flash->erase_opcode;
  181. flash->command[1] = offset >> 16;
  182. flash->command[2] = offset >> 8;
  183. flash->command[3] = offset;
  184. spi_write(flash->spi, flash->command, CMD_SIZE);
  185. return 0;
  186. }
  187. /****************************************************************************/
  188. /*
  189. * MTD implementation
  190. */
  191. /*
  192. * Erase an address range on the flash chip. The address range may extend
  193. * one or more erase sectors. Return an error is there is a problem erasing.
  194. */
  195. static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
  196. {
  197. struct m25p *flash = mtd_to_m25p(mtd);
  198. u32 addr,len;
  199. uint32_t rem;
  200. DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%llx, len %lld\n",
  201. dev_name(&flash->spi->dev), __func__, "at",
  202. (long long)instr->addr, (long long)instr->len);
  203. /* sanity checks */
  204. if (instr->addr + instr->len > flash->mtd.size)
  205. return -EINVAL;
  206. div_u64_rem(instr->len, mtd->erasesize, &rem);
  207. if (rem)
  208. return -EINVAL;
  209. addr = instr->addr;
  210. len = instr->len;
  211. mutex_lock(&flash->lock);
  212. /* whole-chip erase? */
  213. if (len == flash->mtd.size) {
  214. if (erase_chip(flash)) {
  215. instr->state = MTD_ERASE_FAILED;
  216. mutex_unlock(&flash->lock);
  217. return -EIO;
  218. }
  219. /* REVISIT in some cases we could speed up erasing large regions
  220. * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
  221. * to use "small sector erase", but that's not always optimal.
  222. */
  223. /* "sector"-at-a-time erase */
  224. } else {
  225. while (len) {
  226. if (erase_sector(flash, addr)) {
  227. instr->state = MTD_ERASE_FAILED;
  228. mutex_unlock(&flash->lock);
  229. return -EIO;
  230. }
  231. addr += mtd->erasesize;
  232. len -= mtd->erasesize;
  233. }
  234. }
  235. mutex_unlock(&flash->lock);
  236. instr->state = MTD_ERASE_DONE;
  237. mtd_erase_callback(instr);
  238. return 0;
  239. }
  240. /*
  241. * Read an address range from the flash chip. The address range
  242. * may be any size provided it is within the physical boundaries.
  243. */
  244. static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
  245. size_t *retlen, u_char *buf)
  246. {
  247. struct m25p *flash = mtd_to_m25p(mtd);
  248. struct spi_transfer t[2];
  249. struct spi_message m;
  250. DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
  251. dev_name(&flash->spi->dev), __func__, "from",
  252. (u32)from, len);
  253. /* sanity checks */
  254. if (!len)
  255. return 0;
  256. if (from + len > flash->mtd.size)
  257. return -EINVAL;
  258. spi_message_init(&m);
  259. memset(t, 0, (sizeof t));
  260. /* NOTE:
  261. * OPCODE_FAST_READ (if available) is faster.
  262. * Should add 1 byte DUMMY_BYTE.
  263. */
  264. t[0].tx_buf = flash->command;
  265. t[0].len = CMD_SIZE + FAST_READ_DUMMY_BYTE;
  266. spi_message_add_tail(&t[0], &m);
  267. t[1].rx_buf = buf;
  268. t[1].len = len;
  269. spi_message_add_tail(&t[1], &m);
  270. /* Byte count starts at zero. */
  271. if (retlen)
  272. *retlen = 0;
  273. mutex_lock(&flash->lock);
  274. /* Wait till previous write/erase is done. */
  275. if (wait_till_ready(flash)) {
  276. /* REVISIT status return?? */
  277. mutex_unlock(&flash->lock);
  278. return 1;
  279. }
  280. /* FIXME switch to OPCODE_FAST_READ. It's required for higher
  281. * clocks; and at this writing, every chip this driver handles
  282. * supports that opcode.
  283. */
  284. /* Set up the write data buffer. */
  285. flash->command[0] = OPCODE_READ;
  286. flash->command[1] = from >> 16;
  287. flash->command[2] = from >> 8;
  288. flash->command[3] = from;
  289. spi_sync(flash->spi, &m);
  290. *retlen = m.actual_length - CMD_SIZE - FAST_READ_DUMMY_BYTE;
  291. mutex_unlock(&flash->lock);
  292. return 0;
  293. }
  294. /*
  295. * Write an address range to the flash chip. Data must be written in
  296. * FLASH_PAGESIZE chunks. The address range may be any size provided
  297. * it is within the physical boundaries.
  298. */
  299. static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
  300. size_t *retlen, const u_char *buf)
  301. {
  302. struct m25p *flash = mtd_to_m25p(mtd);
  303. u32 page_offset, page_size;
  304. struct spi_transfer t[2];
  305. struct spi_message m;
  306. DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
  307. dev_name(&flash->spi->dev), __func__, "to",
  308. (u32)to, len);
  309. if (retlen)
  310. *retlen = 0;
  311. /* sanity checks */
  312. if (!len)
  313. return(0);
  314. if (to + len > flash->mtd.size)
  315. return -EINVAL;
  316. spi_message_init(&m);
  317. memset(t, 0, (sizeof t));
  318. t[0].tx_buf = flash->command;
  319. t[0].len = CMD_SIZE;
  320. spi_message_add_tail(&t[0], &m);
  321. t[1].tx_buf = buf;
  322. spi_message_add_tail(&t[1], &m);
  323. mutex_lock(&flash->lock);
  324. /* Wait until finished previous write command. */
  325. if (wait_till_ready(flash)) {
  326. mutex_unlock(&flash->lock);
  327. return 1;
  328. }
  329. write_enable(flash);
  330. /* Set up the opcode in the write buffer. */
  331. flash->command[0] = OPCODE_PP;
  332. flash->command[1] = to >> 16;
  333. flash->command[2] = to >> 8;
  334. flash->command[3] = to;
  335. /* what page do we start with? */
  336. page_offset = to % FLASH_PAGESIZE;
  337. /* do all the bytes fit onto one page? */
  338. if (page_offset + len <= FLASH_PAGESIZE) {
  339. t[1].len = len;
  340. spi_sync(flash->spi, &m);
  341. *retlen = m.actual_length - CMD_SIZE;
  342. } else {
  343. u32 i;
  344. /* the size of data remaining on the first page */
  345. page_size = FLASH_PAGESIZE - page_offset;
  346. t[1].len = page_size;
  347. spi_sync(flash->spi, &m);
  348. *retlen = m.actual_length - CMD_SIZE;
  349. /* write everything in PAGESIZE chunks */
  350. for (i = page_size; i < len; i += page_size) {
  351. page_size = len - i;
  352. if (page_size > FLASH_PAGESIZE)
  353. page_size = FLASH_PAGESIZE;
  354. /* write the next page to flash */
  355. flash->command[1] = (to + i) >> 16;
  356. flash->command[2] = (to + i) >> 8;
  357. flash->command[3] = (to + i);
  358. t[1].tx_buf = buf + i;
  359. t[1].len = page_size;
  360. wait_till_ready(flash);
  361. write_enable(flash);
  362. spi_sync(flash->spi, &m);
  363. if (retlen)
  364. *retlen += m.actual_length - CMD_SIZE;
  365. }
  366. }
  367. mutex_unlock(&flash->lock);
  368. return 0;
  369. }
  370. static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
  371. size_t *retlen, const u_char *buf)
  372. {
  373. struct m25p *flash = mtd_to_m25p(mtd);
  374. struct spi_transfer t[2];
  375. struct spi_message m;
  376. size_t actual;
  377. int cmd_sz, ret;
  378. if (retlen)
  379. *retlen = 0;
  380. /* sanity checks */
  381. if (!len)
  382. return 0;
  383. if (to + len > flash->mtd.size)
  384. return -EINVAL;
  385. spi_message_init(&m);
  386. memset(t, 0, (sizeof t));
  387. t[0].tx_buf = flash->command;
  388. t[0].len = CMD_SIZE;
  389. spi_message_add_tail(&t[0], &m);
  390. t[1].tx_buf = buf;
  391. spi_message_add_tail(&t[1], &m);
  392. mutex_lock(&flash->lock);
  393. /* Wait until finished previous write command. */
  394. ret = wait_till_ready(flash);
  395. if (ret)
  396. goto time_out;
  397. write_enable(flash);
  398. actual = to % 2;
  399. /* Start write from odd address. */
  400. if (actual) {
  401. flash->command[0] = OPCODE_BP;
  402. flash->command[1] = to >> 16;
  403. flash->command[2] = to >> 8;
  404. flash->command[3] = to;
  405. /* write one byte. */
  406. t[1].len = 1;
  407. spi_sync(flash->spi, &m);
  408. ret = wait_till_ready(flash);
  409. if (ret)
  410. goto time_out;
  411. *retlen += m.actual_length - CMD_SIZE;
  412. }
  413. to += actual;
  414. flash->command[0] = OPCODE_AAI_WP;
  415. flash->command[1] = to >> 16;
  416. flash->command[2] = to >> 8;
  417. flash->command[3] = to;
  418. /* Write out most of the data here. */
  419. cmd_sz = CMD_SIZE;
  420. for (; actual < len - 1; actual += 2) {
  421. t[0].len = cmd_sz;
  422. /* write two bytes. */
  423. t[1].len = 2;
  424. t[1].tx_buf = buf + actual;
  425. spi_sync(flash->spi, &m);
  426. ret = wait_till_ready(flash);
  427. if (ret)
  428. goto time_out;
  429. *retlen += m.actual_length - cmd_sz;
  430. cmd_sz = 1;
  431. to += 2;
  432. }
  433. write_disable(flash);
  434. ret = wait_till_ready(flash);
  435. if (ret)
  436. goto time_out;
  437. /* Write out trailing byte if it exists. */
  438. if (actual != len) {
  439. write_enable(flash);
  440. flash->command[0] = OPCODE_BP;
  441. flash->command[1] = to >> 16;
  442. flash->command[2] = to >> 8;
  443. flash->command[3] = to;
  444. t[0].len = CMD_SIZE;
  445. t[1].len = 1;
  446. t[1].tx_buf = buf + actual;
  447. spi_sync(flash->spi, &m);
  448. ret = wait_till_ready(flash);
  449. if (ret)
  450. goto time_out;
  451. *retlen += m.actual_length - CMD_SIZE;
  452. write_disable(flash);
  453. }
  454. time_out:
  455. mutex_unlock(&flash->lock);
  456. return ret;
  457. }
  458. /****************************************************************************/
  459. /*
  460. * SPI device driver setup and teardown
  461. */
  462. struct flash_info {
  463. /* JEDEC id zero means "no ID" (most older chips); otherwise it has
  464. * a high byte of zero plus three data bytes: the manufacturer id,
  465. * then a two byte device id.
  466. */
  467. u32 jedec_id;
  468. u16 ext_id;
  469. /* The size listed here is what works with OPCODE_SE, which isn't
  470. * necessarily called a "sector" by the vendor.
  471. */
  472. unsigned sector_size;
  473. u16 n_sectors;
  474. u16 flags;
  475. #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
  476. };
  477. #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
  478. ((kernel_ulong_t)&(struct flash_info) { \
  479. .jedec_id = (_jedec_id), \
  480. .ext_id = (_ext_id), \
  481. .sector_size = (_sector_size), \
  482. .n_sectors = (_n_sectors), \
  483. .flags = (_flags), \
  484. })
  485. /* NOTE: double check command sets and memory organization when you add
  486. * more flash chips. This current list focusses on newer chips, which
  487. * have been converging on command sets which including JEDEC ID.
  488. */
  489. static const struct spi_device_id m25p_ids[] = {
  490. /* Atmel -- some are (confusingly) marketed as "DataFlash" */
  491. { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
  492. { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
  493. { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
  494. { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
  495. { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
  496. { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
  497. { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
  498. { "at26df321", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
  499. /* Macronix */
  500. { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
  501. { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
  502. { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
  503. { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
  504. /* Spansion -- single (large) sector size only, at least
  505. * for the chips listed here (without boot sectors).
  506. */
  507. { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
  508. { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
  509. { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
  510. { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
  511. { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
  512. { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
  513. { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
  514. { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
  515. { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
  516. /* SST -- large erase sizes are "overlays", "sectors" are 4K */
  517. { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
  518. { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
  519. { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
  520. { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
  521. { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
  522. { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
  523. { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
  524. { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
  525. /* ST Microelectronics -- newer production may have feature updates */
  526. { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
  527. { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
  528. { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
  529. { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
  530. { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
  531. { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
  532. { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
  533. { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
  534. { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
  535. { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
  536. { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
  537. { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
  538. { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
  539. { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
  540. /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
  541. { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
  542. { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
  543. { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
  544. { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
  545. { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
  546. { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
  547. { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
  548. { },
  549. };
  550. MODULE_DEVICE_TABLE(spi, m25p_ids);
  551. static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi)
  552. {
  553. int tmp;
  554. u8 code = OPCODE_RDID;
  555. u8 id[5];
  556. u32 jedec;
  557. u16 ext_jedec;
  558. struct flash_info *info;
  559. /* JEDEC also defines an optional "extended device information"
  560. * string for after vendor-specific data, after the three bytes
  561. * we use here. Supporting some chips might require using it.
  562. */
  563. tmp = spi_write_then_read(spi, &code, 1, id, 5);
  564. if (tmp < 0) {
  565. DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n",
  566. dev_name(&spi->dev), tmp);
  567. return NULL;
  568. }
  569. jedec = id[0];
  570. jedec = jedec << 8;
  571. jedec |= id[1];
  572. jedec = jedec << 8;
  573. jedec |= id[2];
  574. ext_jedec = id[3] << 8 | id[4];
  575. for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
  576. info = (void *)m25p_ids[tmp].driver_data;
  577. if (info->jedec_id == jedec) {
  578. if (info->ext_id != 0 && info->ext_id != ext_jedec)
  579. continue;
  580. return &m25p_ids[tmp];
  581. }
  582. }
  583. return NULL;
  584. }
  585. /*
  586. * board specific setup should have ensured the SPI clock used here
  587. * matches what the READ command supports, at least until this driver
  588. * understands FAST_READ (for clocks over 25 MHz).
  589. */
  590. static int __devinit m25p_probe(struct spi_device *spi)
  591. {
  592. const struct spi_device_id *id;
  593. struct flash_platform_data *data;
  594. struct m25p *flash;
  595. struct flash_info *info;
  596. unsigned i;
  597. /* Platform data helps sort out which chip type we have, as
  598. * well as how this board partitions it. If we don't have
  599. * a chip ID, try the JEDEC id commands; they'll work for most
  600. * newer chips, even if we don't recognize the particular chip.
  601. */
  602. data = spi->dev.platform_data;
  603. if (data && data->type) {
  604. for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
  605. id = &m25p_ids[i];
  606. info = (void *)m25p_ids[i].driver_data;
  607. if (strcmp(data->type, id->name))
  608. continue;
  609. break;
  610. }
  611. /* unrecognized chip? */
  612. if (i == ARRAY_SIZE(m25p_ids) - 1) {
  613. DEBUG(MTD_DEBUG_LEVEL0, "%s: unrecognized id %s\n",
  614. dev_name(&spi->dev), data->type);
  615. info = NULL;
  616. /* recognized; is that chip really what's there? */
  617. } else if (info->jedec_id) {
  618. id = jedec_probe(spi);
  619. if (id != &m25p_ids[i]) {
  620. dev_warn(&spi->dev, "found %s, expected %s\n",
  621. id ? id->name : "UNKNOWN",
  622. m25p_ids[i].name);
  623. info = NULL;
  624. }
  625. }
  626. } else {
  627. id = jedec_probe(spi);
  628. if (!id)
  629. id = spi_get_device_id(spi);
  630. info = (void *)id->driver_data;
  631. }
  632. if (!info)
  633. return -ENODEV;
  634. flash = kzalloc(sizeof *flash, GFP_KERNEL);
  635. if (!flash)
  636. return -ENOMEM;
  637. flash->command = kmalloc(CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
  638. if (!flash->command) {
  639. kfree(flash);
  640. return -ENOMEM;
  641. }
  642. flash->spi = spi;
  643. mutex_init(&flash->lock);
  644. dev_set_drvdata(&spi->dev, flash);
  645. /*
  646. * Atmel and SST serial flash tend to power
  647. * up with the software protection bits set
  648. */
  649. if (info->jedec_id >> 16 == 0x1f ||
  650. info->jedec_id >> 16 == 0xbf) {
  651. write_enable(flash);
  652. write_sr(flash, 0);
  653. }
  654. if (data && data->name)
  655. flash->mtd.name = data->name;
  656. else
  657. flash->mtd.name = dev_name(&spi->dev);
  658. flash->mtd.type = MTD_NORFLASH;
  659. flash->mtd.writesize = 1;
  660. flash->mtd.flags = MTD_CAP_NORFLASH;
  661. flash->mtd.size = info->sector_size * info->n_sectors;
  662. flash->mtd.erase = m25p80_erase;
  663. flash->mtd.read = m25p80_read;
  664. /* sst flash chips use AAI word program */
  665. if (info->jedec_id >> 16 == 0xbf)
  666. flash->mtd.write = sst_write;
  667. else
  668. flash->mtd.write = m25p80_write;
  669. /* prefer "small sector" erase if possible */
  670. if (info->flags & SECT_4K) {
  671. flash->erase_opcode = OPCODE_BE_4K;
  672. flash->mtd.erasesize = 4096;
  673. } else {
  674. flash->erase_opcode = OPCODE_SE;
  675. flash->mtd.erasesize = info->sector_size;
  676. }
  677. flash->mtd.dev.parent = &spi->dev;
  678. dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
  679. (long long)flash->mtd.size >> 10);
  680. DEBUG(MTD_DEBUG_LEVEL2,
  681. "mtd .name = %s, .size = 0x%llx (%lldMiB) "
  682. ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
  683. flash->mtd.name,
  684. (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
  685. flash->mtd.erasesize, flash->mtd.erasesize / 1024,
  686. flash->mtd.numeraseregions);
  687. if (flash->mtd.numeraseregions)
  688. for (i = 0; i < flash->mtd.numeraseregions; i++)
  689. DEBUG(MTD_DEBUG_LEVEL2,
  690. "mtd.eraseregions[%d] = { .offset = 0x%llx, "
  691. ".erasesize = 0x%.8x (%uKiB), "
  692. ".numblocks = %d }\n",
  693. i, (long long)flash->mtd.eraseregions[i].offset,
  694. flash->mtd.eraseregions[i].erasesize,
  695. flash->mtd.eraseregions[i].erasesize / 1024,
  696. flash->mtd.eraseregions[i].numblocks);
  697. /* partitions should match sector boundaries; and it may be good to
  698. * use readonly partitions for writeprotected sectors (BP2..BP0).
  699. */
  700. if (mtd_has_partitions()) {
  701. struct mtd_partition *parts = NULL;
  702. int nr_parts = 0;
  703. if (mtd_has_cmdlinepart()) {
  704. static const char *part_probes[]
  705. = { "cmdlinepart", NULL, };
  706. nr_parts = parse_mtd_partitions(&flash->mtd,
  707. part_probes, &parts, 0);
  708. }
  709. if (nr_parts <= 0 && data && data->parts) {
  710. parts = data->parts;
  711. nr_parts = data->nr_parts;
  712. }
  713. if (nr_parts > 0) {
  714. for (i = 0; i < nr_parts; i++) {
  715. DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = "
  716. "{.name = %s, .offset = 0x%llx, "
  717. ".size = 0x%llx (%lldKiB) }\n",
  718. i, parts[i].name,
  719. (long long)parts[i].offset,
  720. (long long)parts[i].size,
  721. (long long)(parts[i].size >> 10));
  722. }
  723. flash->partitioned = 1;
  724. return add_mtd_partitions(&flash->mtd, parts, nr_parts);
  725. }
  726. } else if (data && data->nr_parts)
  727. dev_warn(&spi->dev, "ignoring %d default partitions on %s\n",
  728. data->nr_parts, data->name);
  729. return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0;
  730. }
  731. static int __devexit m25p_remove(struct spi_device *spi)
  732. {
  733. struct m25p *flash = dev_get_drvdata(&spi->dev);
  734. int status;
  735. /* Clean up MTD stuff. */
  736. if (mtd_has_partitions() && flash->partitioned)
  737. status = del_mtd_partitions(&flash->mtd);
  738. else
  739. status = del_mtd_device(&flash->mtd);
  740. if (status == 0) {
  741. kfree(flash->command);
  742. kfree(flash);
  743. }
  744. return 0;
  745. }
  746. static struct spi_driver m25p80_driver = {
  747. .driver = {
  748. .name = "m25p80",
  749. .bus = &spi_bus_type,
  750. .owner = THIS_MODULE,
  751. },
  752. .id_table = m25p_ids,
  753. .probe = m25p_probe,
  754. .remove = __devexit_p(m25p_remove),
  755. /* REVISIT: many of these chips have deep power-down modes, which
  756. * should clearly be entered on suspend() to minimize power use.
  757. * And also when they're otherwise idle...
  758. */
  759. };
  760. static int __init m25p80_init(void)
  761. {
  762. return spi_register_driver(&m25p80_driver);
  763. }
  764. static void __exit m25p80_exit(void)
  765. {
  766. spi_unregister_driver(&m25p80_driver);
  767. }
  768. module_init(m25p80_init);
  769. module_exit(m25p80_exit);
  770. MODULE_LICENSE("GPL");
  771. MODULE_AUTHOR("Mike Lavender");
  772. MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");