device.h 18 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #ifndef MLX4_DEVICE_H
  33. #define MLX4_DEVICE_H
  34. #include <linux/pci.h>
  35. #include <linux/completion.h>
  36. #include <linux/radix-tree.h>
  37. #include <linux/atomic.h>
  38. #define MAX_MSIX_P_PORT 17
  39. #define MAX_MSIX 64
  40. #define MSIX_LEGACY_SZ 4
  41. #define MIN_MSIX_P_PORT 5
  42. enum {
  43. MLX4_FLAG_MSI_X = 1 << 0,
  44. MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
  45. MLX4_FLAG_MASTER = 1 << 2,
  46. MLX4_FLAG_SLAVE = 1 << 3,
  47. MLX4_FLAG_SRIOV = 1 << 4,
  48. };
  49. enum {
  50. MLX4_MAX_PORTS = 2
  51. };
  52. enum {
  53. MLX4_BOARD_ID_LEN = 64
  54. };
  55. enum {
  56. MLX4_MAX_NUM_PF = 16,
  57. MLX4_MAX_NUM_VF = 64,
  58. MLX4_MFUNC_MAX = 80,
  59. MLX4_MFUNC_EQ_NUM = 4,
  60. MLX4_MFUNC_MAX_EQES = 8,
  61. MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
  62. };
  63. enum {
  64. MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
  65. MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
  66. MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
  67. MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
  68. MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
  69. MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
  70. MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
  71. MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
  72. MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
  73. MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
  74. MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
  75. MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
  76. MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
  77. MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
  78. MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
  79. MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
  80. MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
  81. MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
  82. MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
  83. MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
  84. MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
  85. MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
  86. MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
  87. MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
  88. MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
  89. MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55
  90. };
  91. enum {
  92. MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
  93. MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
  94. MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2
  95. };
  96. #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
  97. enum {
  98. MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
  99. MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
  100. MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
  101. MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
  102. MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
  103. };
  104. enum mlx4_event {
  105. MLX4_EVENT_TYPE_COMP = 0x00,
  106. MLX4_EVENT_TYPE_PATH_MIG = 0x01,
  107. MLX4_EVENT_TYPE_COMM_EST = 0x02,
  108. MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
  109. MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
  110. MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
  111. MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
  112. MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
  113. MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
  114. MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
  115. MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
  116. MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
  117. MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
  118. MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
  119. MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
  120. MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
  121. MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
  122. MLX4_EVENT_TYPE_CMD = 0x0a,
  123. MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
  124. MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
  125. MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
  126. MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
  127. MLX4_EVENT_TYPE_NONE = 0xff,
  128. };
  129. enum {
  130. MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
  131. MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
  132. };
  133. enum {
  134. MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
  135. };
  136. enum {
  137. MLX4_PERM_LOCAL_READ = 1 << 10,
  138. MLX4_PERM_LOCAL_WRITE = 1 << 11,
  139. MLX4_PERM_REMOTE_READ = 1 << 12,
  140. MLX4_PERM_REMOTE_WRITE = 1 << 13,
  141. MLX4_PERM_ATOMIC = 1 << 14
  142. };
  143. enum {
  144. MLX4_OPCODE_NOP = 0x00,
  145. MLX4_OPCODE_SEND_INVAL = 0x01,
  146. MLX4_OPCODE_RDMA_WRITE = 0x08,
  147. MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
  148. MLX4_OPCODE_SEND = 0x0a,
  149. MLX4_OPCODE_SEND_IMM = 0x0b,
  150. MLX4_OPCODE_LSO = 0x0e,
  151. MLX4_OPCODE_RDMA_READ = 0x10,
  152. MLX4_OPCODE_ATOMIC_CS = 0x11,
  153. MLX4_OPCODE_ATOMIC_FA = 0x12,
  154. MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
  155. MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
  156. MLX4_OPCODE_BIND_MW = 0x18,
  157. MLX4_OPCODE_FMR = 0x19,
  158. MLX4_OPCODE_LOCAL_INVAL = 0x1b,
  159. MLX4_OPCODE_CONFIG_CMD = 0x1f,
  160. MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
  161. MLX4_RECV_OPCODE_SEND = 0x01,
  162. MLX4_RECV_OPCODE_SEND_IMM = 0x02,
  163. MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
  164. MLX4_CQE_OPCODE_ERROR = 0x1e,
  165. MLX4_CQE_OPCODE_RESIZE = 0x16,
  166. };
  167. enum {
  168. MLX4_STAT_RATE_OFFSET = 5
  169. };
  170. enum mlx4_protocol {
  171. MLX4_PROT_IB_IPV6 = 0,
  172. MLX4_PROT_ETH,
  173. MLX4_PROT_IB_IPV4,
  174. MLX4_PROT_FCOE
  175. };
  176. enum {
  177. MLX4_MTT_FLAG_PRESENT = 1
  178. };
  179. enum mlx4_qp_region {
  180. MLX4_QP_REGION_FW = 0,
  181. MLX4_QP_REGION_ETH_ADDR,
  182. MLX4_QP_REGION_FC_ADDR,
  183. MLX4_QP_REGION_FC_EXCH,
  184. MLX4_NUM_QP_REGION
  185. };
  186. enum mlx4_port_type {
  187. MLX4_PORT_TYPE_NONE = 0,
  188. MLX4_PORT_TYPE_IB = 1,
  189. MLX4_PORT_TYPE_ETH = 2,
  190. MLX4_PORT_TYPE_AUTO = 3
  191. };
  192. enum mlx4_special_vlan_idx {
  193. MLX4_NO_VLAN_IDX = 0,
  194. MLX4_VLAN_MISS_IDX,
  195. MLX4_VLAN_REGULAR
  196. };
  197. enum mlx4_steer_type {
  198. MLX4_MC_STEER = 0,
  199. MLX4_UC_STEER,
  200. MLX4_NUM_STEERS
  201. };
  202. enum {
  203. MLX4_NUM_FEXCH = 64 * 1024,
  204. };
  205. enum {
  206. MLX4_MAX_FAST_REG_PAGES = 511,
  207. };
  208. static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
  209. {
  210. return (major << 32) | (minor << 16) | subminor;
  211. }
  212. struct mlx4_caps {
  213. u64 fw_ver;
  214. u32 function;
  215. int num_ports;
  216. int vl_cap[MLX4_MAX_PORTS + 1];
  217. int ib_mtu_cap[MLX4_MAX_PORTS + 1];
  218. __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
  219. u64 def_mac[MLX4_MAX_PORTS + 1];
  220. int eth_mtu_cap[MLX4_MAX_PORTS + 1];
  221. int gid_table_len[MLX4_MAX_PORTS + 1];
  222. int pkey_table_len[MLX4_MAX_PORTS + 1];
  223. int trans_type[MLX4_MAX_PORTS + 1];
  224. int vendor_oui[MLX4_MAX_PORTS + 1];
  225. int wavelength[MLX4_MAX_PORTS + 1];
  226. u64 trans_code[MLX4_MAX_PORTS + 1];
  227. int local_ca_ack_delay;
  228. int num_uars;
  229. u32 uar_page_size;
  230. int bf_reg_size;
  231. int bf_regs_per_page;
  232. int max_sq_sg;
  233. int max_rq_sg;
  234. int num_qps;
  235. int max_wqes;
  236. int max_sq_desc_sz;
  237. int max_rq_desc_sz;
  238. int max_qp_init_rdma;
  239. int max_qp_dest_rdma;
  240. int sqp_start;
  241. int num_srqs;
  242. int max_srq_wqes;
  243. int max_srq_sge;
  244. int reserved_srqs;
  245. int num_cqs;
  246. int max_cqes;
  247. int reserved_cqs;
  248. int num_eqs;
  249. int reserved_eqs;
  250. int num_comp_vectors;
  251. int comp_pool;
  252. int num_mpts;
  253. int max_fmr_maps;
  254. int num_mtts;
  255. int fmr_reserved_mtts;
  256. int reserved_mtts;
  257. int reserved_mrws;
  258. int reserved_uars;
  259. int num_mgms;
  260. int num_amgms;
  261. int reserved_mcgs;
  262. int num_qp_per_mgm;
  263. int num_pds;
  264. int reserved_pds;
  265. int max_xrcds;
  266. int reserved_xrcds;
  267. int mtt_entry_sz;
  268. u32 max_msg_sz;
  269. u32 page_size_cap;
  270. u64 flags;
  271. u64 flags2;
  272. u32 bmme_flags;
  273. u32 reserved_lkey;
  274. u16 stat_rate_support;
  275. u8 port_width_cap[MLX4_MAX_PORTS + 1];
  276. int max_gso_sz;
  277. int max_rss_tbl_sz;
  278. int reserved_qps_cnt[MLX4_NUM_QP_REGION];
  279. int reserved_qps;
  280. int reserved_qps_base[MLX4_NUM_QP_REGION];
  281. int log_num_macs;
  282. int log_num_vlans;
  283. int log_num_prios;
  284. enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
  285. u8 supported_type[MLX4_MAX_PORTS + 1];
  286. u8 suggested_type[MLX4_MAX_PORTS + 1];
  287. u8 default_sense[MLX4_MAX_PORTS + 1];
  288. u32 port_mask[MLX4_MAX_PORTS + 1];
  289. enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
  290. u32 max_counters;
  291. u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
  292. };
  293. struct mlx4_buf_list {
  294. void *buf;
  295. dma_addr_t map;
  296. };
  297. struct mlx4_buf {
  298. struct mlx4_buf_list direct;
  299. struct mlx4_buf_list *page_list;
  300. int nbufs;
  301. int npages;
  302. int page_shift;
  303. };
  304. struct mlx4_mtt {
  305. u32 offset;
  306. int order;
  307. int page_shift;
  308. };
  309. enum {
  310. MLX4_DB_PER_PAGE = PAGE_SIZE / 4
  311. };
  312. struct mlx4_db_pgdir {
  313. struct list_head list;
  314. DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
  315. DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
  316. unsigned long *bits[2];
  317. __be32 *db_page;
  318. dma_addr_t db_dma;
  319. };
  320. struct mlx4_ib_user_db_page;
  321. struct mlx4_db {
  322. __be32 *db;
  323. union {
  324. struct mlx4_db_pgdir *pgdir;
  325. struct mlx4_ib_user_db_page *user_page;
  326. } u;
  327. dma_addr_t dma;
  328. int index;
  329. int order;
  330. };
  331. struct mlx4_hwq_resources {
  332. struct mlx4_db db;
  333. struct mlx4_mtt mtt;
  334. struct mlx4_buf buf;
  335. };
  336. struct mlx4_mr {
  337. struct mlx4_mtt mtt;
  338. u64 iova;
  339. u64 size;
  340. u32 key;
  341. u32 pd;
  342. u32 access;
  343. int enabled;
  344. };
  345. struct mlx4_fmr {
  346. struct mlx4_mr mr;
  347. struct mlx4_mpt_entry *mpt;
  348. __be64 *mtts;
  349. dma_addr_t dma_handle;
  350. int max_pages;
  351. int max_maps;
  352. int maps;
  353. u8 page_shift;
  354. };
  355. struct mlx4_uar {
  356. unsigned long pfn;
  357. int index;
  358. struct list_head bf_list;
  359. unsigned free_bf_bmap;
  360. void __iomem *map;
  361. void __iomem *bf_map;
  362. };
  363. struct mlx4_bf {
  364. unsigned long offset;
  365. int buf_size;
  366. struct mlx4_uar *uar;
  367. void __iomem *reg;
  368. };
  369. struct mlx4_cq {
  370. void (*comp) (struct mlx4_cq *);
  371. void (*event) (struct mlx4_cq *, enum mlx4_event);
  372. struct mlx4_uar *uar;
  373. u32 cons_index;
  374. __be32 *set_ci_db;
  375. __be32 *arm_db;
  376. int arm_sn;
  377. int cqn;
  378. unsigned vector;
  379. atomic_t refcount;
  380. struct completion free;
  381. };
  382. struct mlx4_qp {
  383. void (*event) (struct mlx4_qp *, enum mlx4_event);
  384. int qpn;
  385. atomic_t refcount;
  386. struct completion free;
  387. };
  388. struct mlx4_srq {
  389. void (*event) (struct mlx4_srq *, enum mlx4_event);
  390. int srqn;
  391. int max;
  392. int max_gs;
  393. int wqe_shift;
  394. atomic_t refcount;
  395. struct completion free;
  396. };
  397. struct mlx4_av {
  398. __be32 port_pd;
  399. u8 reserved1;
  400. u8 g_slid;
  401. __be16 dlid;
  402. u8 reserved2;
  403. u8 gid_index;
  404. u8 stat_rate;
  405. u8 hop_limit;
  406. __be32 sl_tclass_flowlabel;
  407. u8 dgid[16];
  408. };
  409. struct mlx4_eth_av {
  410. __be32 port_pd;
  411. u8 reserved1;
  412. u8 smac_idx;
  413. u16 reserved2;
  414. u8 reserved3;
  415. u8 gid_index;
  416. u8 stat_rate;
  417. u8 hop_limit;
  418. __be32 sl_tclass_flowlabel;
  419. u8 dgid[16];
  420. u32 reserved4[2];
  421. __be16 vlan;
  422. u8 mac[6];
  423. };
  424. union mlx4_ext_av {
  425. struct mlx4_av ib;
  426. struct mlx4_eth_av eth;
  427. };
  428. struct mlx4_counter {
  429. u8 reserved1[3];
  430. u8 counter_mode;
  431. __be32 num_ifc;
  432. u32 reserved2[2];
  433. __be64 rx_frames;
  434. __be64 rx_bytes;
  435. __be64 tx_frames;
  436. __be64 tx_bytes;
  437. };
  438. struct mlx4_dev {
  439. struct pci_dev *pdev;
  440. unsigned long flags;
  441. unsigned long num_slaves;
  442. struct mlx4_caps caps;
  443. struct radix_tree_root qp_table_tree;
  444. u8 rev_id;
  445. char board_id[MLX4_BOARD_ID_LEN];
  446. int num_vfs;
  447. };
  448. struct mlx4_init_port_param {
  449. int set_guid0;
  450. int set_node_guid;
  451. int set_si_guid;
  452. u16 mtu;
  453. int port_width_cap;
  454. u16 vl_cap;
  455. u16 max_gid;
  456. u16 max_pkey;
  457. u64 guid0;
  458. u64 node_guid;
  459. u64 si_guid;
  460. };
  461. #define mlx4_foreach_port(port, dev, type) \
  462. for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
  463. if ((type) == (dev)->caps.port_mask[(port)])
  464. #define mlx4_foreach_ib_transport_port(port, dev) \
  465. for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
  466. if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
  467. ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
  468. static inline int mlx4_is_master(struct mlx4_dev *dev)
  469. {
  470. return dev->flags & MLX4_FLAG_MASTER;
  471. }
  472. static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
  473. {
  474. return (qpn < dev->caps.sqp_start + 8);
  475. }
  476. static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
  477. {
  478. return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
  479. }
  480. static inline int mlx4_is_slave(struct mlx4_dev *dev)
  481. {
  482. return dev->flags & MLX4_FLAG_SLAVE;
  483. }
  484. int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
  485. struct mlx4_buf *buf);
  486. void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
  487. static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
  488. {
  489. if (BITS_PER_LONG == 64 || buf->nbufs == 1)
  490. return buf->direct.buf + offset;
  491. else
  492. return buf->page_list[offset >> PAGE_SHIFT].buf +
  493. (offset & (PAGE_SIZE - 1));
  494. }
  495. int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
  496. void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
  497. int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
  498. void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
  499. int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
  500. void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
  501. int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
  502. void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
  503. int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
  504. struct mlx4_mtt *mtt);
  505. void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
  506. u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
  507. int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
  508. int npages, int page_shift, struct mlx4_mr *mr);
  509. void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
  510. int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
  511. int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  512. int start_index, int npages, u64 *page_list);
  513. int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  514. struct mlx4_buf *buf);
  515. int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
  516. void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
  517. int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
  518. int size, int max_direct);
  519. void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
  520. int size);
  521. int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
  522. struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
  523. unsigned vector, int collapsed);
  524. void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
  525. int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
  526. void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
  527. int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
  528. void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
  529. int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
  530. struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
  531. void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
  532. int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
  533. int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
  534. int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
  535. int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
  536. int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  537. int block_mcast_loopback, enum mlx4_protocol prot);
  538. int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  539. enum mlx4_protocol prot);
  540. int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  541. int block_mcast_loopback, enum mlx4_protocol protocol);
  542. int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  543. enum mlx4_protocol protocol);
  544. int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
  545. int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
  546. int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
  547. int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
  548. int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
  549. int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
  550. void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
  551. int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
  552. int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
  553. void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
  554. void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
  555. int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
  556. u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
  557. int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
  558. u8 promisc);
  559. int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
  560. int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
  561. void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
  562. int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
  563. int npages, u64 iova, u32 *lkey, u32 *rkey);
  564. int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
  565. int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
  566. int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
  567. void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
  568. u32 *lkey, u32 *rkey);
  569. int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
  570. int mlx4_SYNC_TPT(struct mlx4_dev *dev);
  571. int mlx4_test_interrupts(struct mlx4_dev *dev);
  572. int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
  573. void mlx4_release_eq(struct mlx4_dev *dev, int vec);
  574. int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
  575. int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
  576. int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
  577. void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
  578. #endif /* MLX4_DEVICE_H */