samsung-pinctrl.txt 9.5 KB

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  1. Samsung GPIO and Pin Mux/Config controller
  2. Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
  3. controller. It controls the input/output settings on the available pads/pins
  4. and also provides ability to multiplex and configure the output of various
  5. on-chip controllers onto these pads.
  6. Required Properties:
  7. - compatible: should be one of the following.
  8. - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
  9. - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
  10. - reg: Base address of the pin controller hardware module and length of
  11. the address space it occupies.
  12. - Pin banks as child nodes: Pin banks of the controller are represented by child
  13. nodes of the controller node. Bank name is taken from name of the node. Each
  14. bank node must contain following properties:
  15. - gpio-controller: identifies the node as a gpio controller and pin bank.
  16. - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
  17. binding is used, the amount of cells must be specified as 2. See generic
  18. GPIO binding documentation for description of particular cells.
  19. - Pin mux/config groups as child nodes: The pin mux (selecting pin function
  20. mode) and pin config (pull up/down, driver strength) settings are represented
  21. as child nodes of the pin-controller node. There should be atleast one
  22. child node and there is no limit on the count of these child nodes.
  23. The child node should contain a list of pin(s) on which a particular pin
  24. function selection or pin configuration (or both) have to applied. This
  25. list of pins is specified using the property name "samsung,pins". There
  26. should be atleast one pin specfied for this property and there is no upper
  27. limit on the count of pins that can be specified. The pins are specified
  28. using pin names which are derived from the hardware manual of the SoC. As
  29. an example, the pins in GPA0 bank of the pin controller can be represented
  30. as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
  31. The format of the pin names should be (as per the hardware manual)
  32. "[pin bank name]-[pin number within the bank]".
  33. The pin function selection that should be applied on the pins listed in the
  34. child node is specified using the "samsung,pin-function" property. The value
  35. of this property that should be applied to each of the pins listed in the
  36. "samsung,pins" property should be picked from the hardware manual of the SoC
  37. for the specified pin group. This property is optional in the child node if
  38. no specific function selection is desired for the pins listed in the child
  39. node. The value of this property is used as-is to program the pin-controller
  40. function selector register of the pin-bank.
  41. The child node can also optionally specify one or more of the pin
  42. configuration that should be applied on all the pins listed in the
  43. "samsung,pins" property of the child node. The following pin configuration
  44. properties are supported.
  45. - samsung,pin-pud: Pull up/down configuration.
  46. - samsung,pin-drv: Drive strength configuration.
  47. - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
  48. - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
  49. The values specified by these config properties should be derived from the
  50. hardware manual and these values are programmed as-is into the pin
  51. pull up/down and driver strength register of the pin-controller.
  52. Note: A child should include atleast a pin function selection property or
  53. pin configuration property (one or more) or both.
  54. The client nodes that require a particular pin function selection and/or
  55. pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
  56. file.
  57. External GPIO and Wakeup Interrupts:
  58. The controller supports two types of external interrupts over gpio. The first
  59. is the external gpio interrupt and second is the external wakeup interrupts.
  60. The difference between the two is that the external wakeup interrupts can be
  61. used as system wakeup events.
  62. A. External GPIO Interrupts: For supporting external gpio interrupts, the
  63. following properties should be specified in the pin-controller device node.
  64. - interrupt-parent: phandle of the interrupt parent to which the external
  65. GPIO interrupts are forwarded to.
  66. - interrupts: interrupt specifier for the controller. The format and value of
  67. the interrupt specifier depends on the interrupt parent for the controller.
  68. In addition, following properties must be present in node of every bank
  69. of pins supporting GPIO interrupts:
  70. - interrupt-controller: identifies the controller node as interrupt-parent.
  71. - #interrupt-cells: the value of this property should be 2.
  72. - First Cell: represents the external gpio interrupt number local to the
  73. external gpio interrupt space of the controller.
  74. - Second Cell: flags to identify the type of the interrupt
  75. - 1 = rising edge triggered
  76. - 2 = falling edge triggered
  77. - 3 = rising and falling edge triggered
  78. - 4 = high level triggered
  79. - 8 = low level triggered
  80. B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
  81. child node representing the external wakeup interrupt controller should be
  82. included in the pin-controller device node. This child node should include
  83. the following properties.
  84. - compatible: identifies the type of the external wakeup interrupt controller
  85. The possible values are:
  86. - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
  87. found on Samsung Exynos4210 SoC.
  88. - interrupt-parent: phandle of the interrupt parent to which the external
  89. wakeup interrupts are forwarded to.
  90. - interrupts: interrupt used by multiplexed wakeup interrupts.
  91. In addition, following properties must be present in node of every bank
  92. of pins supporting wake-up interrupts:
  93. - interrupt-controller: identifies the node as interrupt-parent.
  94. - #interrupt-cells: the value of this property should be 2
  95. - First Cell: represents the external wakeup interrupt number local to
  96. the external wakeup interrupt space of the controller.
  97. - Second Cell: flags to identify the type of the interrupt
  98. - 1 = rising edge triggered
  99. - 2 = falling edge triggered
  100. - 3 = rising and falling edge triggered
  101. - 4 = high level triggered
  102. - 8 = low level triggered
  103. Node of every bank of pins supporting direct wake-up interrupts (without
  104. multiplexing) must contain following properties:
  105. - interrupt-parent: phandle of the interrupt parent to which the external
  106. wakeup interrupts are forwarded to.
  107. - interrupts: interrupts of the interrupt parent which are used for external
  108. wakeup interrupts from pins of the bank, must contain interrupts for all
  109. pins of the bank.
  110. Aliases:
  111. All the pin controller nodes should be represented in the aliases node using
  112. the following format 'pinctrl{n}' where n is a unique number for the alias.
  113. Example: A pin-controller node with pin banks:
  114. pinctrl_0: pinctrl@11400000 {
  115. compatible = "samsung,pinctrl-exynos4210";
  116. reg = <0x11400000 0x1000>;
  117. interrupts = <0 47 0>;
  118. /* ... */
  119. /* Pin bank without external interrupts */
  120. gpy0: gpy0 {
  121. gpio-controller;
  122. #gpio-cells = <2>;
  123. };
  124. /* ... */
  125. /* Pin bank with external GPIO or muxed wake-up interrupts */
  126. gpj0: gpj0 {
  127. gpio-controller;
  128. #gpio-cells = <2>;
  129. interrupt-controller;
  130. #interrupt-cells = <2>;
  131. };
  132. /* ... */
  133. /* Pin bank with external direct wake-up interrupts */
  134. gpx0: gpx0 {
  135. gpio-controller;
  136. #gpio-cells = <2>;
  137. interrupt-controller;
  138. interrupt-parent = <&gic>;
  139. interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  140. <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
  141. #interrupt-cells = <2>;
  142. };
  143. /* ... */
  144. };
  145. Example 1: A pin-controller node with pin groups.
  146. pinctrl_0: pinctrl@11400000 {
  147. compatible = "samsung,pinctrl-exynos4210";
  148. reg = <0x11400000 0x1000>;
  149. interrupts = <0 47 0>;
  150. /* ... */
  151. uart0_data: uart0-data {
  152. samsung,pins = "gpa0-0", "gpa0-1";
  153. samsung,pin-function = <2>;
  154. samsung,pin-pud = <0>;
  155. samsung,pin-drv = <0>;
  156. };
  157. uart0_fctl: uart0-fctl {
  158. samsung,pins = "gpa0-2", "gpa0-3";
  159. samsung,pin-function = <2>;
  160. samsung,pin-pud = <0>;
  161. samsung,pin-drv = <0>;
  162. };
  163. uart1_data: uart1-data {
  164. samsung,pins = "gpa0-4", "gpa0-5";
  165. samsung,pin-function = <2>;
  166. samsung,pin-pud = <0>;
  167. samsung,pin-drv = <0>;
  168. };
  169. uart1_fctl: uart1-fctl {
  170. samsung,pins = "gpa0-6", "gpa0-7";
  171. samsung,pin-function = <2>;
  172. samsung,pin-pud = <0>;
  173. samsung,pin-drv = <0>;
  174. };
  175. i2c2_bus: i2c2-bus {
  176. samsung,pins = "gpa0-6", "gpa0-7";
  177. samsung,pin-function = <3>;
  178. samsung,pin-pud = <3>;
  179. samsung,pin-drv = <0>;
  180. };
  181. };
  182. Example 2: A pin-controller node with external wakeup interrupt controller node.
  183. pinctrl_1: pinctrl@11000000 {
  184. compatible = "samsung,pinctrl-exynos4210";
  185. reg = <0x11000000 0x1000>;
  186. interrupts = <0 46 0>
  187. /* ... */
  188. wakeup-interrupt-controller {
  189. compatible = "samsung,exynos4210-wakeup-eint";
  190. interrupt-parent = <&gic>;
  191. interrupts = <0 32 0>;
  192. };
  193. };
  194. Example 3: A uart client node that supports 'default' and 'flow-control' states.
  195. uart@13800000 {
  196. compatible = "samsung,exynos4210-uart";
  197. reg = <0x13800000 0x100>;
  198. interrupts = <0 52 0>;
  199. pinctrl-names = "default", "flow-control;
  200. pinctrl-0 = <&uart0_data>;
  201. pinctrl-1 = <&uart0_data &uart0_fctl>;
  202. };
  203. Example 4: Set up the default pin state for uart controller.
  204. static int s3c24xx_serial_probe(struct platform_device *pdev) {
  205. struct pinctrl *pinctrl;
  206. /* ... */
  207. pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
  208. }