tc35815.c 64 KB

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  1. /*
  2. * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
  3. *
  4. * Based on skelton.c by Donald Becker.
  5. *
  6. * This driver is a replacement of older and less maintained version.
  7. * This is a header of the older version:
  8. * -----<snip>-----
  9. * Copyright 2001 MontaVista Software Inc.
  10. * Author: MontaVista Software, Inc.
  11. * ahennessy@mvista.com
  12. * Copyright (C) 2000-2001 Toshiba Corporation
  13. * static const char *version =
  14. * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
  15. * -----<snip>-----
  16. *
  17. * This file is subject to the terms and conditions of the GNU General Public
  18. * License. See the file "COPYING" in the main directory of this archive
  19. * for more details.
  20. *
  21. * (C) Copyright TOSHIBA CORPORATION 2004-2005
  22. * All Rights Reserved.
  23. */
  24. #define DRV_VERSION "1.39"
  25. static const char *version = "tc35815.c:v" DRV_VERSION "\n";
  26. #define MODNAME "tc35815"
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/types.h>
  30. #include <linux/fcntl.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/ioport.h>
  33. #include <linux/in.h>
  34. #include <linux/if_vlan.h>
  35. #include <linux/slab.h>
  36. #include <linux/string.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/errno.h>
  39. #include <linux/init.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/etherdevice.h>
  42. #include <linux/skbuff.h>
  43. #include <linux/delay.h>
  44. #include <linux/pci.h>
  45. #include <linux/phy.h>
  46. #include <linux/workqueue.h>
  47. #include <linux/platform_device.h>
  48. #include <asm/io.h>
  49. #include <asm/byteorder.h>
  50. enum tc35815_chiptype {
  51. TC35815CF = 0,
  52. TC35815_NWU,
  53. TC35815_TX4939,
  54. };
  55. /* indexed by tc35815_chiptype, above */
  56. static const struct {
  57. const char *name;
  58. } chip_info[] __devinitdata = {
  59. { "TOSHIBA TC35815CF 10/100BaseTX" },
  60. { "TOSHIBA TC35815 with Wake on LAN" },
  61. { "TOSHIBA TC35815/TX4939" },
  62. };
  63. static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = {
  64. {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
  65. {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
  66. {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
  67. {0,}
  68. };
  69. MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
  70. /* see MODULE_PARM_DESC */
  71. static struct tc35815_options {
  72. int speed;
  73. int duplex;
  74. } options;
  75. /*
  76. * Registers
  77. */
  78. struct tc35815_regs {
  79. __u32 DMA_Ctl; /* 0x00 */
  80. __u32 TxFrmPtr;
  81. __u32 TxThrsh;
  82. __u32 TxPollCtr;
  83. __u32 BLFrmPtr;
  84. __u32 RxFragSize;
  85. __u32 Int_En;
  86. __u32 FDA_Bas;
  87. __u32 FDA_Lim; /* 0x20 */
  88. __u32 Int_Src;
  89. __u32 unused0[2];
  90. __u32 PauseCnt;
  91. __u32 RemPauCnt;
  92. __u32 TxCtlFrmStat;
  93. __u32 unused1;
  94. __u32 MAC_Ctl; /* 0x40 */
  95. __u32 CAM_Ctl;
  96. __u32 Tx_Ctl;
  97. __u32 Tx_Stat;
  98. __u32 Rx_Ctl;
  99. __u32 Rx_Stat;
  100. __u32 MD_Data;
  101. __u32 MD_CA;
  102. __u32 CAM_Adr; /* 0x60 */
  103. __u32 CAM_Data;
  104. __u32 CAM_Ena;
  105. __u32 PROM_Ctl;
  106. __u32 PROM_Data;
  107. __u32 Algn_Cnt;
  108. __u32 CRC_Cnt;
  109. __u32 Miss_Cnt;
  110. };
  111. /*
  112. * Bit assignments
  113. */
  114. /* DMA_Ctl bit asign ------------------------------------------------------- */
  115. #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
  116. #define DMA_RxAlign_1 0x00400000
  117. #define DMA_RxAlign_2 0x00800000
  118. #define DMA_RxAlign_3 0x00c00000
  119. #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
  120. #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
  121. #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
  122. #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
  123. #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
  124. #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
  125. #define DMA_TestMode 0x00002000 /* 1:Test Mode */
  126. #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
  127. #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
  128. /* RxFragSize bit asign ---------------------------------------------------- */
  129. #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
  130. #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
  131. /* MAC_Ctl bit asign ------------------------------------------------------- */
  132. #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
  133. #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
  134. #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
  135. #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
  136. #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
  137. #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
  138. #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
  139. #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
  140. #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
  141. #define MAC_Reset 0x00000004 /* 1:Software Reset */
  142. #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
  143. #define MAC_HaltReq 0x00000001 /* 1:Halt request */
  144. /* PROM_Ctl bit asign ------------------------------------------------------ */
  145. #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
  146. #define PROM_Read 0x00004000 /*10:Read operation */
  147. #define PROM_Write 0x00002000 /*01:Write operation */
  148. #define PROM_Erase 0x00006000 /*11:Erase operation */
  149. /*00:Enable or Disable Writting, */
  150. /* as specified in PROM_Addr. */
  151. #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
  152. /*00xxxx: disable */
  153. /* CAM_Ctl bit asign ------------------------------------------------------- */
  154. #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
  155. #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
  156. /* accept other */
  157. #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
  158. #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
  159. #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
  160. /* CAM_Ena bit asign ------------------------------------------------------- */
  161. #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
  162. #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
  163. #define CAM_Ena_Bit(index) (1 << (index))
  164. #define CAM_ENTRY_DESTINATION 0
  165. #define CAM_ENTRY_SOURCE 1
  166. #define CAM_ENTRY_MACCTL 20
  167. /* Tx_Ctl bit asign -------------------------------------------------------- */
  168. #define Tx_En 0x00000001 /* 1:Transmit enable */
  169. #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
  170. #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
  171. #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
  172. #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
  173. #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
  174. #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
  175. #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
  176. #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
  177. #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
  178. #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
  179. #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
  180. /* Tx_Stat bit asign ------------------------------------------------------- */
  181. #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
  182. #define Tx_ExColl 0x00000010 /* Excessive Collision */
  183. #define Tx_TXDefer 0x00000020 /* Transmit Defered */
  184. #define Tx_Paused 0x00000040 /* Transmit Paused */
  185. #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
  186. #define Tx_Under 0x00000100 /* Underrun */
  187. #define Tx_Defer 0x00000200 /* Deferral */
  188. #define Tx_NCarr 0x00000400 /* No Carrier */
  189. #define Tx_10Stat 0x00000800 /* 10Mbps Status */
  190. #define Tx_LateColl 0x00001000 /* Late Collision */
  191. #define Tx_TxPar 0x00002000 /* Tx Parity Error */
  192. #define Tx_Comp 0x00004000 /* Completion */
  193. #define Tx_Halted 0x00008000 /* Tx Halted */
  194. #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
  195. /* Rx_Ctl bit asign -------------------------------------------------------- */
  196. #define Rx_EnGood 0x00004000 /* 1:Enable Good */
  197. #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
  198. #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
  199. #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
  200. #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
  201. #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
  202. #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
  203. #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
  204. #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
  205. #define Rx_LongEn 0x00000004 /* 1:Long Enable */
  206. #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
  207. #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
  208. /* Rx_Stat bit asign ------------------------------------------------------- */
  209. #define Rx_Halted 0x00008000 /* Rx Halted */
  210. #define Rx_Good 0x00004000 /* Rx Good */
  211. #define Rx_RxPar 0x00002000 /* Rx Parity Error */
  212. #define Rx_TypePkt 0x00001000 /* Rx Type Packet */
  213. #define Rx_LongErr 0x00000800 /* Rx Long Error */
  214. #define Rx_Over 0x00000400 /* Rx Overflow */
  215. #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
  216. #define Rx_Align 0x00000100 /* Rx Alignment Error */
  217. #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
  218. #define Rx_IntRx 0x00000040 /* Rx Interrupt */
  219. #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
  220. #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
  221. #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
  222. /* Int_En bit asign -------------------------------------------------------- */
  223. #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
  224. #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
  225. #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
  226. #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
  227. #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
  228. #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
  229. #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
  230. #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
  231. #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
  232. #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
  233. #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
  234. #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
  235. /* Exhausted Enable */
  236. /* Int_Src bit asign ------------------------------------------------------- */
  237. #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
  238. #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
  239. #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
  240. #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
  241. #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
  242. #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
  243. #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
  244. #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
  245. #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
  246. #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
  247. #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
  248. #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
  249. #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
  250. #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
  251. #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
  252. /* MD_CA bit asign --------------------------------------------------------- */
  253. #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
  254. #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
  255. #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
  256. /*
  257. * Descriptors
  258. */
  259. /* Frame descripter */
  260. struct FDesc {
  261. volatile __u32 FDNext;
  262. volatile __u32 FDSystem;
  263. volatile __u32 FDStat;
  264. volatile __u32 FDCtl;
  265. };
  266. /* Buffer descripter */
  267. struct BDesc {
  268. volatile __u32 BuffData;
  269. volatile __u32 BDCtl;
  270. };
  271. #define FD_ALIGN 16
  272. /* Frame Descripter bit asign ---------------------------------------------- */
  273. #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
  274. #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
  275. #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
  276. #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
  277. #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
  278. #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
  279. #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
  280. #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
  281. #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
  282. #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
  283. #define FD_BDCnt_SHIFT 16
  284. /* Buffer Descripter bit asign --------------------------------------------- */
  285. #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
  286. #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
  287. #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
  288. #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
  289. #define BD_RxBDID_SHIFT 16
  290. #define BD_RxBDSeqN_SHIFT 24
  291. /* Some useful constants. */
  292. #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
  293. Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
  294. Tx_En) /* maybe 0x7b01 */
  295. /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
  296. #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
  297. | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
  298. #define INT_EN_CMD (Int_NRAbtEn | \
  299. Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
  300. Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
  301. Int_STargAbtEn | \
  302. Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
  303. #define DMA_CTL_CMD DMA_BURST_SIZE
  304. #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
  305. /* Tuning parameters */
  306. #define DMA_BURST_SIZE 32
  307. #define TX_THRESHOLD 1024
  308. /* used threshold with packet max byte for low pci transfer ability.*/
  309. #define TX_THRESHOLD_MAX 1536
  310. /* setting threshold max value when overrun error occured this count. */
  311. #define TX_THRESHOLD_KEEP_LIMIT 10
  312. /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
  313. #define FD_PAGE_NUM 4
  314. #define RX_BUF_NUM 128 /* < 256 */
  315. #define RX_FD_NUM 256 /* >= 32 */
  316. #define TX_FD_NUM 128
  317. #if RX_CTL_CMD & Rx_LongEn
  318. #define RX_BUF_SIZE PAGE_SIZE
  319. #elif RX_CTL_CMD & Rx_StripCRC
  320. #define RX_BUF_SIZE \
  321. L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
  322. #else
  323. #define RX_BUF_SIZE \
  324. L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
  325. #endif
  326. #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
  327. #define NAPI_WEIGHT 16
  328. struct TxFD {
  329. struct FDesc fd;
  330. struct BDesc bd;
  331. struct BDesc unused;
  332. };
  333. struct RxFD {
  334. struct FDesc fd;
  335. struct BDesc bd[0]; /* variable length */
  336. };
  337. struct FrFD {
  338. struct FDesc fd;
  339. struct BDesc bd[RX_BUF_NUM];
  340. };
  341. #define tc_readl(addr) ioread32(addr)
  342. #define tc_writel(d, addr) iowrite32(d, addr)
  343. #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
  344. /* Information that need to be kept for each controller. */
  345. struct tc35815_local {
  346. struct pci_dev *pci_dev;
  347. struct net_device *dev;
  348. struct napi_struct napi;
  349. /* statistics */
  350. struct {
  351. int max_tx_qlen;
  352. int tx_ints;
  353. int rx_ints;
  354. int tx_underrun;
  355. } lstats;
  356. /* Tx control lock. This protects the transmit buffer ring
  357. * state along with the "tx full" state of the driver. This
  358. * means all netif_queue flow control actions are protected
  359. * by this lock as well.
  360. */
  361. spinlock_t lock;
  362. spinlock_t rx_lock;
  363. struct mii_bus *mii_bus;
  364. struct phy_device *phy_dev;
  365. int duplex;
  366. int speed;
  367. int link;
  368. struct work_struct restart_work;
  369. /*
  370. * Transmitting: Batch Mode.
  371. * 1 BD in 1 TxFD.
  372. * Receiving: Non-Packing Mode.
  373. * 1 circular FD for Free Buffer List.
  374. * RX_BUF_NUM BD in Free Buffer FD.
  375. * One Free Buffer BD has ETH_FRAME_LEN data buffer.
  376. */
  377. void *fd_buf; /* for TxFD, RxFD, FrFD */
  378. dma_addr_t fd_buf_dma;
  379. struct TxFD *tfd_base;
  380. unsigned int tfd_start;
  381. unsigned int tfd_end;
  382. struct RxFD *rfd_base;
  383. struct RxFD *rfd_limit;
  384. struct RxFD *rfd_cur;
  385. struct FrFD *fbl_ptr;
  386. unsigned int fbl_count;
  387. struct {
  388. struct sk_buff *skb;
  389. dma_addr_t skb_dma;
  390. } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
  391. u32 msg_enable;
  392. enum tc35815_chiptype chiptype;
  393. };
  394. static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
  395. {
  396. return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
  397. }
  398. #ifdef DEBUG
  399. static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
  400. {
  401. return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
  402. }
  403. #endif
  404. static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
  405. struct pci_dev *hwdev,
  406. dma_addr_t *dma_handle)
  407. {
  408. struct sk_buff *skb;
  409. skb = dev_alloc_skb(RX_BUF_SIZE);
  410. if (!skb)
  411. return NULL;
  412. *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
  413. PCI_DMA_FROMDEVICE);
  414. if (pci_dma_mapping_error(hwdev, *dma_handle)) {
  415. dev_kfree_skb_any(skb);
  416. return NULL;
  417. }
  418. skb_reserve(skb, 2); /* make IP header 4byte aligned */
  419. return skb;
  420. }
  421. static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
  422. {
  423. pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
  424. PCI_DMA_FROMDEVICE);
  425. dev_kfree_skb_any(skb);
  426. }
  427. /* Index to functions, as function prototypes. */
  428. static int tc35815_open(struct net_device *dev);
  429. static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
  430. static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
  431. static int tc35815_rx(struct net_device *dev, int limit);
  432. static int tc35815_poll(struct napi_struct *napi, int budget);
  433. static void tc35815_txdone(struct net_device *dev);
  434. static int tc35815_close(struct net_device *dev);
  435. static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
  436. static void tc35815_set_multicast_list(struct net_device *dev);
  437. static void tc35815_tx_timeout(struct net_device *dev);
  438. static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  439. #ifdef CONFIG_NET_POLL_CONTROLLER
  440. static void tc35815_poll_controller(struct net_device *dev);
  441. #endif
  442. static const struct ethtool_ops tc35815_ethtool_ops;
  443. /* Example routines you must write ;->. */
  444. static void tc35815_chip_reset(struct net_device *dev);
  445. static void tc35815_chip_init(struct net_device *dev);
  446. #ifdef DEBUG
  447. static void panic_queues(struct net_device *dev);
  448. #endif
  449. static void tc35815_restart_work(struct work_struct *work);
  450. static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  451. {
  452. struct net_device *dev = bus->priv;
  453. struct tc35815_regs __iomem *tr =
  454. (struct tc35815_regs __iomem *)dev->base_addr;
  455. unsigned long timeout = jiffies + HZ;
  456. tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
  457. udelay(12); /* it takes 32 x 400ns at least */
  458. while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
  459. if (time_after(jiffies, timeout))
  460. return -EIO;
  461. cpu_relax();
  462. }
  463. return tc_readl(&tr->MD_Data) & 0xffff;
  464. }
  465. static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
  466. {
  467. struct net_device *dev = bus->priv;
  468. struct tc35815_regs __iomem *tr =
  469. (struct tc35815_regs __iomem *)dev->base_addr;
  470. unsigned long timeout = jiffies + HZ;
  471. tc_writel(val, &tr->MD_Data);
  472. tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
  473. &tr->MD_CA);
  474. udelay(12); /* it takes 32 x 400ns at least */
  475. while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
  476. if (time_after(jiffies, timeout))
  477. return -EIO;
  478. cpu_relax();
  479. }
  480. return 0;
  481. }
  482. static void tc_handle_link_change(struct net_device *dev)
  483. {
  484. struct tc35815_local *lp = netdev_priv(dev);
  485. struct phy_device *phydev = lp->phy_dev;
  486. unsigned long flags;
  487. int status_change = 0;
  488. spin_lock_irqsave(&lp->lock, flags);
  489. if (phydev->link &&
  490. (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
  491. struct tc35815_regs __iomem *tr =
  492. (struct tc35815_regs __iomem *)dev->base_addr;
  493. u32 reg;
  494. reg = tc_readl(&tr->MAC_Ctl);
  495. reg |= MAC_HaltReq;
  496. tc_writel(reg, &tr->MAC_Ctl);
  497. if (phydev->duplex == DUPLEX_FULL)
  498. reg |= MAC_FullDup;
  499. else
  500. reg &= ~MAC_FullDup;
  501. tc_writel(reg, &tr->MAC_Ctl);
  502. reg &= ~MAC_HaltReq;
  503. tc_writel(reg, &tr->MAC_Ctl);
  504. /*
  505. * TX4939 PCFG.SPEEDn bit will be changed on
  506. * NETDEV_CHANGE event.
  507. */
  508. /*
  509. * WORKAROUND: enable LostCrS only if half duplex
  510. * operation.
  511. * (TX4939 does not have EnLCarr)
  512. */
  513. if (phydev->duplex == DUPLEX_HALF &&
  514. lp->chiptype != TC35815_TX4939)
  515. tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
  516. &tr->Tx_Ctl);
  517. lp->speed = phydev->speed;
  518. lp->duplex = phydev->duplex;
  519. status_change = 1;
  520. }
  521. if (phydev->link != lp->link) {
  522. if (phydev->link) {
  523. /* delayed promiscuous enabling */
  524. if (dev->flags & IFF_PROMISC)
  525. tc35815_set_multicast_list(dev);
  526. } else {
  527. lp->speed = 0;
  528. lp->duplex = -1;
  529. }
  530. lp->link = phydev->link;
  531. status_change = 1;
  532. }
  533. spin_unlock_irqrestore(&lp->lock, flags);
  534. if (status_change && netif_msg_link(lp)) {
  535. phy_print_status(phydev);
  536. pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
  537. dev->name,
  538. phy_read(phydev, MII_BMCR),
  539. phy_read(phydev, MII_BMSR),
  540. phy_read(phydev, MII_LPA));
  541. }
  542. }
  543. static int tc_mii_probe(struct net_device *dev)
  544. {
  545. struct tc35815_local *lp = netdev_priv(dev);
  546. struct phy_device *phydev = NULL;
  547. int phy_addr;
  548. u32 dropmask;
  549. /* find the first phy */
  550. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  551. if (lp->mii_bus->phy_map[phy_addr]) {
  552. if (phydev) {
  553. printk(KERN_ERR "%s: multiple PHYs found\n",
  554. dev->name);
  555. return -EINVAL;
  556. }
  557. phydev = lp->mii_bus->phy_map[phy_addr];
  558. break;
  559. }
  560. }
  561. if (!phydev) {
  562. printk(KERN_ERR "%s: no PHY found\n", dev->name);
  563. return -ENODEV;
  564. }
  565. /* attach the mac to the phy */
  566. phydev = phy_connect(dev, dev_name(&phydev->dev),
  567. &tc_handle_link_change, 0,
  568. lp->chiptype == TC35815_TX4939 ?
  569. PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
  570. if (IS_ERR(phydev)) {
  571. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  572. return PTR_ERR(phydev);
  573. }
  574. printk(KERN_INFO "%s: attached PHY driver [%s] "
  575. "(mii_bus:phy_addr=%s, id=%x)\n",
  576. dev->name, phydev->drv->name, dev_name(&phydev->dev),
  577. phydev->phy_id);
  578. /* mask with MAC supported features */
  579. phydev->supported &= PHY_BASIC_FEATURES;
  580. dropmask = 0;
  581. if (options.speed == 10)
  582. dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
  583. else if (options.speed == 100)
  584. dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
  585. if (options.duplex == 1)
  586. dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
  587. else if (options.duplex == 2)
  588. dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
  589. phydev->supported &= ~dropmask;
  590. phydev->advertising = phydev->supported;
  591. lp->link = 0;
  592. lp->speed = 0;
  593. lp->duplex = -1;
  594. lp->phy_dev = phydev;
  595. return 0;
  596. }
  597. static int tc_mii_init(struct net_device *dev)
  598. {
  599. struct tc35815_local *lp = netdev_priv(dev);
  600. int err;
  601. int i;
  602. lp->mii_bus = mdiobus_alloc();
  603. if (lp->mii_bus == NULL) {
  604. err = -ENOMEM;
  605. goto err_out;
  606. }
  607. lp->mii_bus->name = "tc35815_mii_bus";
  608. lp->mii_bus->read = tc_mdio_read;
  609. lp->mii_bus->write = tc_mdio_write;
  610. snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
  611. (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
  612. lp->mii_bus->priv = dev;
  613. lp->mii_bus->parent = &lp->pci_dev->dev;
  614. lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
  615. if (!lp->mii_bus->irq) {
  616. err = -ENOMEM;
  617. goto err_out_free_mii_bus;
  618. }
  619. for (i = 0; i < PHY_MAX_ADDR; i++)
  620. lp->mii_bus->irq[i] = PHY_POLL;
  621. err = mdiobus_register(lp->mii_bus);
  622. if (err)
  623. goto err_out_free_mdio_irq;
  624. err = tc_mii_probe(dev);
  625. if (err)
  626. goto err_out_unregister_bus;
  627. return 0;
  628. err_out_unregister_bus:
  629. mdiobus_unregister(lp->mii_bus);
  630. err_out_free_mdio_irq:
  631. kfree(lp->mii_bus->irq);
  632. err_out_free_mii_bus:
  633. mdiobus_free(lp->mii_bus);
  634. err_out:
  635. return err;
  636. }
  637. #ifdef CONFIG_CPU_TX49XX
  638. /*
  639. * Find a platform_device providing a MAC address. The platform code
  640. * should provide a "tc35815-mac" device with a MAC address in its
  641. * platform_data.
  642. */
  643. static int __devinit tc35815_mac_match(struct device *dev, void *data)
  644. {
  645. struct platform_device *plat_dev = to_platform_device(dev);
  646. struct pci_dev *pci_dev = data;
  647. unsigned int id = pci_dev->irq;
  648. return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
  649. }
  650. static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
  651. {
  652. struct tc35815_local *lp = netdev_priv(dev);
  653. struct device *pd = bus_find_device(&platform_bus_type, NULL,
  654. lp->pci_dev, tc35815_mac_match);
  655. if (pd) {
  656. if (pd->platform_data)
  657. memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
  658. put_device(pd);
  659. return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
  660. }
  661. return -ENODEV;
  662. }
  663. #else
  664. static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
  665. {
  666. return -ENODEV;
  667. }
  668. #endif
  669. static int __devinit tc35815_init_dev_addr(struct net_device *dev)
  670. {
  671. struct tc35815_regs __iomem *tr =
  672. (struct tc35815_regs __iomem *)dev->base_addr;
  673. int i;
  674. while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
  675. ;
  676. for (i = 0; i < 6; i += 2) {
  677. unsigned short data;
  678. tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
  679. while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
  680. ;
  681. data = tc_readl(&tr->PROM_Data);
  682. dev->dev_addr[i] = data & 0xff;
  683. dev->dev_addr[i+1] = data >> 8;
  684. }
  685. if (!is_valid_ether_addr(dev->dev_addr))
  686. return tc35815_read_plat_dev_addr(dev);
  687. return 0;
  688. }
  689. static const struct net_device_ops tc35815_netdev_ops = {
  690. .ndo_open = tc35815_open,
  691. .ndo_stop = tc35815_close,
  692. .ndo_start_xmit = tc35815_send_packet,
  693. .ndo_get_stats = tc35815_get_stats,
  694. .ndo_set_multicast_list = tc35815_set_multicast_list,
  695. .ndo_tx_timeout = tc35815_tx_timeout,
  696. .ndo_do_ioctl = tc35815_ioctl,
  697. .ndo_validate_addr = eth_validate_addr,
  698. .ndo_change_mtu = eth_change_mtu,
  699. .ndo_set_mac_address = eth_mac_addr,
  700. #ifdef CONFIG_NET_POLL_CONTROLLER
  701. .ndo_poll_controller = tc35815_poll_controller,
  702. #endif
  703. };
  704. static int __devinit tc35815_init_one(struct pci_dev *pdev,
  705. const struct pci_device_id *ent)
  706. {
  707. void __iomem *ioaddr = NULL;
  708. struct net_device *dev;
  709. struct tc35815_local *lp;
  710. int rc;
  711. static int printed_version;
  712. if (!printed_version++) {
  713. printk(version);
  714. dev_printk(KERN_DEBUG, &pdev->dev,
  715. "speed:%d duplex:%d\n",
  716. options.speed, options.duplex);
  717. }
  718. if (!pdev->irq) {
  719. dev_warn(&pdev->dev, "no IRQ assigned.\n");
  720. return -ENODEV;
  721. }
  722. /* dev zeroed in alloc_etherdev */
  723. dev = alloc_etherdev(sizeof(*lp));
  724. if (dev == NULL) {
  725. dev_err(&pdev->dev, "unable to alloc new ethernet\n");
  726. return -ENOMEM;
  727. }
  728. SET_NETDEV_DEV(dev, &pdev->dev);
  729. lp = netdev_priv(dev);
  730. lp->dev = dev;
  731. /* enable device (incl. PCI PM wakeup), and bus-mastering */
  732. rc = pcim_enable_device(pdev);
  733. if (rc)
  734. goto err_out;
  735. rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
  736. if (rc)
  737. goto err_out;
  738. pci_set_master(pdev);
  739. ioaddr = pcim_iomap_table(pdev)[1];
  740. /* Initialize the device structure. */
  741. dev->netdev_ops = &tc35815_netdev_ops;
  742. dev->ethtool_ops = &tc35815_ethtool_ops;
  743. dev->watchdog_timeo = TC35815_TX_TIMEOUT;
  744. netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
  745. dev->irq = pdev->irq;
  746. dev->base_addr = (unsigned long)ioaddr;
  747. INIT_WORK(&lp->restart_work, tc35815_restart_work);
  748. spin_lock_init(&lp->lock);
  749. spin_lock_init(&lp->rx_lock);
  750. lp->pci_dev = pdev;
  751. lp->chiptype = ent->driver_data;
  752. lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
  753. pci_set_drvdata(pdev, dev);
  754. /* Soft reset the chip. */
  755. tc35815_chip_reset(dev);
  756. /* Retrieve the ethernet address. */
  757. if (tc35815_init_dev_addr(dev)) {
  758. dev_warn(&pdev->dev, "not valid ether addr\n");
  759. random_ether_addr(dev->dev_addr);
  760. }
  761. rc = register_netdev(dev);
  762. if (rc)
  763. goto err_out_iounmap;
  764. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  765. printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
  766. dev->name,
  767. chip_info[ent->driver_data].name,
  768. dev->base_addr,
  769. dev->dev_addr,
  770. dev->irq);
  771. rc = tc_mii_init(dev);
  772. if (rc)
  773. goto err_out_unregister;
  774. return 0;
  775. err_out_unregister:
  776. unregister_netdev(dev);
  777. err_out_iounmap:
  778. pcim_iounmap_regions(pdev, 1 << 1);
  779. err_out:
  780. free_netdev(dev);
  781. return rc;
  782. }
  783. static void __devexit tc35815_remove_one(struct pci_dev *pdev)
  784. {
  785. struct net_device *dev = pci_get_drvdata(pdev);
  786. struct tc35815_local *lp = netdev_priv(dev);
  787. phy_disconnect(lp->phy_dev);
  788. mdiobus_unregister(lp->mii_bus);
  789. kfree(lp->mii_bus->irq);
  790. mdiobus_free(lp->mii_bus);
  791. unregister_netdev(dev);
  792. free_netdev(dev);
  793. pci_set_drvdata(pdev, NULL);
  794. }
  795. static int
  796. tc35815_init_queues(struct net_device *dev)
  797. {
  798. struct tc35815_local *lp = netdev_priv(dev);
  799. int i;
  800. unsigned long fd_addr;
  801. if (!lp->fd_buf) {
  802. BUG_ON(sizeof(struct FDesc) +
  803. sizeof(struct BDesc) * RX_BUF_NUM +
  804. sizeof(struct FDesc) * RX_FD_NUM +
  805. sizeof(struct TxFD) * TX_FD_NUM >
  806. PAGE_SIZE * FD_PAGE_NUM);
  807. lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
  808. PAGE_SIZE * FD_PAGE_NUM,
  809. &lp->fd_buf_dma);
  810. if (!lp->fd_buf)
  811. return -ENOMEM;
  812. for (i = 0; i < RX_BUF_NUM; i++) {
  813. lp->rx_skbs[i].skb =
  814. alloc_rxbuf_skb(dev, lp->pci_dev,
  815. &lp->rx_skbs[i].skb_dma);
  816. if (!lp->rx_skbs[i].skb) {
  817. while (--i >= 0) {
  818. free_rxbuf_skb(lp->pci_dev,
  819. lp->rx_skbs[i].skb,
  820. lp->rx_skbs[i].skb_dma);
  821. lp->rx_skbs[i].skb = NULL;
  822. }
  823. pci_free_consistent(lp->pci_dev,
  824. PAGE_SIZE * FD_PAGE_NUM,
  825. lp->fd_buf,
  826. lp->fd_buf_dma);
  827. lp->fd_buf = NULL;
  828. return -ENOMEM;
  829. }
  830. }
  831. printk(KERN_DEBUG "%s: FD buf %p DataBuf",
  832. dev->name, lp->fd_buf);
  833. printk("\n");
  834. } else {
  835. for (i = 0; i < FD_PAGE_NUM; i++)
  836. clear_page((void *)((unsigned long)lp->fd_buf +
  837. i * PAGE_SIZE));
  838. }
  839. fd_addr = (unsigned long)lp->fd_buf;
  840. /* Free Descriptors (for Receive) */
  841. lp->rfd_base = (struct RxFD *)fd_addr;
  842. fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
  843. for (i = 0; i < RX_FD_NUM; i++)
  844. lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
  845. lp->rfd_cur = lp->rfd_base;
  846. lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
  847. /* Transmit Descriptors */
  848. lp->tfd_base = (struct TxFD *)fd_addr;
  849. fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
  850. for (i = 0; i < TX_FD_NUM; i++) {
  851. lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
  852. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
  853. lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
  854. }
  855. lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
  856. lp->tfd_start = 0;
  857. lp->tfd_end = 0;
  858. /* Buffer List (for Receive) */
  859. lp->fbl_ptr = (struct FrFD *)fd_addr;
  860. lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
  861. lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
  862. /*
  863. * move all allocated skbs to head of rx_skbs[] array.
  864. * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
  865. * tc35815_rx() had failed.
  866. */
  867. lp->fbl_count = 0;
  868. for (i = 0; i < RX_BUF_NUM; i++) {
  869. if (lp->rx_skbs[i].skb) {
  870. if (i != lp->fbl_count) {
  871. lp->rx_skbs[lp->fbl_count].skb =
  872. lp->rx_skbs[i].skb;
  873. lp->rx_skbs[lp->fbl_count].skb_dma =
  874. lp->rx_skbs[i].skb_dma;
  875. }
  876. lp->fbl_count++;
  877. }
  878. }
  879. for (i = 0; i < RX_BUF_NUM; i++) {
  880. if (i >= lp->fbl_count) {
  881. lp->fbl_ptr->bd[i].BuffData = 0;
  882. lp->fbl_ptr->bd[i].BDCtl = 0;
  883. continue;
  884. }
  885. lp->fbl_ptr->bd[i].BuffData =
  886. cpu_to_le32(lp->rx_skbs[i].skb_dma);
  887. /* BDID is index of FrFD.bd[] */
  888. lp->fbl_ptr->bd[i].BDCtl =
  889. cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
  890. RX_BUF_SIZE);
  891. }
  892. printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
  893. dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
  894. return 0;
  895. }
  896. static void
  897. tc35815_clear_queues(struct net_device *dev)
  898. {
  899. struct tc35815_local *lp = netdev_priv(dev);
  900. int i;
  901. for (i = 0; i < TX_FD_NUM; i++) {
  902. u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
  903. struct sk_buff *skb =
  904. fdsystem != 0xffffffff ?
  905. lp->tx_skbs[fdsystem].skb : NULL;
  906. #ifdef DEBUG
  907. if (lp->tx_skbs[i].skb != skb) {
  908. printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
  909. panic_queues(dev);
  910. }
  911. #else
  912. BUG_ON(lp->tx_skbs[i].skb != skb);
  913. #endif
  914. if (skb) {
  915. pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
  916. lp->tx_skbs[i].skb = NULL;
  917. lp->tx_skbs[i].skb_dma = 0;
  918. dev_kfree_skb_any(skb);
  919. }
  920. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
  921. }
  922. tc35815_init_queues(dev);
  923. }
  924. static void
  925. tc35815_free_queues(struct net_device *dev)
  926. {
  927. struct tc35815_local *lp = netdev_priv(dev);
  928. int i;
  929. if (lp->tfd_base) {
  930. for (i = 0; i < TX_FD_NUM; i++) {
  931. u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
  932. struct sk_buff *skb =
  933. fdsystem != 0xffffffff ?
  934. lp->tx_skbs[fdsystem].skb : NULL;
  935. #ifdef DEBUG
  936. if (lp->tx_skbs[i].skb != skb) {
  937. printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
  938. panic_queues(dev);
  939. }
  940. #else
  941. BUG_ON(lp->tx_skbs[i].skb != skb);
  942. #endif
  943. if (skb) {
  944. dev_kfree_skb(skb);
  945. pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
  946. lp->tx_skbs[i].skb = NULL;
  947. lp->tx_skbs[i].skb_dma = 0;
  948. }
  949. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
  950. }
  951. }
  952. lp->rfd_base = NULL;
  953. lp->rfd_limit = NULL;
  954. lp->rfd_cur = NULL;
  955. lp->fbl_ptr = NULL;
  956. for (i = 0; i < RX_BUF_NUM; i++) {
  957. if (lp->rx_skbs[i].skb) {
  958. free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
  959. lp->rx_skbs[i].skb_dma);
  960. lp->rx_skbs[i].skb = NULL;
  961. }
  962. }
  963. if (lp->fd_buf) {
  964. pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
  965. lp->fd_buf, lp->fd_buf_dma);
  966. lp->fd_buf = NULL;
  967. }
  968. }
  969. static void
  970. dump_txfd(struct TxFD *fd)
  971. {
  972. printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
  973. le32_to_cpu(fd->fd.FDNext),
  974. le32_to_cpu(fd->fd.FDSystem),
  975. le32_to_cpu(fd->fd.FDStat),
  976. le32_to_cpu(fd->fd.FDCtl));
  977. printk("BD: ");
  978. printk(" %08x %08x",
  979. le32_to_cpu(fd->bd.BuffData),
  980. le32_to_cpu(fd->bd.BDCtl));
  981. printk("\n");
  982. }
  983. static int
  984. dump_rxfd(struct RxFD *fd)
  985. {
  986. int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
  987. if (bd_count > 8)
  988. bd_count = 8;
  989. printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
  990. le32_to_cpu(fd->fd.FDNext),
  991. le32_to_cpu(fd->fd.FDSystem),
  992. le32_to_cpu(fd->fd.FDStat),
  993. le32_to_cpu(fd->fd.FDCtl));
  994. if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
  995. return 0;
  996. printk("BD: ");
  997. for (i = 0; i < bd_count; i++)
  998. printk(" %08x %08x",
  999. le32_to_cpu(fd->bd[i].BuffData),
  1000. le32_to_cpu(fd->bd[i].BDCtl));
  1001. printk("\n");
  1002. return bd_count;
  1003. }
  1004. #ifdef DEBUG
  1005. static void
  1006. dump_frfd(struct FrFD *fd)
  1007. {
  1008. int i;
  1009. printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
  1010. le32_to_cpu(fd->fd.FDNext),
  1011. le32_to_cpu(fd->fd.FDSystem),
  1012. le32_to_cpu(fd->fd.FDStat),
  1013. le32_to_cpu(fd->fd.FDCtl));
  1014. printk("BD: ");
  1015. for (i = 0; i < RX_BUF_NUM; i++)
  1016. printk(" %08x %08x",
  1017. le32_to_cpu(fd->bd[i].BuffData),
  1018. le32_to_cpu(fd->bd[i].BDCtl));
  1019. printk("\n");
  1020. }
  1021. static void
  1022. panic_queues(struct net_device *dev)
  1023. {
  1024. struct tc35815_local *lp = netdev_priv(dev);
  1025. int i;
  1026. printk("TxFD base %p, start %u, end %u\n",
  1027. lp->tfd_base, lp->tfd_start, lp->tfd_end);
  1028. printk("RxFD base %p limit %p cur %p\n",
  1029. lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
  1030. printk("FrFD %p\n", lp->fbl_ptr);
  1031. for (i = 0; i < TX_FD_NUM; i++)
  1032. dump_txfd(&lp->tfd_base[i]);
  1033. for (i = 0; i < RX_FD_NUM; i++) {
  1034. int bd_count = dump_rxfd(&lp->rfd_base[i]);
  1035. i += (bd_count + 1) / 2; /* skip BDs */
  1036. }
  1037. dump_frfd(lp->fbl_ptr);
  1038. panic("%s: Illegal queue state.", dev->name);
  1039. }
  1040. #endif
  1041. static void print_eth(const u8 *add)
  1042. {
  1043. printk(KERN_DEBUG "print_eth(%p)\n", add);
  1044. printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
  1045. add + 6, add, add[12], add[13]);
  1046. }
  1047. static int tc35815_tx_full(struct net_device *dev)
  1048. {
  1049. struct tc35815_local *lp = netdev_priv(dev);
  1050. return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
  1051. }
  1052. static void tc35815_restart(struct net_device *dev)
  1053. {
  1054. struct tc35815_local *lp = netdev_priv(dev);
  1055. if (lp->phy_dev) {
  1056. int timeout;
  1057. phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
  1058. timeout = 100;
  1059. while (--timeout) {
  1060. if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
  1061. break;
  1062. udelay(1);
  1063. }
  1064. if (!timeout)
  1065. printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
  1066. }
  1067. spin_lock_bh(&lp->rx_lock);
  1068. spin_lock_irq(&lp->lock);
  1069. tc35815_chip_reset(dev);
  1070. tc35815_clear_queues(dev);
  1071. tc35815_chip_init(dev);
  1072. /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
  1073. tc35815_set_multicast_list(dev);
  1074. spin_unlock_irq(&lp->lock);
  1075. spin_unlock_bh(&lp->rx_lock);
  1076. netif_wake_queue(dev);
  1077. }
  1078. static void tc35815_restart_work(struct work_struct *work)
  1079. {
  1080. struct tc35815_local *lp =
  1081. container_of(work, struct tc35815_local, restart_work);
  1082. struct net_device *dev = lp->dev;
  1083. tc35815_restart(dev);
  1084. }
  1085. static void tc35815_schedule_restart(struct net_device *dev)
  1086. {
  1087. struct tc35815_local *lp = netdev_priv(dev);
  1088. struct tc35815_regs __iomem *tr =
  1089. (struct tc35815_regs __iomem *)dev->base_addr;
  1090. unsigned long flags;
  1091. /* disable interrupts */
  1092. spin_lock_irqsave(&lp->lock, flags);
  1093. tc_writel(0, &tr->Int_En);
  1094. tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
  1095. schedule_work(&lp->restart_work);
  1096. spin_unlock_irqrestore(&lp->lock, flags);
  1097. }
  1098. static void tc35815_tx_timeout(struct net_device *dev)
  1099. {
  1100. struct tc35815_regs __iomem *tr =
  1101. (struct tc35815_regs __iomem *)dev->base_addr;
  1102. printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
  1103. dev->name, tc_readl(&tr->Tx_Stat));
  1104. /* Try to restart the adaptor. */
  1105. tc35815_schedule_restart(dev);
  1106. dev->stats.tx_errors++;
  1107. }
  1108. /*
  1109. * Open/initialize the controller. This is called (in the current kernel)
  1110. * sometime after booting when the 'ifconfig' program is run.
  1111. *
  1112. * This routine should set everything up anew at each open, even
  1113. * registers that "should" only need to be set once at boot, so that
  1114. * there is non-reboot way to recover if something goes wrong.
  1115. */
  1116. static int
  1117. tc35815_open(struct net_device *dev)
  1118. {
  1119. struct tc35815_local *lp = netdev_priv(dev);
  1120. /*
  1121. * This is used if the interrupt line can turned off (shared).
  1122. * See 3c503.c for an example of selecting the IRQ at config-time.
  1123. */
  1124. if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
  1125. dev->name, dev))
  1126. return -EAGAIN;
  1127. tc35815_chip_reset(dev);
  1128. if (tc35815_init_queues(dev) != 0) {
  1129. free_irq(dev->irq, dev);
  1130. return -EAGAIN;
  1131. }
  1132. napi_enable(&lp->napi);
  1133. /* Reset the hardware here. Don't forget to set the station address. */
  1134. spin_lock_irq(&lp->lock);
  1135. tc35815_chip_init(dev);
  1136. spin_unlock_irq(&lp->lock);
  1137. netif_carrier_off(dev);
  1138. /* schedule a link state check */
  1139. phy_start(lp->phy_dev);
  1140. /* We are now ready to accept transmit requeusts from
  1141. * the queueing layer of the networking.
  1142. */
  1143. netif_start_queue(dev);
  1144. return 0;
  1145. }
  1146. /* This will only be invoked if your driver is _not_ in XOFF state.
  1147. * What this means is that you need not check it, and that this
  1148. * invariant will hold if you make sure that the netif_*_queue()
  1149. * calls are done at the proper times.
  1150. */
  1151. static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
  1152. {
  1153. struct tc35815_local *lp = netdev_priv(dev);
  1154. struct TxFD *txfd;
  1155. unsigned long flags;
  1156. /* If some error occurs while trying to transmit this
  1157. * packet, you should return '1' from this function.
  1158. * In such a case you _may not_ do anything to the
  1159. * SKB, it is still owned by the network queueing
  1160. * layer when an error is returned. This means you
  1161. * may not modify any SKB fields, you may not free
  1162. * the SKB, etc.
  1163. */
  1164. /* This is the most common case for modern hardware.
  1165. * The spinlock protects this code from the TX complete
  1166. * hardware interrupt handler. Queue flow control is
  1167. * thus managed under this lock as well.
  1168. */
  1169. spin_lock_irqsave(&lp->lock, flags);
  1170. /* failsafe... (handle txdone now if half of FDs are used) */
  1171. if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
  1172. TX_FD_NUM / 2)
  1173. tc35815_txdone(dev);
  1174. if (netif_msg_pktdata(lp))
  1175. print_eth(skb->data);
  1176. #ifdef DEBUG
  1177. if (lp->tx_skbs[lp->tfd_start].skb) {
  1178. printk("%s: tx_skbs conflict.\n", dev->name);
  1179. panic_queues(dev);
  1180. }
  1181. #else
  1182. BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
  1183. #endif
  1184. lp->tx_skbs[lp->tfd_start].skb = skb;
  1185. lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
  1186. /*add to ring */
  1187. txfd = &lp->tfd_base[lp->tfd_start];
  1188. txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
  1189. txfd->bd.BDCtl = cpu_to_le32(skb->len);
  1190. txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
  1191. txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
  1192. if (lp->tfd_start == lp->tfd_end) {
  1193. struct tc35815_regs __iomem *tr =
  1194. (struct tc35815_regs __iomem *)dev->base_addr;
  1195. /* Start DMA Transmitter. */
  1196. txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
  1197. txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
  1198. if (netif_msg_tx_queued(lp)) {
  1199. printk("%s: starting TxFD.\n", dev->name);
  1200. dump_txfd(txfd);
  1201. }
  1202. tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
  1203. } else {
  1204. txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
  1205. if (netif_msg_tx_queued(lp)) {
  1206. printk("%s: queueing TxFD.\n", dev->name);
  1207. dump_txfd(txfd);
  1208. }
  1209. }
  1210. lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
  1211. /* If we just used up the very last entry in the
  1212. * TX ring on this device, tell the queueing
  1213. * layer to send no more.
  1214. */
  1215. if (tc35815_tx_full(dev)) {
  1216. if (netif_msg_tx_queued(lp))
  1217. printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
  1218. netif_stop_queue(dev);
  1219. }
  1220. /* When the TX completion hw interrupt arrives, this
  1221. * is when the transmit statistics are updated.
  1222. */
  1223. spin_unlock_irqrestore(&lp->lock, flags);
  1224. return NETDEV_TX_OK;
  1225. }
  1226. #define FATAL_ERROR_INT \
  1227. (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
  1228. static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
  1229. {
  1230. static int count;
  1231. printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
  1232. dev->name, status);
  1233. if (status & Int_IntPCI)
  1234. printk(" IntPCI");
  1235. if (status & Int_DmParErr)
  1236. printk(" DmParErr");
  1237. if (status & Int_IntNRAbt)
  1238. printk(" IntNRAbt");
  1239. printk("\n");
  1240. if (count++ > 100)
  1241. panic("%s: Too many fatal errors.", dev->name);
  1242. printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
  1243. /* Try to restart the adaptor. */
  1244. tc35815_schedule_restart(dev);
  1245. }
  1246. static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
  1247. {
  1248. struct tc35815_local *lp = netdev_priv(dev);
  1249. int ret = -1;
  1250. /* Fatal errors... */
  1251. if (status & FATAL_ERROR_INT) {
  1252. tc35815_fatal_error_interrupt(dev, status);
  1253. return 0;
  1254. }
  1255. /* recoverable errors */
  1256. if (status & Int_IntFDAEx) {
  1257. if (netif_msg_rx_err(lp))
  1258. dev_warn(&dev->dev,
  1259. "Free Descriptor Area Exhausted (%#x).\n",
  1260. status);
  1261. dev->stats.rx_dropped++;
  1262. ret = 0;
  1263. }
  1264. if (status & Int_IntBLEx) {
  1265. if (netif_msg_rx_err(lp))
  1266. dev_warn(&dev->dev,
  1267. "Buffer List Exhausted (%#x).\n",
  1268. status);
  1269. dev->stats.rx_dropped++;
  1270. ret = 0;
  1271. }
  1272. if (status & Int_IntExBD) {
  1273. if (netif_msg_rx_err(lp))
  1274. dev_warn(&dev->dev,
  1275. "Excessive Buffer Descriptiors (%#x).\n",
  1276. status);
  1277. dev->stats.rx_length_errors++;
  1278. ret = 0;
  1279. }
  1280. /* normal notification */
  1281. if (status & Int_IntMacRx) {
  1282. /* Got a packet(s). */
  1283. ret = tc35815_rx(dev, limit);
  1284. lp->lstats.rx_ints++;
  1285. }
  1286. if (status & Int_IntMacTx) {
  1287. /* Transmit complete. */
  1288. lp->lstats.tx_ints++;
  1289. spin_lock_irq(&lp->lock);
  1290. tc35815_txdone(dev);
  1291. spin_unlock_irq(&lp->lock);
  1292. if (ret < 0)
  1293. ret = 0;
  1294. }
  1295. return ret;
  1296. }
  1297. /*
  1298. * The typical workload of the driver:
  1299. * Handle the network interface interrupts.
  1300. */
  1301. static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
  1302. {
  1303. struct net_device *dev = dev_id;
  1304. struct tc35815_local *lp = netdev_priv(dev);
  1305. struct tc35815_regs __iomem *tr =
  1306. (struct tc35815_regs __iomem *)dev->base_addr;
  1307. u32 dmactl = tc_readl(&tr->DMA_Ctl);
  1308. if (!(dmactl & DMA_IntMask)) {
  1309. /* disable interrupts */
  1310. tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
  1311. if (napi_schedule_prep(&lp->napi))
  1312. __napi_schedule(&lp->napi);
  1313. else {
  1314. printk(KERN_ERR "%s: interrupt taken in poll\n",
  1315. dev->name);
  1316. BUG();
  1317. }
  1318. (void)tc_readl(&tr->Int_Src); /* flush */
  1319. return IRQ_HANDLED;
  1320. }
  1321. return IRQ_NONE;
  1322. }
  1323. #ifdef CONFIG_NET_POLL_CONTROLLER
  1324. static void tc35815_poll_controller(struct net_device *dev)
  1325. {
  1326. disable_irq(dev->irq);
  1327. tc35815_interrupt(dev->irq, dev);
  1328. enable_irq(dev->irq);
  1329. }
  1330. #endif
  1331. /* We have a good packet(s), get it/them out of the buffers. */
  1332. static int
  1333. tc35815_rx(struct net_device *dev, int limit)
  1334. {
  1335. struct tc35815_local *lp = netdev_priv(dev);
  1336. unsigned int fdctl;
  1337. int i;
  1338. int received = 0;
  1339. while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
  1340. int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
  1341. int pkt_len = fdctl & FD_FDLength_MASK;
  1342. int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
  1343. #ifdef DEBUG
  1344. struct RxFD *next_rfd;
  1345. #endif
  1346. #if (RX_CTL_CMD & Rx_StripCRC) == 0
  1347. pkt_len -= ETH_FCS_LEN;
  1348. #endif
  1349. if (netif_msg_rx_status(lp))
  1350. dump_rxfd(lp->rfd_cur);
  1351. if (status & Rx_Good) {
  1352. struct sk_buff *skb;
  1353. unsigned char *data;
  1354. int cur_bd;
  1355. if (--limit < 0)
  1356. break;
  1357. BUG_ON(bd_count > 1);
  1358. cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
  1359. & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
  1360. #ifdef DEBUG
  1361. if (cur_bd >= RX_BUF_NUM) {
  1362. printk("%s: invalid BDID.\n", dev->name);
  1363. panic_queues(dev);
  1364. }
  1365. BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
  1366. (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
  1367. if (!lp->rx_skbs[cur_bd].skb) {
  1368. printk("%s: NULL skb.\n", dev->name);
  1369. panic_queues(dev);
  1370. }
  1371. #else
  1372. BUG_ON(cur_bd >= RX_BUF_NUM);
  1373. #endif
  1374. skb = lp->rx_skbs[cur_bd].skb;
  1375. prefetch(skb->data);
  1376. lp->rx_skbs[cur_bd].skb = NULL;
  1377. pci_unmap_single(lp->pci_dev,
  1378. lp->rx_skbs[cur_bd].skb_dma,
  1379. RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  1380. if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
  1381. memmove(skb->data, skb->data - NET_IP_ALIGN,
  1382. pkt_len);
  1383. data = skb_put(skb, pkt_len);
  1384. if (netif_msg_pktdata(lp))
  1385. print_eth(data);
  1386. skb->protocol = eth_type_trans(skb, dev);
  1387. netif_receive_skb(skb);
  1388. received++;
  1389. dev->stats.rx_packets++;
  1390. dev->stats.rx_bytes += pkt_len;
  1391. } else {
  1392. dev->stats.rx_errors++;
  1393. if (netif_msg_rx_err(lp))
  1394. dev_info(&dev->dev, "Rx error (status %x)\n",
  1395. status & Rx_Stat_Mask);
  1396. /* WORKAROUND: LongErr and CRCErr means Overflow. */
  1397. if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
  1398. status &= ~(Rx_LongErr|Rx_CRCErr);
  1399. status |= Rx_Over;
  1400. }
  1401. if (status & Rx_LongErr)
  1402. dev->stats.rx_length_errors++;
  1403. if (status & Rx_Over)
  1404. dev->stats.rx_fifo_errors++;
  1405. if (status & Rx_CRCErr)
  1406. dev->stats.rx_crc_errors++;
  1407. if (status & Rx_Align)
  1408. dev->stats.rx_frame_errors++;
  1409. }
  1410. if (bd_count > 0) {
  1411. /* put Free Buffer back to controller */
  1412. int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
  1413. unsigned char id =
  1414. (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
  1415. #ifdef DEBUG
  1416. if (id >= RX_BUF_NUM) {
  1417. printk("%s: invalid BDID.\n", dev->name);
  1418. panic_queues(dev);
  1419. }
  1420. #else
  1421. BUG_ON(id >= RX_BUF_NUM);
  1422. #endif
  1423. /* free old buffers */
  1424. lp->fbl_count--;
  1425. while (lp->fbl_count < RX_BUF_NUM)
  1426. {
  1427. unsigned char curid =
  1428. (id + 1 + lp->fbl_count) % RX_BUF_NUM;
  1429. struct BDesc *bd = &lp->fbl_ptr->bd[curid];
  1430. #ifdef DEBUG
  1431. bdctl = le32_to_cpu(bd->BDCtl);
  1432. if (bdctl & BD_CownsBD) {
  1433. printk("%s: Freeing invalid BD.\n",
  1434. dev->name);
  1435. panic_queues(dev);
  1436. }
  1437. #endif
  1438. /* pass BD to controller */
  1439. if (!lp->rx_skbs[curid].skb) {
  1440. lp->rx_skbs[curid].skb =
  1441. alloc_rxbuf_skb(dev,
  1442. lp->pci_dev,
  1443. &lp->rx_skbs[curid].skb_dma);
  1444. if (!lp->rx_skbs[curid].skb)
  1445. break; /* try on next reception */
  1446. bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
  1447. }
  1448. /* Note: BDLength was modified by chip. */
  1449. bd->BDCtl = cpu_to_le32(BD_CownsBD |
  1450. (curid << BD_RxBDID_SHIFT) |
  1451. RX_BUF_SIZE);
  1452. lp->fbl_count++;
  1453. }
  1454. }
  1455. /* put RxFD back to controller */
  1456. #ifdef DEBUG
  1457. next_rfd = fd_bus_to_virt(lp,
  1458. le32_to_cpu(lp->rfd_cur->fd.FDNext));
  1459. if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
  1460. printk("%s: RxFD FDNext invalid.\n", dev->name);
  1461. panic_queues(dev);
  1462. }
  1463. #endif
  1464. for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
  1465. /* pass FD to controller */
  1466. #ifdef DEBUG
  1467. lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
  1468. #else
  1469. lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
  1470. #endif
  1471. lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
  1472. lp->rfd_cur++;
  1473. }
  1474. if (lp->rfd_cur > lp->rfd_limit)
  1475. lp->rfd_cur = lp->rfd_base;
  1476. #ifdef DEBUG
  1477. if (lp->rfd_cur != next_rfd)
  1478. printk("rfd_cur = %p, next_rfd %p\n",
  1479. lp->rfd_cur, next_rfd);
  1480. #endif
  1481. }
  1482. return received;
  1483. }
  1484. static int tc35815_poll(struct napi_struct *napi, int budget)
  1485. {
  1486. struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
  1487. struct net_device *dev = lp->dev;
  1488. struct tc35815_regs __iomem *tr =
  1489. (struct tc35815_regs __iomem *)dev->base_addr;
  1490. int received = 0, handled;
  1491. u32 status;
  1492. spin_lock(&lp->rx_lock);
  1493. status = tc_readl(&tr->Int_Src);
  1494. do {
  1495. /* BLEx, FDAEx will be cleared later */
  1496. tc_writel(status & ~(Int_BLEx | Int_FDAEx),
  1497. &tr->Int_Src); /* write to clear */
  1498. handled = tc35815_do_interrupt(dev, status, budget - received);
  1499. if (status & (Int_BLEx | Int_FDAEx))
  1500. tc_writel(status & (Int_BLEx | Int_FDAEx),
  1501. &tr->Int_Src);
  1502. if (handled >= 0) {
  1503. received += handled;
  1504. if (received >= budget)
  1505. break;
  1506. }
  1507. status = tc_readl(&tr->Int_Src);
  1508. } while (status);
  1509. spin_unlock(&lp->rx_lock);
  1510. if (received < budget) {
  1511. napi_complete(napi);
  1512. /* enable interrupts */
  1513. tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
  1514. }
  1515. return received;
  1516. }
  1517. #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
  1518. static void
  1519. tc35815_check_tx_stat(struct net_device *dev, int status)
  1520. {
  1521. struct tc35815_local *lp = netdev_priv(dev);
  1522. const char *msg = NULL;
  1523. /* count collisions */
  1524. if (status & Tx_ExColl)
  1525. dev->stats.collisions += 16;
  1526. if (status & Tx_TxColl_MASK)
  1527. dev->stats.collisions += status & Tx_TxColl_MASK;
  1528. /* TX4939 does not have NCarr */
  1529. if (lp->chiptype == TC35815_TX4939)
  1530. status &= ~Tx_NCarr;
  1531. /* WORKAROUND: ignore LostCrS in full duplex operation */
  1532. if (!lp->link || lp->duplex == DUPLEX_FULL)
  1533. status &= ~Tx_NCarr;
  1534. if (!(status & TX_STA_ERR)) {
  1535. /* no error. */
  1536. dev->stats.tx_packets++;
  1537. return;
  1538. }
  1539. dev->stats.tx_errors++;
  1540. if (status & Tx_ExColl) {
  1541. dev->stats.tx_aborted_errors++;
  1542. msg = "Excessive Collision.";
  1543. }
  1544. if (status & Tx_Under) {
  1545. dev->stats.tx_fifo_errors++;
  1546. msg = "Tx FIFO Underrun.";
  1547. if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
  1548. lp->lstats.tx_underrun++;
  1549. if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
  1550. struct tc35815_regs __iomem *tr =
  1551. (struct tc35815_regs __iomem *)dev->base_addr;
  1552. tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
  1553. msg = "Tx FIFO Underrun.Change Tx threshold to max.";
  1554. }
  1555. }
  1556. }
  1557. if (status & Tx_Defer) {
  1558. dev->stats.tx_fifo_errors++;
  1559. msg = "Excessive Deferral.";
  1560. }
  1561. if (status & Tx_NCarr) {
  1562. dev->stats.tx_carrier_errors++;
  1563. msg = "Lost Carrier Sense.";
  1564. }
  1565. if (status & Tx_LateColl) {
  1566. dev->stats.tx_aborted_errors++;
  1567. msg = "Late Collision.";
  1568. }
  1569. if (status & Tx_TxPar) {
  1570. dev->stats.tx_fifo_errors++;
  1571. msg = "Transmit Parity Error.";
  1572. }
  1573. if (status & Tx_SQErr) {
  1574. dev->stats.tx_heartbeat_errors++;
  1575. msg = "Signal Quality Error.";
  1576. }
  1577. if (msg && netif_msg_tx_err(lp))
  1578. printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
  1579. }
  1580. /* This handles TX complete events posted by the device
  1581. * via interrupts.
  1582. */
  1583. static void
  1584. tc35815_txdone(struct net_device *dev)
  1585. {
  1586. struct tc35815_local *lp = netdev_priv(dev);
  1587. struct TxFD *txfd;
  1588. unsigned int fdctl;
  1589. txfd = &lp->tfd_base[lp->tfd_end];
  1590. while (lp->tfd_start != lp->tfd_end &&
  1591. !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
  1592. int status = le32_to_cpu(txfd->fd.FDStat);
  1593. struct sk_buff *skb;
  1594. unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
  1595. u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
  1596. if (netif_msg_tx_done(lp)) {
  1597. printk("%s: complete TxFD.\n", dev->name);
  1598. dump_txfd(txfd);
  1599. }
  1600. tc35815_check_tx_stat(dev, status);
  1601. skb = fdsystem != 0xffffffff ?
  1602. lp->tx_skbs[fdsystem].skb : NULL;
  1603. #ifdef DEBUG
  1604. if (lp->tx_skbs[lp->tfd_end].skb != skb) {
  1605. printk("%s: tx_skbs mismatch.\n", dev->name);
  1606. panic_queues(dev);
  1607. }
  1608. #else
  1609. BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
  1610. #endif
  1611. if (skb) {
  1612. dev->stats.tx_bytes += skb->len;
  1613. pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
  1614. lp->tx_skbs[lp->tfd_end].skb = NULL;
  1615. lp->tx_skbs[lp->tfd_end].skb_dma = 0;
  1616. dev_kfree_skb_any(skb);
  1617. }
  1618. txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
  1619. lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
  1620. txfd = &lp->tfd_base[lp->tfd_end];
  1621. #ifdef DEBUG
  1622. if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
  1623. printk("%s: TxFD FDNext invalid.\n", dev->name);
  1624. panic_queues(dev);
  1625. }
  1626. #endif
  1627. if (fdnext & FD_Next_EOL) {
  1628. /* DMA Transmitter has been stopping... */
  1629. if (lp->tfd_end != lp->tfd_start) {
  1630. struct tc35815_regs __iomem *tr =
  1631. (struct tc35815_regs __iomem *)dev->base_addr;
  1632. int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
  1633. struct TxFD *txhead = &lp->tfd_base[head];
  1634. int qlen = (lp->tfd_start + TX_FD_NUM
  1635. - lp->tfd_end) % TX_FD_NUM;
  1636. #ifdef DEBUG
  1637. if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
  1638. printk("%s: TxFD FDCtl invalid.\n", dev->name);
  1639. panic_queues(dev);
  1640. }
  1641. #endif
  1642. /* log max queue length */
  1643. if (lp->lstats.max_tx_qlen < qlen)
  1644. lp->lstats.max_tx_qlen = qlen;
  1645. /* start DMA Transmitter again */
  1646. txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
  1647. txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
  1648. if (netif_msg_tx_queued(lp)) {
  1649. printk("%s: start TxFD on queue.\n",
  1650. dev->name);
  1651. dump_txfd(txfd);
  1652. }
  1653. tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
  1654. }
  1655. break;
  1656. }
  1657. }
  1658. /* If we had stopped the queue due to a "tx full"
  1659. * condition, and space has now been made available,
  1660. * wake up the queue.
  1661. */
  1662. if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
  1663. netif_wake_queue(dev);
  1664. }
  1665. /* The inverse routine to tc35815_open(). */
  1666. static int
  1667. tc35815_close(struct net_device *dev)
  1668. {
  1669. struct tc35815_local *lp = netdev_priv(dev);
  1670. netif_stop_queue(dev);
  1671. napi_disable(&lp->napi);
  1672. if (lp->phy_dev)
  1673. phy_stop(lp->phy_dev);
  1674. cancel_work_sync(&lp->restart_work);
  1675. /* Flush the Tx and disable Rx here. */
  1676. tc35815_chip_reset(dev);
  1677. free_irq(dev->irq, dev);
  1678. tc35815_free_queues(dev);
  1679. return 0;
  1680. }
  1681. /*
  1682. * Get the current statistics.
  1683. * This may be called with the card open or closed.
  1684. */
  1685. static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
  1686. {
  1687. struct tc35815_regs __iomem *tr =
  1688. (struct tc35815_regs __iomem *)dev->base_addr;
  1689. if (netif_running(dev))
  1690. /* Update the statistics from the device registers. */
  1691. dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
  1692. return &dev->stats;
  1693. }
  1694. static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
  1695. {
  1696. struct tc35815_local *lp = netdev_priv(dev);
  1697. struct tc35815_regs __iomem *tr =
  1698. (struct tc35815_regs __iomem *)dev->base_addr;
  1699. int cam_index = index * 6;
  1700. u32 cam_data;
  1701. u32 saved_addr;
  1702. saved_addr = tc_readl(&tr->CAM_Adr);
  1703. if (netif_msg_hw(lp))
  1704. printk(KERN_DEBUG "%s: CAM %d: %pM\n",
  1705. dev->name, index, addr);
  1706. if (index & 1) {
  1707. /* read modify write */
  1708. tc_writel(cam_index - 2, &tr->CAM_Adr);
  1709. cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
  1710. cam_data |= addr[0] << 8 | addr[1];
  1711. tc_writel(cam_data, &tr->CAM_Data);
  1712. /* write whole word */
  1713. tc_writel(cam_index + 2, &tr->CAM_Adr);
  1714. cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
  1715. tc_writel(cam_data, &tr->CAM_Data);
  1716. } else {
  1717. /* write whole word */
  1718. tc_writel(cam_index, &tr->CAM_Adr);
  1719. cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
  1720. tc_writel(cam_data, &tr->CAM_Data);
  1721. /* read modify write */
  1722. tc_writel(cam_index + 4, &tr->CAM_Adr);
  1723. cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
  1724. cam_data |= addr[4] << 24 | (addr[5] << 16);
  1725. tc_writel(cam_data, &tr->CAM_Data);
  1726. }
  1727. tc_writel(saved_addr, &tr->CAM_Adr);
  1728. }
  1729. /*
  1730. * Set or clear the multicast filter for this adaptor.
  1731. * num_addrs == -1 Promiscuous mode, receive all packets
  1732. * num_addrs == 0 Normal mode, clear multicast list
  1733. * num_addrs > 0 Multicast mode, receive normal and MC packets,
  1734. * and do best-effort filtering.
  1735. */
  1736. static void
  1737. tc35815_set_multicast_list(struct net_device *dev)
  1738. {
  1739. struct tc35815_regs __iomem *tr =
  1740. (struct tc35815_regs __iomem *)dev->base_addr;
  1741. if (dev->flags & IFF_PROMISC) {
  1742. /* With some (all?) 100MHalf HUB, controller will hang
  1743. * if we enabled promiscuous mode before linkup... */
  1744. struct tc35815_local *lp = netdev_priv(dev);
  1745. if (!lp->link)
  1746. return;
  1747. /* Enable promiscuous mode */
  1748. tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
  1749. } else if ((dev->flags & IFF_ALLMULTI) ||
  1750. netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
  1751. /* CAM 0, 1, 20 are reserved. */
  1752. /* Disable promiscuous mode, use normal mode. */
  1753. tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
  1754. } else if (!netdev_mc_empty(dev)) {
  1755. struct netdev_hw_addr *ha;
  1756. int i;
  1757. int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
  1758. tc_writel(0, &tr->CAM_Ctl);
  1759. /* Walk the address list, and load the filter */
  1760. i = 0;
  1761. netdev_for_each_mc_addr(ha, dev) {
  1762. /* entry 0,1 is reserved. */
  1763. tc35815_set_cam_entry(dev, i + 2, ha->addr);
  1764. ena_bits |= CAM_Ena_Bit(i + 2);
  1765. i++;
  1766. }
  1767. tc_writel(ena_bits, &tr->CAM_Ena);
  1768. tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
  1769. } else {
  1770. tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
  1771. tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
  1772. }
  1773. }
  1774. static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1775. {
  1776. struct tc35815_local *lp = netdev_priv(dev);
  1777. strcpy(info->driver, MODNAME);
  1778. strcpy(info->version, DRV_VERSION);
  1779. strcpy(info->bus_info, pci_name(lp->pci_dev));
  1780. }
  1781. static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1782. {
  1783. struct tc35815_local *lp = netdev_priv(dev);
  1784. if (!lp->phy_dev)
  1785. return -ENODEV;
  1786. return phy_ethtool_gset(lp->phy_dev, cmd);
  1787. }
  1788. static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1789. {
  1790. struct tc35815_local *lp = netdev_priv(dev);
  1791. if (!lp->phy_dev)
  1792. return -ENODEV;
  1793. return phy_ethtool_sset(lp->phy_dev, cmd);
  1794. }
  1795. static u32 tc35815_get_msglevel(struct net_device *dev)
  1796. {
  1797. struct tc35815_local *lp = netdev_priv(dev);
  1798. return lp->msg_enable;
  1799. }
  1800. static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
  1801. {
  1802. struct tc35815_local *lp = netdev_priv(dev);
  1803. lp->msg_enable = datum;
  1804. }
  1805. static int tc35815_get_sset_count(struct net_device *dev, int sset)
  1806. {
  1807. struct tc35815_local *lp = netdev_priv(dev);
  1808. switch (sset) {
  1809. case ETH_SS_STATS:
  1810. return sizeof(lp->lstats) / sizeof(int);
  1811. default:
  1812. return -EOPNOTSUPP;
  1813. }
  1814. }
  1815. static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
  1816. {
  1817. struct tc35815_local *lp = netdev_priv(dev);
  1818. data[0] = lp->lstats.max_tx_qlen;
  1819. data[1] = lp->lstats.tx_ints;
  1820. data[2] = lp->lstats.rx_ints;
  1821. data[3] = lp->lstats.tx_underrun;
  1822. }
  1823. static struct {
  1824. const char str[ETH_GSTRING_LEN];
  1825. } ethtool_stats_keys[] = {
  1826. { "max_tx_qlen" },
  1827. { "tx_ints" },
  1828. { "rx_ints" },
  1829. { "tx_underrun" },
  1830. };
  1831. static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  1832. {
  1833. memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
  1834. }
  1835. static const struct ethtool_ops tc35815_ethtool_ops = {
  1836. .get_drvinfo = tc35815_get_drvinfo,
  1837. .get_settings = tc35815_get_settings,
  1838. .set_settings = tc35815_set_settings,
  1839. .get_link = ethtool_op_get_link,
  1840. .get_msglevel = tc35815_get_msglevel,
  1841. .set_msglevel = tc35815_set_msglevel,
  1842. .get_strings = tc35815_get_strings,
  1843. .get_sset_count = tc35815_get_sset_count,
  1844. .get_ethtool_stats = tc35815_get_ethtool_stats,
  1845. };
  1846. static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1847. {
  1848. struct tc35815_local *lp = netdev_priv(dev);
  1849. if (!netif_running(dev))
  1850. return -EINVAL;
  1851. if (!lp->phy_dev)
  1852. return -ENODEV;
  1853. return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
  1854. }
  1855. static void tc35815_chip_reset(struct net_device *dev)
  1856. {
  1857. struct tc35815_regs __iomem *tr =
  1858. (struct tc35815_regs __iomem *)dev->base_addr;
  1859. int i;
  1860. /* reset the controller */
  1861. tc_writel(MAC_Reset, &tr->MAC_Ctl);
  1862. udelay(4); /* 3200ns */
  1863. i = 0;
  1864. while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
  1865. if (i++ > 100) {
  1866. printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
  1867. break;
  1868. }
  1869. mdelay(1);
  1870. }
  1871. tc_writel(0, &tr->MAC_Ctl);
  1872. /* initialize registers to default value */
  1873. tc_writel(0, &tr->DMA_Ctl);
  1874. tc_writel(0, &tr->TxThrsh);
  1875. tc_writel(0, &tr->TxPollCtr);
  1876. tc_writel(0, &tr->RxFragSize);
  1877. tc_writel(0, &tr->Int_En);
  1878. tc_writel(0, &tr->FDA_Bas);
  1879. tc_writel(0, &tr->FDA_Lim);
  1880. tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
  1881. tc_writel(0, &tr->CAM_Ctl);
  1882. tc_writel(0, &tr->Tx_Ctl);
  1883. tc_writel(0, &tr->Rx_Ctl);
  1884. tc_writel(0, &tr->CAM_Ena);
  1885. (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
  1886. /* initialize internal SRAM */
  1887. tc_writel(DMA_TestMode, &tr->DMA_Ctl);
  1888. for (i = 0; i < 0x1000; i += 4) {
  1889. tc_writel(i, &tr->CAM_Adr);
  1890. tc_writel(0, &tr->CAM_Data);
  1891. }
  1892. tc_writel(0, &tr->DMA_Ctl);
  1893. }
  1894. static void tc35815_chip_init(struct net_device *dev)
  1895. {
  1896. struct tc35815_local *lp = netdev_priv(dev);
  1897. struct tc35815_regs __iomem *tr =
  1898. (struct tc35815_regs __iomem *)dev->base_addr;
  1899. unsigned long txctl = TX_CTL_CMD;
  1900. /* load station address to CAM */
  1901. tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
  1902. /* Enable CAM (broadcast and unicast) */
  1903. tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
  1904. tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
  1905. /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
  1906. if (HAVE_DMA_RXALIGN(lp))
  1907. tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
  1908. else
  1909. tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
  1910. tc_writel(0, &tr->TxPollCtr); /* Batch mode */
  1911. tc_writel(TX_THRESHOLD, &tr->TxThrsh);
  1912. tc_writel(INT_EN_CMD, &tr->Int_En);
  1913. /* set queues */
  1914. tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
  1915. tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
  1916. &tr->FDA_Lim);
  1917. /*
  1918. * Activation method:
  1919. * First, enable the MAC Transmitter and the DMA Receive circuits.
  1920. * Then enable the DMA Transmitter and the MAC Receive circuits.
  1921. */
  1922. tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
  1923. tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
  1924. /* start MAC transmitter */
  1925. /* TX4939 does not have EnLCarr */
  1926. if (lp->chiptype == TC35815_TX4939)
  1927. txctl &= ~Tx_EnLCarr;
  1928. /* WORKAROUND: ignore LostCrS in full duplex operation */
  1929. if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
  1930. txctl &= ~Tx_EnLCarr;
  1931. tc_writel(txctl, &tr->Tx_Ctl);
  1932. }
  1933. #ifdef CONFIG_PM
  1934. static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
  1935. {
  1936. struct net_device *dev = pci_get_drvdata(pdev);
  1937. struct tc35815_local *lp = netdev_priv(dev);
  1938. unsigned long flags;
  1939. pci_save_state(pdev);
  1940. if (!netif_running(dev))
  1941. return 0;
  1942. netif_device_detach(dev);
  1943. if (lp->phy_dev)
  1944. phy_stop(lp->phy_dev);
  1945. spin_lock_irqsave(&lp->lock, flags);
  1946. tc35815_chip_reset(dev);
  1947. spin_unlock_irqrestore(&lp->lock, flags);
  1948. pci_set_power_state(pdev, PCI_D3hot);
  1949. return 0;
  1950. }
  1951. static int tc35815_resume(struct pci_dev *pdev)
  1952. {
  1953. struct net_device *dev = pci_get_drvdata(pdev);
  1954. struct tc35815_local *lp = netdev_priv(dev);
  1955. pci_restore_state(pdev);
  1956. if (!netif_running(dev))
  1957. return 0;
  1958. pci_set_power_state(pdev, PCI_D0);
  1959. tc35815_restart(dev);
  1960. netif_carrier_off(dev);
  1961. if (lp->phy_dev)
  1962. phy_start(lp->phy_dev);
  1963. netif_device_attach(dev);
  1964. return 0;
  1965. }
  1966. #endif /* CONFIG_PM */
  1967. static struct pci_driver tc35815_pci_driver = {
  1968. .name = MODNAME,
  1969. .id_table = tc35815_pci_tbl,
  1970. .probe = tc35815_init_one,
  1971. .remove = __devexit_p(tc35815_remove_one),
  1972. #ifdef CONFIG_PM
  1973. .suspend = tc35815_suspend,
  1974. .resume = tc35815_resume,
  1975. #endif
  1976. };
  1977. module_param_named(speed, options.speed, int, 0);
  1978. MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
  1979. module_param_named(duplex, options.duplex, int, 0);
  1980. MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
  1981. static int __init tc35815_init_module(void)
  1982. {
  1983. return pci_register_driver(&tc35815_pci_driver);
  1984. }
  1985. static void __exit tc35815_cleanup_module(void)
  1986. {
  1987. pci_unregister_driver(&tc35815_pci_driver);
  1988. }
  1989. module_init(tc35815_init_module);
  1990. module_exit(tc35815_cleanup_module);
  1991. MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
  1992. MODULE_LICENSE("GPL");