gdth.c 177 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: gdth_bufflen
  87. * buffer: gdth_sglist
  88. * dma_handle: unused
  89. * buffers_residual: gdth_sg_count
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #ifdef GDTH_RTC
  117. #include <linux/mc146818rtc.h>
  118. #endif
  119. #include <linux/reboot.h>
  120. #include <asm/dma.h>
  121. #include <asm/system.h>
  122. #include <asm/io.h>
  123. #include <asm/uaccess.h>
  124. #include <linux/spinlock.h>
  125. #include <linux/blkdev.h>
  126. #include <linux/scatterlist.h>
  127. #include "scsi.h"
  128. #include <scsi/scsi_host.h>
  129. #include "gdth.h"
  130. static void gdth_delay(int milliseconds);
  131. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  132. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  133. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  134. int gdth_from_wait, int* pIndex);
  135. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  136. Scsi_Cmnd *scp);
  137. static int gdth_async_event(gdth_ha_str *ha);
  138. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  139. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  140. static void gdth_next(gdth_ha_str *ha);
  141. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  142. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  143. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  144. ushort idx, gdth_evt_data *evt);
  145. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  146. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  147. gdth_evt_str *estr);
  148. static void gdth_clear_events(void);
  149. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  150. char *buffer, ushort count, int to_buffer);
  151. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  152. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  153. static void gdth_enable_int(gdth_ha_str *ha);
  154. static int gdth_test_busy(gdth_ha_str *ha);
  155. static int gdth_get_cmd_index(gdth_ha_str *ha);
  156. static void gdth_release_event(gdth_ha_str *ha);
  157. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  158. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  159. ulong32 p1, ulong64 p2,ulong64 p3);
  160. static int gdth_search_drives(gdth_ha_str *ha);
  161. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  162. static const char *gdth_ctr_name(gdth_ha_str *ha);
  163. static int gdth_open(struct inode *inode, struct file *filep);
  164. static int gdth_close(struct inode *inode, struct file *filep);
  165. static int gdth_ioctl(struct inode *inode, struct file *filep,
  166. unsigned int cmd, unsigned long arg);
  167. static void gdth_flush(gdth_ha_str *ha);
  168. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  169. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  170. struct gdth_cmndinfo *cmndinfo);
  171. static void gdth_scsi_done(struct scsi_cmnd *scp);
  172. #ifdef DEBUG_GDTH
  173. static unchar DebugState = DEBUG_GDTH;
  174. #ifdef __SERIAL__
  175. #define MAX_SERBUF 160
  176. static void ser_init(void);
  177. static void ser_puts(char *str);
  178. static void ser_putc(char c);
  179. static int ser_printk(const char *fmt, ...);
  180. static char strbuf[MAX_SERBUF+1];
  181. #ifdef __COM2__
  182. #define COM_BASE 0x2f8
  183. #else
  184. #define COM_BASE 0x3f8
  185. #endif
  186. static void ser_init()
  187. {
  188. unsigned port=COM_BASE;
  189. outb(0x80,port+3);
  190. outb(0,port+1);
  191. /* 19200 Baud, if 9600: outb(12,port) */
  192. outb(6, port);
  193. outb(3,port+3);
  194. outb(0,port+1);
  195. /*
  196. ser_putc('I');
  197. ser_putc(' ');
  198. */
  199. }
  200. static void ser_puts(char *str)
  201. {
  202. char *ptr;
  203. ser_init();
  204. for (ptr=str;*ptr;++ptr)
  205. ser_putc(*ptr);
  206. }
  207. static void ser_putc(char c)
  208. {
  209. unsigned port=COM_BASE;
  210. while ((inb(port+5) & 0x20)==0);
  211. outb(c,port);
  212. if (c==0x0a)
  213. {
  214. while ((inb(port+5) & 0x20)==0);
  215. outb(0x0d,port);
  216. }
  217. }
  218. static int ser_printk(const char *fmt, ...)
  219. {
  220. va_list args;
  221. int i;
  222. va_start(args,fmt);
  223. i = vsprintf(strbuf,fmt,args);
  224. ser_puts(strbuf);
  225. va_end(args);
  226. return i;
  227. }
  228. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  229. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  230. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  231. #else /* !__SERIAL__ */
  232. #define TRACE(a) {if (DebugState==1) {printk a;}}
  233. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  234. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  235. #endif
  236. #else /* !DEBUG */
  237. #define TRACE(a)
  238. #define TRACE2(a)
  239. #define TRACE3(a)
  240. #endif
  241. #ifdef GDTH_STATISTICS
  242. static ulong32 max_rq=0, max_index=0, max_sg=0;
  243. #ifdef INT_COAL
  244. static ulong32 max_int_coal=0;
  245. #endif
  246. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  247. static struct timer_list gdth_timer;
  248. #endif
  249. #define PTR2USHORT(a) (ushort)(ulong)(a)
  250. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  251. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  252. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  253. #ifdef CONFIG_ISA
  254. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  255. #endif
  256. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  257. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  258. #endif
  259. static unchar gdth_polling; /* polling if TRUE */
  260. static int gdth_ctr_count = 0; /* controller count */
  261. static LIST_HEAD(gdth_instances); /* controller list */
  262. static unchar gdth_write_through = FALSE; /* write through */
  263. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  264. static int elastidx;
  265. static int eoldidx;
  266. static int major;
  267. #define DIN 1 /* IN data direction */
  268. #define DOU 2 /* OUT data direction */
  269. #define DNO DIN /* no data transfer */
  270. #define DUN DIN /* unknown data direction */
  271. static unchar gdth_direction_tab[0x100] = {
  272. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  273. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  274. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  275. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  276. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  277. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  278. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  283. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  284. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  285. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  288. };
  289. /* LILO and modprobe/insmod parameters */
  290. /* IRQ list for GDT3000/3020 EISA controllers */
  291. static int irq[MAXHA] __initdata =
  292. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  293. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  294. /* disable driver flag */
  295. static int disable __initdata = 0;
  296. /* reserve flag */
  297. static int reserve_mode = 1;
  298. /* reserve list */
  299. static int reserve_list[MAX_RES_ARGS] =
  300. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  301. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  302. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  303. /* scan order for PCI controllers */
  304. static int reverse_scan = 0;
  305. /* virtual channel for the host drives */
  306. static int hdr_channel = 0;
  307. /* max. IDs per channel */
  308. static int max_ids = MAXID;
  309. /* rescan all IDs */
  310. static int rescan = 0;
  311. /* shared access */
  312. static int shared_access = 1;
  313. /* enable support for EISA and ISA controllers */
  314. static int probe_eisa_isa = 0;
  315. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  316. static int force_dma32 = 0;
  317. /* parameters for modprobe/insmod */
  318. module_param_array(irq, int, NULL, 0);
  319. module_param(disable, int, 0);
  320. module_param(reserve_mode, int, 0);
  321. module_param_array(reserve_list, int, NULL, 0);
  322. module_param(reverse_scan, int, 0);
  323. module_param(hdr_channel, int, 0);
  324. module_param(max_ids, int, 0);
  325. module_param(rescan, int, 0);
  326. module_param(shared_access, int, 0);
  327. module_param(probe_eisa_isa, int, 0);
  328. module_param(force_dma32, int, 0);
  329. MODULE_AUTHOR("Achim Leubner");
  330. MODULE_LICENSE("GPL");
  331. /* ioctl interface */
  332. static const struct file_operations gdth_fops = {
  333. .ioctl = gdth_ioctl,
  334. .open = gdth_open,
  335. .release = gdth_close,
  336. };
  337. /*
  338. * gdth scsi_command access wrappers.
  339. * below 6 functions are used throughout the driver to access scsi_command's
  340. * io parameters. The reason we do not use the regular accessors from
  341. * scsi_cmnd.h is because of gdth_execute(). Since it is unrecommended for
  342. * llds to directly set scsi_cmnd's IO members. This driver will use SCp
  343. * members for IO parameters, and will copy scsi_cmnd's members to Scp
  344. * members in queuecommand. For internal commands through gdth_execute()
  345. * SCp's members will be set directly.
  346. */
  347. static inline unsigned gdth_bufflen(struct scsi_cmnd *cmd)
  348. {
  349. return (unsigned)cmd->SCp.this_residual;
  350. }
  351. static inline void gdth_set_bufflen(struct scsi_cmnd *cmd, unsigned bufflen)
  352. {
  353. cmd->SCp.this_residual = bufflen;
  354. }
  355. static inline unsigned gdth_sg_count(struct scsi_cmnd *cmd)
  356. {
  357. return (unsigned)cmd->SCp.buffers_residual;
  358. }
  359. static inline void gdth_set_sg_count(struct scsi_cmnd *cmd, unsigned sg_count)
  360. {
  361. cmd->SCp.buffers_residual = sg_count;
  362. }
  363. static inline struct scatterlist *gdth_sglist(struct scsi_cmnd *cmd)
  364. {
  365. return cmd->SCp.buffer;
  366. }
  367. static inline void gdth_set_sglist(struct scsi_cmnd *cmd,
  368. struct scatterlist *sglist)
  369. {
  370. cmd->SCp.buffer = sglist;
  371. }
  372. #include "gdth_proc.h"
  373. #include "gdth_proc.c"
  374. static gdth_ha_str *gdth_find_ha(int hanum)
  375. {
  376. gdth_ha_str *ha;
  377. list_for_each_entry(ha, &gdth_instances, list)
  378. if (hanum == ha->hanum)
  379. return ha;
  380. return NULL;
  381. }
  382. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  383. {
  384. struct gdth_cmndinfo *priv = NULL;
  385. ulong flags;
  386. int i;
  387. spin_lock_irqsave(&ha->smp_lock, flags);
  388. for (i=0; i<GDTH_MAXCMDS; ++i) {
  389. if (ha->cmndinfo[i].index == 0) {
  390. priv = &ha->cmndinfo[i];
  391. priv->index = i+1;
  392. memset(priv, 0, sizeof(*priv));
  393. break;
  394. }
  395. }
  396. spin_unlock_irqrestore(&ha->smp_lock, flags);
  397. return priv;
  398. }
  399. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  400. {
  401. BUG_ON(!priv);
  402. priv->index = 0;
  403. }
  404. static void gdth_delay(int milliseconds)
  405. {
  406. if (milliseconds == 0) {
  407. udelay(1);
  408. } else {
  409. mdelay(milliseconds);
  410. }
  411. }
  412. static void gdth_scsi_done(struct scsi_cmnd *scp)
  413. {
  414. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  415. int internal_command = cmndinfo->internal_command;
  416. TRACE2(("gdth_scsi_done()\n"));
  417. gdth_put_cmndinfo(cmndinfo);
  418. scp->host_scribble = NULL;
  419. if (internal_command)
  420. complete((struct completion *)scp->request);
  421. else
  422. scp->scsi_done(scp);
  423. }
  424. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  425. int timeout, u32 *info)
  426. {
  427. gdth_ha_str *ha = shost_priv(sdev->host);
  428. Scsi_Cmnd *scp;
  429. struct gdth_cmndinfo cmndinfo;
  430. struct scatterlist one_sg;
  431. DECLARE_COMPLETION_ONSTACK(wait);
  432. int rval;
  433. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  434. if (!scp)
  435. return -ENOMEM;
  436. scp->device = sdev;
  437. memset(&cmndinfo, 0, sizeof(cmndinfo));
  438. /* use request field to save the ptr. to completion struct. */
  439. scp->request = (struct request *)&wait;
  440. scp->timeout_per_command = timeout*HZ;
  441. sg_init_one(&one_sg, gdtcmd, sizeof(*gdtcmd));
  442. gdth_set_sglist(scp, &one_sg);
  443. gdth_set_sg_count(scp, 1);
  444. gdth_set_bufflen(scp, sizeof(*gdtcmd));
  445. scp->cmd_len = 12;
  446. memcpy(scp->cmnd, cmnd, 12);
  447. cmndinfo.priority = IOCTL_PRI;
  448. cmndinfo.internal_command = 1;
  449. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  450. __gdth_queuecommand(ha, scp, &cmndinfo);
  451. wait_for_completion(&wait);
  452. rval = cmndinfo.status;
  453. if (info)
  454. *info = cmndinfo.info;
  455. kfree(scp);
  456. return rval;
  457. }
  458. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  459. int timeout, u32 *info)
  460. {
  461. struct scsi_device *sdev = scsi_get_host_dev(shost);
  462. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  463. scsi_free_host_dev(sdev);
  464. return rval;
  465. }
  466. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  467. {
  468. *cyls = size /HEADS/SECS;
  469. if (*cyls <= MAXCYLS) {
  470. *heads = HEADS;
  471. *secs = SECS;
  472. } else { /* too high for 64*32 */
  473. *cyls = size /MEDHEADS/MEDSECS;
  474. if (*cyls <= MAXCYLS) {
  475. *heads = MEDHEADS;
  476. *secs = MEDSECS;
  477. } else { /* too high for 127*63 */
  478. *cyls = size /BIGHEADS/BIGSECS;
  479. *heads = BIGHEADS;
  480. *secs = BIGSECS;
  481. }
  482. }
  483. }
  484. /* controller search and initialization functions */
  485. #ifdef CONFIG_EISA
  486. static int __init gdth_search_eisa(ushort eisa_adr)
  487. {
  488. ulong32 id;
  489. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  490. id = inl(eisa_adr+ID0REG);
  491. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  492. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  493. return 0; /* not EISA configured */
  494. return 1;
  495. }
  496. if (id == GDT3_ID) /* GDT3000 */
  497. return 1;
  498. return 0;
  499. }
  500. #endif /* CONFIG_EISA */
  501. #ifdef CONFIG_ISA
  502. static int __init gdth_search_isa(ulong32 bios_adr)
  503. {
  504. void __iomem *addr;
  505. ulong32 id;
  506. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  507. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  508. id = readl(addr);
  509. iounmap(addr);
  510. if (id == GDT2_ID) /* GDT2000 */
  511. return 1;
  512. }
  513. return 0;
  514. }
  515. #endif /* CONFIG_ISA */
  516. #ifdef CONFIG_PCI
  517. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  518. ushort vendor, ushort dev);
  519. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  520. {
  521. ushort device, cnt;
  522. TRACE(("gdth_search_pci()\n"));
  523. cnt = 0;
  524. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  525. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  526. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  527. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  528. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  529. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  530. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  531. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  532. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  533. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  534. PCI_DEVICE_ID_INTEL_SRC);
  535. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  536. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  537. return cnt;
  538. }
  539. /* Vortex only makes RAID controllers.
  540. * We do not really want to specify all 550 ids here, so wildcard match.
  541. */
  542. static struct pci_device_id gdthtable[] __maybe_unused = {
  543. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  544. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  545. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  546. {0}
  547. };
  548. MODULE_DEVICE_TABLE(pci,gdthtable);
  549. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  550. ushort vendor, ushort device)
  551. {
  552. ulong base0, base1, base2;
  553. struct pci_dev *pdev;
  554. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  555. *cnt, vendor, device));
  556. pdev = NULL;
  557. while ((pdev = pci_get_device(vendor, device, pdev))
  558. != NULL) {
  559. if (pci_enable_device(pdev))
  560. continue;
  561. if (*cnt >= MAXHA) {
  562. pci_dev_put(pdev);
  563. return;
  564. }
  565. /* GDT PCI controller found, resources are already in pdev */
  566. pcistr[*cnt].pdev = pdev;
  567. pcistr[*cnt].irq = pdev->irq;
  568. base0 = pci_resource_flags(pdev, 0);
  569. base1 = pci_resource_flags(pdev, 1);
  570. base2 = pci_resource_flags(pdev, 2);
  571. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  572. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  573. if (!(base0 & IORESOURCE_MEM))
  574. continue;
  575. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  576. } else { /* GDT6110, GDT6120, .. */
  577. if (!(base0 & IORESOURCE_MEM) ||
  578. !(base2 & IORESOURCE_MEM) ||
  579. !(base1 & IORESOURCE_IO))
  580. continue;
  581. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  582. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  583. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  584. }
  585. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  586. pcistr[*cnt].pdev->bus->number,
  587. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  588. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  589. (*cnt)++;
  590. }
  591. }
  592. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  593. {
  594. gdth_pci_str temp;
  595. int i, changed;
  596. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  597. if (cnt == 0)
  598. return;
  599. do {
  600. changed = FALSE;
  601. for (i = 0; i < cnt-1; ++i) {
  602. if (!reverse_scan) {
  603. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  604. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  605. PCI_SLOT(pcistr[i].pdev->devfn) >
  606. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  607. temp = pcistr[i];
  608. pcistr[i] = pcistr[i+1];
  609. pcistr[i+1] = temp;
  610. changed = TRUE;
  611. }
  612. } else {
  613. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  614. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  615. PCI_SLOT(pcistr[i].pdev->devfn) <
  616. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  617. temp = pcistr[i];
  618. pcistr[i] = pcistr[i+1];
  619. pcistr[i+1] = temp;
  620. changed = TRUE;
  621. }
  622. }
  623. }
  624. } while (changed);
  625. }
  626. #endif /* CONFIG_PCI */
  627. #ifdef CONFIG_EISA
  628. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  629. {
  630. ulong32 retries,id;
  631. unchar prot_ver,eisacf,i,irq_found;
  632. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  633. /* disable board interrupts, deinitialize services */
  634. outb(0xff,eisa_adr+EDOORREG);
  635. outb(0x00,eisa_adr+EDENABREG);
  636. outb(0x00,eisa_adr+EINTENABREG);
  637. outb(0xff,eisa_adr+LDOORREG);
  638. retries = INIT_RETRIES;
  639. gdth_delay(20);
  640. while (inb(eisa_adr+EDOORREG) != 0xff) {
  641. if (--retries == 0) {
  642. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  643. return 0;
  644. }
  645. gdth_delay(1);
  646. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  647. }
  648. prot_ver = inb(eisa_adr+MAILBOXREG);
  649. outb(0xff,eisa_adr+EDOORREG);
  650. if (prot_ver != PROTOCOL_VERSION) {
  651. printk("GDT-EISA: Illegal protocol version\n");
  652. return 0;
  653. }
  654. ha->bmic = eisa_adr;
  655. ha->brd_phys = (ulong32)eisa_adr >> 12;
  656. outl(0,eisa_adr+MAILBOXREG);
  657. outl(0,eisa_adr+MAILBOXREG+4);
  658. outl(0,eisa_adr+MAILBOXREG+8);
  659. outl(0,eisa_adr+MAILBOXREG+12);
  660. /* detect IRQ */
  661. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  662. ha->oem_id = OEM_ID_ICP;
  663. ha->type = GDT_EISA;
  664. ha->stype = id;
  665. outl(1,eisa_adr+MAILBOXREG+8);
  666. outb(0xfe,eisa_adr+LDOORREG);
  667. retries = INIT_RETRIES;
  668. gdth_delay(20);
  669. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  670. if (--retries == 0) {
  671. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  672. return 0;
  673. }
  674. gdth_delay(1);
  675. }
  676. ha->irq = inb(eisa_adr+MAILBOXREG);
  677. outb(0xff,eisa_adr+EDOORREG);
  678. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  679. /* check the result */
  680. if (ha->irq == 0) {
  681. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  682. for (i = 0, irq_found = FALSE;
  683. i < MAXHA && irq[i] != 0xff; ++i) {
  684. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  685. irq_found = TRUE;
  686. break;
  687. }
  688. }
  689. if (irq_found) {
  690. ha->irq = irq[i];
  691. irq[i] = 0;
  692. printk("GDT-EISA: Can not detect controller IRQ,\n");
  693. printk("Use IRQ setting from command line (IRQ = %d)\n",
  694. ha->irq);
  695. } else {
  696. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  697. printk("the controller BIOS or use command line parameters\n");
  698. return 0;
  699. }
  700. }
  701. } else {
  702. eisacf = inb(eisa_adr+EISAREG) & 7;
  703. if (eisacf > 4) /* level triggered */
  704. eisacf -= 4;
  705. ha->irq = gdth_irq_tab[eisacf];
  706. ha->oem_id = OEM_ID_ICP;
  707. ha->type = GDT_EISA;
  708. ha->stype = id;
  709. }
  710. ha->dma64_support = 0;
  711. return 1;
  712. }
  713. #endif /* CONFIG_EISA */
  714. #ifdef CONFIG_ISA
  715. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  716. {
  717. register gdt2_dpram_str __iomem *dp2_ptr;
  718. int i;
  719. unchar irq_drq,prot_ver;
  720. ulong32 retries;
  721. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  722. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  723. if (ha->brd == NULL) {
  724. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  725. return 0;
  726. }
  727. dp2_ptr = ha->brd;
  728. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  729. /* reset interface area */
  730. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  731. if (readl(&dp2_ptr->u) != 0) {
  732. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  733. iounmap(ha->brd);
  734. return 0;
  735. }
  736. /* disable board interrupts, read DRQ and IRQ */
  737. writeb(0xff, &dp2_ptr->io.irqdel);
  738. writeb(0x00, &dp2_ptr->io.irqen);
  739. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  740. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  741. irq_drq = readb(&dp2_ptr->io.rq);
  742. for (i=0; i<3; ++i) {
  743. if ((irq_drq & 1)==0)
  744. break;
  745. irq_drq >>= 1;
  746. }
  747. ha->drq = gdth_drq_tab[i];
  748. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  749. for (i=1; i<5; ++i) {
  750. if ((irq_drq & 1)==0)
  751. break;
  752. irq_drq >>= 1;
  753. }
  754. ha->irq = gdth_irq_tab[i];
  755. /* deinitialize services */
  756. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  757. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  758. writeb(0, &dp2_ptr->io.event);
  759. retries = INIT_RETRIES;
  760. gdth_delay(20);
  761. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  762. if (--retries == 0) {
  763. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  764. iounmap(ha->brd);
  765. return 0;
  766. }
  767. gdth_delay(1);
  768. }
  769. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  770. writeb(0, &dp2_ptr->u.ic.Status);
  771. writeb(0xff, &dp2_ptr->io.irqdel);
  772. if (prot_ver != PROTOCOL_VERSION) {
  773. printk("GDT-ISA: Illegal protocol version\n");
  774. iounmap(ha->brd);
  775. return 0;
  776. }
  777. ha->oem_id = OEM_ID_ICP;
  778. ha->type = GDT_ISA;
  779. ha->ic_all_size = sizeof(dp2_ptr->u);
  780. ha->stype= GDT2_ID;
  781. ha->brd_phys = bios_adr >> 4;
  782. /* special request to controller BIOS */
  783. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  784. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  785. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  786. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  787. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  788. writeb(0, &dp2_ptr->io.event);
  789. retries = INIT_RETRIES;
  790. gdth_delay(20);
  791. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  792. if (--retries == 0) {
  793. printk("GDT-ISA: Initialization error\n");
  794. iounmap(ha->brd);
  795. return 0;
  796. }
  797. gdth_delay(1);
  798. }
  799. writeb(0, &dp2_ptr->u.ic.Status);
  800. writeb(0xff, &dp2_ptr->io.irqdel);
  801. ha->dma64_support = 0;
  802. return 1;
  803. }
  804. #endif /* CONFIG_ISA */
  805. #ifdef CONFIG_PCI
  806. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  807. {
  808. register gdt6_dpram_str __iomem *dp6_ptr;
  809. register gdt6c_dpram_str __iomem *dp6c_ptr;
  810. register gdt6m_dpram_str __iomem *dp6m_ptr;
  811. ulong32 retries;
  812. unchar prot_ver;
  813. ushort command;
  814. int i, found = FALSE;
  815. TRACE(("gdth_init_pci()\n"));
  816. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  817. ha->oem_id = OEM_ID_INTEL;
  818. else
  819. ha->oem_id = OEM_ID_ICP;
  820. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  821. ha->stype = (ulong32)pcistr->pdev->device;
  822. ha->irq = pcistr->irq;
  823. ha->pdev = pcistr->pdev;
  824. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  825. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  826. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  827. if (ha->brd == NULL) {
  828. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  829. return 0;
  830. }
  831. /* check and reset interface area */
  832. dp6_ptr = ha->brd;
  833. writel(DPMEM_MAGIC, &dp6_ptr->u);
  834. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  835. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  836. pcistr->dpmem);
  837. found = FALSE;
  838. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  839. iounmap(ha->brd);
  840. ha->brd = ioremap(i, sizeof(ushort));
  841. if (ha->brd == NULL) {
  842. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  843. return 0;
  844. }
  845. if (readw(ha->brd) != 0xffff) {
  846. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  847. continue;
  848. }
  849. iounmap(ha->brd);
  850. pci_write_config_dword(pcistr->pdev,
  851. PCI_BASE_ADDRESS_0, i);
  852. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  853. if (ha->brd == NULL) {
  854. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  855. return 0;
  856. }
  857. dp6_ptr = ha->brd;
  858. writel(DPMEM_MAGIC, &dp6_ptr->u);
  859. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  860. printk("GDT-PCI: Use free address at 0x%x\n", i);
  861. found = TRUE;
  862. break;
  863. }
  864. }
  865. if (!found) {
  866. printk("GDT-PCI: No free address found!\n");
  867. iounmap(ha->brd);
  868. return 0;
  869. }
  870. }
  871. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  872. if (readl(&dp6_ptr->u) != 0) {
  873. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  874. iounmap(ha->brd);
  875. return 0;
  876. }
  877. /* disable board interrupts, deinit services */
  878. writeb(0xff, &dp6_ptr->io.irqdel);
  879. writeb(0x00, &dp6_ptr->io.irqen);
  880. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  881. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  882. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  883. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  884. writeb(0, &dp6_ptr->io.event);
  885. retries = INIT_RETRIES;
  886. gdth_delay(20);
  887. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  888. if (--retries == 0) {
  889. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  890. iounmap(ha->brd);
  891. return 0;
  892. }
  893. gdth_delay(1);
  894. }
  895. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  896. writeb(0, &dp6_ptr->u.ic.S_Status);
  897. writeb(0xff, &dp6_ptr->io.irqdel);
  898. if (prot_ver != PROTOCOL_VERSION) {
  899. printk("GDT-PCI: Illegal protocol version\n");
  900. iounmap(ha->brd);
  901. return 0;
  902. }
  903. ha->type = GDT_PCI;
  904. ha->ic_all_size = sizeof(dp6_ptr->u);
  905. /* special command to controller BIOS */
  906. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  907. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  908. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  909. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  910. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  911. writeb(0, &dp6_ptr->io.event);
  912. retries = INIT_RETRIES;
  913. gdth_delay(20);
  914. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  915. if (--retries == 0) {
  916. printk("GDT-PCI: Initialization error\n");
  917. iounmap(ha->brd);
  918. return 0;
  919. }
  920. gdth_delay(1);
  921. }
  922. writeb(0, &dp6_ptr->u.ic.S_Status);
  923. writeb(0xff, &dp6_ptr->io.irqdel);
  924. ha->dma64_support = 0;
  925. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  926. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  927. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  928. pcistr->dpmem,ha->irq));
  929. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  930. if (ha->brd == NULL) {
  931. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  932. iounmap(ha->brd);
  933. return 0;
  934. }
  935. /* check and reset interface area */
  936. dp6c_ptr = ha->brd;
  937. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  938. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  939. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  940. pcistr->dpmem);
  941. found = FALSE;
  942. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  943. iounmap(ha->brd);
  944. ha->brd = ioremap(i, sizeof(ushort));
  945. if (ha->brd == NULL) {
  946. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  947. return 0;
  948. }
  949. if (readw(ha->brd) != 0xffff) {
  950. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  951. continue;
  952. }
  953. iounmap(ha->brd);
  954. pci_write_config_dword(pcistr->pdev,
  955. PCI_BASE_ADDRESS_2, i);
  956. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  957. if (ha->brd == NULL) {
  958. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  959. return 0;
  960. }
  961. dp6c_ptr = ha->brd;
  962. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  963. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  964. printk("GDT-PCI: Use free address at 0x%x\n", i);
  965. found = TRUE;
  966. break;
  967. }
  968. }
  969. if (!found) {
  970. printk("GDT-PCI: No free address found!\n");
  971. iounmap(ha->brd);
  972. return 0;
  973. }
  974. }
  975. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  976. if (readl(&dp6c_ptr->u) != 0) {
  977. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  978. iounmap(ha->brd);
  979. return 0;
  980. }
  981. /* disable board interrupts, deinit services */
  982. outb(0x00,PTR2USHORT(&ha->plx->control1));
  983. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  984. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  985. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  986. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  987. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  988. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  989. retries = INIT_RETRIES;
  990. gdth_delay(20);
  991. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  992. if (--retries == 0) {
  993. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  994. iounmap(ha->brd);
  995. return 0;
  996. }
  997. gdth_delay(1);
  998. }
  999. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  1000. writeb(0, &dp6c_ptr->u.ic.Status);
  1001. if (prot_ver != PROTOCOL_VERSION) {
  1002. printk("GDT-PCI: Illegal protocol version\n");
  1003. iounmap(ha->brd);
  1004. return 0;
  1005. }
  1006. ha->type = GDT_PCINEW;
  1007. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1008. /* special command to controller BIOS */
  1009. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1010. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1011. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1012. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1013. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1014. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1015. retries = INIT_RETRIES;
  1016. gdth_delay(20);
  1017. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1018. if (--retries == 0) {
  1019. printk("GDT-PCI: Initialization error\n");
  1020. iounmap(ha->brd);
  1021. return 0;
  1022. }
  1023. gdth_delay(1);
  1024. }
  1025. writeb(0, &dp6c_ptr->u.ic.S_Status);
  1026. ha->dma64_support = 0;
  1027. } else { /* MPR */
  1028. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1029. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1030. if (ha->brd == NULL) {
  1031. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1032. return 0;
  1033. }
  1034. /* manipulate config. space to enable DPMEM, start RP controller */
  1035. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1036. command |= 6;
  1037. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1038. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1039. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1040. i = 0xFEFF0001UL;
  1041. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1042. gdth_delay(1);
  1043. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1044. pci_resource_start(pcistr->pdev, 8));
  1045. dp6m_ptr = ha->brd;
  1046. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1047. * Aditional check needed for Xscale based RAID controllers */
  1048. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1049. gdth_delay(1);
  1050. /* check and reset interface area */
  1051. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1052. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1053. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1054. pcistr->dpmem);
  1055. found = FALSE;
  1056. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1057. iounmap(ha->brd);
  1058. ha->brd = ioremap(i, sizeof(ushort));
  1059. if (ha->brd == NULL) {
  1060. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1061. return 0;
  1062. }
  1063. if (readw(ha->brd) != 0xffff) {
  1064. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1065. continue;
  1066. }
  1067. iounmap(ha->brd);
  1068. pci_write_config_dword(pcistr->pdev,
  1069. PCI_BASE_ADDRESS_0, i);
  1070. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1071. if (ha->brd == NULL) {
  1072. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1073. return 0;
  1074. }
  1075. dp6m_ptr = ha->brd;
  1076. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1077. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1078. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1079. found = TRUE;
  1080. break;
  1081. }
  1082. }
  1083. if (!found) {
  1084. printk("GDT-PCI: No free address found!\n");
  1085. iounmap(ha->brd);
  1086. return 0;
  1087. }
  1088. }
  1089. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1090. /* disable board interrupts, deinit services */
  1091. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1092. &dp6m_ptr->i960r.edoor_en_reg);
  1093. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1094. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1095. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1096. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1097. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1098. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1099. retries = INIT_RETRIES;
  1100. gdth_delay(20);
  1101. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1102. if (--retries == 0) {
  1103. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1104. iounmap(ha->brd);
  1105. return 0;
  1106. }
  1107. gdth_delay(1);
  1108. }
  1109. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1110. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1111. if (prot_ver != PROTOCOL_VERSION) {
  1112. printk("GDT-PCI: Illegal protocol version\n");
  1113. iounmap(ha->brd);
  1114. return 0;
  1115. }
  1116. ha->type = GDT_PCIMPR;
  1117. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1118. /* special command to controller BIOS */
  1119. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1120. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1121. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1122. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1123. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1124. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1125. retries = INIT_RETRIES;
  1126. gdth_delay(20);
  1127. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1128. if (--retries == 0) {
  1129. printk("GDT-PCI: Initialization error\n");
  1130. iounmap(ha->brd);
  1131. return 0;
  1132. }
  1133. gdth_delay(1);
  1134. }
  1135. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1136. /* read FW version to detect 64-bit DMA support */
  1137. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1138. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1139. retries = INIT_RETRIES;
  1140. gdth_delay(20);
  1141. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1142. if (--retries == 0) {
  1143. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1144. iounmap(ha->brd);
  1145. return 0;
  1146. }
  1147. gdth_delay(1);
  1148. }
  1149. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1150. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1151. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1152. ha->dma64_support = 0;
  1153. else
  1154. ha->dma64_support = 1;
  1155. }
  1156. return 1;
  1157. }
  1158. #endif /* CONFIG_PCI */
  1159. /* controller protocol functions */
  1160. static void __init gdth_enable_int(gdth_ha_str *ha)
  1161. {
  1162. ulong flags;
  1163. gdt2_dpram_str __iomem *dp2_ptr;
  1164. gdt6_dpram_str __iomem *dp6_ptr;
  1165. gdt6m_dpram_str __iomem *dp6m_ptr;
  1166. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1167. spin_lock_irqsave(&ha->smp_lock, flags);
  1168. if (ha->type == GDT_EISA) {
  1169. outb(0xff, ha->bmic + EDOORREG);
  1170. outb(0xff, ha->bmic + EDENABREG);
  1171. outb(0x01, ha->bmic + EINTENABREG);
  1172. } else if (ha->type == GDT_ISA) {
  1173. dp2_ptr = ha->brd;
  1174. writeb(1, &dp2_ptr->io.irqdel);
  1175. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1176. writeb(1, &dp2_ptr->io.irqen);
  1177. } else if (ha->type == GDT_PCI) {
  1178. dp6_ptr = ha->brd;
  1179. writeb(1, &dp6_ptr->io.irqdel);
  1180. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1181. writeb(1, &dp6_ptr->io.irqen);
  1182. } else if (ha->type == GDT_PCINEW) {
  1183. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1184. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1185. } else if (ha->type == GDT_PCIMPR) {
  1186. dp6m_ptr = ha->brd;
  1187. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1188. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1189. &dp6m_ptr->i960r.edoor_en_reg);
  1190. }
  1191. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1192. }
  1193. /* return IStatus if interrupt was from this card else 0 */
  1194. static unchar gdth_get_status(gdth_ha_str *ha)
  1195. {
  1196. unchar IStatus = 0;
  1197. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1198. if (ha->type == GDT_EISA)
  1199. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1200. else if (ha->type == GDT_ISA)
  1201. IStatus =
  1202. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1203. else if (ha->type == GDT_PCI)
  1204. IStatus =
  1205. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1206. else if (ha->type == GDT_PCINEW)
  1207. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1208. else if (ha->type == GDT_PCIMPR)
  1209. IStatus =
  1210. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1211. return IStatus;
  1212. }
  1213. static int gdth_test_busy(gdth_ha_str *ha)
  1214. {
  1215. register int gdtsema0 = 0;
  1216. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1217. if (ha->type == GDT_EISA)
  1218. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1219. else if (ha->type == GDT_ISA)
  1220. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1221. else if (ha->type == GDT_PCI)
  1222. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1223. else if (ha->type == GDT_PCINEW)
  1224. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1225. else if (ha->type == GDT_PCIMPR)
  1226. gdtsema0 =
  1227. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1228. return (gdtsema0 & 1);
  1229. }
  1230. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1231. {
  1232. int i;
  1233. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1234. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1235. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1236. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1237. ha->cmd_tab[i].service = ha->pccb->Service;
  1238. ha->pccb->CommandIndex = (ulong32)i+2;
  1239. return (i+2);
  1240. }
  1241. }
  1242. return 0;
  1243. }
  1244. static void gdth_set_sema0(gdth_ha_str *ha)
  1245. {
  1246. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1247. if (ha->type == GDT_EISA) {
  1248. outb(1, ha->bmic + SEMA0REG);
  1249. } else if (ha->type == GDT_ISA) {
  1250. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1251. } else if (ha->type == GDT_PCI) {
  1252. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1253. } else if (ha->type == GDT_PCINEW) {
  1254. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1255. } else if (ha->type == GDT_PCIMPR) {
  1256. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1257. }
  1258. }
  1259. static void gdth_copy_command(gdth_ha_str *ha)
  1260. {
  1261. register gdth_cmd_str *cmd_ptr;
  1262. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1263. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1264. gdt6_dpram_str __iomem *dp6_ptr;
  1265. gdt2_dpram_str __iomem *dp2_ptr;
  1266. ushort cp_count,dp_offset,cmd_no;
  1267. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1268. cp_count = ha->cmd_len;
  1269. dp_offset= ha->cmd_offs_dpmem;
  1270. cmd_no = ha->cmd_cnt;
  1271. cmd_ptr = ha->pccb;
  1272. ++ha->cmd_cnt;
  1273. if (ha->type == GDT_EISA)
  1274. return; /* no DPMEM, no copy */
  1275. /* set cpcount dword aligned */
  1276. if (cp_count & 3)
  1277. cp_count += (4 - (cp_count & 3));
  1278. ha->cmd_offs_dpmem += cp_count;
  1279. /* set offset and service, copy command to DPMEM */
  1280. if (ha->type == GDT_ISA) {
  1281. dp2_ptr = ha->brd;
  1282. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1283. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1284. writew((ushort)cmd_ptr->Service,
  1285. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1286. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1287. } else if (ha->type == GDT_PCI) {
  1288. dp6_ptr = ha->brd;
  1289. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1290. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1291. writew((ushort)cmd_ptr->Service,
  1292. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1293. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1294. } else if (ha->type == GDT_PCINEW) {
  1295. dp6c_ptr = ha->brd;
  1296. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1297. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1298. writew((ushort)cmd_ptr->Service,
  1299. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1300. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1301. } else if (ha->type == GDT_PCIMPR) {
  1302. dp6m_ptr = ha->brd;
  1303. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1304. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1305. writew((ushort)cmd_ptr->Service,
  1306. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1307. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1308. }
  1309. }
  1310. static void gdth_release_event(gdth_ha_str *ha)
  1311. {
  1312. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1313. #ifdef GDTH_STATISTICS
  1314. {
  1315. ulong32 i,j;
  1316. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1317. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1318. ++i;
  1319. }
  1320. if (max_index < i) {
  1321. max_index = i;
  1322. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1323. }
  1324. }
  1325. #endif
  1326. if (ha->pccb->OpCode == GDT_INIT)
  1327. ha->pccb->Service |= 0x80;
  1328. if (ha->type == GDT_EISA) {
  1329. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1330. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1331. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1332. } else if (ha->type == GDT_ISA) {
  1333. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1334. } else if (ha->type == GDT_PCI) {
  1335. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1336. } else if (ha->type == GDT_PCINEW) {
  1337. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1338. } else if (ha->type == GDT_PCIMPR) {
  1339. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1340. }
  1341. }
  1342. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1343. {
  1344. int answer_found = FALSE;
  1345. int wait_index = 0;
  1346. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1347. if (index == 0)
  1348. return 1; /* no wait required */
  1349. do {
  1350. __gdth_interrupt(ha, true, &wait_index);
  1351. if (wait_index == index) {
  1352. answer_found = TRUE;
  1353. break;
  1354. }
  1355. gdth_delay(1);
  1356. } while (--time);
  1357. while (gdth_test_busy(ha))
  1358. gdth_delay(0);
  1359. return (answer_found);
  1360. }
  1361. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1362. ulong32 p1, ulong64 p2, ulong64 p3)
  1363. {
  1364. register gdth_cmd_str *cmd_ptr;
  1365. int retries,index;
  1366. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1367. cmd_ptr = ha->pccb;
  1368. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1369. /* make command */
  1370. for (retries = INIT_RETRIES;;) {
  1371. cmd_ptr->Service = service;
  1372. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1373. if (!(index=gdth_get_cmd_index(ha))) {
  1374. TRACE(("GDT: No free command index found\n"));
  1375. return 0;
  1376. }
  1377. gdth_set_sema0(ha);
  1378. cmd_ptr->OpCode = opcode;
  1379. cmd_ptr->BoardNode = LOCALBOARD;
  1380. if (service == CACHESERVICE) {
  1381. if (opcode == GDT_IOCTL) {
  1382. cmd_ptr->u.ioctl.subfunc = p1;
  1383. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1384. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1385. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1386. } else {
  1387. if (ha->cache_feat & GDT_64BIT) {
  1388. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1389. cmd_ptr->u.cache64.BlockNo = p2;
  1390. } else {
  1391. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1392. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1393. }
  1394. }
  1395. } else if (service == SCSIRAWSERVICE) {
  1396. if (ha->raw_feat & GDT_64BIT) {
  1397. cmd_ptr->u.raw64.direction = p1;
  1398. cmd_ptr->u.raw64.bus = (unchar)p2;
  1399. cmd_ptr->u.raw64.target = (unchar)p3;
  1400. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1401. } else {
  1402. cmd_ptr->u.raw.direction = p1;
  1403. cmd_ptr->u.raw.bus = (unchar)p2;
  1404. cmd_ptr->u.raw.target = (unchar)p3;
  1405. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1406. }
  1407. } else if (service == SCREENSERVICE) {
  1408. if (opcode == GDT_REALTIME) {
  1409. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1410. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1411. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1412. }
  1413. }
  1414. ha->cmd_len = sizeof(gdth_cmd_str);
  1415. ha->cmd_offs_dpmem = 0;
  1416. ha->cmd_cnt = 0;
  1417. gdth_copy_command(ha);
  1418. gdth_release_event(ha);
  1419. gdth_delay(20);
  1420. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1421. printk("GDT: Initialization error (timeout service %d)\n",service);
  1422. return 0;
  1423. }
  1424. if (ha->status != S_BSY || --retries == 0)
  1425. break;
  1426. gdth_delay(1);
  1427. }
  1428. return (ha->status != S_OK ? 0:1);
  1429. }
  1430. /* search for devices */
  1431. static int __init gdth_search_drives(gdth_ha_str *ha)
  1432. {
  1433. ushort cdev_cnt, i;
  1434. int ok;
  1435. ulong32 bus_no, drv_cnt, drv_no, j;
  1436. gdth_getch_str *chn;
  1437. gdth_drlist_str *drl;
  1438. gdth_iochan_str *ioc;
  1439. gdth_raw_iochan_str *iocr;
  1440. gdth_arcdl_str *alst;
  1441. gdth_alist_str *alst2;
  1442. gdth_oem_str_ioctl *oemstr;
  1443. #ifdef INT_COAL
  1444. gdth_perf_modes *pmod;
  1445. #endif
  1446. #ifdef GDTH_RTC
  1447. unchar rtc[12];
  1448. ulong flags;
  1449. #endif
  1450. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1451. ok = 0;
  1452. /* initialize controller services, at first: screen service */
  1453. ha->screen_feat = 0;
  1454. if (!force_dma32) {
  1455. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1456. if (ok)
  1457. ha->screen_feat = GDT_64BIT;
  1458. }
  1459. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1460. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1461. if (!ok) {
  1462. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1463. ha->hanum, ha->status);
  1464. return 0;
  1465. }
  1466. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1467. #ifdef GDTH_RTC
  1468. /* read realtime clock info, send to controller */
  1469. /* 1. wait for the falling edge of update flag */
  1470. spin_lock_irqsave(&rtc_lock, flags);
  1471. for (j = 0; j < 1000000; ++j)
  1472. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1473. break;
  1474. for (j = 0; j < 1000000; ++j)
  1475. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1476. break;
  1477. /* 2. read info */
  1478. do {
  1479. for (j = 0; j < 12; ++j)
  1480. rtc[j] = CMOS_READ(j);
  1481. } while (rtc[0] != CMOS_READ(0));
  1482. spin_unlock_irqrestore(&rtc_lock, flags);
  1483. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1484. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1485. /* 3. send to controller firmware */
  1486. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1487. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1488. #endif
  1489. /* unfreeze all IOs */
  1490. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1491. /* initialize cache service */
  1492. ha->cache_feat = 0;
  1493. if (!force_dma32) {
  1494. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1495. 0, 0);
  1496. if (ok)
  1497. ha->cache_feat = GDT_64BIT;
  1498. }
  1499. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1500. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1501. if (!ok) {
  1502. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1503. ha->hanum, ha->status);
  1504. return 0;
  1505. }
  1506. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1507. cdev_cnt = (ushort)ha->info;
  1508. ha->fw_vers = ha->service;
  1509. #ifdef INT_COAL
  1510. if (ha->type == GDT_PCIMPR) {
  1511. /* set perf. modes */
  1512. pmod = (gdth_perf_modes *)ha->pscratch;
  1513. pmod->version = 1;
  1514. pmod->st_mode = 1; /* enable one status buffer */
  1515. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1516. pmod->st_buff_indx1 = COALINDEX;
  1517. pmod->st_buff_addr2 = 0;
  1518. pmod->st_buff_u_addr2 = 0;
  1519. pmod->st_buff_indx2 = 0;
  1520. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1521. pmod->cmd_mode = 0; // disable all cmd buffers
  1522. pmod->cmd_buff_addr1 = 0;
  1523. pmod->cmd_buff_u_addr1 = 0;
  1524. pmod->cmd_buff_indx1 = 0;
  1525. pmod->cmd_buff_addr2 = 0;
  1526. pmod->cmd_buff_u_addr2 = 0;
  1527. pmod->cmd_buff_indx2 = 0;
  1528. pmod->cmd_buff_size = 0;
  1529. pmod->reserved1 = 0;
  1530. pmod->reserved2 = 0;
  1531. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1532. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1533. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1534. }
  1535. }
  1536. #endif
  1537. /* detect number of buses - try new IOCTL */
  1538. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1539. iocr->hdr.version = 0xffffffff;
  1540. iocr->hdr.list_entries = MAXBUS;
  1541. iocr->hdr.first_chan = 0;
  1542. iocr->hdr.last_chan = MAXBUS-1;
  1543. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1544. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1545. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1546. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1547. ha->bus_cnt = iocr->hdr.chan_count;
  1548. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1549. if (iocr->list[bus_no].proc_id < MAXID)
  1550. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1551. else
  1552. ha->bus_id[bus_no] = 0xff;
  1553. }
  1554. } else {
  1555. /* old method */
  1556. chn = (gdth_getch_str *)ha->pscratch;
  1557. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1558. chn->channel_no = bus_no;
  1559. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1560. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1561. IO_CHANNEL | INVALID_CHANNEL,
  1562. sizeof(gdth_getch_str))) {
  1563. if (bus_no == 0) {
  1564. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1565. ha->hanum, ha->status);
  1566. return 0;
  1567. }
  1568. break;
  1569. }
  1570. if (chn->siop_id < MAXID)
  1571. ha->bus_id[bus_no] = chn->siop_id;
  1572. else
  1573. ha->bus_id[bus_no] = 0xff;
  1574. }
  1575. ha->bus_cnt = (unchar)bus_no;
  1576. }
  1577. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1578. /* read cache configuration */
  1579. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1580. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1581. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1582. ha->hanum, ha->status);
  1583. return 0;
  1584. }
  1585. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1586. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1587. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1588. ha->cpar.write_back,ha->cpar.block_size));
  1589. /* read board info and features */
  1590. ha->more_proc = FALSE;
  1591. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1592. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1593. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1594. sizeof(gdth_binfo_str));
  1595. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1596. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1597. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1598. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1599. ha->more_proc = TRUE;
  1600. }
  1601. } else {
  1602. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1603. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1604. }
  1605. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1606. /* read more informations */
  1607. if (ha->more_proc) {
  1608. /* physical drives, channel addresses */
  1609. ioc = (gdth_iochan_str *)ha->pscratch;
  1610. ioc->hdr.version = 0xffffffff;
  1611. ioc->hdr.list_entries = MAXBUS;
  1612. ioc->hdr.first_chan = 0;
  1613. ioc->hdr.last_chan = MAXBUS-1;
  1614. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1615. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1616. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1617. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1618. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1619. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1620. }
  1621. } else {
  1622. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1623. ha->raw[bus_no].address = IO_CHANNEL;
  1624. ha->raw[bus_no].local_no = bus_no;
  1625. }
  1626. }
  1627. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1628. chn = (gdth_getch_str *)ha->pscratch;
  1629. chn->channel_no = ha->raw[bus_no].local_no;
  1630. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1631. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1632. ha->raw[bus_no].address | INVALID_CHANNEL,
  1633. sizeof(gdth_getch_str))) {
  1634. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1635. TRACE2(("Channel %d: %d phys. drives\n",
  1636. bus_no,chn->drive_cnt));
  1637. }
  1638. if (ha->raw[bus_no].pdev_cnt > 0) {
  1639. drl = (gdth_drlist_str *)ha->pscratch;
  1640. drl->sc_no = ha->raw[bus_no].local_no;
  1641. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1642. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1643. SCSI_DR_LIST | L_CTRL_PATTERN,
  1644. ha->raw[bus_no].address | INVALID_CHANNEL,
  1645. sizeof(gdth_drlist_str))) {
  1646. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1647. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1648. } else {
  1649. ha->raw[bus_no].pdev_cnt = 0;
  1650. }
  1651. }
  1652. }
  1653. /* logical drives */
  1654. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1655. INVALID_CHANNEL,sizeof(ulong32))) {
  1656. drv_cnt = *(ulong32 *)ha->pscratch;
  1657. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1658. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1659. for (j = 0; j < drv_cnt; ++j) {
  1660. drv_no = ((ulong32 *)ha->pscratch)[j];
  1661. if (drv_no < MAX_LDRIVES) {
  1662. ha->hdr[drv_no].is_logdrv = TRUE;
  1663. TRACE2(("Drive %d is log. drive\n",drv_no));
  1664. }
  1665. }
  1666. }
  1667. alst = (gdth_arcdl_str *)ha->pscratch;
  1668. alst->entries_avail = MAX_LDRIVES;
  1669. alst->first_entry = 0;
  1670. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1671. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1672. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1673. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1674. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1675. for (j = 0; j < alst->entries_init; ++j) {
  1676. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1677. ha->hdr[j].is_master = alst->list[j].is_master;
  1678. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1679. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1680. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1681. }
  1682. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1683. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1684. 0, 35 * sizeof(gdth_alist_str))) {
  1685. for (j = 0; j < 35; ++j) {
  1686. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1687. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1688. ha->hdr[j].is_master = alst2->is_master;
  1689. ha->hdr[j].is_parity = alst2->is_parity;
  1690. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1691. ha->hdr[j].master_no = alst2->cd_handle;
  1692. }
  1693. }
  1694. }
  1695. }
  1696. /* initialize raw service */
  1697. ha->raw_feat = 0;
  1698. if (!force_dma32) {
  1699. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1700. if (ok)
  1701. ha->raw_feat = GDT_64BIT;
  1702. }
  1703. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1704. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1705. if (!ok) {
  1706. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1707. ha->hanum, ha->status);
  1708. return 0;
  1709. }
  1710. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1711. /* set/get features raw service (scatter/gather) */
  1712. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1713. 0, 0)) {
  1714. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1715. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1716. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1717. ha->info));
  1718. ha->raw_feat |= (ushort)ha->info;
  1719. }
  1720. }
  1721. /* set/get features cache service (equal to raw service) */
  1722. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1723. SCATTER_GATHER,0)) {
  1724. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1725. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1726. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1727. ha->info));
  1728. ha->cache_feat |= (ushort)ha->info;
  1729. }
  1730. }
  1731. /* reserve drives for raw service */
  1732. if (reserve_mode != 0) {
  1733. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1734. reserve_mode == 1 ? 1 : 3, 0, 0);
  1735. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1736. ha->status));
  1737. }
  1738. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1739. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1740. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1741. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1742. reserve_list[i], reserve_list[i+1],
  1743. reserve_list[i+2], reserve_list[i+3]));
  1744. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1745. reserve_list[i+1], reserve_list[i+2] |
  1746. (reserve_list[i+3] << 8))) {
  1747. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1748. ha->hanum, ha->status);
  1749. }
  1750. }
  1751. }
  1752. /* Determine OEM string using IOCTL */
  1753. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1754. oemstr->params.ctl_version = 0x01;
  1755. oemstr->params.buffer_size = sizeof(oemstr->text);
  1756. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1757. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1758. sizeof(gdth_oem_str_ioctl))) {
  1759. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1760. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1761. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1762. /* Save the Host Drive inquiry data */
  1763. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1764. sizeof(ha->oem_name));
  1765. } else {
  1766. /* Old method, based on PCI ID */
  1767. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1768. printk("GDT-HA %d: Name: %s\n",
  1769. ha->hanum, ha->binfo.type_string);
  1770. if (ha->oem_id == OEM_ID_INTEL)
  1771. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1772. else
  1773. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1774. }
  1775. /* scanning for host drives */
  1776. for (i = 0; i < cdev_cnt; ++i)
  1777. gdth_analyse_hdrive(ha, i);
  1778. TRACE(("gdth_search_drives() OK\n"));
  1779. return 1;
  1780. }
  1781. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1782. {
  1783. ulong32 drv_cyls;
  1784. int drv_hds, drv_secs;
  1785. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1786. if (hdrive >= MAX_HDRIVES)
  1787. return 0;
  1788. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1789. return 0;
  1790. ha->hdr[hdrive].present = TRUE;
  1791. ha->hdr[hdrive].size = ha->info;
  1792. /* evaluate mapping (sectors per head, heads per cylinder) */
  1793. ha->hdr[hdrive].size &= ~SECS32;
  1794. if (ha->info2 == 0) {
  1795. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1796. } else {
  1797. drv_hds = ha->info2 & 0xff;
  1798. drv_secs = (ha->info2 >> 8) & 0xff;
  1799. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1800. }
  1801. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1802. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1803. /* round size */
  1804. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1805. if (ha->cache_feat & GDT_64BIT) {
  1806. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1807. && ha->info2 != 0) {
  1808. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1809. }
  1810. }
  1811. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1812. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1813. /* get informations about device */
  1814. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1815. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1816. hdrive,ha->info));
  1817. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1818. }
  1819. /* cluster info */
  1820. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1821. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1822. hdrive,ha->info));
  1823. if (!shared_access)
  1824. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1825. }
  1826. /* R/W attributes */
  1827. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1828. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1829. hdrive,ha->info));
  1830. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1831. }
  1832. return 1;
  1833. }
  1834. /* command queueing/sending functions */
  1835. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1836. {
  1837. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1838. register Scsi_Cmnd *pscp;
  1839. register Scsi_Cmnd *nscp;
  1840. ulong flags;
  1841. unchar b, t;
  1842. TRACE(("gdth_putq() priority %d\n",priority));
  1843. spin_lock_irqsave(&ha->smp_lock, flags);
  1844. if (!cmndinfo->internal_command) {
  1845. cmndinfo->priority = priority;
  1846. b = scp->device->channel;
  1847. t = scp->device->id;
  1848. if (priority >= DEFAULT_PRI) {
  1849. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1850. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1851. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1852. cmndinfo->timeout = gdth_update_timeout(scp, 0);
  1853. }
  1854. }
  1855. }
  1856. if (ha->req_first==NULL) {
  1857. ha->req_first = scp; /* queue was empty */
  1858. scp->SCp.ptr = NULL;
  1859. } else { /* queue not empty */
  1860. pscp = ha->req_first;
  1861. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1862. /* priority: 0-highest,..,0xff-lowest */
  1863. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1864. pscp = nscp;
  1865. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1866. }
  1867. pscp->SCp.ptr = (char *)scp;
  1868. scp->SCp.ptr = (char *)nscp;
  1869. }
  1870. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1871. #ifdef GDTH_STATISTICS
  1872. flags = 0;
  1873. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1874. ++flags;
  1875. if (max_rq < flags) {
  1876. max_rq = flags;
  1877. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1878. }
  1879. #endif
  1880. }
  1881. static void gdth_next(gdth_ha_str *ha)
  1882. {
  1883. register Scsi_Cmnd *pscp;
  1884. register Scsi_Cmnd *nscp;
  1885. unchar b, t, l, firsttime;
  1886. unchar this_cmd, next_cmd;
  1887. ulong flags = 0;
  1888. int cmd_index;
  1889. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1890. if (!gdth_polling)
  1891. spin_lock_irqsave(&ha->smp_lock, flags);
  1892. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1893. this_cmd = firsttime = TRUE;
  1894. next_cmd = gdth_polling ? FALSE:TRUE;
  1895. cmd_index = 0;
  1896. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1897. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1898. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1899. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1900. if (!nscp_cmndinfo->internal_command) {
  1901. b = nscp->device->channel;
  1902. t = nscp->device->id;
  1903. l = nscp->device->lun;
  1904. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1905. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1906. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1907. continue;
  1908. }
  1909. } else
  1910. b = t = l = 0;
  1911. if (firsttime) {
  1912. if (gdth_test_busy(ha)) { /* controller busy ? */
  1913. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1914. if (!gdth_polling) {
  1915. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1916. return;
  1917. }
  1918. while (gdth_test_busy(ha))
  1919. gdth_delay(1);
  1920. }
  1921. firsttime = FALSE;
  1922. }
  1923. if (!nscp_cmndinfo->internal_command) {
  1924. if (nscp_cmndinfo->phase == -1) {
  1925. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1926. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1927. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1928. b, t, l));
  1929. /* TEST_UNIT_READY -> set scan mode */
  1930. if ((ha->scan_mode & 0x0f) == 0) {
  1931. if (b == 0 && t == 0 && l == 0) {
  1932. ha->scan_mode |= 1;
  1933. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1934. }
  1935. } else if ((ha->scan_mode & 0x0f) == 1) {
  1936. if (b == 0 && ((t == 0 && l == 1) ||
  1937. (t == 1 && l == 0))) {
  1938. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1939. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1940. | SCSIRAWSERVICE;
  1941. ha->scan_mode = 0x12;
  1942. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1943. ha->scan_mode));
  1944. } else {
  1945. ha->scan_mode &= 0x10;
  1946. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1947. }
  1948. } else if (ha->scan_mode == 0x12) {
  1949. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1950. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1951. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1952. ha->scan_mode &= 0x10;
  1953. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1954. ha->scan_mode));
  1955. }
  1956. }
  1957. }
  1958. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1959. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1960. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1961. /* always GDT_CLUST_INFO! */
  1962. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1963. }
  1964. }
  1965. }
  1966. if (nscp_cmndinfo->OpCode != -1) {
  1967. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1968. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1969. this_cmd = FALSE;
  1970. next_cmd = FALSE;
  1971. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1972. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1973. this_cmd = FALSE;
  1974. next_cmd = FALSE;
  1975. } else {
  1976. memset((char*)nscp->sense_buffer,0,16);
  1977. nscp->sense_buffer[0] = 0x70;
  1978. nscp->sense_buffer[2] = NOT_READY;
  1979. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1980. if (!nscp_cmndinfo->wait_for_completion)
  1981. nscp_cmndinfo->wait_for_completion++;
  1982. else
  1983. gdth_scsi_done(nscp);
  1984. }
  1985. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1986. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1987. this_cmd = FALSE;
  1988. next_cmd = FALSE;
  1989. } else if (b != ha->virt_bus) {
  1990. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1991. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1992. this_cmd = FALSE;
  1993. else
  1994. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1995. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1996. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1997. nscp->cmnd[0], b, t, l));
  1998. nscp->result = DID_BAD_TARGET << 16;
  1999. if (!nscp_cmndinfo->wait_for_completion)
  2000. nscp_cmndinfo->wait_for_completion++;
  2001. else
  2002. gdth_scsi_done(nscp);
  2003. } else {
  2004. switch (nscp->cmnd[0]) {
  2005. case TEST_UNIT_READY:
  2006. case INQUIRY:
  2007. case REQUEST_SENSE:
  2008. case READ_CAPACITY:
  2009. case VERIFY:
  2010. case START_STOP:
  2011. case MODE_SENSE:
  2012. case SERVICE_ACTION_IN:
  2013. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2014. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2015. nscp->cmnd[4],nscp->cmnd[5]));
  2016. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2017. /* return UNIT_ATTENTION */
  2018. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2019. nscp->cmnd[0], t));
  2020. ha->hdr[t].media_changed = FALSE;
  2021. memset((char*)nscp->sense_buffer,0,16);
  2022. nscp->sense_buffer[0] = 0x70;
  2023. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2024. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2025. if (!nscp_cmndinfo->wait_for_completion)
  2026. nscp_cmndinfo->wait_for_completion++;
  2027. else
  2028. gdth_scsi_done(nscp);
  2029. } else if (gdth_internal_cache_cmd(ha, nscp))
  2030. gdth_scsi_done(nscp);
  2031. break;
  2032. case ALLOW_MEDIUM_REMOVAL:
  2033. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2034. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2035. nscp->cmnd[4],nscp->cmnd[5]));
  2036. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2037. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2038. nscp->result = DID_OK << 16;
  2039. nscp->sense_buffer[0] = 0;
  2040. if (!nscp_cmndinfo->wait_for_completion)
  2041. nscp_cmndinfo->wait_for_completion++;
  2042. else
  2043. gdth_scsi_done(nscp);
  2044. } else {
  2045. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2046. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2047. nscp->cmnd[4],nscp->cmnd[3]));
  2048. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2049. this_cmd = FALSE;
  2050. }
  2051. break;
  2052. case RESERVE:
  2053. case RELEASE:
  2054. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2055. "RESERVE" : "RELEASE"));
  2056. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2057. this_cmd = FALSE;
  2058. break;
  2059. case READ_6:
  2060. case WRITE_6:
  2061. case READ_10:
  2062. case WRITE_10:
  2063. case READ_16:
  2064. case WRITE_16:
  2065. if (ha->hdr[t].media_changed) {
  2066. /* return UNIT_ATTENTION */
  2067. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2068. nscp->cmnd[0], t));
  2069. ha->hdr[t].media_changed = FALSE;
  2070. memset((char*)nscp->sense_buffer,0,16);
  2071. nscp->sense_buffer[0] = 0x70;
  2072. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2073. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2074. if (!nscp_cmndinfo->wait_for_completion)
  2075. nscp_cmndinfo->wait_for_completion++;
  2076. else
  2077. gdth_scsi_done(nscp);
  2078. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2079. this_cmd = FALSE;
  2080. break;
  2081. default:
  2082. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2083. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2084. nscp->cmnd[4],nscp->cmnd[5]));
  2085. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2086. ha->hanum, nscp->cmnd[0]);
  2087. nscp->result = DID_ABORT << 16;
  2088. if (!nscp_cmndinfo->wait_for_completion)
  2089. nscp_cmndinfo->wait_for_completion++;
  2090. else
  2091. gdth_scsi_done(nscp);
  2092. break;
  2093. }
  2094. }
  2095. if (!this_cmd)
  2096. break;
  2097. if (nscp == ha->req_first)
  2098. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2099. else
  2100. pscp->SCp.ptr = nscp->SCp.ptr;
  2101. if (!next_cmd)
  2102. break;
  2103. }
  2104. if (ha->cmd_cnt > 0) {
  2105. gdth_release_event(ha);
  2106. }
  2107. if (!gdth_polling)
  2108. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2109. if (gdth_polling && ha->cmd_cnt > 0) {
  2110. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2111. printk("GDT-HA %d: Command %d timed out !\n",
  2112. ha->hanum, cmd_index);
  2113. }
  2114. }
  2115. /*
  2116. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2117. * buffers, kmap_atomic() as needed.
  2118. */
  2119. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2120. char *buffer, ushort count, int to_buffer)
  2121. {
  2122. ushort cpcount,i, max_sg = gdth_sg_count(scp);
  2123. ushort cpsum,cpnow;
  2124. struct scatterlist *sl;
  2125. char *address;
  2126. cpcount = min_t(ushort, count, gdth_bufflen(scp));
  2127. if (cpcount) {
  2128. cpsum=0;
  2129. scsi_for_each_sg(scp, sl, max_sg, i) {
  2130. unsigned long flags;
  2131. cpnow = (ushort)sl->length;
  2132. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2133. cpnow, cpsum, cpcount, gdth_bufflen(scp)));
  2134. if (cpsum+cpnow > cpcount)
  2135. cpnow = cpcount - cpsum;
  2136. cpsum += cpnow;
  2137. if (!sg_page(sl)) {
  2138. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2139. ha->hanum);
  2140. return;
  2141. }
  2142. local_irq_save(flags);
  2143. address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
  2144. if (to_buffer)
  2145. memcpy(buffer, address, cpnow);
  2146. else
  2147. memcpy(address, buffer, cpnow);
  2148. flush_dcache_page(sg_page(sl));
  2149. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2150. local_irq_restore(flags);
  2151. if (cpsum == cpcount)
  2152. break;
  2153. buffer += cpnow;
  2154. }
  2155. } else if (count) {
  2156. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2157. ha->hanum);
  2158. WARN_ON(1);
  2159. }
  2160. }
  2161. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2162. {
  2163. unchar t;
  2164. gdth_inq_data inq;
  2165. gdth_rdcap_data rdc;
  2166. gdth_sense_data sd;
  2167. gdth_modep_data mpd;
  2168. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2169. t = scp->device->id;
  2170. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2171. scp->cmnd[0],t));
  2172. scp->result = DID_OK << 16;
  2173. scp->sense_buffer[0] = 0;
  2174. switch (scp->cmnd[0]) {
  2175. case TEST_UNIT_READY:
  2176. case VERIFY:
  2177. case START_STOP:
  2178. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2179. break;
  2180. case INQUIRY:
  2181. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2182. t,ha->hdr[t].devtype));
  2183. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2184. /* you can here set all disks to removable, if you want to do
  2185. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2186. inq.modif_rmb = 0x00;
  2187. if ((ha->hdr[t].devtype & 1) ||
  2188. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2189. inq.modif_rmb = 0x80;
  2190. inq.version = 2;
  2191. inq.resp_aenc = 2;
  2192. inq.add_length= 32;
  2193. strcpy(inq.vendor,ha->oem_name);
  2194. sprintf(inq.product,"Host Drive #%02d",t);
  2195. strcpy(inq.revision," ");
  2196. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data), 0);
  2197. break;
  2198. case REQUEST_SENSE:
  2199. TRACE2(("Request sense hdrive %d\n",t));
  2200. sd.errorcode = 0x70;
  2201. sd.segno = 0x00;
  2202. sd.key = NO_SENSE;
  2203. sd.info = 0;
  2204. sd.add_length= 0;
  2205. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data), 0);
  2206. break;
  2207. case MODE_SENSE:
  2208. TRACE2(("Mode sense hdrive %d\n",t));
  2209. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2210. mpd.hd.data_length = sizeof(gdth_modep_data);
  2211. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2212. mpd.hd.bd_length = sizeof(mpd.bd);
  2213. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2214. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2215. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2216. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data), 0);
  2217. break;
  2218. case READ_CAPACITY:
  2219. TRACE2(("Read capacity hdrive %d\n",t));
  2220. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2221. rdc.last_block_no = 0xffffffff;
  2222. else
  2223. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2224. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2225. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data), 0);
  2226. break;
  2227. case SERVICE_ACTION_IN:
  2228. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2229. (ha->cache_feat & GDT_64BIT)) {
  2230. gdth_rdcap16_data rdc16;
  2231. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2232. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2233. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2234. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2235. sizeof(gdth_rdcap16_data), 0);
  2236. } else {
  2237. scp->result = DID_ABORT << 16;
  2238. }
  2239. break;
  2240. default:
  2241. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2242. break;
  2243. }
  2244. if (!cmndinfo->wait_for_completion)
  2245. cmndinfo->wait_for_completion++;
  2246. else
  2247. return 1;
  2248. return 0;
  2249. }
  2250. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2251. {
  2252. register gdth_cmd_str *cmdp;
  2253. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2254. ulong32 cnt, blockcnt;
  2255. ulong64 no, blockno;
  2256. int i, cmd_index, read_write, sgcnt, mode64;
  2257. cmdp = ha->pccb;
  2258. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2259. scp->cmnd[0],scp->cmd_len,hdrive));
  2260. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2261. return 0;
  2262. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2263. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2264. not required, should not occur due to error return on
  2265. READ_CAPACITY_16 */
  2266. cmdp->Service = CACHESERVICE;
  2267. cmdp->RequestBuffer = scp;
  2268. /* search free command index */
  2269. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2270. TRACE(("GDT: No free command index found\n"));
  2271. return 0;
  2272. }
  2273. /* if it's the first command, set command semaphore */
  2274. if (ha->cmd_cnt == 0)
  2275. gdth_set_sema0(ha);
  2276. /* fill command */
  2277. read_write = 0;
  2278. if (cmndinfo->OpCode != -1)
  2279. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2280. else if (scp->cmnd[0] == RESERVE)
  2281. cmdp->OpCode = GDT_RESERVE_DRV;
  2282. else if (scp->cmnd[0] == RELEASE)
  2283. cmdp->OpCode = GDT_RELEASE_DRV;
  2284. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2285. if (scp->cmnd[4] & 1) /* prevent ? */
  2286. cmdp->OpCode = GDT_MOUNT;
  2287. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2288. cmdp->OpCode = GDT_UNMOUNT;
  2289. else
  2290. cmdp->OpCode = GDT_FLUSH;
  2291. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2292. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2293. ) {
  2294. read_write = 1;
  2295. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2296. (ha->cache_feat & GDT_WR_THROUGH)))
  2297. cmdp->OpCode = GDT_WRITE_THR;
  2298. else
  2299. cmdp->OpCode = GDT_WRITE;
  2300. } else {
  2301. read_write = 2;
  2302. cmdp->OpCode = GDT_READ;
  2303. }
  2304. cmdp->BoardNode = LOCALBOARD;
  2305. if (mode64) {
  2306. cmdp->u.cache64.DeviceNo = hdrive;
  2307. cmdp->u.cache64.BlockNo = 1;
  2308. cmdp->u.cache64.sg_canz = 0;
  2309. } else {
  2310. cmdp->u.cache.DeviceNo = hdrive;
  2311. cmdp->u.cache.BlockNo = 1;
  2312. cmdp->u.cache.sg_canz = 0;
  2313. }
  2314. if (read_write) {
  2315. if (scp->cmd_len == 16) {
  2316. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2317. blockno = be64_to_cpu(no);
  2318. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2319. blockcnt = be32_to_cpu(cnt);
  2320. } else if (scp->cmd_len == 10) {
  2321. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2322. blockno = be32_to_cpu(no);
  2323. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2324. blockcnt = be16_to_cpu(cnt);
  2325. } else {
  2326. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2327. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2328. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2329. }
  2330. if (mode64) {
  2331. cmdp->u.cache64.BlockNo = blockno;
  2332. cmdp->u.cache64.BlockCnt = blockcnt;
  2333. } else {
  2334. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2335. cmdp->u.cache.BlockCnt = blockcnt;
  2336. }
  2337. if (gdth_bufflen(scp)) {
  2338. cmndinfo->dma_dir = (read_write == 1 ?
  2339. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2340. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2341. cmndinfo->dma_dir);
  2342. if (mode64) {
  2343. struct scatterlist *sl;
  2344. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2345. cmdp->u.cache64.sg_canz = sgcnt;
  2346. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2347. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2348. #ifdef GDTH_DMA_STATISTICS
  2349. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2350. ha->dma64_cnt++;
  2351. else
  2352. ha->dma32_cnt++;
  2353. #endif
  2354. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2355. }
  2356. } else {
  2357. struct scatterlist *sl;
  2358. cmdp->u.cache.DestAddr= 0xffffffff;
  2359. cmdp->u.cache.sg_canz = sgcnt;
  2360. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2361. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2362. #ifdef GDTH_DMA_STATISTICS
  2363. ha->dma32_cnt++;
  2364. #endif
  2365. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2366. }
  2367. }
  2368. #ifdef GDTH_STATISTICS
  2369. if (max_sg < (ulong32)sgcnt) {
  2370. max_sg = (ulong32)sgcnt;
  2371. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2372. }
  2373. #endif
  2374. }
  2375. }
  2376. /* evaluate command size, check space */
  2377. if (mode64) {
  2378. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2379. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2380. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2381. cmdp->u.cache64.sg_lst[0].sg_len));
  2382. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2383. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2384. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2385. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2386. } else {
  2387. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2388. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2389. cmdp->u.cache.sg_lst[0].sg_ptr,
  2390. cmdp->u.cache.sg_lst[0].sg_len));
  2391. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2392. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2393. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2394. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2395. }
  2396. if (ha->cmd_len & 3)
  2397. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2398. if (ha->cmd_cnt > 0) {
  2399. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2400. ha->ic_all_size) {
  2401. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2402. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2403. return 0;
  2404. }
  2405. }
  2406. /* copy command */
  2407. gdth_copy_command(ha);
  2408. return cmd_index;
  2409. }
  2410. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2411. {
  2412. register gdth_cmd_str *cmdp;
  2413. ushort i;
  2414. dma_addr_t sense_paddr;
  2415. int cmd_index, sgcnt, mode64;
  2416. unchar t,l;
  2417. struct page *page;
  2418. ulong offset;
  2419. struct gdth_cmndinfo *cmndinfo;
  2420. t = scp->device->id;
  2421. l = scp->device->lun;
  2422. cmdp = ha->pccb;
  2423. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2424. scp->cmnd[0],b,t,l));
  2425. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2426. return 0;
  2427. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2428. cmdp->Service = SCSIRAWSERVICE;
  2429. cmdp->RequestBuffer = scp;
  2430. /* search free command index */
  2431. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2432. TRACE(("GDT: No free command index found\n"));
  2433. return 0;
  2434. }
  2435. /* if it's the first command, set command semaphore */
  2436. if (ha->cmd_cnt == 0)
  2437. gdth_set_sema0(ha);
  2438. cmndinfo = gdth_cmnd_priv(scp);
  2439. /* fill command */
  2440. if (cmndinfo->OpCode != -1) {
  2441. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2442. cmdp->BoardNode = LOCALBOARD;
  2443. if (mode64) {
  2444. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2445. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2446. cmdp->OpCode, cmdp->u.raw64.direction));
  2447. /* evaluate command size */
  2448. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2449. } else {
  2450. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2451. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2452. cmdp->OpCode, cmdp->u.raw.direction));
  2453. /* evaluate command size */
  2454. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2455. }
  2456. } else {
  2457. page = virt_to_page(scp->sense_buffer);
  2458. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2459. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2460. 16,PCI_DMA_FROMDEVICE);
  2461. cmndinfo->sense_paddr = sense_paddr;
  2462. cmdp->OpCode = GDT_WRITE; /* always */
  2463. cmdp->BoardNode = LOCALBOARD;
  2464. if (mode64) {
  2465. cmdp->u.raw64.reserved = 0;
  2466. cmdp->u.raw64.mdisc_time = 0;
  2467. cmdp->u.raw64.mcon_time = 0;
  2468. cmdp->u.raw64.clen = scp->cmd_len;
  2469. cmdp->u.raw64.target = t;
  2470. cmdp->u.raw64.lun = l;
  2471. cmdp->u.raw64.bus = b;
  2472. cmdp->u.raw64.priority = 0;
  2473. cmdp->u.raw64.sdlen = gdth_bufflen(scp);
  2474. cmdp->u.raw64.sense_len = 16;
  2475. cmdp->u.raw64.sense_data = sense_paddr;
  2476. cmdp->u.raw64.direction =
  2477. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2478. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2479. cmdp->u.raw64.sg_ranz = 0;
  2480. } else {
  2481. cmdp->u.raw.reserved = 0;
  2482. cmdp->u.raw.mdisc_time = 0;
  2483. cmdp->u.raw.mcon_time = 0;
  2484. cmdp->u.raw.clen = scp->cmd_len;
  2485. cmdp->u.raw.target = t;
  2486. cmdp->u.raw.lun = l;
  2487. cmdp->u.raw.bus = b;
  2488. cmdp->u.raw.priority = 0;
  2489. cmdp->u.raw.link_p = 0;
  2490. cmdp->u.raw.sdlen = gdth_bufflen(scp);
  2491. cmdp->u.raw.sense_len = 16;
  2492. cmdp->u.raw.sense_data = sense_paddr;
  2493. cmdp->u.raw.direction =
  2494. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2495. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2496. cmdp->u.raw.sg_ranz = 0;
  2497. }
  2498. if (gdth_bufflen(scp)) {
  2499. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2500. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2501. cmndinfo->dma_dir);
  2502. if (mode64) {
  2503. struct scatterlist *sl;
  2504. cmdp->u.raw64.sdata = (ulong64)-1;
  2505. cmdp->u.raw64.sg_ranz = sgcnt;
  2506. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2507. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2508. #ifdef GDTH_DMA_STATISTICS
  2509. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2510. ha->dma64_cnt++;
  2511. else
  2512. ha->dma32_cnt++;
  2513. #endif
  2514. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2515. }
  2516. } else {
  2517. struct scatterlist *sl;
  2518. cmdp->u.raw.sdata = 0xffffffff;
  2519. cmdp->u.raw.sg_ranz = sgcnt;
  2520. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2521. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2522. #ifdef GDTH_DMA_STATISTICS
  2523. ha->dma32_cnt++;
  2524. #endif
  2525. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2526. }
  2527. }
  2528. #ifdef GDTH_STATISTICS
  2529. if (max_sg < sgcnt) {
  2530. max_sg = sgcnt;
  2531. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2532. }
  2533. #endif
  2534. }
  2535. if (mode64) {
  2536. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2537. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2538. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2539. cmdp->u.raw64.sg_lst[0].sg_len));
  2540. /* evaluate command size */
  2541. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2542. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2543. } else {
  2544. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2545. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2546. cmdp->u.raw.sg_lst[0].sg_ptr,
  2547. cmdp->u.raw.sg_lst[0].sg_len));
  2548. /* evaluate command size */
  2549. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2550. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2551. }
  2552. }
  2553. /* check space */
  2554. if (ha->cmd_len & 3)
  2555. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2556. if (ha->cmd_cnt > 0) {
  2557. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2558. ha->ic_all_size) {
  2559. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2560. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2561. return 0;
  2562. }
  2563. }
  2564. /* copy command */
  2565. gdth_copy_command(ha);
  2566. return cmd_index;
  2567. }
  2568. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2569. {
  2570. register gdth_cmd_str *cmdp;
  2571. int cmd_index;
  2572. cmdp= ha->pccb;
  2573. TRACE2(("gdth_special_cmd(): "));
  2574. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2575. return 0;
  2576. gdth_copy_internal_data(ha, scp, (char *)cmdp, sizeof(gdth_cmd_str), 1);
  2577. cmdp->RequestBuffer = scp;
  2578. /* search free command index */
  2579. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2580. TRACE(("GDT: No free command index found\n"));
  2581. return 0;
  2582. }
  2583. /* if it's the first command, set command semaphore */
  2584. if (ha->cmd_cnt == 0)
  2585. gdth_set_sema0(ha);
  2586. /* evaluate command size, check space */
  2587. if (cmdp->OpCode == GDT_IOCTL) {
  2588. TRACE2(("IOCTL\n"));
  2589. ha->cmd_len =
  2590. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2591. } else if (cmdp->Service == CACHESERVICE) {
  2592. TRACE2(("cache command %d\n",cmdp->OpCode));
  2593. if (ha->cache_feat & GDT_64BIT)
  2594. ha->cmd_len =
  2595. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2596. else
  2597. ha->cmd_len =
  2598. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2599. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2600. TRACE2(("raw command %d\n",cmdp->OpCode));
  2601. if (ha->raw_feat & GDT_64BIT)
  2602. ha->cmd_len =
  2603. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2604. else
  2605. ha->cmd_len =
  2606. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2607. }
  2608. if (ha->cmd_len & 3)
  2609. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2610. if (ha->cmd_cnt > 0) {
  2611. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2612. ha->ic_all_size) {
  2613. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2614. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2615. return 0;
  2616. }
  2617. }
  2618. /* copy command */
  2619. gdth_copy_command(ha);
  2620. return cmd_index;
  2621. }
  2622. /* Controller event handling functions */
  2623. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2624. ushort idx, gdth_evt_data *evt)
  2625. {
  2626. gdth_evt_str *e;
  2627. struct timeval tv;
  2628. /* no GDTH_LOCK_HA() ! */
  2629. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2630. if (source == 0) /* no source -> no event */
  2631. return NULL;
  2632. if (ebuffer[elastidx].event_source == source &&
  2633. ebuffer[elastidx].event_idx == idx &&
  2634. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2635. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2636. (char *)&evt->eu, evt->size)) ||
  2637. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2638. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2639. (char *)&evt->event_string)))) {
  2640. e = &ebuffer[elastidx];
  2641. do_gettimeofday(&tv);
  2642. e->last_stamp = tv.tv_sec;
  2643. ++e->same_count;
  2644. } else {
  2645. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2646. ++elastidx;
  2647. if (elastidx == MAX_EVENTS)
  2648. elastidx = 0;
  2649. if (elastidx == eoldidx) { /* reached mark ? */
  2650. ++eoldidx;
  2651. if (eoldidx == MAX_EVENTS)
  2652. eoldidx = 0;
  2653. }
  2654. }
  2655. e = &ebuffer[elastidx];
  2656. e->event_source = source;
  2657. e->event_idx = idx;
  2658. do_gettimeofday(&tv);
  2659. e->first_stamp = e->last_stamp = tv.tv_sec;
  2660. e->same_count = 1;
  2661. e->event_data = *evt;
  2662. e->application = 0;
  2663. }
  2664. return e;
  2665. }
  2666. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2667. {
  2668. gdth_evt_str *e;
  2669. int eindex;
  2670. ulong flags;
  2671. TRACE2(("gdth_read_event() handle %d\n", handle));
  2672. spin_lock_irqsave(&ha->smp_lock, flags);
  2673. if (handle == -1)
  2674. eindex = eoldidx;
  2675. else
  2676. eindex = handle;
  2677. estr->event_source = 0;
  2678. if (eindex >= MAX_EVENTS) {
  2679. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2680. return eindex;
  2681. }
  2682. e = &ebuffer[eindex];
  2683. if (e->event_source != 0) {
  2684. if (eindex != elastidx) {
  2685. if (++eindex == MAX_EVENTS)
  2686. eindex = 0;
  2687. } else {
  2688. eindex = -1;
  2689. }
  2690. memcpy(estr, e, sizeof(gdth_evt_str));
  2691. }
  2692. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2693. return eindex;
  2694. }
  2695. static void gdth_readapp_event(gdth_ha_str *ha,
  2696. unchar application, gdth_evt_str *estr)
  2697. {
  2698. gdth_evt_str *e;
  2699. int eindex;
  2700. ulong flags;
  2701. unchar found = FALSE;
  2702. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2703. spin_lock_irqsave(&ha->smp_lock, flags);
  2704. eindex = eoldidx;
  2705. for (;;) {
  2706. e = &ebuffer[eindex];
  2707. if (e->event_source == 0)
  2708. break;
  2709. if ((e->application & application) == 0) {
  2710. e->application |= application;
  2711. found = TRUE;
  2712. break;
  2713. }
  2714. if (eindex == elastidx)
  2715. break;
  2716. if (++eindex == MAX_EVENTS)
  2717. eindex = 0;
  2718. }
  2719. if (found)
  2720. memcpy(estr, e, sizeof(gdth_evt_str));
  2721. else
  2722. estr->event_source = 0;
  2723. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2724. }
  2725. static void gdth_clear_events(void)
  2726. {
  2727. TRACE(("gdth_clear_events()"));
  2728. eoldidx = elastidx = 0;
  2729. ebuffer[0].event_source = 0;
  2730. }
  2731. /* SCSI interface functions */
  2732. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2733. int gdth_from_wait, int* pIndex)
  2734. {
  2735. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2736. gdt6_dpram_str __iomem *dp6_ptr;
  2737. gdt2_dpram_str __iomem *dp2_ptr;
  2738. Scsi_Cmnd *scp;
  2739. int rval, i;
  2740. unchar IStatus;
  2741. ushort Service;
  2742. ulong flags = 0;
  2743. #ifdef INT_COAL
  2744. int coalesced = FALSE;
  2745. int next = FALSE;
  2746. gdth_coal_status *pcs = NULL;
  2747. int act_int_coal = 0;
  2748. #endif
  2749. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2750. /* if polling and not from gdth_wait() -> return */
  2751. if (gdth_polling) {
  2752. if (!gdth_from_wait) {
  2753. return IRQ_HANDLED;
  2754. }
  2755. }
  2756. if (!gdth_polling)
  2757. spin_lock_irqsave(&ha->smp_lock, flags);
  2758. /* search controller */
  2759. IStatus = gdth_get_status(ha);
  2760. if (IStatus == 0) {
  2761. /* spurious interrupt */
  2762. if (!gdth_polling)
  2763. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2764. return IRQ_HANDLED;
  2765. }
  2766. #ifdef GDTH_STATISTICS
  2767. ++act_ints;
  2768. #endif
  2769. #ifdef INT_COAL
  2770. /* See if the fw is returning coalesced status */
  2771. if (IStatus == COALINDEX) {
  2772. /* Coalesced status. Setup the initial status
  2773. buffer pointer and flags */
  2774. pcs = ha->coal_stat;
  2775. coalesced = TRUE;
  2776. next = TRUE;
  2777. }
  2778. do {
  2779. if (coalesced) {
  2780. /* For coalesced requests all status
  2781. information is found in the status buffer */
  2782. IStatus = (unchar)(pcs->status & 0xff);
  2783. }
  2784. #endif
  2785. if (ha->type == GDT_EISA) {
  2786. if (IStatus & 0x80) { /* error flag */
  2787. IStatus &= ~0x80;
  2788. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2789. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2790. } else /* no error */
  2791. ha->status = S_OK;
  2792. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2793. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2794. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2795. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2796. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2797. } else if (ha->type == GDT_ISA) {
  2798. dp2_ptr = ha->brd;
  2799. if (IStatus & 0x80) { /* error flag */
  2800. IStatus &= ~0x80;
  2801. ha->status = readw(&dp2_ptr->u.ic.Status);
  2802. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2803. } else /* no error */
  2804. ha->status = S_OK;
  2805. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2806. ha->service = readw(&dp2_ptr->u.ic.Service);
  2807. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2808. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2809. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2810. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2811. } else if (ha->type == GDT_PCI) {
  2812. dp6_ptr = ha->brd;
  2813. if (IStatus & 0x80) { /* error flag */
  2814. IStatus &= ~0x80;
  2815. ha->status = readw(&dp6_ptr->u.ic.Status);
  2816. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2817. } else /* no error */
  2818. ha->status = S_OK;
  2819. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2820. ha->service = readw(&dp6_ptr->u.ic.Service);
  2821. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2822. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2823. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2824. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2825. } else if (ha->type == GDT_PCINEW) {
  2826. if (IStatus & 0x80) { /* error flag */
  2827. IStatus &= ~0x80;
  2828. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2829. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2830. } else
  2831. ha->status = S_OK;
  2832. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2833. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2834. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2835. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2836. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2837. } else if (ha->type == GDT_PCIMPR) {
  2838. dp6m_ptr = ha->brd;
  2839. if (IStatus & 0x80) { /* error flag */
  2840. IStatus &= ~0x80;
  2841. #ifdef INT_COAL
  2842. if (coalesced)
  2843. ha->status = pcs->ext_status & 0xffff;
  2844. else
  2845. #endif
  2846. ha->status = readw(&dp6m_ptr->i960r.status);
  2847. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2848. } else /* no error */
  2849. ha->status = S_OK;
  2850. #ifdef INT_COAL
  2851. /* get information */
  2852. if (coalesced) {
  2853. ha->info = pcs->info0;
  2854. ha->info2 = pcs->info1;
  2855. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2856. } else
  2857. #endif
  2858. {
  2859. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2860. ha->service = readw(&dp6m_ptr->i960r.service);
  2861. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2862. }
  2863. /* event string */
  2864. if (IStatus == ASYNCINDEX) {
  2865. if (ha->service != SCREENSERVICE &&
  2866. (ha->fw_vers & 0xff) >= 0x1a) {
  2867. ha->dvr.severity = readb
  2868. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2869. for (i = 0; i < 256; ++i) {
  2870. ha->dvr.event_string[i] = readb
  2871. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2872. if (ha->dvr.event_string[i] == 0)
  2873. break;
  2874. }
  2875. }
  2876. }
  2877. #ifdef INT_COAL
  2878. /* Make sure that non coalesced interrupts get cleared
  2879. before being handled by gdth_async_event/gdth_sync_event */
  2880. if (!coalesced)
  2881. #endif
  2882. {
  2883. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2884. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2885. }
  2886. } else {
  2887. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2888. if (!gdth_polling)
  2889. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2890. return IRQ_HANDLED;
  2891. }
  2892. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2893. IStatus,ha->status,ha->info));
  2894. if (gdth_from_wait) {
  2895. *pIndex = (int)IStatus;
  2896. }
  2897. if (IStatus == ASYNCINDEX) {
  2898. TRACE2(("gdth_interrupt() async. event\n"));
  2899. gdth_async_event(ha);
  2900. if (!gdth_polling)
  2901. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2902. gdth_next(ha);
  2903. return IRQ_HANDLED;
  2904. }
  2905. if (IStatus == SPEZINDEX) {
  2906. TRACE2(("Service unknown or not initialized !\n"));
  2907. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2908. ha->dvr.eu.driver.ionode = ha->hanum;
  2909. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2910. if (!gdth_polling)
  2911. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2912. return IRQ_HANDLED;
  2913. }
  2914. scp = ha->cmd_tab[IStatus-2].cmnd;
  2915. Service = ha->cmd_tab[IStatus-2].service;
  2916. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2917. if (scp == UNUSED_CMND) {
  2918. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2919. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2920. ha->dvr.eu.driver.ionode = ha->hanum;
  2921. ha->dvr.eu.driver.index = IStatus;
  2922. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2923. if (!gdth_polling)
  2924. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2925. return IRQ_HANDLED;
  2926. }
  2927. if (scp == INTERNAL_CMND) {
  2928. TRACE(("gdth_interrupt() answer to internal command\n"));
  2929. if (!gdth_polling)
  2930. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2931. return IRQ_HANDLED;
  2932. }
  2933. TRACE(("gdth_interrupt() sync. status\n"));
  2934. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2935. if (!gdth_polling)
  2936. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2937. if (rval == 2) {
  2938. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2939. } else if (rval == 1) {
  2940. gdth_scsi_done(scp);
  2941. }
  2942. #ifdef INT_COAL
  2943. if (coalesced) {
  2944. /* go to the next status in the status buffer */
  2945. ++pcs;
  2946. #ifdef GDTH_STATISTICS
  2947. ++act_int_coal;
  2948. if (act_int_coal > max_int_coal) {
  2949. max_int_coal = act_int_coal;
  2950. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2951. }
  2952. #endif
  2953. /* see if there is another status */
  2954. if (pcs->status == 0)
  2955. /* Stop the coalesce loop */
  2956. next = FALSE;
  2957. }
  2958. } while (next);
  2959. /* coalescing only for new GDT_PCIMPR controllers available */
  2960. if (ha->type == GDT_PCIMPR && coalesced) {
  2961. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2962. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2963. }
  2964. #endif
  2965. gdth_next(ha);
  2966. return IRQ_HANDLED;
  2967. }
  2968. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2969. {
  2970. gdth_ha_str *ha = dev_id;
  2971. return __gdth_interrupt(ha, false, NULL);
  2972. }
  2973. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2974. Scsi_Cmnd *scp)
  2975. {
  2976. gdth_msg_str *msg;
  2977. gdth_cmd_str *cmdp;
  2978. unchar b, t;
  2979. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2980. cmdp = ha->pccb;
  2981. TRACE(("gdth_sync_event() serv %d status %d\n",
  2982. service,ha->status));
  2983. if (service == SCREENSERVICE) {
  2984. msg = ha->pmsg;
  2985. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2986. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2987. if (msg->msg_len > MSGLEN+1)
  2988. msg->msg_len = MSGLEN+1;
  2989. if (msg->msg_len)
  2990. if (!(msg->msg_answer && msg->msg_ext)) {
  2991. msg->msg_text[msg->msg_len] = '\0';
  2992. printk("%s",msg->msg_text);
  2993. }
  2994. if (msg->msg_ext && !msg->msg_answer) {
  2995. while (gdth_test_busy(ha))
  2996. gdth_delay(0);
  2997. cmdp->Service = SCREENSERVICE;
  2998. cmdp->RequestBuffer = SCREEN_CMND;
  2999. gdth_get_cmd_index(ha);
  3000. gdth_set_sema0(ha);
  3001. cmdp->OpCode = GDT_READ;
  3002. cmdp->BoardNode = LOCALBOARD;
  3003. cmdp->u.screen.reserved = 0;
  3004. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3005. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3006. ha->cmd_offs_dpmem = 0;
  3007. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3008. + sizeof(ulong64);
  3009. ha->cmd_cnt = 0;
  3010. gdth_copy_command(ha);
  3011. gdth_release_event(ha);
  3012. return 0;
  3013. }
  3014. if (msg->msg_answer && msg->msg_alen) {
  3015. /* default answers (getchar() not possible) */
  3016. if (msg->msg_alen == 1) {
  3017. msg->msg_alen = 0;
  3018. msg->msg_len = 1;
  3019. msg->msg_text[0] = 0;
  3020. } else {
  3021. msg->msg_alen -= 2;
  3022. msg->msg_len = 2;
  3023. msg->msg_text[0] = 1;
  3024. msg->msg_text[1] = 0;
  3025. }
  3026. msg->msg_ext = 0;
  3027. msg->msg_answer = 0;
  3028. while (gdth_test_busy(ha))
  3029. gdth_delay(0);
  3030. cmdp->Service = SCREENSERVICE;
  3031. cmdp->RequestBuffer = SCREEN_CMND;
  3032. gdth_get_cmd_index(ha);
  3033. gdth_set_sema0(ha);
  3034. cmdp->OpCode = GDT_WRITE;
  3035. cmdp->BoardNode = LOCALBOARD;
  3036. cmdp->u.screen.reserved = 0;
  3037. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3038. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3039. ha->cmd_offs_dpmem = 0;
  3040. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3041. + sizeof(ulong64);
  3042. ha->cmd_cnt = 0;
  3043. gdth_copy_command(ha);
  3044. gdth_release_event(ha);
  3045. return 0;
  3046. }
  3047. printk("\n");
  3048. } else {
  3049. b = scp->device->channel;
  3050. t = scp->device->id;
  3051. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  3052. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3053. }
  3054. /* cache or raw service */
  3055. if (ha->status == S_BSY) {
  3056. TRACE2(("Controller busy -> retry !\n"));
  3057. if (cmndinfo->OpCode == GDT_MOUNT)
  3058. cmndinfo->OpCode = GDT_CLUST_INFO;
  3059. /* retry */
  3060. return 2;
  3061. }
  3062. if (gdth_bufflen(scp))
  3063. pci_unmap_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  3064. cmndinfo->dma_dir);
  3065. if (cmndinfo->sense_paddr)
  3066. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3067. PCI_DMA_FROMDEVICE);
  3068. if (ha->status == S_OK) {
  3069. cmndinfo->status = S_OK;
  3070. cmndinfo->info = ha->info;
  3071. if (cmndinfo->OpCode != -1) {
  3072. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3073. cmndinfo->OpCode));
  3074. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3075. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3076. ha->hdr[t].cluster_type = (unchar)ha->info;
  3077. if (!(ha->hdr[t].cluster_type &
  3078. CLUSTER_MOUNTED)) {
  3079. /* NOT MOUNTED -> MOUNT */
  3080. cmndinfo->OpCode = GDT_MOUNT;
  3081. if (ha->hdr[t].cluster_type &
  3082. CLUSTER_RESERVED) {
  3083. /* cluster drive RESERVED (on the other node) */
  3084. cmndinfo->phase = -2; /* reservation conflict */
  3085. }
  3086. } else {
  3087. cmndinfo->OpCode = -1;
  3088. }
  3089. } else {
  3090. if (cmndinfo->OpCode == GDT_MOUNT) {
  3091. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3092. ha->hdr[t].media_changed = TRUE;
  3093. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3094. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3095. ha->hdr[t].media_changed = TRUE;
  3096. }
  3097. cmndinfo->OpCode = -1;
  3098. }
  3099. /* retry */
  3100. cmndinfo->priority = HIGH_PRI;
  3101. return 2;
  3102. } else {
  3103. /* RESERVE/RELEASE ? */
  3104. if (scp->cmnd[0] == RESERVE) {
  3105. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3106. } else if (scp->cmnd[0] == RELEASE) {
  3107. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3108. }
  3109. scp->result = DID_OK << 16;
  3110. scp->sense_buffer[0] = 0;
  3111. }
  3112. } else {
  3113. cmndinfo->status = ha->status;
  3114. cmndinfo->info = ha->info;
  3115. if (cmndinfo->OpCode != -1) {
  3116. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3117. cmndinfo->OpCode, ha->status));
  3118. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3119. cmndinfo->OpCode == GDT_SCAN_END) {
  3120. cmndinfo->OpCode = -1;
  3121. /* retry */
  3122. cmndinfo->priority = HIGH_PRI;
  3123. return 2;
  3124. }
  3125. memset((char*)scp->sense_buffer,0,16);
  3126. scp->sense_buffer[0] = 0x70;
  3127. scp->sense_buffer[2] = NOT_READY;
  3128. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3129. } else if (service == CACHESERVICE) {
  3130. if (ha->status == S_CACHE_UNKNOWN &&
  3131. (ha->hdr[t].cluster_type &
  3132. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3133. /* bus reset -> force GDT_CLUST_INFO */
  3134. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3135. }
  3136. memset((char*)scp->sense_buffer,0,16);
  3137. if (ha->status == (ushort)S_CACHE_RESERV) {
  3138. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3139. } else {
  3140. scp->sense_buffer[0] = 0x70;
  3141. scp->sense_buffer[2] = NOT_READY;
  3142. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3143. }
  3144. if (!cmndinfo->internal_command) {
  3145. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3146. ha->dvr.eu.sync.ionode = ha->hanum;
  3147. ha->dvr.eu.sync.service = service;
  3148. ha->dvr.eu.sync.status = ha->status;
  3149. ha->dvr.eu.sync.info = ha->info;
  3150. ha->dvr.eu.sync.hostdrive = t;
  3151. if (ha->status >= 0x8000)
  3152. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3153. else
  3154. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3155. }
  3156. } else {
  3157. /* sense buffer filled from controller firmware (DMA) */
  3158. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3159. scp->result = DID_BAD_TARGET << 16;
  3160. } else {
  3161. scp->result = (DID_OK << 16) | ha->info;
  3162. }
  3163. }
  3164. }
  3165. if (!cmndinfo->wait_for_completion)
  3166. cmndinfo->wait_for_completion++;
  3167. else
  3168. return 1;
  3169. }
  3170. return 0;
  3171. }
  3172. static char *async_cache_tab[] = {
  3173. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3174. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3175. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3176. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3177. /* 2*/ "\005\000\002\006\004"
  3178. "GDT HA %u, Host Drive %lu not ready",
  3179. /* 3*/ "\005\000\002\006\004"
  3180. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3181. /* 4*/ "\005\000\002\006\004"
  3182. "GDT HA %u, mirror update on Host Drive %lu failed",
  3183. /* 5*/ "\005\000\002\006\004"
  3184. "GDT HA %u, Mirror Drive %lu failed",
  3185. /* 6*/ "\005\000\002\006\004"
  3186. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3187. /* 7*/ "\005\000\002\006\004"
  3188. "GDT HA %u, Host Drive %lu write protected",
  3189. /* 8*/ "\005\000\002\006\004"
  3190. "GDT HA %u, media changed in Host Drive %lu",
  3191. /* 9*/ "\005\000\002\006\004"
  3192. "GDT HA %u, Host Drive %lu is offline",
  3193. /*10*/ "\005\000\002\006\004"
  3194. "GDT HA %u, media change of Mirror Drive %lu",
  3195. /*11*/ "\005\000\002\006\004"
  3196. "GDT HA %u, Mirror Drive %lu is write protected",
  3197. /*12*/ "\005\000\002\006\004"
  3198. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3199. /*13*/ "\007\000\002\006\002\010\002"
  3200. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3201. /*14*/ "\005\000\002\006\002"
  3202. "GDT HA %u, Array Drive %u: FAIL state entered",
  3203. /*15*/ "\005\000\002\006\002"
  3204. "GDT HA %u, Array Drive %u: error",
  3205. /*16*/ "\007\000\002\006\002\010\002"
  3206. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3207. /*17*/ "\005\000\002\006\002"
  3208. "GDT HA %u, Array Drive %u: parity build failed",
  3209. /*18*/ "\005\000\002\006\002"
  3210. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3211. /*19*/ "\005\000\002\010\002"
  3212. "GDT HA %u, Test of Hot Fix %u failed",
  3213. /*20*/ "\005\000\002\006\002"
  3214. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3215. /*21*/ "\005\000\002\006\002"
  3216. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3217. /*22*/ "\007\000\002\006\002\010\002"
  3218. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3219. /*23*/ "\005\000\002\006\002"
  3220. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3221. /*24*/ "\005\000\002\010\002"
  3222. "GDT HA %u, mirror update on Cache Drive %u completed",
  3223. /*25*/ "\005\000\002\010\002"
  3224. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3225. /*26*/ "\005\000\002\006\002"
  3226. "GDT HA %u, Array Drive %u: drive rebuild started",
  3227. /*27*/ "\005\000\002\012\001"
  3228. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3229. /*28*/ "\005\000\002\012\001"
  3230. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3231. /*29*/ "\007\000\002\012\001\013\001"
  3232. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3233. /*30*/ "\007\000\002\012\001\013\001"
  3234. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3235. /*31*/ "\007\000\002\012\001\013\001"
  3236. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3237. /*32*/ "\007\000\002\012\001\013\001"
  3238. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3239. /*33*/ "\007\000\002\012\001\013\001"
  3240. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3241. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3242. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3243. /*35*/ "\007\000\002\012\001\013\001"
  3244. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3245. /*36*/ "\007\000\002\012\001\013\001"
  3246. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3247. /*37*/ "\007\000\002\012\001\006\004"
  3248. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3249. /*38*/ "\007\000\002\012\001\013\001"
  3250. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3251. /*39*/ "\007\000\002\012\001\013\001"
  3252. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3253. /*40*/ "\007\000\002\012\001\013\001"
  3254. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3255. /*41*/ "\007\000\002\012\001\013\001"
  3256. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3257. /*42*/ "\005\000\002\006\002"
  3258. "GDT HA %u, Array Drive %u: drive build started",
  3259. /*43*/ "\003\000\002"
  3260. "GDT HA %u, DRAM parity error detected",
  3261. /*44*/ "\005\000\002\006\002"
  3262. "GDT HA %u, Mirror Drive %u: update started",
  3263. /*45*/ "\007\000\002\006\002\010\002"
  3264. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3265. /*46*/ "\005\000\002\006\002"
  3266. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3267. /*47*/ "\005\000\002\006\002"
  3268. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3269. /*48*/ "\005\000\002\006\002"
  3270. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3271. /*49*/ "\005\000\002\006\002"
  3272. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3273. /*50*/ "\007\000\002\012\001\013\001"
  3274. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3275. /*51*/ "\005\000\002\006\002"
  3276. "GDT HA %u, Array Drive %u: expand started",
  3277. /*52*/ "\005\000\002\006\002"
  3278. "GDT HA %u, Array Drive %u: expand finished successfully",
  3279. /*53*/ "\005\000\002\006\002"
  3280. "GDT HA %u, Array Drive %u: expand failed",
  3281. /*54*/ "\003\000\002"
  3282. "GDT HA %u, CPU temperature critical",
  3283. /*55*/ "\003\000\002"
  3284. "GDT HA %u, CPU temperature OK",
  3285. /*56*/ "\005\000\002\006\004"
  3286. "GDT HA %u, Host drive %lu created",
  3287. /*57*/ "\005\000\002\006\002"
  3288. "GDT HA %u, Array Drive %u: expand restarted",
  3289. /*58*/ "\005\000\002\006\002"
  3290. "GDT HA %u, Array Drive %u: expand stopped",
  3291. /*59*/ "\005\000\002\010\002"
  3292. "GDT HA %u, Mirror Drive %u: drive build quited",
  3293. /*60*/ "\005\000\002\006\002"
  3294. "GDT HA %u, Array Drive %u: parity build quited",
  3295. /*61*/ "\005\000\002\006\002"
  3296. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3297. /*62*/ "\005\000\002\006\002"
  3298. "GDT HA %u, Array Drive %u: parity verify started",
  3299. /*63*/ "\005\000\002\006\002"
  3300. "GDT HA %u, Array Drive %u: parity verify done",
  3301. /*64*/ "\005\000\002\006\002"
  3302. "GDT HA %u, Array Drive %u: parity verify failed",
  3303. /*65*/ "\005\000\002\006\002"
  3304. "GDT HA %u, Array Drive %u: parity error detected",
  3305. /*66*/ "\005\000\002\006\002"
  3306. "GDT HA %u, Array Drive %u: parity verify quited",
  3307. /*67*/ "\005\000\002\006\002"
  3308. "GDT HA %u, Host Drive %u reserved",
  3309. /*68*/ "\005\000\002\006\002"
  3310. "GDT HA %u, Host Drive %u mounted and released",
  3311. /*69*/ "\005\000\002\006\002"
  3312. "GDT HA %u, Host Drive %u released",
  3313. /*70*/ "\003\000\002"
  3314. "GDT HA %u, DRAM error detected and corrected with ECC",
  3315. /*71*/ "\003\000\002"
  3316. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3317. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3318. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3319. /*73*/ "\005\000\002\006\002"
  3320. "GDT HA %u, Host drive %u resetted locally",
  3321. /*74*/ "\005\000\002\006\002"
  3322. "GDT HA %u, Host drive %u resetted remotely",
  3323. /*75*/ "\003\000\002"
  3324. "GDT HA %u, async. status 75 unknown",
  3325. };
  3326. static int gdth_async_event(gdth_ha_str *ha)
  3327. {
  3328. gdth_cmd_str *cmdp;
  3329. int cmd_index;
  3330. cmdp= ha->pccb;
  3331. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3332. ha->hanum, ha->service));
  3333. if (ha->service == SCREENSERVICE) {
  3334. if (ha->status == MSG_REQUEST) {
  3335. while (gdth_test_busy(ha))
  3336. gdth_delay(0);
  3337. cmdp->Service = SCREENSERVICE;
  3338. cmdp->RequestBuffer = SCREEN_CMND;
  3339. cmd_index = gdth_get_cmd_index(ha);
  3340. gdth_set_sema0(ha);
  3341. cmdp->OpCode = GDT_READ;
  3342. cmdp->BoardNode = LOCALBOARD;
  3343. cmdp->u.screen.reserved = 0;
  3344. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3345. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3346. ha->cmd_offs_dpmem = 0;
  3347. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3348. + sizeof(ulong64);
  3349. ha->cmd_cnt = 0;
  3350. gdth_copy_command(ha);
  3351. if (ha->type == GDT_EISA)
  3352. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3353. else if (ha->type == GDT_ISA)
  3354. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3355. else
  3356. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3357. (ushort)((ha->brd_phys>>3)&0x1f));
  3358. gdth_release_event(ha);
  3359. }
  3360. } else {
  3361. if (ha->type == GDT_PCIMPR &&
  3362. (ha->fw_vers & 0xff) >= 0x1a) {
  3363. ha->dvr.size = 0;
  3364. ha->dvr.eu.async.ionode = ha->hanum;
  3365. ha->dvr.eu.async.status = ha->status;
  3366. /* severity and event_string already set! */
  3367. } else {
  3368. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3369. ha->dvr.eu.async.ionode = ha->hanum;
  3370. ha->dvr.eu.async.service = ha->service;
  3371. ha->dvr.eu.async.status = ha->status;
  3372. ha->dvr.eu.async.info = ha->info;
  3373. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3374. }
  3375. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3376. gdth_log_event( &ha->dvr, NULL );
  3377. /* new host drive from expand? */
  3378. if (ha->service == CACHESERVICE && ha->status == 56) {
  3379. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3380. (ushort)ha->info));
  3381. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3382. }
  3383. }
  3384. return 1;
  3385. }
  3386. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3387. {
  3388. gdth_stackframe stack;
  3389. char *f = NULL;
  3390. int i,j;
  3391. TRACE2(("gdth_log_event()\n"));
  3392. if (dvr->size == 0) {
  3393. if (buffer == NULL) {
  3394. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3395. } else {
  3396. sprintf(buffer,"Adapter %d: %s\n",
  3397. dvr->eu.async.ionode,dvr->event_string);
  3398. }
  3399. } else if (dvr->eu.async.service == CACHESERVICE &&
  3400. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3401. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3402. dvr->eu.async.status));
  3403. f = async_cache_tab[dvr->eu.async.status];
  3404. /* i: parameter to push, j: stack element to fill */
  3405. for (j=0,i=1; i < f[0]; i+=2) {
  3406. switch (f[i+1]) {
  3407. case 4:
  3408. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3409. break;
  3410. case 2:
  3411. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3412. break;
  3413. case 1:
  3414. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3415. break;
  3416. default:
  3417. break;
  3418. }
  3419. }
  3420. if (buffer == NULL) {
  3421. printk(&f[(int)f[0]],stack);
  3422. printk("\n");
  3423. } else {
  3424. sprintf(buffer,&f[(int)f[0]],stack);
  3425. }
  3426. } else {
  3427. if (buffer == NULL) {
  3428. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3429. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3430. } else {
  3431. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3432. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3433. }
  3434. }
  3435. }
  3436. #ifdef GDTH_STATISTICS
  3437. static void gdth_timeout(ulong data)
  3438. {
  3439. ulong32 i;
  3440. Scsi_Cmnd *nscp;
  3441. gdth_ha_str *ha;
  3442. ulong flags;
  3443. BUG_ON(list_empty(&gdth_instances));
  3444. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3445. spin_lock_irqsave(&ha->smp_lock, flags);
  3446. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3447. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3448. ++act_stats;
  3449. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3450. ++act_rq;
  3451. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3452. act_ints, act_ios, act_stats, act_rq));
  3453. act_ints = act_ios = 0;
  3454. gdth_timer.expires = jiffies + 30 * HZ;
  3455. add_timer(&gdth_timer);
  3456. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3457. }
  3458. #endif
  3459. static void __init internal_setup(char *str,int *ints)
  3460. {
  3461. int i, argc;
  3462. char *cur_str, *argv;
  3463. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3464. str ? str:"NULL", ints ? ints[0]:0));
  3465. /* read irq[] from ints[] */
  3466. if (ints) {
  3467. argc = ints[0];
  3468. if (argc > 0) {
  3469. if (argc > MAXHA)
  3470. argc = MAXHA;
  3471. for (i = 0; i < argc; ++i)
  3472. irq[i] = ints[i+1];
  3473. }
  3474. }
  3475. /* analyse string */
  3476. argv = str;
  3477. while (argv && (cur_str = strchr(argv, ':'))) {
  3478. int val = 0, c = *++cur_str;
  3479. if (c == 'n' || c == 'N')
  3480. val = 0;
  3481. else if (c == 'y' || c == 'Y')
  3482. val = 1;
  3483. else
  3484. val = (int)simple_strtoul(cur_str, NULL, 0);
  3485. if (!strncmp(argv, "disable:", 8))
  3486. disable = val;
  3487. else if (!strncmp(argv, "reserve_mode:", 13))
  3488. reserve_mode = val;
  3489. else if (!strncmp(argv, "reverse_scan:", 13))
  3490. reverse_scan = val;
  3491. else if (!strncmp(argv, "hdr_channel:", 12))
  3492. hdr_channel = val;
  3493. else if (!strncmp(argv, "max_ids:", 8))
  3494. max_ids = val;
  3495. else if (!strncmp(argv, "rescan:", 7))
  3496. rescan = val;
  3497. else if (!strncmp(argv, "shared_access:", 14))
  3498. shared_access = val;
  3499. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3500. probe_eisa_isa = val;
  3501. else if (!strncmp(argv, "reserve_list:", 13)) {
  3502. reserve_list[0] = val;
  3503. for (i = 1; i < MAX_RES_ARGS; i++) {
  3504. cur_str = strchr(cur_str, ',');
  3505. if (!cur_str)
  3506. break;
  3507. if (!isdigit((int)*++cur_str)) {
  3508. --cur_str;
  3509. break;
  3510. }
  3511. reserve_list[i] =
  3512. (int)simple_strtoul(cur_str, NULL, 0);
  3513. }
  3514. if (!cur_str)
  3515. break;
  3516. argv = ++cur_str;
  3517. continue;
  3518. }
  3519. if ((argv = strchr(argv, ',')))
  3520. ++argv;
  3521. }
  3522. }
  3523. int __init option_setup(char *str)
  3524. {
  3525. int ints[MAXHA];
  3526. char *cur = str;
  3527. int i = 1;
  3528. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3529. while (cur && isdigit(*cur) && i <= MAXHA) {
  3530. ints[i++] = simple_strtoul(cur, NULL, 0);
  3531. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3532. }
  3533. ints[0] = i - 1;
  3534. internal_setup(cur, ints);
  3535. return 1;
  3536. }
  3537. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3538. {
  3539. TRACE2(("gdth_ctr_name()\n"));
  3540. if (ha->type == GDT_EISA) {
  3541. switch (ha->stype) {
  3542. case GDT3_ID:
  3543. return("GDT3000/3020");
  3544. case GDT3A_ID:
  3545. return("GDT3000A/3020A/3050A");
  3546. case GDT3B_ID:
  3547. return("GDT3000B/3010A");
  3548. }
  3549. } else if (ha->type == GDT_ISA) {
  3550. return("GDT2000/2020");
  3551. } else if (ha->type == GDT_PCI) {
  3552. switch (ha->pdev->device) {
  3553. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3554. return("GDT6000/6020/6050");
  3555. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3556. return("GDT6000B/6010");
  3557. }
  3558. }
  3559. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3560. return("");
  3561. }
  3562. static const char *gdth_info(struct Scsi_Host *shp)
  3563. {
  3564. gdth_ha_str *ha = shost_priv(shp);
  3565. TRACE2(("gdth_info()\n"));
  3566. return ((const char *)ha->binfo.type_string);
  3567. }
  3568. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3569. {
  3570. gdth_ha_str *ha = shost_priv(scp->device->host);
  3571. int i;
  3572. ulong flags;
  3573. Scsi_Cmnd *cmnd;
  3574. unchar b;
  3575. TRACE2(("gdth_eh_bus_reset()\n"));
  3576. b = scp->device->channel;
  3577. /* clear command tab */
  3578. spin_lock_irqsave(&ha->smp_lock, flags);
  3579. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3580. cmnd = ha->cmd_tab[i].cmnd;
  3581. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3582. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3583. }
  3584. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3585. if (b == ha->virt_bus) {
  3586. /* host drives */
  3587. for (i = 0; i < MAX_HDRIVES; ++i) {
  3588. if (ha->hdr[i].present) {
  3589. spin_lock_irqsave(&ha->smp_lock, flags);
  3590. gdth_polling = TRUE;
  3591. while (gdth_test_busy(ha))
  3592. gdth_delay(0);
  3593. if (gdth_internal_cmd(ha, CACHESERVICE,
  3594. GDT_CLUST_RESET, i, 0, 0))
  3595. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3596. gdth_polling = FALSE;
  3597. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3598. }
  3599. }
  3600. } else {
  3601. /* raw devices */
  3602. spin_lock_irqsave(&ha->smp_lock, flags);
  3603. for (i = 0; i < MAXID; ++i)
  3604. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3605. gdth_polling = TRUE;
  3606. while (gdth_test_busy(ha))
  3607. gdth_delay(0);
  3608. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3609. BUS_L2P(ha,b), 0, 0);
  3610. gdth_polling = FALSE;
  3611. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3612. }
  3613. return SUCCESS;
  3614. }
  3615. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3616. {
  3617. unchar b, t;
  3618. gdth_ha_str *ha = shost_priv(sdev->host);
  3619. struct scsi_device *sd;
  3620. unsigned capacity;
  3621. sd = sdev;
  3622. capacity = cap;
  3623. b = sd->channel;
  3624. t = sd->id;
  3625. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3626. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3627. /* raw device or host drive without mapping information */
  3628. TRACE2(("Evaluate mapping\n"));
  3629. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3630. } else {
  3631. ip[0] = ha->hdr[t].heads;
  3632. ip[1] = ha->hdr[t].secs;
  3633. ip[2] = capacity / ip[0] / ip[1];
  3634. }
  3635. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3636. ip[0],ip[1],ip[2]));
  3637. return 0;
  3638. }
  3639. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3640. void (*done)(struct scsi_cmnd *))
  3641. {
  3642. gdth_ha_str *ha = shost_priv(scp->device->host);
  3643. struct gdth_cmndinfo *cmndinfo;
  3644. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3645. cmndinfo = gdth_get_cmndinfo(ha);
  3646. BUG_ON(!cmndinfo);
  3647. scp->scsi_done = done;
  3648. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3649. cmndinfo->priority = DEFAULT_PRI;
  3650. gdth_set_bufflen(scp, scsi_bufflen(scp));
  3651. gdth_set_sg_count(scp, scsi_sg_count(scp));
  3652. gdth_set_sglist(scp, scsi_sglist(scp));
  3653. return __gdth_queuecommand(ha, scp, cmndinfo);
  3654. }
  3655. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3656. struct gdth_cmndinfo *cmndinfo)
  3657. {
  3658. scp->host_scribble = (unsigned char *)cmndinfo;
  3659. cmndinfo->wait_for_completion = 1;
  3660. cmndinfo->phase = -1;
  3661. cmndinfo->OpCode = -1;
  3662. #ifdef GDTH_STATISTICS
  3663. ++act_ios;
  3664. #endif
  3665. gdth_putq(ha, scp, cmndinfo->priority);
  3666. gdth_next(ha);
  3667. return 0;
  3668. }
  3669. static int gdth_open(struct inode *inode, struct file *filep)
  3670. {
  3671. gdth_ha_str *ha;
  3672. list_for_each_entry(ha, &gdth_instances, list) {
  3673. if (!ha->sdev)
  3674. ha->sdev = scsi_get_host_dev(ha->shost);
  3675. }
  3676. TRACE(("gdth_open()\n"));
  3677. return 0;
  3678. }
  3679. static int gdth_close(struct inode *inode, struct file *filep)
  3680. {
  3681. TRACE(("gdth_close()\n"));
  3682. return 0;
  3683. }
  3684. static int ioc_event(void __user *arg)
  3685. {
  3686. gdth_ioctl_event evt;
  3687. gdth_ha_str *ha;
  3688. ulong flags;
  3689. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3690. return -EFAULT;
  3691. ha = gdth_find_ha(evt.ionode);
  3692. if (!ha)
  3693. return -EFAULT;
  3694. if (evt.erase == 0xff) {
  3695. if (evt.event.event_source == ES_TEST)
  3696. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3697. else if (evt.event.event_source == ES_DRIVER)
  3698. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3699. else if (evt.event.event_source == ES_SYNC)
  3700. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3701. else
  3702. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3703. spin_lock_irqsave(&ha->smp_lock, flags);
  3704. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3705. &evt.event.event_data);
  3706. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3707. } else if (evt.erase == 0xfe) {
  3708. gdth_clear_events();
  3709. } else if (evt.erase == 0) {
  3710. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3711. } else {
  3712. gdth_readapp_event(ha, evt.erase, &evt.event);
  3713. }
  3714. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3715. return -EFAULT;
  3716. return 0;
  3717. }
  3718. static int ioc_lockdrv(void __user *arg)
  3719. {
  3720. gdth_ioctl_lockdrv ldrv;
  3721. unchar i, j;
  3722. ulong flags;
  3723. gdth_ha_str *ha;
  3724. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3725. return -EFAULT;
  3726. ha = gdth_find_ha(ldrv.ionode);
  3727. if (!ha)
  3728. return -EFAULT;
  3729. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3730. j = ldrv.drives[i];
  3731. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3732. continue;
  3733. if (ldrv.lock) {
  3734. spin_lock_irqsave(&ha->smp_lock, flags);
  3735. ha->hdr[j].lock = 1;
  3736. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3737. gdth_wait_completion(ha, ha->bus_cnt, j);
  3738. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3739. } else {
  3740. spin_lock_irqsave(&ha->smp_lock, flags);
  3741. ha->hdr[j].lock = 0;
  3742. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3743. gdth_start_timeout(ha, ha->bus_cnt, j);
  3744. gdth_next(ha);
  3745. }
  3746. }
  3747. return 0;
  3748. }
  3749. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3750. {
  3751. gdth_ioctl_reset res;
  3752. gdth_cmd_str cmd;
  3753. gdth_ha_str *ha;
  3754. int rval;
  3755. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3756. res.number >= MAX_HDRIVES)
  3757. return -EFAULT;
  3758. ha = gdth_find_ha(res.ionode);
  3759. if (!ha)
  3760. return -EFAULT;
  3761. if (!ha->hdr[res.number].present)
  3762. return 0;
  3763. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3764. cmd.Service = CACHESERVICE;
  3765. cmd.OpCode = GDT_CLUST_RESET;
  3766. if (ha->cache_feat & GDT_64BIT)
  3767. cmd.u.cache64.DeviceNo = res.number;
  3768. else
  3769. cmd.u.cache.DeviceNo = res.number;
  3770. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3771. if (rval < 0)
  3772. return rval;
  3773. res.status = rval;
  3774. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3775. return -EFAULT;
  3776. return 0;
  3777. }
  3778. static int ioc_general(void __user *arg, char *cmnd)
  3779. {
  3780. gdth_ioctl_general gen;
  3781. char *buf = NULL;
  3782. ulong64 paddr;
  3783. gdth_ha_str *ha;
  3784. int rval;
  3785. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3786. return -EFAULT;
  3787. ha = gdth_find_ha(gen.ionode);
  3788. if (!ha)
  3789. return -EFAULT;
  3790. if (gen.data_len + gen.sense_len != 0) {
  3791. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3792. FALSE, &paddr)))
  3793. return -EFAULT;
  3794. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3795. gen.data_len + gen.sense_len)) {
  3796. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3797. return -EFAULT;
  3798. }
  3799. if (gen.command.OpCode == GDT_IOCTL) {
  3800. gen.command.u.ioctl.p_param = paddr;
  3801. } else if (gen.command.Service == CACHESERVICE) {
  3802. if (ha->cache_feat & GDT_64BIT) {
  3803. /* copy elements from 32-bit IOCTL structure */
  3804. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3805. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3806. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3807. /* addresses */
  3808. if (ha->cache_feat & SCATTER_GATHER) {
  3809. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3810. gen.command.u.cache64.sg_canz = 1;
  3811. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3812. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3813. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3814. } else {
  3815. gen.command.u.cache64.DestAddr = paddr;
  3816. gen.command.u.cache64.sg_canz = 0;
  3817. }
  3818. } else {
  3819. if (ha->cache_feat & SCATTER_GATHER) {
  3820. gen.command.u.cache.DestAddr = 0xffffffff;
  3821. gen.command.u.cache.sg_canz = 1;
  3822. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3823. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3824. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3825. } else {
  3826. gen.command.u.cache.DestAddr = paddr;
  3827. gen.command.u.cache.sg_canz = 0;
  3828. }
  3829. }
  3830. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3831. if (ha->raw_feat & GDT_64BIT) {
  3832. /* copy elements from 32-bit IOCTL structure */
  3833. char cmd[16];
  3834. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3835. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3836. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3837. gen.command.u.raw64.target = gen.command.u.raw.target;
  3838. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3839. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3840. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3841. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3842. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3843. /* addresses */
  3844. if (ha->raw_feat & SCATTER_GATHER) {
  3845. gen.command.u.raw64.sdata = (ulong64)-1;
  3846. gen.command.u.raw64.sg_ranz = 1;
  3847. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3848. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3849. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3850. } else {
  3851. gen.command.u.raw64.sdata = paddr;
  3852. gen.command.u.raw64.sg_ranz = 0;
  3853. }
  3854. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3855. } else {
  3856. if (ha->raw_feat & SCATTER_GATHER) {
  3857. gen.command.u.raw.sdata = 0xffffffff;
  3858. gen.command.u.raw.sg_ranz = 1;
  3859. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3860. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3861. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3862. } else {
  3863. gen.command.u.raw.sdata = paddr;
  3864. gen.command.u.raw.sg_ranz = 0;
  3865. }
  3866. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3867. }
  3868. } else {
  3869. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3870. return -EFAULT;
  3871. }
  3872. }
  3873. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3874. if (rval < 0)
  3875. return rval;
  3876. gen.status = rval;
  3877. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3878. gen.data_len + gen.sense_len)) {
  3879. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3880. return -EFAULT;
  3881. }
  3882. if (copy_to_user(arg, &gen,
  3883. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3884. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3885. return -EFAULT;
  3886. }
  3887. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3888. return 0;
  3889. }
  3890. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3891. {
  3892. gdth_ioctl_rescan *rsc;
  3893. gdth_cmd_str *cmd;
  3894. gdth_ha_str *ha;
  3895. unchar i;
  3896. int rc = -ENOMEM;
  3897. u32 cluster_type = 0;
  3898. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3899. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3900. if (!rsc || !cmd)
  3901. goto free_fail;
  3902. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3903. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3904. rc = -EFAULT;
  3905. goto free_fail;
  3906. }
  3907. memset(cmd, 0, sizeof(gdth_cmd_str));
  3908. for (i = 0; i < MAX_HDRIVES; ++i) {
  3909. if (!ha->hdr[i].present) {
  3910. rsc->hdr_list[i].bus = 0xff;
  3911. continue;
  3912. }
  3913. rsc->hdr_list[i].bus = ha->virt_bus;
  3914. rsc->hdr_list[i].target = i;
  3915. rsc->hdr_list[i].lun = 0;
  3916. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3917. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3918. cmd->Service = CACHESERVICE;
  3919. cmd->OpCode = GDT_CLUST_INFO;
  3920. if (ha->cache_feat & GDT_64BIT)
  3921. cmd->u.cache64.DeviceNo = i;
  3922. else
  3923. cmd->u.cache.DeviceNo = i;
  3924. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3925. rsc->hdr_list[i].cluster_type = cluster_type;
  3926. }
  3927. }
  3928. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3929. rc = -EFAULT;
  3930. else
  3931. rc = 0;
  3932. free_fail:
  3933. kfree(rsc);
  3934. kfree(cmd);
  3935. return rc;
  3936. }
  3937. static int ioc_rescan(void __user *arg, char *cmnd)
  3938. {
  3939. gdth_ioctl_rescan *rsc;
  3940. gdth_cmd_str *cmd;
  3941. ushort i, status, hdr_cnt;
  3942. ulong32 info;
  3943. int cyls, hds, secs;
  3944. int rc = -ENOMEM;
  3945. ulong flags;
  3946. gdth_ha_str *ha;
  3947. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3948. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3949. if (!cmd || !rsc)
  3950. goto free_fail;
  3951. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3952. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3953. rc = -EFAULT;
  3954. goto free_fail;
  3955. }
  3956. memset(cmd, 0, sizeof(gdth_cmd_str));
  3957. if (rsc->flag == 0) {
  3958. /* old method: re-init. cache service */
  3959. cmd->Service = CACHESERVICE;
  3960. if (ha->cache_feat & GDT_64BIT) {
  3961. cmd->OpCode = GDT_X_INIT_HOST;
  3962. cmd->u.cache64.DeviceNo = LINUX_OS;
  3963. } else {
  3964. cmd->OpCode = GDT_INIT;
  3965. cmd->u.cache.DeviceNo = LINUX_OS;
  3966. }
  3967. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3968. i = 0;
  3969. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3970. } else {
  3971. i = rsc->hdr_no;
  3972. hdr_cnt = i + 1;
  3973. }
  3974. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3975. cmd->Service = CACHESERVICE;
  3976. cmd->OpCode = GDT_INFO;
  3977. if (ha->cache_feat & GDT_64BIT)
  3978. cmd->u.cache64.DeviceNo = i;
  3979. else
  3980. cmd->u.cache.DeviceNo = i;
  3981. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3982. spin_lock_irqsave(&ha->smp_lock, flags);
  3983. rsc->hdr_list[i].bus = ha->virt_bus;
  3984. rsc->hdr_list[i].target = i;
  3985. rsc->hdr_list[i].lun = 0;
  3986. if (status != S_OK) {
  3987. ha->hdr[i].present = FALSE;
  3988. } else {
  3989. ha->hdr[i].present = TRUE;
  3990. ha->hdr[i].size = info;
  3991. /* evaluate mapping */
  3992. ha->hdr[i].size &= ~SECS32;
  3993. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3994. ha->hdr[i].heads = hds;
  3995. ha->hdr[i].secs = secs;
  3996. /* round size */
  3997. ha->hdr[i].size = cyls * hds * secs;
  3998. }
  3999. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4000. if (status != S_OK)
  4001. continue;
  4002. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4003. /* but we need ha->info2, not yet stored in scp->SCp */
  4004. /* devtype, cluster info, R/W attribs */
  4005. cmd->Service = CACHESERVICE;
  4006. cmd->OpCode = GDT_DEVTYPE;
  4007. if (ha->cache_feat & GDT_64BIT)
  4008. cmd->u.cache64.DeviceNo = i;
  4009. else
  4010. cmd->u.cache.DeviceNo = i;
  4011. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4012. spin_lock_irqsave(&ha->smp_lock, flags);
  4013. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4014. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4015. cmd->Service = CACHESERVICE;
  4016. cmd->OpCode = GDT_CLUST_INFO;
  4017. if (ha->cache_feat & GDT_64BIT)
  4018. cmd->u.cache64.DeviceNo = i;
  4019. else
  4020. cmd->u.cache.DeviceNo = i;
  4021. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4022. spin_lock_irqsave(&ha->smp_lock, flags);
  4023. ha->hdr[i].cluster_type =
  4024. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4025. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4026. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4027. cmd->Service = CACHESERVICE;
  4028. cmd->OpCode = GDT_RW_ATTRIBS;
  4029. if (ha->cache_feat & GDT_64BIT)
  4030. cmd->u.cache64.DeviceNo = i;
  4031. else
  4032. cmd->u.cache.DeviceNo = i;
  4033. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4034. spin_lock_irqsave(&ha->smp_lock, flags);
  4035. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4036. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4037. }
  4038. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4039. rc = -EFAULT;
  4040. else
  4041. rc = 0;
  4042. free_fail:
  4043. kfree(rsc);
  4044. kfree(cmd);
  4045. return rc;
  4046. }
  4047. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4048. unsigned int cmd, unsigned long arg)
  4049. {
  4050. gdth_ha_str *ha;
  4051. Scsi_Cmnd *scp;
  4052. ulong flags;
  4053. char cmnd[MAX_COMMAND_SIZE];
  4054. void __user *argp = (void __user *)arg;
  4055. memset(cmnd, 0xff, 12);
  4056. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4057. switch (cmd) {
  4058. case GDTIOCTL_CTRCNT:
  4059. {
  4060. int cnt = gdth_ctr_count;
  4061. if (put_user(cnt, (int __user *)argp))
  4062. return -EFAULT;
  4063. break;
  4064. }
  4065. case GDTIOCTL_DRVERS:
  4066. {
  4067. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4068. if (put_user(ver, (int __user *)argp))
  4069. return -EFAULT;
  4070. break;
  4071. }
  4072. case GDTIOCTL_OSVERS:
  4073. {
  4074. gdth_ioctl_osvers osv;
  4075. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4076. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4077. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4078. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4079. return -EFAULT;
  4080. break;
  4081. }
  4082. case GDTIOCTL_CTRTYPE:
  4083. {
  4084. gdth_ioctl_ctrtype ctrt;
  4085. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4086. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4087. return -EFAULT;
  4088. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4089. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4090. } else {
  4091. if (ha->type != GDT_PCIMPR) {
  4092. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4093. } else {
  4094. ctrt.type =
  4095. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4096. if (ha->stype >= 0x300)
  4097. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4098. else
  4099. ctrt.ext_type = 0x6000 | ha->stype;
  4100. }
  4101. ctrt.device_id = ha->pdev->device;
  4102. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4103. }
  4104. ctrt.info = ha->brd_phys;
  4105. ctrt.oem_id = ha->oem_id;
  4106. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4107. return -EFAULT;
  4108. break;
  4109. }
  4110. case GDTIOCTL_GENERAL:
  4111. return ioc_general(argp, cmnd);
  4112. case GDTIOCTL_EVENT:
  4113. return ioc_event(argp);
  4114. case GDTIOCTL_LOCKDRV:
  4115. return ioc_lockdrv(argp);
  4116. case GDTIOCTL_LOCKCHN:
  4117. {
  4118. gdth_ioctl_lockchn lchn;
  4119. unchar i, j;
  4120. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4121. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4122. return -EFAULT;
  4123. i = lchn.channel;
  4124. if (i < ha->bus_cnt) {
  4125. if (lchn.lock) {
  4126. spin_lock_irqsave(&ha->smp_lock, flags);
  4127. ha->raw[i].lock = 1;
  4128. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4129. for (j = 0; j < ha->tid_cnt; ++j) {
  4130. gdth_wait_completion(ha, i, j);
  4131. gdth_stop_timeout(ha, i, j);
  4132. }
  4133. } else {
  4134. spin_lock_irqsave(&ha->smp_lock, flags);
  4135. ha->raw[i].lock = 0;
  4136. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4137. for (j = 0; j < ha->tid_cnt; ++j) {
  4138. gdth_start_timeout(ha, i, j);
  4139. gdth_next(ha);
  4140. }
  4141. }
  4142. }
  4143. break;
  4144. }
  4145. case GDTIOCTL_RESCAN:
  4146. return ioc_rescan(argp, cmnd);
  4147. case GDTIOCTL_HDRLIST:
  4148. return ioc_hdrlist(argp, cmnd);
  4149. case GDTIOCTL_RESET_BUS:
  4150. {
  4151. gdth_ioctl_reset res;
  4152. int rval;
  4153. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4154. (NULL == (ha = gdth_find_ha(res.ionode))))
  4155. return -EFAULT;
  4156. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4157. if (!scp)
  4158. return -ENOMEM;
  4159. scp->device = ha->sdev;
  4160. scp->cmd_len = 12;
  4161. scp->device->channel = res.number;
  4162. rval = gdth_eh_bus_reset(scp);
  4163. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4164. kfree(scp);
  4165. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4166. return -EFAULT;
  4167. break;
  4168. }
  4169. case GDTIOCTL_RESET_DRV:
  4170. return ioc_resetdrv(argp, cmnd);
  4171. default:
  4172. break;
  4173. }
  4174. return 0;
  4175. }
  4176. /* flush routine */
  4177. static void gdth_flush(gdth_ha_str *ha)
  4178. {
  4179. int i;
  4180. gdth_cmd_str gdtcmd;
  4181. char cmnd[MAX_COMMAND_SIZE];
  4182. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4183. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4184. for (i = 0; i < MAX_HDRIVES; ++i) {
  4185. if (ha->hdr[i].present) {
  4186. gdtcmd.BoardNode = LOCALBOARD;
  4187. gdtcmd.Service = CACHESERVICE;
  4188. gdtcmd.OpCode = GDT_FLUSH;
  4189. if (ha->cache_feat & GDT_64BIT) {
  4190. gdtcmd.u.cache64.DeviceNo = i;
  4191. gdtcmd.u.cache64.BlockNo = 1;
  4192. gdtcmd.u.cache64.sg_canz = 0;
  4193. } else {
  4194. gdtcmd.u.cache.DeviceNo = i;
  4195. gdtcmd.u.cache.BlockNo = 1;
  4196. gdtcmd.u.cache.sg_canz = 0;
  4197. }
  4198. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4199. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4200. }
  4201. }
  4202. }
  4203. /* configure lun */
  4204. static int gdth_slave_configure(struct scsi_device *sdev)
  4205. {
  4206. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4207. sdev->skip_ms_page_3f = 1;
  4208. sdev->skip_ms_page_8 = 1;
  4209. return 0;
  4210. }
  4211. static struct scsi_host_template gdth_template = {
  4212. .name = "GDT SCSI Disk Array Controller",
  4213. .info = gdth_info,
  4214. .queuecommand = gdth_queuecommand,
  4215. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4216. .slave_configure = gdth_slave_configure,
  4217. .bios_param = gdth_bios_param,
  4218. .proc_info = gdth_proc_info,
  4219. .proc_name = "gdth",
  4220. .can_queue = GDTH_MAXCMDS,
  4221. .this_id = -1,
  4222. .sg_tablesize = GDTH_MAXSG,
  4223. .cmd_per_lun = GDTH_MAXC_P_L,
  4224. .unchecked_isa_dma = 1,
  4225. .use_clustering = ENABLE_CLUSTERING,
  4226. };
  4227. #ifdef CONFIG_ISA
  4228. static int __init gdth_isa_probe_one(ulong32 isa_bios)
  4229. {
  4230. struct Scsi_Host *shp;
  4231. gdth_ha_str *ha;
  4232. dma_addr_t scratch_dma_handle = 0;
  4233. int error, i;
  4234. if (!gdth_search_isa(isa_bios))
  4235. return -ENXIO;
  4236. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4237. if (!shp)
  4238. return -ENOMEM;
  4239. ha = shost_priv(shp);
  4240. error = -ENODEV;
  4241. if (!gdth_init_isa(isa_bios,ha))
  4242. goto out_host_put;
  4243. /* controller found and initialized */
  4244. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4245. isa_bios, ha->irq, ha->drq);
  4246. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4247. if (error) {
  4248. printk("GDT-ISA: Unable to allocate IRQ\n");
  4249. goto out_host_put;
  4250. }
  4251. error = request_dma(ha->drq, "gdth");
  4252. if (error) {
  4253. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4254. goto out_free_irq;
  4255. }
  4256. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4257. enable_dma(ha->drq);
  4258. shp->unchecked_isa_dma = 1;
  4259. shp->irq = ha->irq;
  4260. shp->dma_channel = ha->drq;
  4261. ha->hanum = gdth_ctr_count++;
  4262. ha->shost = shp;
  4263. ha->pccb = &ha->cmdext;
  4264. ha->ccb_phys = 0L;
  4265. ha->pdev = NULL;
  4266. error = -ENOMEM;
  4267. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4268. &scratch_dma_handle);
  4269. if (!ha->pscratch)
  4270. goto out_dec_counters;
  4271. ha->scratch_phys = scratch_dma_handle;
  4272. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4273. &scratch_dma_handle);
  4274. if (!ha->pmsg)
  4275. goto out_free_pscratch;
  4276. ha->msg_phys = scratch_dma_handle;
  4277. #ifdef INT_COAL
  4278. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4279. sizeof(gdth_coal_status) * MAXOFFSETS,
  4280. &scratch_dma_handle);
  4281. if (!ha->coal_stat)
  4282. goto out_free_pmsg;
  4283. ha->coal_stat_phys = scratch_dma_handle;
  4284. #endif
  4285. ha->scratch_busy = FALSE;
  4286. ha->req_first = NULL;
  4287. ha->tid_cnt = MAX_HDRIVES;
  4288. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4289. ha->tid_cnt = max_ids;
  4290. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4291. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4292. ha->scan_mode = rescan ? 0x10 : 0;
  4293. error = -ENODEV;
  4294. if (!gdth_search_drives(ha)) {
  4295. printk("GDT-ISA: Error during device scan\n");
  4296. goto out_free_coal_stat;
  4297. }
  4298. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4299. hdr_channel = ha->bus_cnt;
  4300. ha->virt_bus = hdr_channel;
  4301. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4302. shp->max_cmd_len = 16;
  4303. shp->max_id = ha->tid_cnt;
  4304. shp->max_lun = MAXLUN;
  4305. shp->max_channel = ha->bus_cnt;
  4306. spin_lock_init(&ha->smp_lock);
  4307. gdth_enable_int(ha);
  4308. error = scsi_add_host(shp, NULL);
  4309. if (error)
  4310. goto out_free_coal_stat;
  4311. list_add_tail(&ha->list, &gdth_instances);
  4312. scsi_scan_host(shp);
  4313. return 0;
  4314. out_free_coal_stat:
  4315. #ifdef INT_COAL
  4316. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4317. ha->coal_stat, ha->coal_stat_phys);
  4318. out_free_pmsg:
  4319. #endif
  4320. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4321. ha->pmsg, ha->msg_phys);
  4322. out_free_pscratch:
  4323. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4324. ha->pscratch, ha->scratch_phys);
  4325. out_dec_counters:
  4326. gdth_ctr_count--;
  4327. out_free_irq:
  4328. free_irq(ha->irq, ha);
  4329. out_host_put:
  4330. scsi_host_put(shp);
  4331. return error;
  4332. }
  4333. #endif /* CONFIG_ISA */
  4334. #ifdef CONFIG_EISA
  4335. static int __init gdth_eisa_probe_one(ushort eisa_slot)
  4336. {
  4337. struct Scsi_Host *shp;
  4338. gdth_ha_str *ha;
  4339. dma_addr_t scratch_dma_handle = 0;
  4340. int error, i;
  4341. if (!gdth_search_eisa(eisa_slot))
  4342. return -ENXIO;
  4343. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4344. if (!shp)
  4345. return -ENOMEM;
  4346. ha = shost_priv(shp);
  4347. error = -ENODEV;
  4348. if (!gdth_init_eisa(eisa_slot,ha))
  4349. goto out_host_put;
  4350. /* controller found and initialized */
  4351. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4352. eisa_slot >> 12, ha->irq);
  4353. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4354. if (error) {
  4355. printk("GDT-EISA: Unable to allocate IRQ\n");
  4356. goto out_host_put;
  4357. }
  4358. shp->unchecked_isa_dma = 0;
  4359. shp->irq = ha->irq;
  4360. shp->dma_channel = 0xff;
  4361. ha->hanum = gdth_ctr_count++;
  4362. ha->shost = shp;
  4363. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4364. ha->pccb = &ha->cmdext;
  4365. ha->ccb_phys = 0L;
  4366. error = -ENOMEM;
  4367. ha->pdev = NULL;
  4368. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4369. &scratch_dma_handle);
  4370. if (!ha->pscratch)
  4371. goto out_free_irq;
  4372. ha->scratch_phys = scratch_dma_handle;
  4373. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4374. &scratch_dma_handle);
  4375. if (!ha->pmsg)
  4376. goto out_free_pscratch;
  4377. ha->msg_phys = scratch_dma_handle;
  4378. #ifdef INT_COAL
  4379. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4380. sizeof(gdth_coal_status) * MAXOFFSETS,
  4381. &scratch_dma_handle);
  4382. if (!ha->coal_stat)
  4383. goto out_free_pmsg;
  4384. ha->coal_stat_phys = scratch_dma_handle;
  4385. #endif
  4386. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4387. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4388. if (!ha->ccb_phys)
  4389. goto out_free_coal_stat;
  4390. ha->scratch_busy = FALSE;
  4391. ha->req_first = NULL;
  4392. ha->tid_cnt = MAX_HDRIVES;
  4393. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4394. ha->tid_cnt = max_ids;
  4395. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4396. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4397. ha->scan_mode = rescan ? 0x10 : 0;
  4398. if (!gdth_search_drives(ha)) {
  4399. printk("GDT-EISA: Error during device scan\n");
  4400. error = -ENODEV;
  4401. goto out_free_ccb_phys;
  4402. }
  4403. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4404. hdr_channel = ha->bus_cnt;
  4405. ha->virt_bus = hdr_channel;
  4406. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4407. shp->max_cmd_len = 16;
  4408. shp->max_id = ha->tid_cnt;
  4409. shp->max_lun = MAXLUN;
  4410. shp->max_channel = ha->bus_cnt;
  4411. spin_lock_init(&ha->smp_lock);
  4412. gdth_enable_int(ha);
  4413. error = scsi_add_host(shp, NULL);
  4414. if (error)
  4415. goto out_free_coal_stat;
  4416. list_add_tail(&ha->list, &gdth_instances);
  4417. scsi_scan_host(shp);
  4418. return 0;
  4419. out_free_ccb_phys:
  4420. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4421. PCI_DMA_BIDIRECTIONAL);
  4422. out_free_coal_stat:
  4423. #ifdef INT_COAL
  4424. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4425. ha->coal_stat, ha->coal_stat_phys);
  4426. out_free_pmsg:
  4427. #endif
  4428. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4429. ha->pmsg, ha->msg_phys);
  4430. out_free_pscratch:
  4431. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4432. ha->pscratch, ha->scratch_phys);
  4433. out_free_irq:
  4434. free_irq(ha->irq, ha);
  4435. gdth_ctr_count--;
  4436. out_host_put:
  4437. scsi_host_put(shp);
  4438. return error;
  4439. }
  4440. #endif /* CONFIG_EISA */
  4441. #ifdef CONFIG_PCI
  4442. static int __init gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
  4443. {
  4444. struct Scsi_Host *shp;
  4445. gdth_ha_str *ha;
  4446. dma_addr_t scratch_dma_handle = 0;
  4447. int error, i;
  4448. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4449. if (!shp)
  4450. return -ENOMEM;
  4451. ha = shost_priv(shp);
  4452. error = -ENODEV;
  4453. if (!gdth_init_pci(&pcistr[ctr],ha))
  4454. goto out_host_put;
  4455. /* controller found and initialized */
  4456. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4457. pcistr[ctr].pdev->bus->number,
  4458. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4459. ha->irq);
  4460. error = request_irq(ha->irq, gdth_interrupt,
  4461. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4462. if (error) {
  4463. printk("GDT-PCI: Unable to allocate IRQ\n");
  4464. goto out_host_put;
  4465. }
  4466. shp->unchecked_isa_dma = 0;
  4467. shp->irq = ha->irq;
  4468. shp->dma_channel = 0xff;
  4469. ha->hanum = gdth_ctr_count++;
  4470. ha->shost = shp;
  4471. ha->pccb = &ha->cmdext;
  4472. ha->ccb_phys = 0L;
  4473. error = -ENOMEM;
  4474. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4475. &scratch_dma_handle);
  4476. if (!ha->pscratch)
  4477. goto out_free_irq;
  4478. ha->scratch_phys = scratch_dma_handle;
  4479. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4480. &scratch_dma_handle);
  4481. if (!ha->pmsg)
  4482. goto out_free_pscratch;
  4483. ha->msg_phys = scratch_dma_handle;
  4484. #ifdef INT_COAL
  4485. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4486. sizeof(gdth_coal_status) * MAXOFFSETS,
  4487. &scratch_dma_handle);
  4488. if (!ha->coal_stat)
  4489. goto out_free_pmsg;
  4490. ha->coal_stat_phys = scratch_dma_handle;
  4491. #endif
  4492. ha->scratch_busy = FALSE;
  4493. ha->req_first = NULL;
  4494. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4495. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4496. ha->tid_cnt = max_ids;
  4497. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4498. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4499. ha->scan_mode = rescan ? 0x10 : 0;
  4500. error = -ENODEV;
  4501. if (!gdth_search_drives(ha)) {
  4502. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4503. goto out_free_coal_stat;
  4504. }
  4505. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4506. hdr_channel = ha->bus_cnt;
  4507. ha->virt_bus = hdr_channel;
  4508. /* 64-bit DMA only supported from FW >= x.43 */
  4509. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4510. !ha->dma64_support) {
  4511. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4512. printk(KERN_WARNING "GDT-PCI %d: "
  4513. "Unable to set 32-bit DMA\n", ha->hanum);
  4514. goto out_free_coal_stat;
  4515. }
  4516. } else {
  4517. shp->max_cmd_len = 16;
  4518. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4519. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4520. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4521. printk(KERN_WARNING "GDT-PCI %d: "
  4522. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4523. goto out_free_coal_stat;
  4524. }
  4525. }
  4526. shp->max_id = ha->tid_cnt;
  4527. shp->max_lun = MAXLUN;
  4528. shp->max_channel = ha->bus_cnt;
  4529. spin_lock_init(&ha->smp_lock);
  4530. gdth_enable_int(ha);
  4531. error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
  4532. if (error)
  4533. goto out_free_coal_stat;
  4534. list_add_tail(&ha->list, &gdth_instances);
  4535. scsi_scan_host(shp);
  4536. return 0;
  4537. out_free_coal_stat:
  4538. #ifdef INT_COAL
  4539. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4540. ha->coal_stat, ha->coal_stat_phys);
  4541. out_free_pmsg:
  4542. #endif
  4543. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4544. ha->pmsg, ha->msg_phys);
  4545. out_free_pscratch:
  4546. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4547. ha->pscratch, ha->scratch_phys);
  4548. out_free_irq:
  4549. free_irq(ha->irq, ha);
  4550. gdth_ctr_count--;
  4551. out_host_put:
  4552. scsi_host_put(shp);
  4553. return error;
  4554. }
  4555. #endif /* CONFIG_PCI */
  4556. static void gdth_remove_one(gdth_ha_str *ha)
  4557. {
  4558. struct Scsi_Host *shp = ha->shost;
  4559. TRACE2(("gdth_remove_one()\n"));
  4560. scsi_remove_host(shp);
  4561. gdth_flush(ha);
  4562. if (ha->sdev) {
  4563. scsi_free_host_dev(ha->sdev);
  4564. ha->sdev = NULL;
  4565. }
  4566. if (shp->irq)
  4567. free_irq(shp->irq,ha);
  4568. #ifdef CONFIG_ISA
  4569. if (shp->dma_channel != 0xff)
  4570. free_dma(shp->dma_channel);
  4571. #endif
  4572. #ifdef INT_COAL
  4573. if (ha->coal_stat)
  4574. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4575. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4576. #endif
  4577. if (ha->pscratch)
  4578. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4579. ha->pscratch, ha->scratch_phys);
  4580. if (ha->pmsg)
  4581. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4582. ha->pmsg, ha->msg_phys);
  4583. if (ha->ccb_phys)
  4584. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4585. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4586. scsi_host_put(shp);
  4587. }
  4588. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4589. {
  4590. gdth_ha_str *ha;
  4591. TRACE2(("gdth_halt() event %d\n", (int)event));
  4592. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4593. return NOTIFY_DONE;
  4594. list_for_each_entry(ha, &gdth_instances, list)
  4595. gdth_flush(ha);
  4596. return NOTIFY_OK;
  4597. }
  4598. static struct notifier_block gdth_notifier = {
  4599. gdth_halt, NULL, 0
  4600. };
  4601. static int __init gdth_init(void)
  4602. {
  4603. if (disable) {
  4604. printk("GDT-HA: Controller driver disabled from"
  4605. " command line !\n");
  4606. return 0;
  4607. }
  4608. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4609. GDTH_VERSION_STR);
  4610. /* initializations */
  4611. gdth_polling = TRUE;
  4612. gdth_clear_events();
  4613. /* As default we do not probe for EISA or ISA controllers */
  4614. if (probe_eisa_isa) {
  4615. /* scanning for controllers, at first: ISA controller */
  4616. #ifdef CONFIG_ISA
  4617. ulong32 isa_bios;
  4618. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4619. isa_bios += 0x8000UL)
  4620. gdth_isa_probe_one(isa_bios);
  4621. #endif
  4622. #ifdef CONFIG_EISA
  4623. {
  4624. ushort eisa_slot;
  4625. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4626. eisa_slot += 0x1000)
  4627. gdth_eisa_probe_one(eisa_slot);
  4628. }
  4629. #endif
  4630. }
  4631. #ifdef CONFIG_PCI
  4632. /* scanning for PCI controllers */
  4633. {
  4634. gdth_pci_str pcistr[MAXHA];
  4635. int cnt,ctr;
  4636. cnt = gdth_search_pci(pcistr);
  4637. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
  4638. gdth_sort_pci(pcistr,cnt);
  4639. for (ctr = 0; ctr < cnt; ++ctr)
  4640. gdth_pci_probe_one(pcistr, ctr);
  4641. }
  4642. #endif /* CONFIG_PCI */
  4643. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4644. if (list_empty(&gdth_instances))
  4645. return -ENODEV;
  4646. #ifdef GDTH_STATISTICS
  4647. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4648. init_timer(&gdth_timer);
  4649. gdth_timer.expires = jiffies + HZ;
  4650. gdth_timer.data = 0L;
  4651. gdth_timer.function = gdth_timeout;
  4652. add_timer(&gdth_timer);
  4653. #endif
  4654. major = register_chrdev(0,"gdth", &gdth_fops);
  4655. register_reboot_notifier(&gdth_notifier);
  4656. gdth_polling = FALSE;
  4657. return 0;
  4658. }
  4659. static void __exit gdth_exit(void)
  4660. {
  4661. gdth_ha_str *ha;
  4662. unregister_chrdev(major, "gdth");
  4663. unregister_reboot_notifier(&gdth_notifier);
  4664. #ifdef GDTH_STATISTICS
  4665. del_timer_sync(&gdth_timer);
  4666. #endif
  4667. list_for_each_entry(ha, &gdth_instances, list)
  4668. gdth_remove_one(ha);
  4669. }
  4670. module_init(gdth_init);
  4671. module_exit(gdth_exit);
  4672. #ifndef MODULE
  4673. __setup("gdth=", option_setup);
  4674. #endif