dma.h 4.6 KB

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  1. /*
  2. * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. #ifndef IOATDMA_H
  22. #define IOATDMA_H
  23. #include <linux/dmaengine.h>
  24. #include "hw.h"
  25. #include <linux/init.h>
  26. #include <linux/dmapool.h>
  27. #include <linux/cache.h>
  28. #include <linux/pci_ids.h>
  29. #include <net/tcp.h>
  30. #define IOAT_DMA_VERSION "3.64"
  31. #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
  32. #define IOAT_DMA_DCA_ANY_CPU ~0
  33. #define IOAT_WATCHDOG_PERIOD (2 * HZ)
  34. #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
  35. #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  36. #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  37. #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
  38. #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
  39. #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
  40. #define RESET_DELAY msecs_to_jiffies(100)
  41. #define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000))
  42. /*
  43. * workaround for IOAT ver.3.0 null descriptor issue
  44. * (channel returns error when size is 0)
  45. */
  46. #define NULL_DESC_BUFFER_SIZE 1
  47. /**
  48. * struct ioatdma_device - internal representation of a IOAT device
  49. * @pdev: PCI-Express device
  50. * @reg_base: MMIO register space base address
  51. * @dma_pool: for allocating DMA descriptors
  52. * @common: embedded struct dma_device
  53. * @version: version of ioatdma device
  54. * @msix_entries: irq handlers
  55. * @idx: per channel data
  56. */
  57. struct ioatdma_device {
  58. struct pci_dev *pdev;
  59. void __iomem *reg_base;
  60. struct pci_pool *dma_pool;
  61. struct pci_pool *completion_pool;
  62. struct dma_device common;
  63. u8 version;
  64. struct delayed_work work;
  65. struct msix_entry msix_entries[4];
  66. struct ioat_dma_chan *idx[4];
  67. };
  68. /**
  69. * struct ioat_dma_chan - internal representation of a DMA channel
  70. */
  71. struct ioat_dma_chan {
  72. void __iomem *reg_base;
  73. dma_cookie_t completed_cookie;
  74. unsigned long last_completion;
  75. unsigned long last_completion_time;
  76. size_t xfercap; /* XFERCAP register value expanded out */
  77. spinlock_t cleanup_lock;
  78. spinlock_t desc_lock;
  79. struct list_head free_desc;
  80. struct list_head used_desc;
  81. unsigned long watchdog_completion;
  82. int watchdog_tcp_cookie;
  83. u32 watchdog_last_tcp_cookie;
  84. struct delayed_work work;
  85. int pending;
  86. int dmacount;
  87. int desccount;
  88. struct ioatdma_device *device;
  89. struct dma_chan common;
  90. dma_addr_t completion_addr;
  91. union {
  92. u64 full; /* HW completion writeback */
  93. struct {
  94. u32 low;
  95. u32 high;
  96. };
  97. } *completion_virt;
  98. unsigned long last_compl_desc_addr_hw;
  99. struct tasklet_struct cleanup_task;
  100. };
  101. /* wrapper around hardware descriptor format + additional software fields */
  102. /**
  103. * struct ioat_desc_sw - wrapper around hardware descriptor
  104. * @hw: hardware DMA descriptor
  105. * @node: this descriptor will either be on the free list,
  106. * or attached to a transaction list (async_tx.tx_list)
  107. * @tx_cnt: number of descriptors required to complete the transaction
  108. * @txd: the generic software descriptor for all engines
  109. */
  110. struct ioat_desc_sw {
  111. struct ioat_dma_descriptor *hw;
  112. struct list_head node;
  113. int tx_cnt;
  114. size_t len;
  115. dma_addr_t src;
  116. dma_addr_t dst;
  117. struct dma_async_tx_descriptor txd;
  118. };
  119. static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev)
  120. {
  121. #ifdef CONFIG_NET_DMA
  122. switch (dev->version) {
  123. case IOAT_VER_1_2:
  124. sysctl_tcp_dma_copybreak = 4096;
  125. break;
  126. case IOAT_VER_2_0:
  127. sysctl_tcp_dma_copybreak = 2048;
  128. break;
  129. case IOAT_VER_3_0:
  130. sysctl_tcp_dma_copybreak = 262144;
  131. break;
  132. }
  133. #endif
  134. }
  135. struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
  136. void __iomem *iobase);
  137. void ioat_dma_remove(struct ioatdma_device *device);
  138. struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
  139. struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
  140. struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
  141. #endif /* IOATDMA_H */