mpc8377_rdb.dts 8.0 KB

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  1. /*
  2. * MPC8377E RDB Device Tree Source
  3. *
  4. * Copyright 2007, 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. compatible = "fsl,mpc8377rdb";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. aliases {
  17. ethernet0 = &enet0;
  18. ethernet1 = &enet1;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8377@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>;
  34. bus-frequency = <0>;
  35. clock-frequency = <0>;
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>; // 256MB at 0
  41. };
  42. localbus@e0005000 {
  43. #address-cells = <2>;
  44. #size-cells = <1>;
  45. compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
  46. reg = <0xe0005000 0x1000>;
  47. interrupts = <77 0x8>;
  48. interrupt-parent = <&ipic>;
  49. // CS0 and CS1 are swapped when
  50. // booting from nand, but the
  51. // addresses are the same.
  52. ranges = <0x0 0x0 0xfe000000 0x00800000
  53. 0x1 0x0 0xe0600000 0x00008000
  54. 0x2 0x0 0xf0000000 0x00020000
  55. 0x3 0x0 0xfa000000 0x00008000>;
  56. flash@0,0 {
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. compatible = "cfi-flash";
  60. reg = <0x0 0x0 0x800000>;
  61. bank-width = <2>;
  62. device-width = <1>;
  63. };
  64. nand@1,0 {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "fsl,mpc8377-fcm-nand",
  68. "fsl,elbc-fcm-nand";
  69. reg = <0x1 0x0 0x8000>;
  70. u-boot@0 {
  71. reg = <0x0 0x100000>;
  72. read-only;
  73. };
  74. kernel@100000 {
  75. reg = <0x100000 0x300000>;
  76. };
  77. fs@400000 {
  78. reg = <0x400000 0x1c00000>;
  79. };
  80. };
  81. };
  82. immr@e0000000 {
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. device_type = "soc";
  86. compatible = "simple-bus";
  87. ranges = <0x0 0xe0000000 0x00100000>;
  88. reg = <0xe0000000 0x00000200>;
  89. bus-frequency = <0>;
  90. wdt@200 {
  91. device_type = "watchdog";
  92. compatible = "mpc83xx_wdt";
  93. reg = <0x200 0x100>;
  94. };
  95. i2c@3000 {
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. cell-index = <0>;
  99. compatible = "fsl-i2c";
  100. reg = <0x3000 0x100>;
  101. interrupts = <14 0x8>;
  102. interrupt-parent = <&ipic>;
  103. dfsrr;
  104. rtc@68 {
  105. device_type = "rtc";
  106. compatible = "dallas,ds1339";
  107. reg = <0x68>;
  108. };
  109. mcu_pio: mcu@a {
  110. #gpio-cells = <2>;
  111. compatible = "fsl,mc9s08qg8-mpc8377erdb",
  112. "fsl,mcu-mpc8349emitx";
  113. reg = <0x0a>;
  114. gpio-controller;
  115. };
  116. };
  117. i2c@3100 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. cell-index = <1>;
  121. compatible = "fsl-i2c";
  122. reg = <0x3100 0x100>;
  123. interrupts = <15 0x8>;
  124. interrupt-parent = <&ipic>;
  125. dfsrr;
  126. };
  127. spi@7000 {
  128. cell-index = <0>;
  129. compatible = "fsl,spi";
  130. reg = <0x7000 0x1000>;
  131. interrupts = <16 0x8>;
  132. interrupt-parent = <&ipic>;
  133. mode = "cpu";
  134. };
  135. dma@82a8 {
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
  139. reg = <0x82a8 4>;
  140. ranges = <0 0x8100 0x1a8>;
  141. interrupt-parent = <&ipic>;
  142. interrupts = <71 8>;
  143. cell-index = <0>;
  144. dma-channel@0 {
  145. compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
  146. reg = <0 0x80>;
  147. cell-index = <0>;
  148. interrupt-parent = <&ipic>;
  149. interrupts = <71 8>;
  150. };
  151. dma-channel@80 {
  152. compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
  153. reg = <0x80 0x80>;
  154. cell-index = <1>;
  155. interrupt-parent = <&ipic>;
  156. interrupts = <71 8>;
  157. };
  158. dma-channel@100 {
  159. compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
  160. reg = <0x100 0x80>;
  161. cell-index = <2>;
  162. interrupt-parent = <&ipic>;
  163. interrupts = <71 8>;
  164. };
  165. dma-channel@180 {
  166. compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
  167. reg = <0x180 0x28>;
  168. cell-index = <3>;
  169. interrupt-parent = <&ipic>;
  170. interrupts = <71 8>;
  171. };
  172. };
  173. usb@23000 {
  174. compatible = "fsl-usb2-dr";
  175. reg = <0x23000 0x1000>;
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. interrupt-parent = <&ipic>;
  179. interrupts = <38 0x8>;
  180. phy_type = "ulpi";
  181. };
  182. mdio@24520 {
  183. #address-cells = <1>;
  184. #size-cells = <0>;
  185. compatible = "fsl,gianfar-mdio";
  186. reg = <0x24520 0x20>;
  187. phy2: ethernet-phy@2 {
  188. interrupt-parent = <&ipic>;
  189. interrupts = <17 0x8>;
  190. reg = <0x2>;
  191. device_type = "ethernet-phy";
  192. };
  193. tbi0: tbi-phy@11 {
  194. reg = <0x11>;
  195. device_type = "tbi-phy";
  196. };
  197. };
  198. mdio@25520 {
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. compatible = "fsl,gianfar-tbi";
  202. reg = <0x25520 0x20>;
  203. tbi1: tbi-phy@11 {
  204. reg = <0x11>;
  205. device_type = "tbi-phy";
  206. };
  207. };
  208. enet0: ethernet@24000 {
  209. cell-index = <0>;
  210. device_type = "network";
  211. model = "eTSEC";
  212. compatible = "gianfar";
  213. reg = <0x24000 0x1000>;
  214. local-mac-address = [ 00 00 00 00 00 00 ];
  215. interrupts = <32 0x8 33 0x8 34 0x8>;
  216. phy-connection-type = "mii";
  217. interrupt-parent = <&ipic>;
  218. tbi-handle = <&tbi0>;
  219. phy-handle = <&phy2>;
  220. };
  221. enet1: ethernet@25000 {
  222. cell-index = <1>;
  223. device_type = "network";
  224. model = "eTSEC";
  225. compatible = "gianfar";
  226. reg = <0x25000 0x1000>;
  227. local-mac-address = [ 00 00 00 00 00 00 ];
  228. interrupts = <35 0x8 36 0x8 37 0x8>;
  229. phy-connection-type = "mii";
  230. interrupt-parent = <&ipic>;
  231. fixed-link = <1 1 1000 0 0>;
  232. tbi-handle = <&tbi1>;
  233. };
  234. serial0: serial@4500 {
  235. cell-index = <0>;
  236. device_type = "serial";
  237. compatible = "ns16550";
  238. reg = <0x4500 0x100>;
  239. clock-frequency = <0>;
  240. interrupts = <9 0x8>;
  241. interrupt-parent = <&ipic>;
  242. };
  243. serial1: serial@4600 {
  244. cell-index = <1>;
  245. device_type = "serial";
  246. compatible = "ns16550";
  247. reg = <0x4600 0x100>;
  248. clock-frequency = <0>;
  249. interrupts = <10 0x8>;
  250. interrupt-parent = <&ipic>;
  251. };
  252. crypto@30000 {
  253. compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
  254. "fsl,sec2.1", "fsl,sec2.0";
  255. reg = <0x30000 0x10000>;
  256. interrupts = <11 0x8>;
  257. interrupt-parent = <&ipic>;
  258. fsl,num-channels = <4>;
  259. fsl,channel-fifo-len = <24>;
  260. fsl,exec-units-mask = <0x9fe>;
  261. fsl,descriptor-types-mask = <0x3ab0ebf>;
  262. };
  263. sata@18000 {
  264. compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
  265. reg = <0x18000 0x1000>;
  266. interrupts = <44 0x8>;
  267. interrupt-parent = <&ipic>;
  268. };
  269. sata@19000 {
  270. compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
  271. reg = <0x19000 0x1000>;
  272. interrupts = <45 0x8>;
  273. interrupt-parent = <&ipic>;
  274. };
  275. /* IPIC
  276. * interrupts cell = <intr #, sense>
  277. * sense values match linux IORESOURCE_IRQ_* defines:
  278. * sense == 8: Level, low assertion
  279. * sense == 2: Edge, high-to-low change
  280. */
  281. ipic: interrupt-controller@700 {
  282. compatible = "fsl,ipic";
  283. interrupt-controller;
  284. #address-cells = <0>;
  285. #interrupt-cells = <2>;
  286. reg = <0x700 0x100>;
  287. };
  288. };
  289. pci0: pci@e0008500 {
  290. interrupt-map-mask = <0xf800 0 0 7>;
  291. interrupt-map = <
  292. /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
  293. /* IDSEL AD14 IRQ6 inta */
  294. 0x7000 0x0 0x0 0x1 &ipic 22 0x8
  295. /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
  296. 0x7800 0x0 0x0 0x1 &ipic 21 0x8
  297. 0x7800 0x0 0x0 0x2 &ipic 22 0x8
  298. 0x7800 0x0 0x0 0x4 &ipic 23 0x8
  299. /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
  300. 0xE000 0x0 0x0 0x1 &ipic 23 0x8
  301. 0xE000 0x0 0x0 0x2 &ipic 21 0x8
  302. 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
  303. interrupt-parent = <&ipic>;
  304. interrupts = <66 0x8>;
  305. bus-range = <0 0>;
  306. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  307. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  308. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  309. clock-frequency = <66666666>;
  310. #interrupt-cells = <1>;
  311. #size-cells = <2>;
  312. #address-cells = <3>;
  313. reg = <0xe0008500 0x100 /* internal registers */
  314. 0xe0008300 0x8>; /* config space access registers */
  315. compatible = "fsl,mpc8349-pci";
  316. device_type = "pci";
  317. };
  318. };