mpc8349emitx.dts 7.9 KB

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  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITX";
  14. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>;
  43. };
  44. soc8349@e0000000 {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. device_type = "soc";
  48. compatible = "simple-bus";
  49. ranges = <0x0 0xe0000000 0x00100000>;
  50. reg = <0xe0000000 0x00000200>;
  51. bus-frequency = <0>; // from bootloader
  52. wdt@200 {
  53. device_type = "watchdog";
  54. compatible = "mpc83xx_wdt";
  55. reg = <0x200 0x100>;
  56. };
  57. i2c@3000 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. cell-index = <0>;
  61. compatible = "fsl-i2c";
  62. reg = <0x3000 0x100>;
  63. interrupts = <14 0x8>;
  64. interrupt-parent = <&ipic>;
  65. dfsrr;
  66. };
  67. i2c@3100 {
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. cell-index = <1>;
  71. compatible = "fsl-i2c";
  72. reg = <0x3100 0x100>;
  73. interrupts = <15 0x8>;
  74. interrupt-parent = <&ipic>;
  75. dfsrr;
  76. rtc@68 {
  77. device_type = "rtc";
  78. compatible = "dallas,ds1339";
  79. reg = <0x68>;
  80. interrupts = <18 0x8>;
  81. interrupt-parent = <&ipic>;
  82. };
  83. mcu_pio: mcu@a {
  84. #gpio-cells = <2>;
  85. compatible = "fsl,mc9s08qg8-mpc8349emitx",
  86. "fsl,mcu-mpc8349emitx";
  87. reg = <0x0a>;
  88. gpio-controller;
  89. };
  90. };
  91. spi@7000 {
  92. cell-index = <0>;
  93. compatible = "fsl,spi";
  94. reg = <0x7000 0x1000>;
  95. interrupts = <16 0x8>;
  96. interrupt-parent = <&ipic>;
  97. mode = "cpu";
  98. };
  99. dma@82a8 {
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  103. reg = <0x82a8 4>;
  104. ranges = <0 0x8100 0x1a8>;
  105. interrupt-parent = <&ipic>;
  106. interrupts = <71 8>;
  107. cell-index = <0>;
  108. dma-channel@0 {
  109. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  110. reg = <0 0x80>;
  111. cell-index = <0>;
  112. interrupt-parent = <&ipic>;
  113. interrupts = <71 8>;
  114. };
  115. dma-channel@80 {
  116. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  117. reg = <0x80 0x80>;
  118. cell-index = <1>;
  119. interrupt-parent = <&ipic>;
  120. interrupts = <71 8>;
  121. };
  122. dma-channel@100 {
  123. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  124. reg = <0x100 0x80>;
  125. cell-index = <2>;
  126. interrupt-parent = <&ipic>;
  127. interrupts = <71 8>;
  128. };
  129. dma-channel@180 {
  130. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  131. reg = <0x180 0x28>;
  132. cell-index = <3>;
  133. interrupt-parent = <&ipic>;
  134. interrupts = <71 8>;
  135. };
  136. };
  137. usb@22000 {
  138. compatible = "fsl-usb2-mph";
  139. reg = <0x22000 0x1000>;
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. interrupt-parent = <&ipic>;
  143. interrupts = <39 0x8>;
  144. phy_type = "ulpi";
  145. port1;
  146. };
  147. usb@23000 {
  148. compatible = "fsl-usb2-dr";
  149. reg = <0x23000 0x1000>;
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. interrupt-parent = <&ipic>;
  153. interrupts = <38 0x8>;
  154. dr_mode = "peripheral";
  155. phy_type = "ulpi";
  156. };
  157. mdio@24520 {
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. compatible = "fsl,gianfar-mdio";
  161. reg = <0x24520 0x20>;
  162. /* Vitesse 8201 */
  163. phy1c: ethernet-phy@1c {
  164. interrupt-parent = <&ipic>;
  165. interrupts = <18 0x8>;
  166. reg = <0x1c>;
  167. device_type = "ethernet-phy";
  168. };
  169. tbi0: tbi-phy@11 {
  170. reg = <0x11>;
  171. device_type = "tbi-phy";
  172. };
  173. };
  174. mdio@25520 {
  175. #address-cells = <1>;
  176. #size-cells = <0>;
  177. compatible = "fsl,gianfar-tbi";
  178. reg = <0x25520 0x20>;
  179. tbi1: tbi-phy@11 {
  180. reg = <0x11>;
  181. device_type = "tbi-phy";
  182. };
  183. };
  184. enet0: ethernet@24000 {
  185. cell-index = <0>;
  186. device_type = "network";
  187. model = "TSEC";
  188. compatible = "gianfar";
  189. reg = <0x24000 0x1000>;
  190. local-mac-address = [ 00 00 00 00 00 00 ];
  191. interrupts = <32 0x8 33 0x8 34 0x8>;
  192. interrupt-parent = <&ipic>;
  193. tbi-handle = <&tbi0>;
  194. phy-handle = <&phy1c>;
  195. linux,network-index = <0>;
  196. };
  197. enet1: ethernet@25000 {
  198. cell-index = <1>;
  199. device_type = "network";
  200. model = "TSEC";
  201. compatible = "gianfar";
  202. reg = <0x25000 0x1000>;
  203. local-mac-address = [ 00 00 00 00 00 00 ];
  204. interrupts = <35 0x8 36 0x8 37 0x8>;
  205. interrupt-parent = <&ipic>;
  206. /* Vitesse 7385 isn't on the MDIO bus */
  207. fixed-link = <1 1 1000 0 0>;
  208. linux,network-index = <1>;
  209. tbi-handle = <&tbi1>;
  210. };
  211. serial0: serial@4500 {
  212. cell-index = <0>;
  213. device_type = "serial";
  214. compatible = "ns16550";
  215. reg = <0x4500 0x100>;
  216. clock-frequency = <0>; // from bootloader
  217. interrupts = <9 0x8>;
  218. interrupt-parent = <&ipic>;
  219. };
  220. serial1: serial@4600 {
  221. cell-index = <1>;
  222. device_type = "serial";
  223. compatible = "ns16550";
  224. reg = <0x4600 0x100>;
  225. clock-frequency = <0>; // from bootloader
  226. interrupts = <10 0x8>;
  227. interrupt-parent = <&ipic>;
  228. };
  229. crypto@30000 {
  230. compatible = "fsl,sec2.0";
  231. reg = <0x30000 0x10000>;
  232. interrupts = <11 0x8>;
  233. interrupt-parent = <&ipic>;
  234. fsl,num-channels = <4>;
  235. fsl,channel-fifo-len = <24>;
  236. fsl,exec-units-mask = <0x7e>;
  237. fsl,descriptor-types-mask = <0x01010ebf>;
  238. };
  239. ipic: pic@700 {
  240. interrupt-controller;
  241. #address-cells = <0>;
  242. #interrupt-cells = <2>;
  243. reg = <0x700 0x100>;
  244. device_type = "ipic";
  245. };
  246. };
  247. pci0: pci@e0008500 {
  248. cell-index = <1>;
  249. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  250. interrupt-map = <
  251. /* IDSEL 0x10 - SATA */
  252. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  253. >;
  254. interrupt-parent = <&ipic>;
  255. interrupts = <66 0x8>;
  256. bus-range = <0x0 0x0>;
  257. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  258. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  259. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  260. clock-frequency = <66666666>;
  261. #interrupt-cells = <1>;
  262. #size-cells = <2>;
  263. #address-cells = <3>;
  264. reg = <0xe0008500 0x100 /* internal registers */
  265. 0xe0008300 0x8>; /* config space access registers */
  266. compatible = "fsl,mpc8349-pci";
  267. device_type = "pci";
  268. };
  269. pci1: pci@e0008600 {
  270. cell-index = <2>;
  271. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  272. interrupt-map = <
  273. /* IDSEL 0x0E - MiniPCI Slot */
  274. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  275. /* IDSEL 0x0F - PCI Slot */
  276. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  277. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  278. >;
  279. interrupt-parent = <&ipic>;
  280. interrupts = <67 0x8>;
  281. bus-range = <0x0 0x0>;
  282. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  283. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  284. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  285. clock-frequency = <66666666>;
  286. #interrupt-cells = <1>;
  287. #size-cells = <2>;
  288. #address-cells = <3>;
  289. reg = <0xe0008600 0x100 /* internal registers */
  290. 0xe0008380 0x8>; /* config space access registers */
  291. compatible = "fsl,mpc8349-pci";
  292. device_type = "pci";
  293. };
  294. localbus@e0005000 {
  295. #address-cells = <2>;
  296. #size-cells = <1>;
  297. compatible = "fsl,mpc8349e-localbus",
  298. "fsl,pq2pro-localbus";
  299. reg = <0xe0005000 0xd8>;
  300. ranges = <0x3 0x0 0xf0000000 0x210>;
  301. pata@3,0 {
  302. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  303. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  304. reg-shift = <1>;
  305. pio-mode = <6>;
  306. interrupts = <23 0x8>;
  307. interrupt-parent = <&ipic>;
  308. };
  309. };
  310. };