bnx2fc_hwi.c 54 KB

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  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2010 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *conn_destroy);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ALERT PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
  87. fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
  88. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  89. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  90. ((u64) hba->hash_tbl_pbl_dma >> 32);
  91. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  92. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  93. ((u64) hba->t2_hash_tbl_dma >> 32);
  94. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  95. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  96. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  97. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  98. /* fill init3 KWQE */
  99. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  100. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  101. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  102. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  103. fcoe_init3.error_bit_map_lo = 0xffffffff;
  104. fcoe_init3.error_bit_map_hi = 0xffffffff;
  105. fcoe_init3.perf_config = 1;
  106. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  107. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  108. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  109. if (hba->cnic && hba->cnic->submit_kwqes)
  110. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  111. return rc;
  112. }
  113. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  114. {
  115. struct fcoe_kwqe_destroy fcoe_destroy;
  116. struct kwqe *kwqe_arr[2];
  117. int num_kwqes = 1;
  118. int rc = -1;
  119. /* fill destroy KWQE */
  120. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  121. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  122. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  123. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  124. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  125. if (hba->cnic && hba->cnic->submit_kwqes)
  126. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  127. return rc;
  128. }
  129. /**
  130. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  131. *
  132. * @port: port structure pointer
  133. * @tgt: bnx2fc_rport structure pointer
  134. */
  135. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  136. struct bnx2fc_rport *tgt)
  137. {
  138. struct fc_lport *lport = port->lport;
  139. struct bnx2fc_hba *hba = port->priv;
  140. struct kwqe *kwqe_arr[4];
  141. struct fcoe_kwqe_conn_offload1 ofld_req1;
  142. struct fcoe_kwqe_conn_offload2 ofld_req2;
  143. struct fcoe_kwqe_conn_offload3 ofld_req3;
  144. struct fcoe_kwqe_conn_offload4 ofld_req4;
  145. struct fc_rport_priv *rdata = tgt->rdata;
  146. struct fc_rport *rport = tgt->rport;
  147. int num_kwqes = 4;
  148. u32 port_id;
  149. int rc = 0;
  150. u16 conn_id;
  151. /* Initialize offload request 1 structure */
  152. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  153. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  154. ofld_req1.hdr.flags =
  155. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  156. conn_id = (u16)tgt->fcoe_conn_id;
  157. ofld_req1.fcoe_conn_id = conn_id;
  158. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  159. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  160. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  161. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  162. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  163. ofld_req1.rq_first_pbe_addr_hi =
  164. (u32)((u64) tgt->rq_dma >> 32);
  165. ofld_req1.rq_prod = 0x8000;
  166. /* Initialize offload request 2 structure */
  167. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  168. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  169. ofld_req2.hdr.flags =
  170. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  171. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  172. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  173. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  174. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  175. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  176. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  177. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  178. /* Initialize offload request 3 structure */
  179. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  180. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  181. ofld_req3.hdr.flags =
  182. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  183. ofld_req3.vlan_tag = hba->vlan_id <<
  184. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  185. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  186. port_id = fc_host_port_id(lport->host);
  187. if (port_id == 0) {
  188. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  189. return -EINVAL;
  190. }
  191. /*
  192. * Store s_id of the initiator for further reference. This will
  193. * be used during disable/destroy during linkdown processing as
  194. * when the lport is reset, the port_id also is reset to 0
  195. */
  196. tgt->sid = port_id;
  197. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  198. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  199. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  200. port_id = rport->port_id;
  201. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  202. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  203. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  204. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  205. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  206. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  207. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  208. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  209. ofld_req3.rx_open_seqs_exch_c3 = 1;
  210. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  211. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  212. /* set mul_n_port_ids supported flag to 0, until it is supported */
  213. ofld_req3.flags = 0;
  214. /*
  215. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  216. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  217. */
  218. /* Info from PLOGI response */
  219. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  220. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  221. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  222. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  223. /* vlan flag */
  224. ofld_req3.flags |= (hba->vlan_enabled <<
  225. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  226. /* C2_VALID and ACK flags are not set as they are not suppported */
  227. /* Initialize offload request 4 structure */
  228. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  229. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  230. ofld_req4.hdr.flags =
  231. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  232. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  233. ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
  234. /* local mac */
  235. ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
  236. ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
  237. ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
  238. ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
  239. ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
  240. ofld_req4.dst_mac_addr_lo[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  241. ofld_req4.dst_mac_addr_lo[1] = hba->ctlr.dest_addr[4];
  242. ofld_req4.dst_mac_addr_mid[0] = hba->ctlr.dest_addr[3];
  243. ofld_req4.dst_mac_addr_mid[1] = hba->ctlr.dest_addr[2];
  244. ofld_req4.dst_mac_addr_hi[0] = hba->ctlr.dest_addr[1];
  245. ofld_req4.dst_mac_addr_hi[1] = hba->ctlr.dest_addr[0];
  246. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  247. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  248. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  249. ofld_req4.confq_pbl_base_addr_hi =
  250. (u32)((u64) tgt->confq_pbl_dma >> 32);
  251. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  252. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  253. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  254. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  255. if (hba->cnic && hba->cnic->submit_kwqes)
  256. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  257. return rc;
  258. }
  259. /**
  260. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  261. *
  262. * @port: port structure pointer
  263. * @tgt: bnx2fc_rport structure pointer
  264. */
  265. static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  266. struct bnx2fc_rport *tgt)
  267. {
  268. struct kwqe *kwqe_arr[2];
  269. struct bnx2fc_hba *hba = port->priv;
  270. struct fcoe_kwqe_conn_enable_disable enbl_req;
  271. struct fc_lport *lport = port->lport;
  272. struct fc_rport *rport = tgt->rport;
  273. int num_kwqes = 1;
  274. int rc = 0;
  275. u32 port_id;
  276. memset(&enbl_req, 0x00,
  277. sizeof(struct fcoe_kwqe_conn_enable_disable));
  278. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  279. enbl_req.hdr.flags =
  280. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  281. enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
  282. /* local mac */
  283. enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
  284. enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
  285. enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
  286. enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
  287. enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
  288. memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
  289. enbl_req.dst_mac_addr_lo[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  290. enbl_req.dst_mac_addr_lo[1] = hba->ctlr.dest_addr[4];
  291. enbl_req.dst_mac_addr_mid[0] = hba->ctlr.dest_addr[3];
  292. enbl_req.dst_mac_addr_mid[1] = hba->ctlr.dest_addr[2];
  293. enbl_req.dst_mac_addr_hi[0] = hba->ctlr.dest_addr[1];
  294. enbl_req.dst_mac_addr_hi[1] = hba->ctlr.dest_addr[0];
  295. port_id = fc_host_port_id(lport->host);
  296. if (port_id != tgt->sid) {
  297. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  298. "sid = 0x%x\n", port_id, tgt->sid);
  299. port_id = tgt->sid;
  300. }
  301. enbl_req.s_id[0] = (port_id & 0x000000FF);
  302. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  303. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  304. port_id = rport->port_id;
  305. enbl_req.d_id[0] = (port_id & 0x000000FF);
  306. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  307. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  308. enbl_req.vlan_tag = hba->vlan_id <<
  309. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  310. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  311. enbl_req.vlan_flag = hba->vlan_enabled;
  312. enbl_req.context_id = tgt->context_id;
  313. enbl_req.conn_id = tgt->fcoe_conn_id;
  314. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  315. if (hba->cnic && hba->cnic->submit_kwqes)
  316. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  317. return rc;
  318. }
  319. /**
  320. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  321. *
  322. * @port: port structure pointer
  323. * @tgt: bnx2fc_rport structure pointer
  324. */
  325. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  326. struct bnx2fc_rport *tgt)
  327. {
  328. struct bnx2fc_hba *hba = port->priv;
  329. struct fcoe_kwqe_conn_enable_disable disable_req;
  330. struct kwqe *kwqe_arr[2];
  331. struct fc_rport *rport = tgt->rport;
  332. int num_kwqes = 1;
  333. int rc = 0;
  334. u32 port_id;
  335. memset(&disable_req, 0x00,
  336. sizeof(struct fcoe_kwqe_conn_enable_disable));
  337. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  338. disable_req.hdr.flags =
  339. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  340. disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
  341. disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
  342. disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
  343. disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
  344. disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
  345. disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
  346. disable_req.dst_mac_addr_lo[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  347. disable_req.dst_mac_addr_lo[1] = hba->ctlr.dest_addr[4];
  348. disable_req.dst_mac_addr_mid[0] = hba->ctlr.dest_addr[3];
  349. disable_req.dst_mac_addr_mid[1] = hba->ctlr.dest_addr[2];
  350. disable_req.dst_mac_addr_hi[0] = hba->ctlr.dest_addr[1];
  351. disable_req.dst_mac_addr_hi[1] = hba->ctlr.dest_addr[0];
  352. port_id = tgt->sid;
  353. disable_req.s_id[0] = (port_id & 0x000000FF);
  354. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  355. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  356. port_id = rport->port_id;
  357. disable_req.d_id[0] = (port_id & 0x000000FF);
  358. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  359. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  360. disable_req.context_id = tgt->context_id;
  361. disable_req.conn_id = tgt->fcoe_conn_id;
  362. disable_req.vlan_tag = hba->vlan_id <<
  363. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  364. disable_req.vlan_tag |=
  365. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  366. disable_req.vlan_flag = hba->vlan_enabled;
  367. kwqe_arr[0] = (struct kwqe *) &disable_req;
  368. if (hba->cnic && hba->cnic->submit_kwqes)
  369. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  370. return rc;
  371. }
  372. /**
  373. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  374. *
  375. * @port: port structure pointer
  376. * @tgt: bnx2fc_rport structure pointer
  377. */
  378. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  379. struct bnx2fc_rport *tgt)
  380. {
  381. struct fcoe_kwqe_conn_destroy destroy_req;
  382. struct kwqe *kwqe_arr[2];
  383. int num_kwqes = 1;
  384. int rc = 0;
  385. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  386. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  387. destroy_req.hdr.flags =
  388. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  389. destroy_req.context_id = tgt->context_id;
  390. destroy_req.conn_id = tgt->fcoe_conn_id;
  391. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  392. if (hba->cnic && hba->cnic->submit_kwqes)
  393. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  394. return rc;
  395. }
  396. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  397. {
  398. struct bnx2fc_lport *blport;
  399. spin_lock_bh(&hba->hba_lock);
  400. list_for_each_entry(blport, &hba->vports, list) {
  401. if (blport->lport == lport) {
  402. spin_unlock_bh(&hba->hba_lock);
  403. return true;
  404. }
  405. }
  406. spin_unlock_bh(&hba->hba_lock);
  407. return false;
  408. }
  409. static void bnx2fc_unsol_els_work(struct work_struct *work)
  410. {
  411. struct bnx2fc_unsol_els *unsol_els;
  412. struct fc_lport *lport;
  413. struct bnx2fc_hba *hba;
  414. struct fc_frame *fp;
  415. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  416. lport = unsol_els->lport;
  417. fp = unsol_els->fp;
  418. hba = unsol_els->hba;
  419. if (is_valid_lport(hba, lport))
  420. fc_exch_recv(lport, fp);
  421. kfree(unsol_els);
  422. }
  423. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  424. unsigned char *buf,
  425. u32 frame_len, u16 l2_oxid)
  426. {
  427. struct fcoe_port *port = tgt->port;
  428. struct fc_lport *lport = port->lport;
  429. struct bnx2fc_hba *hba = port->priv;
  430. struct bnx2fc_unsol_els *unsol_els;
  431. struct fc_frame_header *fh;
  432. struct fc_frame *fp;
  433. struct sk_buff *skb;
  434. u32 payload_len;
  435. u32 crc;
  436. u8 op;
  437. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  438. if (!unsol_els) {
  439. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  440. return;
  441. }
  442. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  443. l2_oxid, frame_len);
  444. payload_len = frame_len - sizeof(struct fc_frame_header);
  445. fp = fc_frame_alloc(lport, payload_len);
  446. if (!fp) {
  447. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  448. kfree(unsol_els);
  449. return;
  450. }
  451. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  452. /* Copy FC Frame header and payload into the frame */
  453. memcpy(fh, buf, frame_len);
  454. if (l2_oxid != FC_XID_UNKNOWN)
  455. fh->fh_ox_id = htons(l2_oxid);
  456. skb = fp_skb(fp);
  457. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  458. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  459. if (fh->fh_type == FC_TYPE_ELS) {
  460. op = fc_frame_payload_op(fp);
  461. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  462. (op == ELS_FAN) || (op == ELS_CSU)) {
  463. /*
  464. * No need to reply for these
  465. * ELS requests
  466. */
  467. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  468. kfree_skb(skb);
  469. kfree(unsol_els);
  470. return;
  471. }
  472. }
  473. crc = fcoe_fc_crc(fp);
  474. fc_frame_init(fp);
  475. fr_dev(fp) = lport;
  476. fr_sof(fp) = FC_SOF_I3;
  477. fr_eof(fp) = FC_EOF_T;
  478. fr_crc(fp) = cpu_to_le32(~crc);
  479. unsol_els->lport = lport;
  480. unsol_els->hba = hba;
  481. unsol_els->fp = fp;
  482. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  483. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  484. } else {
  485. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  486. kfree_skb(skb);
  487. kfree(unsol_els);
  488. }
  489. }
  490. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  491. {
  492. u8 num_rq;
  493. struct fcoe_err_report_entry *err_entry;
  494. unsigned char *rq_data;
  495. unsigned char *buf = NULL, *buf1;
  496. int i;
  497. u16 xid;
  498. u32 frame_len, len;
  499. struct bnx2fc_cmd *io_req = NULL;
  500. struct fcoe_task_ctx_entry *task, *task_page;
  501. struct bnx2fc_hba *hba = tgt->port->priv;
  502. int task_idx, index;
  503. int rc = 0;
  504. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  505. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  506. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  507. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  508. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  509. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  510. spin_lock_bh(&tgt->tgt_lock);
  511. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  512. spin_unlock_bh(&tgt->tgt_lock);
  513. if (rq_data) {
  514. buf = rq_data;
  515. } else {
  516. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  517. GFP_ATOMIC);
  518. if (!buf1) {
  519. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  520. break;
  521. }
  522. for (i = 0; i < num_rq; i++) {
  523. spin_lock_bh(&tgt->tgt_lock);
  524. rq_data = (unsigned char *)
  525. bnx2fc_get_next_rqe(tgt, 1);
  526. spin_unlock_bh(&tgt->tgt_lock);
  527. len = BNX2FC_RQ_BUF_SZ;
  528. memcpy(buf1, rq_data, len);
  529. buf1 += len;
  530. }
  531. }
  532. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  533. FC_XID_UNKNOWN);
  534. if (buf != rq_data)
  535. kfree(buf);
  536. spin_lock_bh(&tgt->tgt_lock);
  537. bnx2fc_return_rqe(tgt, num_rq);
  538. spin_unlock_bh(&tgt->tgt_lock);
  539. break;
  540. case FCOE_ERROR_DETECTION_CQE_TYPE:
  541. /*
  542. * In case of error reporting CQE a single RQ entry
  543. * is consumed.
  544. */
  545. spin_lock_bh(&tgt->tgt_lock);
  546. num_rq = 1;
  547. err_entry = (struct fcoe_err_report_entry *)
  548. bnx2fc_get_next_rqe(tgt, 1);
  549. xid = err_entry->fc_hdr.ox_id;
  550. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  551. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  552. err_entry->data.err_warn_bitmap_hi,
  553. err_entry->data.err_warn_bitmap_lo);
  554. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  555. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  556. bnx2fc_return_rqe(tgt, 1);
  557. if (xid > BNX2FC_MAX_XID) {
  558. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  559. xid);
  560. spin_unlock_bh(&tgt->tgt_lock);
  561. break;
  562. }
  563. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  564. index = xid % BNX2FC_TASKS_PER_PAGE;
  565. task_page = (struct fcoe_task_ctx_entry *)
  566. hba->task_ctx[task_idx];
  567. task = &(task_page[index]);
  568. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  569. if (!io_req) {
  570. spin_unlock_bh(&tgt->tgt_lock);
  571. break;
  572. }
  573. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  574. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  575. spin_unlock_bh(&tgt->tgt_lock);
  576. break;
  577. }
  578. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  579. &io_req->req_flags)) {
  580. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  581. "progress.. ignore unsol err\n");
  582. spin_unlock_bh(&tgt->tgt_lock);
  583. break;
  584. }
  585. /*
  586. * If ABTS is already in progress, and FW error is
  587. * received after that, do not cancel the timeout_work
  588. * and let the error recovery continue by explicitly
  589. * logging out the target, when the ABTS eventually
  590. * times out.
  591. */
  592. if (!test_and_set_bit(BNX2FC_FLAG_ISSUE_ABTS,
  593. &io_req->req_flags)) {
  594. /*
  595. * Cancel the timeout_work, as we received IO
  596. * completion with FW error.
  597. */
  598. if (cancel_delayed_work(&io_req->timeout_work))
  599. kref_put(&io_req->refcount,
  600. bnx2fc_cmd_release); /* timer hold */
  601. rc = bnx2fc_initiate_abts(io_req);
  602. if (rc != SUCCESS) {
  603. BNX2FC_IO_DBG(io_req, "err_warn: initiate_abts "
  604. "failed. issue cleanup\n");
  605. rc = bnx2fc_initiate_cleanup(io_req);
  606. BUG_ON(rc);
  607. }
  608. } else
  609. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  610. "in ABTS processing\n", xid);
  611. spin_unlock_bh(&tgt->tgt_lock);
  612. break;
  613. case FCOE_WARNING_DETECTION_CQE_TYPE:
  614. /*
  615. *In case of warning reporting CQE a single RQ entry
  616. * is consumes.
  617. */
  618. spin_lock_bh(&tgt->tgt_lock);
  619. num_rq = 1;
  620. err_entry = (struct fcoe_err_report_entry *)
  621. bnx2fc_get_next_rqe(tgt, 1);
  622. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  623. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  624. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  625. err_entry->data.err_warn_bitmap_hi,
  626. err_entry->data.err_warn_bitmap_lo);
  627. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  628. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  629. bnx2fc_return_rqe(tgt, 1);
  630. spin_unlock_bh(&tgt->tgt_lock);
  631. break;
  632. default:
  633. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  634. break;
  635. }
  636. }
  637. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  638. {
  639. struct fcoe_task_ctx_entry *task;
  640. struct fcoe_task_ctx_entry *task_page;
  641. struct fcoe_port *port = tgt->port;
  642. struct bnx2fc_hba *hba = port->priv;
  643. struct bnx2fc_cmd *io_req;
  644. int task_idx, index;
  645. u16 xid;
  646. u8 cmd_type;
  647. u8 rx_state = 0;
  648. u8 num_rq;
  649. spin_lock_bh(&tgt->tgt_lock);
  650. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  651. if (xid >= BNX2FC_MAX_TASKS) {
  652. printk(KERN_ERR PFX "ERROR:xid out of range\n");
  653. spin_unlock_bh(&tgt->tgt_lock);
  654. return;
  655. }
  656. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  657. index = xid % BNX2FC_TASKS_PER_PAGE;
  658. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  659. task = &(task_page[index]);
  660. num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
  661. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
  662. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
  663. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  664. if (io_req == NULL) {
  665. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  666. spin_unlock_bh(&tgt->tgt_lock);
  667. return;
  668. }
  669. /* Timestamp IO completion time */
  670. cmd_type = io_req->cmd_type;
  671. rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
  672. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
  673. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
  674. /* Process other IO completion types */
  675. switch (cmd_type) {
  676. case BNX2FC_SCSI_CMD:
  677. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  678. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  679. spin_unlock_bh(&tgt->tgt_lock);
  680. return;
  681. }
  682. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  683. bnx2fc_process_abts_compl(io_req, task, num_rq);
  684. else if (rx_state ==
  685. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  686. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  687. else
  688. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  689. rx_state);
  690. break;
  691. case BNX2FC_TASK_MGMT_CMD:
  692. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  693. bnx2fc_process_tm_compl(io_req, task, num_rq);
  694. break;
  695. case BNX2FC_ABTS:
  696. /*
  697. * ABTS request received by firmware. ABTS response
  698. * will be delivered to the task belonging to the IO
  699. * that was aborted
  700. */
  701. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  702. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  703. break;
  704. case BNX2FC_ELS:
  705. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
  706. bnx2fc_process_els_compl(io_req, task, num_rq);
  707. else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  708. bnx2fc_process_abts_compl(io_req, task, num_rq);
  709. else if (rx_state ==
  710. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  711. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  712. else
  713. printk(KERN_ERR PFX "Invalid rx state = %d\n",
  714. rx_state);
  715. break;
  716. case BNX2FC_CLEANUP:
  717. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  718. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  719. break;
  720. default:
  721. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  722. break;
  723. }
  724. spin_unlock_bh(&tgt->tgt_lock);
  725. }
  726. void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
  727. {
  728. struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
  729. u32 msg;
  730. wmb();
  731. rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
  732. FCOE_CQE_TOGGLE_BIT_SHIFT);
  733. msg = *((u32 *)rx_db);
  734. writel(cpu_to_le32(msg), tgt->ctx_base);
  735. mmiowb();
  736. }
  737. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  738. {
  739. struct bnx2fc_work *work;
  740. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  741. if (!work)
  742. return NULL;
  743. INIT_LIST_HEAD(&work->list);
  744. work->tgt = tgt;
  745. work->wqe = wqe;
  746. return work;
  747. }
  748. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  749. {
  750. struct fcoe_cqe *cq;
  751. u32 cq_cons;
  752. struct fcoe_cqe *cqe;
  753. u32 num_free_sqes = 0;
  754. u16 wqe;
  755. /*
  756. * cq_lock is a low contention lock used to protect
  757. * the CQ data structure from being freed up during
  758. * the upload operation
  759. */
  760. spin_lock_bh(&tgt->cq_lock);
  761. if (!tgt->cq) {
  762. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  763. spin_unlock_bh(&tgt->cq_lock);
  764. return 0;
  765. }
  766. cq = tgt->cq;
  767. cq_cons = tgt->cq_cons_idx;
  768. cqe = &cq[cq_cons];
  769. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  770. (tgt->cq_curr_toggle_bit <<
  771. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  772. /* new entry on the cq */
  773. if (wqe & FCOE_CQE_CQE_TYPE) {
  774. /* Unsolicited event notification */
  775. bnx2fc_process_unsol_compl(tgt, wqe);
  776. } else {
  777. /* Pending work request completion */
  778. struct bnx2fc_work *work = NULL;
  779. struct bnx2fc_percpu_s *fps = NULL;
  780. unsigned int cpu = wqe % num_possible_cpus();
  781. fps = &per_cpu(bnx2fc_percpu, cpu);
  782. spin_lock_bh(&fps->fp_work_lock);
  783. if (unlikely(!fps->iothread))
  784. goto unlock;
  785. work = bnx2fc_alloc_work(tgt, wqe);
  786. if (work)
  787. list_add_tail(&work->list,
  788. &fps->work_list);
  789. unlock:
  790. spin_unlock_bh(&fps->fp_work_lock);
  791. /* Pending work request completion */
  792. if (fps->iothread && work)
  793. wake_up_process(fps->iothread);
  794. else
  795. bnx2fc_process_cq_compl(tgt, wqe);
  796. }
  797. cqe++;
  798. tgt->cq_cons_idx++;
  799. num_free_sqes++;
  800. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  801. tgt->cq_cons_idx = 0;
  802. cqe = cq;
  803. tgt->cq_curr_toggle_bit =
  804. 1 - tgt->cq_curr_toggle_bit;
  805. }
  806. }
  807. bnx2fc_arm_cq(tgt);
  808. atomic_add(num_free_sqes, &tgt->free_sqes);
  809. spin_unlock_bh(&tgt->cq_lock);
  810. return 0;
  811. }
  812. /**
  813. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  814. *
  815. * @hba: adapter structure pointer
  816. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  817. *
  818. * Fast path event notification handler
  819. */
  820. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  821. struct fcoe_kcqe *new_cqe_kcqe)
  822. {
  823. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  824. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  825. if (!tgt) {
  826. printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
  827. return;
  828. }
  829. bnx2fc_process_new_cqes(tgt);
  830. }
  831. /**
  832. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  833. *
  834. * @hba: adapter structure pointer
  835. * @ofld_kcqe: connection offload kcqe pointer
  836. *
  837. * handle session offload completion, enable the session if offload is
  838. * successful.
  839. */
  840. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  841. struct fcoe_kcqe *ofld_kcqe)
  842. {
  843. struct bnx2fc_rport *tgt;
  844. struct fcoe_port *port;
  845. u32 conn_id;
  846. u32 context_id;
  847. int rc;
  848. conn_id = ofld_kcqe->fcoe_conn_id;
  849. context_id = ofld_kcqe->fcoe_conn_context_id;
  850. tgt = hba->tgt_ofld_list[conn_id];
  851. if (!tgt) {
  852. printk(KERN_ERR PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  853. return;
  854. }
  855. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  856. ofld_kcqe->fcoe_conn_context_id);
  857. port = tgt->port;
  858. if (hba != tgt->port->priv) {
  859. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  860. goto ofld_cmpl_err;
  861. }
  862. /*
  863. * cnic has allocated a context_id for this session; use this
  864. * while enabling the session.
  865. */
  866. tgt->context_id = context_id;
  867. if (ofld_kcqe->completion_status) {
  868. if (ofld_kcqe->completion_status ==
  869. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  870. printk(KERN_ERR PFX "unable to allocate FCoE context "
  871. "resources\n");
  872. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  873. }
  874. goto ofld_cmpl_err;
  875. } else {
  876. /* now enable the session */
  877. rc = bnx2fc_send_session_enable_req(port, tgt);
  878. if (rc) {
  879. printk(KERN_ERR PFX "enable session failed\n");
  880. goto ofld_cmpl_err;
  881. }
  882. }
  883. return;
  884. ofld_cmpl_err:
  885. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  886. wake_up_interruptible(&tgt->ofld_wait);
  887. }
  888. /**
  889. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  890. *
  891. * @hba: adapter structure pointer
  892. * @ofld_kcqe: connection offload kcqe pointer
  893. *
  894. * handle session enable completion, mark the rport as ready
  895. */
  896. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  897. struct fcoe_kcqe *ofld_kcqe)
  898. {
  899. struct bnx2fc_rport *tgt;
  900. u32 conn_id;
  901. u32 context_id;
  902. context_id = ofld_kcqe->fcoe_conn_context_id;
  903. conn_id = ofld_kcqe->fcoe_conn_id;
  904. tgt = hba->tgt_ofld_list[conn_id];
  905. if (!tgt) {
  906. printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  907. return;
  908. }
  909. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  910. ofld_kcqe->fcoe_conn_context_id);
  911. /*
  912. * context_id should be the same for this target during offload
  913. * and enable
  914. */
  915. if (tgt->context_id != context_id) {
  916. printk(KERN_ERR PFX "context id mis-match\n");
  917. return;
  918. }
  919. if (hba != tgt->port->priv) {
  920. printk(KERN_ALERT PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  921. goto enbl_cmpl_err;
  922. }
  923. if (ofld_kcqe->completion_status) {
  924. goto enbl_cmpl_err;
  925. } else {
  926. /* enable successful - rport ready for issuing IOs */
  927. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  928. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  929. wake_up_interruptible(&tgt->ofld_wait);
  930. }
  931. return;
  932. enbl_cmpl_err:
  933. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  934. wake_up_interruptible(&tgt->ofld_wait);
  935. }
  936. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  937. struct fcoe_kcqe *disable_kcqe)
  938. {
  939. struct bnx2fc_rport *tgt;
  940. u32 conn_id;
  941. conn_id = disable_kcqe->fcoe_conn_id;
  942. tgt = hba->tgt_ofld_list[conn_id];
  943. if (!tgt) {
  944. printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
  945. return;
  946. }
  947. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  948. if (disable_kcqe->completion_status) {
  949. printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
  950. disable_kcqe->completion_status);
  951. return;
  952. } else {
  953. /* disable successful */
  954. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  955. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  956. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  957. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  958. wake_up_interruptible(&tgt->upld_wait);
  959. }
  960. }
  961. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  962. struct fcoe_kcqe *destroy_kcqe)
  963. {
  964. struct bnx2fc_rport *tgt;
  965. u32 conn_id;
  966. conn_id = destroy_kcqe->fcoe_conn_id;
  967. tgt = hba->tgt_ofld_list[conn_id];
  968. if (!tgt) {
  969. printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
  970. return;
  971. }
  972. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  973. if (destroy_kcqe->completion_status) {
  974. printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
  975. destroy_kcqe->completion_status);
  976. return;
  977. } else {
  978. /* destroy successful */
  979. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  980. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  981. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  982. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  983. wake_up_interruptible(&tgt->upld_wait);
  984. }
  985. }
  986. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  987. {
  988. switch (err_code) {
  989. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  990. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  991. break;
  992. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  993. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  994. break;
  995. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  996. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  997. break;
  998. case FCOE_KCQE_COMPLETION_STATUS_ERROR:
  999. printk(KERN_ERR PFX "init failure due to compl status err\n");
  1000. break;
  1001. case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
  1002. printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
  1003. break;
  1004. default:
  1005. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  1006. }
  1007. }
  1008. /**
  1009. * bnx2fc_indicae_kcqe - process KCQE
  1010. *
  1011. * @hba: adapter structure pointer
  1012. * @kcqe: kcqe pointer
  1013. * @num_cqe: Number of completion queue elements
  1014. *
  1015. * Generic KCQ event handler
  1016. */
  1017. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  1018. u32 num_cqe)
  1019. {
  1020. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1021. int i = 0;
  1022. struct fcoe_kcqe *kcqe = NULL;
  1023. while (i < num_cqe) {
  1024. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1025. switch (kcqe->op_code) {
  1026. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1027. bnx2fc_fastpath_notification(hba, kcqe);
  1028. break;
  1029. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1030. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1031. break;
  1032. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1033. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1034. break;
  1035. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1036. if (kcqe->completion_status !=
  1037. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1038. bnx2fc_init_failure(hba,
  1039. kcqe->completion_status);
  1040. } else {
  1041. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1042. bnx2fc_get_link_state(hba);
  1043. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1044. (u8)hba->pcidev->bus->number);
  1045. }
  1046. break;
  1047. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1048. if (kcqe->completion_status !=
  1049. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1050. printk(KERN_ERR PFX "DESTROY failed\n");
  1051. } else {
  1052. printk(KERN_ERR PFX "DESTROY success\n");
  1053. }
  1054. hba->flags |= BNX2FC_FLAG_DESTROY_CMPL;
  1055. wake_up_interruptible(&hba->destroy_wait);
  1056. break;
  1057. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1058. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1059. break;
  1060. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1061. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1062. break;
  1063. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1064. if (kcqe->completion_status !=
  1065. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1066. printk(KERN_ERR PFX "STAT failed\n");
  1067. complete(&hba->stat_req_done);
  1068. break;
  1069. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1070. /* fall thru */
  1071. default:
  1072. printk(KERN_ERR PFX "unknown opcode 0x%x\n",
  1073. kcqe->op_code);
  1074. }
  1075. }
  1076. }
  1077. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1078. {
  1079. struct fcoe_sqe *sqe;
  1080. sqe = &tgt->sq[tgt->sq_prod_idx];
  1081. /* Fill SQ WQE */
  1082. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1083. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1084. /* Advance SQ Prod Idx */
  1085. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1086. tgt->sq_prod_idx = 0;
  1087. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1088. }
  1089. }
  1090. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1091. {
  1092. struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
  1093. u32 msg;
  1094. wmb();
  1095. sq_db->prod = tgt->sq_prod_idx |
  1096. (tgt->sq_curr_toggle_bit << 15);
  1097. msg = *((u32 *)sq_db);
  1098. writel(cpu_to_le32(msg), tgt->ctx_base);
  1099. mmiowb();
  1100. }
  1101. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1102. {
  1103. u32 context_id = tgt->context_id;
  1104. struct fcoe_port *port = tgt->port;
  1105. u32 reg_off;
  1106. resource_size_t reg_base;
  1107. struct bnx2fc_hba *hba = port->priv;
  1108. reg_base = pci_resource_start(hba->pcidev,
  1109. BNX2X_DOORBELL_PCI_BAR);
  1110. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1111. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1112. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1113. if (!tgt->ctx_base)
  1114. return -ENOMEM;
  1115. return 0;
  1116. }
  1117. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1118. {
  1119. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1120. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1121. return NULL;
  1122. tgt->rq_cons_idx += num_items;
  1123. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1124. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1125. return buf;
  1126. }
  1127. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1128. {
  1129. /* return the rq buffer */
  1130. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1131. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1132. /* Wrap around RQ */
  1133. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1134. }
  1135. tgt->rq_prod_idx = next_prod_idx;
  1136. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1137. }
  1138. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1139. struct fcoe_task_ctx_entry *task,
  1140. u16 orig_xid)
  1141. {
  1142. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1143. struct bnx2fc_rport *tgt = io_req->tgt;
  1144. u32 context_id = tgt->context_id;
  1145. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1146. /* Tx Write Rx Read */
  1147. /* init flags */
  1148. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1149. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1150. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1151. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1152. task->txwr_rxrd.const_ctx.init_flags |=
  1153. FCOE_TASK_DEV_TYPE_DISK <<
  1154. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1155. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1156. /* Tx flags */
  1157. task->txwr_rxrd.const_ctx.tx_flags =
  1158. FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1159. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1160. /* Rx Read Tx Write */
  1161. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1162. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1163. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1164. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1165. }
  1166. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1167. struct fcoe_task_ctx_entry *task)
  1168. {
  1169. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1170. struct bnx2fc_rport *tgt = io_req->tgt;
  1171. struct fc_frame_header *fc_hdr;
  1172. struct fcoe_ext_mul_sges_ctx *sgl;
  1173. u8 task_type = 0;
  1174. u64 *hdr;
  1175. u64 temp_hdr[3];
  1176. u32 context_id;
  1177. /* Obtain task_type */
  1178. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1179. (io_req->cmd_type == BNX2FC_ELS)) {
  1180. task_type = FCOE_TASK_TYPE_MIDPATH;
  1181. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1182. task_type = FCOE_TASK_TYPE_ABTS;
  1183. }
  1184. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1185. /* Setup the task from io_req for easy reference */
  1186. io_req->task = task;
  1187. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1188. io_req->cmd_type, task_type);
  1189. /* Tx only */
  1190. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1191. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1192. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1193. (u32)mp_req->mp_req_bd_dma;
  1194. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1195. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1196. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
  1197. }
  1198. /* Tx Write Rx Read */
  1199. /* init flags */
  1200. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1201. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1202. task->txwr_rxrd.const_ctx.init_flags |=
  1203. FCOE_TASK_DEV_TYPE_DISK <<
  1204. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1205. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1206. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1207. /* tx flags */
  1208. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1209. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1210. /* Rx Write Tx Read */
  1211. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1212. /* rx flags */
  1213. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1214. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1215. context_id = tgt->context_id;
  1216. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1217. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1218. fc_hdr = &(mp_req->req_fc_hdr);
  1219. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1220. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1221. fc_hdr->fh_rx_id = htons(0xffff);
  1222. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1223. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1224. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1225. }
  1226. /* Fill FC Header into middle path buffer */
  1227. hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
  1228. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1229. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1230. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1231. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1232. /* Rx Only */
  1233. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1234. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1235. sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
  1236. sgl->mul_sgl.cur_sge_addr.hi =
  1237. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1238. sgl->mul_sgl.sgl_size = 1;
  1239. }
  1240. }
  1241. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1242. struct fcoe_task_ctx_entry *task)
  1243. {
  1244. u8 task_type;
  1245. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1246. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1247. struct bnx2fc_rport *tgt = io_req->tgt;
  1248. struct fcoe_cached_sge_ctx *cached_sge;
  1249. struct fcoe_ext_mul_sges_ctx *sgl;
  1250. u64 *fcp_cmnd;
  1251. u64 tmp_fcp_cmnd[4];
  1252. u32 context_id;
  1253. int cnt, i;
  1254. int bd_count;
  1255. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1256. /* Setup the task from io_req for easy reference */
  1257. io_req->task = task;
  1258. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1259. task_type = FCOE_TASK_TYPE_WRITE;
  1260. else
  1261. task_type = FCOE_TASK_TYPE_READ;
  1262. /* Tx only */
  1263. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1264. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1265. (u32)bd_tbl->bd_tbl_dma;
  1266. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1267. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1268. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1269. bd_tbl->bd_valid;
  1270. }
  1271. /*Tx Write Rx Read */
  1272. /* Init state to NORMAL */
  1273. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1274. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1275. task->txwr_rxrd.const_ctx.init_flags |=
  1276. FCOE_TASK_DEV_TYPE_DISK <<
  1277. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1278. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1279. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1280. /* tx flags */
  1281. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1282. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1283. /* Set initial seq counter */
  1284. task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
  1285. /* Fill FCP_CMND IU */
  1286. fcp_cmnd = (u64 *)
  1287. task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
  1288. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1289. /* swap fcp_cmnd */
  1290. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1291. for (i = 0; i < cnt; i++) {
  1292. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1293. fcp_cmnd++;
  1294. }
  1295. /* Rx Write Tx Read */
  1296. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1297. context_id = tgt->context_id;
  1298. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1299. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1300. /* rx flags */
  1301. /* Set state to "waiting for the first packet" */
  1302. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1303. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1304. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1305. /* Rx Only */
  1306. cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
  1307. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1308. bd_count = bd_tbl->bd_valid;
  1309. if (task_type == FCOE_TASK_TYPE_READ) {
  1310. if (bd_count == 1) {
  1311. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1312. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1313. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1314. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1315. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1316. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1317. } else if (bd_count == 2) {
  1318. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1319. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1320. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1321. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1322. fcoe_bd_tbl++;
  1323. cached_sge->second_buf_addr.lo =
  1324. fcoe_bd_tbl->buf_addr_lo;
  1325. cached_sge->second_buf_addr.hi =
  1326. fcoe_bd_tbl->buf_addr_hi;
  1327. cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
  1328. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1329. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1330. } else {
  1331. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1332. sgl->mul_sgl.cur_sge_addr.hi =
  1333. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1334. sgl->mul_sgl.sgl_size = bd_count;
  1335. }
  1336. }
  1337. }
  1338. /**
  1339. * bnx2fc_setup_task_ctx - allocate and map task context
  1340. *
  1341. * @hba: pointer to adapter structure
  1342. *
  1343. * allocate memory for task context, and associated BD table to be used
  1344. * by firmware
  1345. *
  1346. */
  1347. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1348. {
  1349. int rc = 0;
  1350. struct regpair *task_ctx_bdt;
  1351. dma_addr_t addr;
  1352. int i;
  1353. /*
  1354. * Allocate task context bd table. A page size of bd table
  1355. * can map 256 buffers. Each buffer contains 32 task context
  1356. * entries. Hence the limit with one page is 8192 task context
  1357. * entries.
  1358. */
  1359. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1360. PAGE_SIZE,
  1361. &hba->task_ctx_bd_dma,
  1362. GFP_KERNEL);
  1363. if (!hba->task_ctx_bd_tbl) {
  1364. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1365. rc = -1;
  1366. goto out;
  1367. }
  1368. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1369. /*
  1370. * Allocate task_ctx which is an array of pointers pointing to
  1371. * a page containing 32 task contexts
  1372. */
  1373. hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
  1374. GFP_KERNEL);
  1375. if (!hba->task_ctx) {
  1376. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1377. rc = -1;
  1378. goto out1;
  1379. }
  1380. /*
  1381. * Allocate task_ctx_dma which is an array of dma addresses
  1382. */
  1383. hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
  1384. sizeof(dma_addr_t)), GFP_KERNEL);
  1385. if (!hba->task_ctx_dma) {
  1386. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1387. rc = -1;
  1388. goto out2;
  1389. }
  1390. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1391. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1392. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1393. PAGE_SIZE,
  1394. &hba->task_ctx_dma[i],
  1395. GFP_KERNEL);
  1396. if (!hba->task_ctx[i]) {
  1397. printk(KERN_ERR PFX "unable to alloc task context\n");
  1398. rc = -1;
  1399. goto out3;
  1400. }
  1401. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1402. addr = (u64)hba->task_ctx_dma[i];
  1403. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1404. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1405. task_ctx_bdt++;
  1406. }
  1407. return 0;
  1408. out3:
  1409. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1410. if (hba->task_ctx[i]) {
  1411. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1412. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1413. hba->task_ctx[i] = NULL;
  1414. }
  1415. }
  1416. kfree(hba->task_ctx_dma);
  1417. hba->task_ctx_dma = NULL;
  1418. out2:
  1419. kfree(hba->task_ctx);
  1420. hba->task_ctx = NULL;
  1421. out1:
  1422. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1423. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1424. hba->task_ctx_bd_tbl = NULL;
  1425. out:
  1426. return rc;
  1427. }
  1428. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1429. {
  1430. int i;
  1431. if (hba->task_ctx_bd_tbl) {
  1432. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1433. hba->task_ctx_bd_tbl,
  1434. hba->task_ctx_bd_dma);
  1435. hba->task_ctx_bd_tbl = NULL;
  1436. }
  1437. if (hba->task_ctx) {
  1438. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1439. if (hba->task_ctx[i]) {
  1440. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1441. hba->task_ctx[i],
  1442. hba->task_ctx_dma[i]);
  1443. hba->task_ctx[i] = NULL;
  1444. }
  1445. }
  1446. kfree(hba->task_ctx);
  1447. hba->task_ctx = NULL;
  1448. }
  1449. kfree(hba->task_ctx_dma);
  1450. hba->task_ctx_dma = NULL;
  1451. }
  1452. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1453. {
  1454. int i;
  1455. int segment_count;
  1456. int hash_table_size;
  1457. u32 *pbl;
  1458. segment_count = hba->hash_tbl_segment_count;
  1459. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1460. sizeof(struct fcoe_hash_table_entry);
  1461. pbl = hba->hash_tbl_pbl;
  1462. for (i = 0; i < segment_count; ++i) {
  1463. dma_addr_t dma_address;
  1464. dma_address = le32_to_cpu(*pbl);
  1465. ++pbl;
  1466. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1467. ++pbl;
  1468. dma_free_coherent(&hba->pcidev->dev,
  1469. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1470. hba->hash_tbl_segments[i],
  1471. dma_address);
  1472. }
  1473. if (hba->hash_tbl_pbl) {
  1474. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1475. hba->hash_tbl_pbl,
  1476. hba->hash_tbl_pbl_dma);
  1477. hba->hash_tbl_pbl = NULL;
  1478. }
  1479. }
  1480. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1481. {
  1482. int i;
  1483. int hash_table_size;
  1484. int segment_count;
  1485. int segment_array_size;
  1486. int dma_segment_array_size;
  1487. dma_addr_t *dma_segment_array;
  1488. u32 *pbl;
  1489. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1490. sizeof(struct fcoe_hash_table_entry);
  1491. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1492. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1493. hba->hash_tbl_segment_count = segment_count;
  1494. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1495. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1496. if (!hba->hash_tbl_segments) {
  1497. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1498. return -ENOMEM;
  1499. }
  1500. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1501. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1502. if (!dma_segment_array) {
  1503. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1504. return -ENOMEM;
  1505. }
  1506. for (i = 0; i < segment_count; ++i) {
  1507. hba->hash_tbl_segments[i] =
  1508. dma_alloc_coherent(&hba->pcidev->dev,
  1509. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1510. &dma_segment_array[i],
  1511. GFP_KERNEL);
  1512. if (!hba->hash_tbl_segments[i]) {
  1513. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1514. while (--i >= 0) {
  1515. dma_free_coherent(&hba->pcidev->dev,
  1516. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1517. hba->hash_tbl_segments[i],
  1518. dma_segment_array[i]);
  1519. hba->hash_tbl_segments[i] = NULL;
  1520. }
  1521. kfree(dma_segment_array);
  1522. return -ENOMEM;
  1523. }
  1524. memset(hba->hash_tbl_segments[i], 0,
  1525. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1526. }
  1527. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1528. PAGE_SIZE,
  1529. &hba->hash_tbl_pbl_dma,
  1530. GFP_KERNEL);
  1531. if (!hba->hash_tbl_pbl) {
  1532. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1533. kfree(dma_segment_array);
  1534. return -ENOMEM;
  1535. }
  1536. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1537. pbl = hba->hash_tbl_pbl;
  1538. for (i = 0; i < segment_count; ++i) {
  1539. u64 paddr = dma_segment_array[i];
  1540. *pbl = cpu_to_le32((u32) paddr);
  1541. ++pbl;
  1542. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1543. ++pbl;
  1544. }
  1545. pbl = hba->hash_tbl_pbl;
  1546. i = 0;
  1547. while (*pbl && *(pbl + 1)) {
  1548. u32 lo;
  1549. u32 hi;
  1550. lo = *pbl;
  1551. ++pbl;
  1552. hi = *pbl;
  1553. ++pbl;
  1554. ++i;
  1555. }
  1556. kfree(dma_segment_array);
  1557. return 0;
  1558. }
  1559. /**
  1560. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1561. *
  1562. * @hba: Pointer to adapter structure
  1563. *
  1564. */
  1565. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1566. {
  1567. u64 addr;
  1568. u32 mem_size;
  1569. int i;
  1570. if (bnx2fc_allocate_hash_table(hba))
  1571. return -ENOMEM;
  1572. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1573. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1574. &hba->t2_hash_tbl_ptr_dma,
  1575. GFP_KERNEL);
  1576. if (!hba->t2_hash_tbl_ptr) {
  1577. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1578. bnx2fc_free_fw_resc(hba);
  1579. return -ENOMEM;
  1580. }
  1581. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1582. mem_size = BNX2FC_NUM_MAX_SESS *
  1583. sizeof(struct fcoe_t2_hash_table_entry);
  1584. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1585. &hba->t2_hash_tbl_dma,
  1586. GFP_KERNEL);
  1587. if (!hba->t2_hash_tbl) {
  1588. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1589. bnx2fc_free_fw_resc(hba);
  1590. return -ENOMEM;
  1591. }
  1592. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1593. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1594. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1595. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1596. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1597. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1598. }
  1599. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1600. PAGE_SIZE, &hba->dummy_buf_dma,
  1601. GFP_KERNEL);
  1602. if (!hba->dummy_buffer) {
  1603. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1604. bnx2fc_free_fw_resc(hba);
  1605. return -ENOMEM;
  1606. }
  1607. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1608. PAGE_SIZE,
  1609. &hba->stats_buf_dma,
  1610. GFP_KERNEL);
  1611. if (!hba->stats_buffer) {
  1612. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1613. bnx2fc_free_fw_resc(hba);
  1614. return -ENOMEM;
  1615. }
  1616. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1617. return 0;
  1618. }
  1619. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1620. {
  1621. u32 mem_size;
  1622. if (hba->stats_buffer) {
  1623. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1624. hba->stats_buffer, hba->stats_buf_dma);
  1625. hba->stats_buffer = NULL;
  1626. }
  1627. if (hba->dummy_buffer) {
  1628. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1629. hba->dummy_buffer, hba->dummy_buf_dma);
  1630. hba->dummy_buffer = NULL;
  1631. }
  1632. if (hba->t2_hash_tbl_ptr) {
  1633. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1634. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1635. hba->t2_hash_tbl_ptr,
  1636. hba->t2_hash_tbl_ptr_dma);
  1637. hba->t2_hash_tbl_ptr = NULL;
  1638. }
  1639. if (hba->t2_hash_tbl) {
  1640. mem_size = BNX2FC_NUM_MAX_SESS *
  1641. sizeof(struct fcoe_t2_hash_table_entry);
  1642. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1643. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1644. hba->t2_hash_tbl = NULL;
  1645. }
  1646. bnx2fc_free_hash_table(hba);
  1647. }