solos-pci.c 30 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define DATA_RAM_SIZE 32768
  55. #define BUF_SIZE 4096
  56. #define FPGA_PAGE 528 /* FPGA flash page size*/
  57. #define SOLOS_PAGE 512 /* Solos flash page size*/
  58. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  59. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  60. #define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
  61. #define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
  62. static int debug = 0;
  63. static int atmdebug = 0;
  64. static int firmware_upgrade = 0;
  65. static int fpga_upgrade = 0;
  66. struct pkt_hdr {
  67. __le16 size;
  68. __le16 vpi;
  69. __le16 vci;
  70. __le16 type;
  71. };
  72. #define PKT_DATA 0
  73. #define PKT_COMMAND 1
  74. #define PKT_POPEN 3
  75. #define PKT_PCLOSE 4
  76. #define PKT_STATUS 5
  77. struct solos_card {
  78. void __iomem *config_regs;
  79. void __iomem *buffers;
  80. int nr_ports;
  81. struct pci_dev *dev;
  82. struct atm_dev *atmdev[4];
  83. struct tasklet_struct tlet;
  84. spinlock_t tx_lock;
  85. spinlock_t tx_queue_lock;
  86. spinlock_t cli_queue_lock;
  87. spinlock_t param_queue_lock;
  88. struct list_head param_queue;
  89. struct sk_buff_head tx_queue[4];
  90. struct sk_buff_head cli_queue[4];
  91. wait_queue_head_t param_wq;
  92. wait_queue_head_t fw_wq;
  93. };
  94. struct solos_param {
  95. struct list_head list;
  96. pid_t pid;
  97. int port;
  98. struct sk_buff *response;
  99. wait_queue_head_t wq;
  100. };
  101. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  102. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  103. MODULE_DESCRIPTION("Solos PCI driver");
  104. MODULE_VERSION(VERSION);
  105. MODULE_LICENSE("GPL");
  106. MODULE_PARM_DESC(debug, "Enable Loopback");
  107. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  108. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  109. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  110. module_param(debug, int, 0444);
  111. module_param(atmdebug, int, 0644);
  112. module_param(firmware_upgrade, int, 0444);
  113. module_param(fpga_upgrade, int, 0444);
  114. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  115. struct atm_vcc *vcc);
  116. static int fpga_tx(struct solos_card *);
  117. static irqreturn_t solos_irq(int irq, void *dev_id);
  118. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  119. static int list_vccs(int vci);
  120. static void release_vccs(struct atm_dev *dev);
  121. static int atm_init(struct solos_card *);
  122. static void atm_remove(struct solos_card *);
  123. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  124. static void solos_bh(unsigned long);
  125. static int print_buffer(struct sk_buff *buf);
  126. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  127. {
  128. if (vcc->pop)
  129. vcc->pop(vcc, skb);
  130. else
  131. dev_kfree_skb_any(skb);
  132. }
  133. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  134. char *buf)
  135. {
  136. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  137. struct solos_card *card = atmdev->dev_data;
  138. struct solos_param prm;
  139. struct sk_buff *skb;
  140. struct pkt_hdr *header;
  141. int buflen;
  142. buflen = strlen(attr->attr.name) + 10;
  143. skb = alloc_skb(buflen, GFP_KERNEL);
  144. if (!skb) {
  145. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  146. return -ENOMEM;
  147. }
  148. header = (void *)skb_put(skb, sizeof(*header));
  149. buflen = snprintf((void *)&header[1], buflen - 1,
  150. "L%05d\n%s\n", current->pid, attr->attr.name);
  151. skb_put(skb, buflen);
  152. header->size = cpu_to_le16(buflen);
  153. header->vpi = cpu_to_le16(0);
  154. header->vci = cpu_to_le16(0);
  155. header->type = cpu_to_le16(PKT_COMMAND);
  156. prm.pid = current->pid;
  157. prm.response = NULL;
  158. prm.port = SOLOS_CHAN(atmdev);
  159. spin_lock_irq(&card->param_queue_lock);
  160. list_add(&prm.list, &card->param_queue);
  161. spin_unlock_irq(&card->param_queue_lock);
  162. fpga_queue(card, prm.port, skb, NULL);
  163. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  164. spin_lock_irq(&card->param_queue_lock);
  165. list_del(&prm.list);
  166. spin_unlock_irq(&card->param_queue_lock);
  167. if (!prm.response)
  168. return -EIO;
  169. buflen = prm.response->len;
  170. memcpy(buf, prm.response->data, buflen);
  171. kfree_skb(prm.response);
  172. return buflen;
  173. }
  174. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  175. const char *buf, size_t count)
  176. {
  177. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  178. struct solos_card *card = atmdev->dev_data;
  179. struct solos_param prm;
  180. struct sk_buff *skb;
  181. struct pkt_hdr *header;
  182. int buflen;
  183. ssize_t ret;
  184. buflen = strlen(attr->attr.name) + 11 + count;
  185. skb = alloc_skb(buflen, GFP_KERNEL);
  186. if (!skb) {
  187. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  188. return -ENOMEM;
  189. }
  190. header = (void *)skb_put(skb, sizeof(*header));
  191. buflen = snprintf((void *)&header[1], buflen - 1,
  192. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  193. skb_put(skb, buflen);
  194. header->size = cpu_to_le16(buflen);
  195. header->vpi = cpu_to_le16(0);
  196. header->vci = cpu_to_le16(0);
  197. header->type = cpu_to_le16(PKT_COMMAND);
  198. prm.pid = current->pid;
  199. prm.response = NULL;
  200. prm.port = SOLOS_CHAN(atmdev);
  201. spin_lock_irq(&card->param_queue_lock);
  202. list_add(&prm.list, &card->param_queue);
  203. spin_unlock_irq(&card->param_queue_lock);
  204. fpga_queue(card, prm.port, skb, NULL);
  205. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  206. spin_lock_irq(&card->param_queue_lock);
  207. list_del(&prm.list);
  208. spin_unlock_irq(&card->param_queue_lock);
  209. skb = prm.response;
  210. if (!skb)
  211. return -EIO;
  212. buflen = skb->len;
  213. /* Sometimes it has a newline, sometimes it doesn't. */
  214. if (skb->data[buflen - 1] == '\n')
  215. buflen--;
  216. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  217. ret = count;
  218. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  219. ret = -EIO;
  220. else {
  221. /* We know we have enough space allocated for this; we allocated
  222. it ourselves */
  223. skb->data[buflen] = 0;
  224. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  225. skb->data);
  226. ret = -EIO;
  227. }
  228. kfree_skb(skb);
  229. return ret;
  230. }
  231. static char *next_string(struct sk_buff *skb)
  232. {
  233. int i = 0;
  234. char *this = skb->data;
  235. while (i < skb->len) {
  236. if (this[i] == '\n') {
  237. this[i] = 0;
  238. skb_pull(skb, i);
  239. return this;
  240. }
  241. }
  242. return NULL;
  243. }
  244. /*
  245. * Status packet has fields separated by \n, starting with a version number
  246. * for the information therein. Fields are....
  247. *
  248. * packet version
  249. * TxBitRate (version >= 1)
  250. * RxBitRate (version >= 1)
  251. * State (version >= 1)
  252. */
  253. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  254. {
  255. char *str, *end;
  256. int ver, rate_up, rate_down, state;
  257. if (!card->atmdev[port])
  258. return -ENODEV;
  259. str = next_string(skb);
  260. if (!str)
  261. return -EIO;
  262. ver = simple_strtol(str, NULL, 10);
  263. if (ver < 1) {
  264. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  265. ver);
  266. return -EIO;
  267. }
  268. str = next_string(skb);
  269. rate_up = simple_strtol(str, &end, 10);
  270. if (*end)
  271. return -EIO;
  272. str = next_string(skb);
  273. rate_down = simple_strtol(str, &end, 10);
  274. if (*end)
  275. return -EIO;
  276. str = next_string(skb);
  277. if (!strcmp(str, "Showtime"))
  278. state = ATM_PHY_SIG_FOUND;
  279. else {
  280. state = ATM_PHY_SIG_LOST;
  281. release_vccs(card->atmdev[port]);
  282. }
  283. card->atmdev[port]->link_rate = rate_down;
  284. card->atmdev[port]->signal = state;
  285. dev_info(&card->dev->dev, "ATM state: '%s', %d/%d kb/s up/down.\n",
  286. str, rate_up/1000, rate_down/1000);
  287. return 0;
  288. }
  289. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  290. {
  291. struct solos_param *prm;
  292. unsigned long flags;
  293. int cmdpid;
  294. int found = 0;
  295. if (skb->len < 7)
  296. return 0;
  297. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  298. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  299. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  300. skb->data[6] != '\n')
  301. return 0;
  302. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  303. spin_lock_irqsave(&card->param_queue_lock, flags);
  304. list_for_each_entry(prm, &card->param_queue, list) {
  305. if (prm->port == port && prm->pid == cmdpid) {
  306. prm->response = skb;
  307. skb_pull(skb, 7);
  308. wake_up(&card->param_wq);
  309. found = 1;
  310. break;
  311. }
  312. }
  313. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  314. return found;
  315. }
  316. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  317. char *buf)
  318. {
  319. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  320. struct solos_card *card = atmdev->dev_data;
  321. struct sk_buff *skb;
  322. spin_lock(&card->cli_queue_lock);
  323. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  324. spin_unlock(&card->cli_queue_lock);
  325. if(skb == NULL)
  326. return sprintf(buf, "No data.\n");
  327. memcpy(buf, skb->data, skb->len);
  328. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  329. kfree_skb(skb);
  330. return skb->len;
  331. }
  332. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  333. {
  334. struct sk_buff *skb;
  335. struct pkt_hdr *header;
  336. // dev_dbg(&card->dev->dev, "size: %d\n", size);
  337. if (size > (BUF_SIZE - sizeof(*header))) {
  338. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  339. return 0;
  340. }
  341. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  342. if (!skb) {
  343. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  344. return 0;
  345. }
  346. header = (void *)skb_put(skb, sizeof(*header));
  347. header->size = cpu_to_le16(size);
  348. header->vpi = cpu_to_le16(0);
  349. header->vci = cpu_to_le16(0);
  350. header->type = cpu_to_le16(PKT_COMMAND);
  351. memcpy(skb_put(skb, size), buf, size);
  352. fpga_queue(card, dev, skb, NULL);
  353. return 0;
  354. }
  355. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  356. const char *buf, size_t count)
  357. {
  358. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  359. struct solos_card *card = atmdev->dev_data;
  360. int err;
  361. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  362. return err?:count;
  363. }
  364. static DEVICE_ATTR(console, 0644, console_show, console_store);
  365. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  366. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  367. #include "solos-attrlist.c"
  368. #undef SOLOS_ATTR_RO
  369. #undef SOLOS_ATTR_RW
  370. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  371. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  372. static struct attribute *solos_attrs[] = {
  373. #include "solos-attrlist.c"
  374. NULL
  375. };
  376. static struct attribute_group solos_attr_group = {
  377. .attrs = solos_attrs,
  378. .name = "parameters",
  379. };
  380. static int flash_upgrade(struct solos_card *card, int chip)
  381. {
  382. const struct firmware *fw;
  383. const char *fw_name;
  384. uint32_t data32 = 0;
  385. int blocksize = 0;
  386. int numblocks = 0;
  387. int offset;
  388. if (chip == 0) {
  389. fw_name = "solos-FPGA.bin";
  390. blocksize = FPGA_BLOCK;
  391. } else {
  392. fw_name = "solos-Firmware.bin";
  393. blocksize = SOLOS_BLOCK;
  394. }
  395. if (request_firmware(&fw, fw_name, &card->dev->dev))
  396. return -ENOENT;
  397. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  398. numblocks = fw->size / blocksize;
  399. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  400. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  401. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  402. iowrite32(1, card->config_regs + FPGA_MODE);
  403. data32 = ioread32(card->config_regs + FPGA_MODE);
  404. /* Set mode to Chip Erase */
  405. dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
  406. chip?"Solos":"FPGA");
  407. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  408. iowrite32(1, card->config_regs + WRITE_FLASH);
  409. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  410. for (offset = 0; offset < fw->size; offset += blocksize) {
  411. int i;
  412. /* Clear write flag */
  413. iowrite32(0, card->config_regs + WRITE_FLASH);
  414. /* Set mode to Block Write */
  415. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  416. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  417. /* Copy block to buffer, swapping each 16 bits */
  418. for(i = 0; i < blocksize; i += 4) {
  419. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  420. iowrite32(word, RX_BUF(card, 3) + i);
  421. }
  422. /* Specify block number and then trigger flash write */
  423. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  424. iowrite32(1, card->config_regs + WRITE_FLASH);
  425. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  426. }
  427. release_firmware(fw);
  428. iowrite32(0, card->config_regs + WRITE_FLASH);
  429. iowrite32(0, card->config_regs + FPGA_MODE);
  430. iowrite32(0, card->config_regs + FLASH_MODE);
  431. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  432. return 0;
  433. }
  434. static irqreturn_t solos_irq(int irq, void *dev_id)
  435. {
  436. struct solos_card *card = dev_id;
  437. int handled = 1;
  438. //ACK IRQ
  439. iowrite32(0, card->config_regs + IRQ_CLEAR);
  440. //Disable IRQs from FPGA
  441. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  442. if (card->atmdev[0])
  443. tasklet_schedule(&card->tlet);
  444. else
  445. wake_up(&card->fw_wq);
  446. //Enable IRQs from FPGA
  447. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  448. return IRQ_RETVAL(handled);
  449. }
  450. void solos_bh(unsigned long card_arg)
  451. {
  452. struct solos_card *card = (void *)card_arg;
  453. int port;
  454. uint32_t card_flags;
  455. uint32_t tx_mask;
  456. uint32_t rx_done = 0;
  457. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  458. /* The TX bits are set if the channel is busy; clear if not. We want to
  459. invoke fpga_tx() unless _all_ the bits for active channels are set */
  460. tx_mask = (1 << card->nr_ports) - 1;
  461. if ((card_flags & tx_mask) != tx_mask)
  462. fpga_tx(card);
  463. for (port = 0; port < card->nr_ports; port++) {
  464. if (card_flags & (0x10 << port)) {
  465. struct pkt_hdr header;
  466. struct sk_buff *skb;
  467. struct atm_vcc *vcc;
  468. int size;
  469. rx_done |= 0x10 << port;
  470. memcpy_fromio(&header, RX_BUF(card, port), sizeof(header));
  471. size = le16_to_cpu(header.size);
  472. skb = alloc_skb(size + 1, GFP_ATOMIC);
  473. if (!skb) {
  474. if (net_ratelimit())
  475. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  476. continue;
  477. }
  478. memcpy_fromio(skb_put(skb, size),
  479. RX_BUF(card, port) + sizeof(header),
  480. size);
  481. if (atmdebug) {
  482. dev_info(&card->dev->dev, "Received: device %d\n", port);
  483. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  484. size, le16_to_cpu(header.vpi),
  485. le16_to_cpu(header.vci));
  486. print_buffer(skb);
  487. }
  488. switch (le16_to_cpu(header.type)) {
  489. case PKT_DATA:
  490. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header.vpi),
  491. le16_to_cpu(header.vci));
  492. if (!vcc) {
  493. if (net_ratelimit())
  494. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  495. le16_to_cpu(header.vci), le16_to_cpu(header.vpi),
  496. port);
  497. continue;
  498. }
  499. atm_charge(vcc, skb->truesize);
  500. vcc->push(vcc, skb);
  501. atomic_inc(&vcc->stats->rx);
  502. break;
  503. case PKT_STATUS:
  504. process_status(card, port, skb);
  505. dev_kfree_skb(skb);
  506. break;
  507. case PKT_COMMAND:
  508. default: /* FIXME: Not really, surely? */
  509. if (process_command(card, port, skb))
  510. break;
  511. spin_lock(&card->cli_queue_lock);
  512. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  513. if (net_ratelimit())
  514. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  515. port);
  516. } else
  517. skb_queue_tail(&card->cli_queue[port], skb);
  518. spin_unlock(&card->cli_queue_lock);
  519. break;
  520. }
  521. }
  522. }
  523. if (rx_done)
  524. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  525. return;
  526. }
  527. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  528. {
  529. struct hlist_head *head;
  530. struct atm_vcc *vcc = NULL;
  531. struct hlist_node *node;
  532. struct sock *s;
  533. read_lock(&vcc_sklist_lock);
  534. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  535. sk_for_each(s, node, head) {
  536. vcc = atm_sk(s);
  537. if (vcc->dev == dev && vcc->vci == vci &&
  538. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  539. goto out;
  540. }
  541. vcc = NULL;
  542. out:
  543. read_unlock(&vcc_sklist_lock);
  544. return vcc;
  545. }
  546. static int list_vccs(int vci)
  547. {
  548. struct hlist_head *head;
  549. struct atm_vcc *vcc;
  550. struct hlist_node *node;
  551. struct sock *s;
  552. int num_found = 0;
  553. int i;
  554. read_lock(&vcc_sklist_lock);
  555. if (vci != 0){
  556. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  557. sk_for_each(s, node, head) {
  558. num_found ++;
  559. vcc = atm_sk(s);
  560. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  561. vcc->dev->number,
  562. vcc->vpi,
  563. vcc->vci);
  564. }
  565. } else {
  566. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  567. head = &vcc_hash[i];
  568. sk_for_each(s, node, head) {
  569. num_found ++;
  570. vcc = atm_sk(s);
  571. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  572. vcc->dev->number,
  573. vcc->vpi,
  574. vcc->vci);
  575. }
  576. }
  577. }
  578. read_unlock(&vcc_sklist_lock);
  579. return num_found;
  580. }
  581. static void release_vccs(struct atm_dev *dev)
  582. {
  583. int i;
  584. write_lock_irq(&vcc_sklist_lock);
  585. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  586. struct hlist_head *head = &vcc_hash[i];
  587. struct hlist_node *node, *tmp;
  588. struct sock *s;
  589. struct atm_vcc *vcc;
  590. sk_for_each_safe(s, node, tmp, head) {
  591. vcc = atm_sk(s);
  592. if (vcc->dev == dev) {
  593. vcc_release_async(vcc, -EPIPE);
  594. sk_del_node_init(s);
  595. }
  596. }
  597. }
  598. write_unlock_irq(&vcc_sklist_lock);
  599. }
  600. static int popen(struct atm_vcc *vcc)
  601. {
  602. struct solos_card *card = vcc->dev->dev_data;
  603. struct sk_buff *skb;
  604. struct pkt_hdr *header;
  605. if (vcc->qos.aal != ATM_AAL5) {
  606. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  607. vcc->qos.aal);
  608. return -EINVAL;
  609. }
  610. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  611. if (!skb && net_ratelimit()) {
  612. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  613. return -ENOMEM;
  614. }
  615. header = (void *)skb_put(skb, sizeof(*header));
  616. header->size = cpu_to_le16(0);
  617. header->vpi = cpu_to_le16(vcc->vpi);
  618. header->vci = cpu_to_le16(vcc->vci);
  619. header->type = cpu_to_le16(PKT_POPEN);
  620. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  621. // dev_dbg(&card->dev->dev, "Open for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  622. set_bit(ATM_VF_ADDR, &vcc->flags); // accept the vpi / vci
  623. set_bit(ATM_VF_READY, &vcc->flags);
  624. list_vccs(0);
  625. return 0;
  626. }
  627. static void pclose(struct atm_vcc *vcc)
  628. {
  629. struct solos_card *card = vcc->dev->dev_data;
  630. struct sk_buff *skb;
  631. struct pkt_hdr *header;
  632. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  633. if (!skb) {
  634. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  635. return;
  636. }
  637. header = (void *)skb_put(skb, sizeof(*header));
  638. header->size = cpu_to_le16(0);
  639. header->vpi = cpu_to_le16(vcc->vpi);
  640. header->vci = cpu_to_le16(vcc->vci);
  641. header->type = cpu_to_le16(PKT_PCLOSE);
  642. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  643. // dev_dbg(&card->dev->dev, "Close for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  644. clear_bit(ATM_VF_ADDR, &vcc->flags);
  645. clear_bit(ATM_VF_READY, &vcc->flags);
  646. return;
  647. }
  648. static int print_buffer(struct sk_buff *buf)
  649. {
  650. int len,i;
  651. char msg[500];
  652. char item[10];
  653. len = buf->len;
  654. for (i = 0; i < len; i++){
  655. if(i % 8 == 0)
  656. sprintf(msg, "%02X: ", i);
  657. sprintf(item,"%02X ",*(buf->data + i));
  658. strcat(msg, item);
  659. if(i % 8 == 7) {
  660. sprintf(item, "\n");
  661. strcat(msg, item);
  662. printk(KERN_DEBUG "%s", msg);
  663. }
  664. }
  665. if (i % 8 != 0) {
  666. sprintf(item, "\n");
  667. strcat(msg, item);
  668. printk(KERN_DEBUG "%s", msg);
  669. }
  670. printk(KERN_DEBUG "\n");
  671. return 0;
  672. }
  673. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  674. struct atm_vcc *vcc)
  675. {
  676. int old_len;
  677. *(void **)skb->cb = vcc;
  678. spin_lock(&card->tx_queue_lock);
  679. old_len = skb_queue_len(&card->tx_queue[port]);
  680. skb_queue_tail(&card->tx_queue[port], skb);
  681. spin_unlock(&card->tx_queue_lock);
  682. /* If TX might need to be started, do so */
  683. if (!old_len)
  684. fpga_tx(card);
  685. }
  686. static int fpga_tx(struct solos_card *card)
  687. {
  688. uint32_t tx_pending;
  689. uint32_t tx_started = 0;
  690. struct sk_buff *skb;
  691. struct atm_vcc *vcc;
  692. unsigned char port;
  693. unsigned long flags;
  694. spin_lock_irqsave(&card->tx_lock, flags);
  695. tx_pending = ioread32(card->config_regs + FLAGS_ADDR);
  696. dev_vdbg(&card->dev->dev, "TX Flags are %X\n", tx_pending);
  697. for (port = 0; port < card->nr_ports; port++) {
  698. if (!(tx_pending & (1 << port))) {
  699. spin_lock(&card->tx_queue_lock);
  700. skb = skb_dequeue(&card->tx_queue[port]);
  701. spin_unlock(&card->tx_queue_lock);
  702. if (!skb)
  703. continue;
  704. if (atmdebug) {
  705. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  706. port);
  707. print_buffer(skb);
  708. }
  709. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  710. vcc = *(void **)skb->cb;
  711. if (vcc) {
  712. atomic_inc(&vcc->stats->tx);
  713. solos_pop(vcc, skb);
  714. } else
  715. dev_kfree_skb_irq(skb);
  716. tx_started |= 1 << port; //Set TX full flag
  717. }
  718. }
  719. if (tx_started)
  720. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  721. spin_unlock_irqrestore(&card->tx_lock, flags);
  722. return 0;
  723. }
  724. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  725. {
  726. struct solos_card *card = vcc->dev->dev_data;
  727. struct sk_buff *skb2 = NULL;
  728. struct pkt_hdr *header;
  729. int pktlen;
  730. //dev_dbg(&card->dev->dev, "psend called.\n");
  731. //dev_dbg(&card->dev->dev, "dev,vpi,vci = %d,%d,%d\n",SOLOS_CHAN(vcc->dev),vcc->vpi,vcc->vci);
  732. if (debug) {
  733. skb2 = atm_alloc_charge(vcc, skb->len, GFP_ATOMIC);
  734. if (skb2) {
  735. memcpy(skb2->data, skb->data, skb->len);
  736. skb_put(skb2, skb->len);
  737. vcc->push(vcc, skb2);
  738. atomic_inc(&vcc->stats->rx);
  739. }
  740. atomic_inc(&vcc->stats->tx);
  741. solos_pop(vcc, skb);
  742. return 0;
  743. }
  744. pktlen = skb->len;
  745. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  746. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  747. solos_pop(vcc, skb);
  748. return 0;
  749. }
  750. if (!skb_clone_writable(skb, sizeof(*header))) {
  751. int expand_by = 0;
  752. int ret;
  753. if (skb_headroom(skb) < sizeof(*header))
  754. expand_by = sizeof(*header) - skb_headroom(skb);
  755. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  756. if (ret) {
  757. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  758. solos_pop(vcc, skb);
  759. return ret;
  760. }
  761. }
  762. header = (void *)skb_push(skb, sizeof(*header));
  763. /* This does _not_ include the size of the header */
  764. header->size = cpu_to_le16(pktlen);
  765. header->vpi = cpu_to_le16(vcc->vpi);
  766. header->vci = cpu_to_le16(vcc->vci);
  767. header->type = cpu_to_le16(PKT_DATA);
  768. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  769. return 0;
  770. }
  771. static struct atmdev_ops fpga_ops = {
  772. .open = popen,
  773. .close = pclose,
  774. .ioctl = NULL,
  775. .getsockopt = NULL,
  776. .setsockopt = NULL,
  777. .send = psend,
  778. .send_oam = NULL,
  779. .phy_put = NULL,
  780. .phy_get = NULL,
  781. .change_qos = NULL,
  782. .proc_read = NULL,
  783. .owner = THIS_MODULE
  784. };
  785. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  786. {
  787. int err, i;
  788. uint16_t fpga_ver;
  789. uint8_t major_ver, minor_ver;
  790. uint32_t data32;
  791. struct solos_card *card;
  792. if (debug)
  793. return 0;
  794. card = kzalloc(sizeof(*card), GFP_KERNEL);
  795. if (!card)
  796. return -ENOMEM;
  797. card->dev = dev;
  798. init_waitqueue_head(&card->fw_wq);
  799. init_waitqueue_head(&card->param_wq);
  800. err = pci_enable_device(dev);
  801. if (err) {
  802. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  803. goto out;
  804. }
  805. err = pci_request_regions(dev, "solos");
  806. if (err) {
  807. dev_warn(&dev->dev, "Failed to request regions\n");
  808. goto out;
  809. }
  810. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  811. if (!card->config_regs) {
  812. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  813. goto out_release_regions;
  814. }
  815. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  816. if (!card->buffers) {
  817. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  818. goto out_unmap_config;
  819. }
  820. // for(i=0;i<64 ;i+=4){
  821. // data32=ioread32(card->buffers + i);
  822. // dev_dbg(&card->dev->dev, "%08lX\n",(unsigned long)data32);
  823. // }
  824. //Fill Config Mem with zeros
  825. for(i = 0; i < 128; i += 4)
  826. iowrite32(0, card->config_regs + i);
  827. //Set RX empty flags
  828. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  829. data32 = ioread32(card->config_regs + FPGA_VER);
  830. fpga_ver = (data32 & 0x0000FFFF);
  831. major_ver = ((data32 & 0xFF000000) >> 24);
  832. minor_ver = ((data32 & 0x00FF0000) >> 16);
  833. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  834. major_ver, minor_ver, fpga_ver);
  835. card->nr_ports = 2; /* FIXME: Detect daughterboard */
  836. pci_set_drvdata(dev, card);
  837. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  838. spin_lock_init(&card->tx_lock);
  839. spin_lock_init(&card->tx_queue_lock);
  840. spin_lock_init(&card->cli_queue_lock);
  841. spin_lock_init(&card->param_queue_lock);
  842. INIT_LIST_HEAD(&card->param_queue);
  843. /*
  844. // Set Loopback mode
  845. data32 = 0x00010000;
  846. iowrite32(data32,card->config_regs + FLAGS_ADDR);
  847. */
  848. /*
  849. // Fill Buffers with zeros
  850. for (i = 0; i < BUF_SIZE * 8; i += 4)
  851. iowrite32(0, card->buffers + i);
  852. */
  853. /*
  854. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  855. iowrite32(0x12345678, card->buffers + i + (0*BUF_SIZE));
  856. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  857. iowrite32(0xabcdef98, card->buffers + i + (1*BUF_SIZE));
  858. // Read Config Memory
  859. printk(KERN_DEBUG "Reading Config MEM\n");
  860. i = 0;
  861. for(i = 0; i < 16; i++) {
  862. data32=ioread32(card->buffers + i*(BUF_SIZE/2));
  863. printk(KERN_ALERT "Addr: %lX Data: %08lX\n",
  864. (unsigned long)(addr_start + i*(BUF_SIZE/2)),
  865. (unsigned long)data32);
  866. }
  867. */
  868. //dev_dbg(&card->dev->dev, "Requesting IRQ: %d\n",dev->irq);
  869. err = request_irq(dev->irq, solos_irq, IRQF_DISABLED|IRQF_SHARED,
  870. "solos-pci", card);
  871. if (err) {
  872. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  873. goto out_unmap_both;
  874. }
  875. // Enable IRQs
  876. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  877. if (fpga_upgrade)
  878. flash_upgrade(card, 0);
  879. if (firmware_upgrade)
  880. flash_upgrade(card, 1);
  881. err = atm_init(card);
  882. if (err)
  883. goto out_free_irq;
  884. return 0;
  885. out_free_irq:
  886. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  887. free_irq(dev->irq, card);
  888. tasklet_kill(&card->tlet);
  889. out_unmap_both:
  890. pci_set_drvdata(dev, NULL);
  891. pci_iounmap(dev, card->config_regs);
  892. out_unmap_config:
  893. pci_iounmap(dev, card->buffers);
  894. out_release_regions:
  895. pci_release_regions(dev);
  896. out:
  897. return err;
  898. }
  899. static int atm_init(struct solos_card *card)
  900. {
  901. int i;
  902. for (i = 0; i < card->nr_ports; i++) {
  903. struct sk_buff *skb;
  904. struct pkt_hdr *header;
  905. skb_queue_head_init(&card->tx_queue[i]);
  906. skb_queue_head_init(&card->cli_queue[i]);
  907. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  908. if (!card->atmdev[i]) {
  909. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  910. atm_remove(card);
  911. return -ENODEV;
  912. }
  913. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  914. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  915. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  916. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  917. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  918. card->atmdev[i]->ci_range.vpi_bits = 8;
  919. card->atmdev[i]->ci_range.vci_bits = 16;
  920. card->atmdev[i]->dev_data = card;
  921. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  922. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  923. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  924. if (!skb) {
  925. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  926. continue;
  927. }
  928. header = (void *)skb_put(skb, sizeof(*header));
  929. header->size = cpu_to_le16(0);
  930. header->vpi = cpu_to_le16(0);
  931. header->vci = cpu_to_le16(0);
  932. header->type = cpu_to_le16(PKT_STATUS);
  933. fpga_queue(card, i, skb, NULL);
  934. }
  935. return 0;
  936. }
  937. static void atm_remove(struct solos_card *card)
  938. {
  939. int i;
  940. for (i = 0; i < card->nr_ports; i++) {
  941. if (card->atmdev[i]) {
  942. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  943. atm_dev_deregister(card->atmdev[i]);
  944. }
  945. }
  946. }
  947. static void fpga_remove(struct pci_dev *dev)
  948. {
  949. struct solos_card *card = pci_get_drvdata(dev);
  950. if (debug)
  951. return;
  952. atm_remove(card);
  953. dev_vdbg(&dev->dev, "Freeing IRQ\n");
  954. // Disable IRQs from FPGA
  955. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  956. free_irq(dev->irq, card);
  957. tasklet_kill(&card->tlet);
  958. // iowrite32(0x01,pciregs);
  959. dev_vdbg(&dev->dev, "Unmapping PCI resource\n");
  960. pci_iounmap(dev, card->buffers);
  961. pci_iounmap(dev, card->config_regs);
  962. dev_vdbg(&dev->dev, "Releasing PCI Region\n");
  963. pci_release_regions(dev);
  964. pci_disable_device(dev);
  965. pci_set_drvdata(dev, NULL);
  966. kfree(card);
  967. // dev_dbg(&card->dev->dev, "fpga_remove\n");
  968. return;
  969. }
  970. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  971. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  972. { 0, }
  973. };
  974. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  975. static struct pci_driver fpga_driver = {
  976. .name = "solos",
  977. .id_table = fpga_pci_tbl,
  978. .probe = fpga_probe,
  979. .remove = fpga_remove,
  980. };
  981. static int __init solos_pci_init(void)
  982. {
  983. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  984. return pci_register_driver(&fpga_driver);
  985. }
  986. static void __exit solos_pci_exit(void)
  987. {
  988. pci_unregister_driver(&fpga_driver);
  989. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  990. }
  991. module_init(solos_pci_init);
  992. module_exit(solos_pci_exit);