s5p_mfc.c 40 KB

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  1. /*
  2. * Samsung S5P Multi Format Codec v 5.1
  3. *
  4. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  5. * Kamil Debski, <k.debski@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/sched.h>
  19. #include <linux/slab.h>
  20. #include <linux/videodev2.h>
  21. #include <media/v4l2-event.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/of.h>
  24. #include <media/videobuf2-core.h>
  25. #include "s5p_mfc_common.h"
  26. #include "s5p_mfc_ctrl.h"
  27. #include "s5p_mfc_debug.h"
  28. #include "s5p_mfc_dec.h"
  29. #include "s5p_mfc_enc.h"
  30. #include "s5p_mfc_intr.h"
  31. #include "s5p_mfc_opr.h"
  32. #include "s5p_mfc_cmd.h"
  33. #include "s5p_mfc_pm.h"
  34. #define S5P_MFC_NAME "s5p-mfc"
  35. #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
  36. #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
  37. int debug;
  38. module_param(debug, int, S_IRUGO | S_IWUSR);
  39. MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
  40. /* Helper functions for interrupt processing */
  41. /* Remove from hw execution round robin */
  42. void clear_work_bit(struct s5p_mfc_ctx *ctx)
  43. {
  44. struct s5p_mfc_dev *dev = ctx->dev;
  45. spin_lock(&dev->condlock);
  46. __clear_bit(ctx->num, &dev->ctx_work_bits);
  47. spin_unlock(&dev->condlock);
  48. }
  49. /* Add to hw execution round robin */
  50. void set_work_bit(struct s5p_mfc_ctx *ctx)
  51. {
  52. struct s5p_mfc_dev *dev = ctx->dev;
  53. spin_lock(&dev->condlock);
  54. __set_bit(ctx->num, &dev->ctx_work_bits);
  55. spin_unlock(&dev->condlock);
  56. }
  57. /* Remove from hw execution round robin */
  58. void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  59. {
  60. struct s5p_mfc_dev *dev = ctx->dev;
  61. unsigned long flags;
  62. spin_lock_irqsave(&dev->condlock, flags);
  63. __clear_bit(ctx->num, &dev->ctx_work_bits);
  64. spin_unlock_irqrestore(&dev->condlock, flags);
  65. }
  66. /* Add to hw execution round robin */
  67. void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  68. {
  69. struct s5p_mfc_dev *dev = ctx->dev;
  70. unsigned long flags;
  71. spin_lock_irqsave(&dev->condlock, flags);
  72. __set_bit(ctx->num, &dev->ctx_work_bits);
  73. spin_unlock_irqrestore(&dev->condlock, flags);
  74. }
  75. /* Wake up context wait_queue */
  76. static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
  77. unsigned int err)
  78. {
  79. ctx->int_cond = 1;
  80. ctx->int_type = reason;
  81. ctx->int_err = err;
  82. wake_up(&ctx->queue);
  83. }
  84. /* Wake up device wait_queue */
  85. static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
  86. unsigned int err)
  87. {
  88. dev->int_cond = 1;
  89. dev->int_type = reason;
  90. dev->int_err = err;
  91. wake_up(&dev->queue);
  92. }
  93. static void s5p_mfc_watchdog(unsigned long arg)
  94. {
  95. struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
  96. if (test_bit(0, &dev->hw_lock))
  97. atomic_inc(&dev->watchdog_cnt);
  98. if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
  99. /* This means that hw is busy and no interrupts were
  100. * generated by hw for the Nth time of running this
  101. * watchdog timer. This usually means a serious hw
  102. * error. Now it is time to kill all instances and
  103. * reset the MFC. */
  104. mfc_err("Time out during waiting for HW\n");
  105. queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
  106. }
  107. dev->watchdog_timer.expires = jiffies +
  108. msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
  109. add_timer(&dev->watchdog_timer);
  110. }
  111. static void s5p_mfc_watchdog_worker(struct work_struct *work)
  112. {
  113. struct s5p_mfc_dev *dev;
  114. struct s5p_mfc_ctx *ctx;
  115. unsigned long flags;
  116. int mutex_locked;
  117. int i, ret;
  118. dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
  119. mfc_err("Driver timeout error handling\n");
  120. /* Lock the mutex that protects open and release.
  121. * This is necessary as they may load and unload firmware. */
  122. mutex_locked = mutex_trylock(&dev->mfc_mutex);
  123. if (!mutex_locked)
  124. mfc_err("Error: some instance may be closing/opening\n");
  125. spin_lock_irqsave(&dev->irqlock, flags);
  126. s5p_mfc_clock_off();
  127. for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
  128. ctx = dev->ctx[i];
  129. if (!ctx)
  130. continue;
  131. ctx->state = MFCINST_ERROR;
  132. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
  133. &ctx->vq_dst);
  134. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
  135. &ctx->vq_src);
  136. clear_work_bit(ctx);
  137. wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
  138. }
  139. clear_bit(0, &dev->hw_lock);
  140. spin_unlock_irqrestore(&dev->irqlock, flags);
  141. /* Double check if there is at least one instance running.
  142. * If no instance is in memory than no firmware should be present */
  143. if (dev->num_inst > 0) {
  144. ret = s5p_mfc_reload_firmware(dev);
  145. if (ret) {
  146. mfc_err("Failed to reload FW\n");
  147. goto unlock;
  148. }
  149. s5p_mfc_clock_on();
  150. ret = s5p_mfc_init_hw(dev);
  151. if (ret)
  152. mfc_err("Failed to reinit FW\n");
  153. }
  154. unlock:
  155. if (mutex_locked)
  156. mutex_unlock(&dev->mfc_mutex);
  157. }
  158. static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file)
  159. {
  160. struct video_device *vdev = video_devdata(file);
  161. if (!vdev) {
  162. mfc_err("failed to get video_device");
  163. return MFCNODE_INVALID;
  164. }
  165. if (vdev->index == 0)
  166. return MFCNODE_DECODER;
  167. else if (vdev->index == 1)
  168. return MFCNODE_ENCODER;
  169. return MFCNODE_INVALID;
  170. }
  171. static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
  172. {
  173. mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
  174. mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
  175. mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
  176. }
  177. static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
  178. {
  179. struct s5p_mfc_buf *dst_buf;
  180. struct s5p_mfc_dev *dev = ctx->dev;
  181. ctx->state = MFCINST_FINISHED;
  182. ctx->sequence++;
  183. while (!list_empty(&ctx->dst_queue)) {
  184. dst_buf = list_entry(ctx->dst_queue.next,
  185. struct s5p_mfc_buf, list);
  186. mfc_debug(2, "Cleaning up buffer: %d\n",
  187. dst_buf->b->v4l2_buf.index);
  188. vb2_set_plane_payload(dst_buf->b, 0, 0);
  189. vb2_set_plane_payload(dst_buf->b, 1, 0);
  190. list_del(&dst_buf->list);
  191. ctx->dst_queue_cnt--;
  192. dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
  193. if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
  194. s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
  195. dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
  196. else
  197. dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
  198. ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
  199. vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
  200. }
  201. }
  202. static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
  203. {
  204. struct s5p_mfc_dev *dev = ctx->dev;
  205. struct s5p_mfc_buf *dst_buf, *src_buf;
  206. size_t dec_y_addr;
  207. unsigned int frame_type;
  208. dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
  209. frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
  210. /* Copy timestamp / timecode from decoded src to dst and set
  211. appropraite flags */
  212. src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
  213. list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
  214. if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
  215. memcpy(&dst_buf->b->v4l2_buf.timecode,
  216. &src_buf->b->v4l2_buf.timecode,
  217. sizeof(struct v4l2_timecode));
  218. memcpy(&dst_buf->b->v4l2_buf.timestamp,
  219. &src_buf->b->v4l2_buf.timestamp,
  220. sizeof(struct timeval));
  221. switch (frame_type) {
  222. case S5P_FIMV_DECODE_FRAME_I_FRAME:
  223. dst_buf->b->v4l2_buf.flags |=
  224. V4L2_BUF_FLAG_KEYFRAME;
  225. break;
  226. case S5P_FIMV_DECODE_FRAME_P_FRAME:
  227. dst_buf->b->v4l2_buf.flags |=
  228. V4L2_BUF_FLAG_PFRAME;
  229. break;
  230. case S5P_FIMV_DECODE_FRAME_B_FRAME:
  231. dst_buf->b->v4l2_buf.flags |=
  232. V4L2_BUF_FLAG_BFRAME;
  233. break;
  234. }
  235. break;
  236. }
  237. }
  238. }
  239. static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
  240. {
  241. struct s5p_mfc_dev *dev = ctx->dev;
  242. struct s5p_mfc_buf *dst_buf;
  243. size_t dspl_y_addr;
  244. unsigned int frame_type;
  245. unsigned int index;
  246. dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
  247. frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
  248. /* If frame is same as previous then skip and do not dequeue */
  249. if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
  250. if (!ctx->after_packed_pb)
  251. ctx->sequence++;
  252. ctx->after_packed_pb = 0;
  253. return;
  254. }
  255. ctx->sequence++;
  256. /* The MFC returns address of the buffer, now we have to
  257. * check which videobuf does it correspond to */
  258. list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
  259. /* Check if this is the buffer we're looking for */
  260. if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
  261. list_del(&dst_buf->list);
  262. ctx->dst_queue_cnt--;
  263. dst_buf->b->v4l2_buf.sequence = ctx->sequence;
  264. if (s5p_mfc_hw_call(dev->mfc_ops,
  265. get_pic_type_top, ctx) ==
  266. s5p_mfc_hw_call(dev->mfc_ops,
  267. get_pic_type_bot, ctx))
  268. dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
  269. else
  270. dst_buf->b->v4l2_buf.field =
  271. V4L2_FIELD_INTERLACED;
  272. vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
  273. vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
  274. clear_bit(dst_buf->b->v4l2_buf.index,
  275. &ctx->dec_dst_flag);
  276. vb2_buffer_done(dst_buf->b,
  277. err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  278. index = dst_buf->b->v4l2_buf.index;
  279. break;
  280. }
  281. }
  282. }
  283. /* Handle frame decoding interrupt */
  284. static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
  285. unsigned int reason, unsigned int err)
  286. {
  287. struct s5p_mfc_dev *dev = ctx->dev;
  288. unsigned int dst_frame_status;
  289. struct s5p_mfc_buf *src_buf;
  290. unsigned long flags;
  291. unsigned int res_change;
  292. unsigned int index;
  293. dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
  294. & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
  295. res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
  296. & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
  297. >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
  298. mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
  299. if (ctx->state == MFCINST_RES_CHANGE_INIT)
  300. ctx->state = MFCINST_RES_CHANGE_FLUSH;
  301. if (res_change == S5P_FIMV_RES_INCREASE ||
  302. res_change == S5P_FIMV_RES_DECREASE) {
  303. ctx->state = MFCINST_RES_CHANGE_INIT;
  304. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  305. wake_up_ctx(ctx, reason, err);
  306. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  307. BUG();
  308. s5p_mfc_clock_off();
  309. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  310. return;
  311. }
  312. if (ctx->dpb_flush_flag)
  313. ctx->dpb_flush_flag = 0;
  314. spin_lock_irqsave(&dev->irqlock, flags);
  315. /* All frames remaining in the buffer have been extracted */
  316. if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
  317. if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
  318. s5p_mfc_handle_frame_all_extracted(ctx);
  319. ctx->state = MFCINST_RES_CHANGE_END;
  320. goto leave_handle_frame;
  321. } else {
  322. s5p_mfc_handle_frame_all_extracted(ctx);
  323. }
  324. }
  325. if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
  326. dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
  327. s5p_mfc_handle_frame_copy_time(ctx);
  328. /* A frame has been decoded and is in the buffer */
  329. if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
  330. dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
  331. s5p_mfc_handle_frame_new(ctx, err);
  332. } else {
  333. mfc_debug(2, "No frame decode\n");
  334. }
  335. /* Mark source buffer as complete */
  336. if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
  337. && !list_empty(&ctx->src_queue)) {
  338. src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
  339. list);
  340. ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
  341. get_consumed_stream, dev);
  342. if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
  343. ctx->consumed_stream + STUFF_BYTE <
  344. src_buf->b->v4l2_planes[0].bytesused) {
  345. /* Run MFC again on the same buffer */
  346. mfc_debug(2, "Running again the same buffer\n");
  347. ctx->after_packed_pb = 1;
  348. } else {
  349. index = src_buf->b->v4l2_buf.index;
  350. mfc_debug(2, "MFC needs next buffer\n");
  351. ctx->consumed_stream = 0;
  352. list_del(&src_buf->list);
  353. ctx->src_queue_cnt--;
  354. if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
  355. vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
  356. else
  357. vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
  358. }
  359. }
  360. leave_handle_frame:
  361. spin_unlock_irqrestore(&dev->irqlock, flags);
  362. if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
  363. || ctx->dst_queue_cnt < ctx->dpb_count)
  364. clear_work_bit(ctx);
  365. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  366. wake_up_ctx(ctx, reason, err);
  367. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  368. BUG();
  369. s5p_mfc_clock_off();
  370. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  371. }
  372. /* Error handling for interrupt */
  373. static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx,
  374. unsigned int reason, unsigned int err)
  375. {
  376. struct s5p_mfc_dev *dev;
  377. unsigned long flags;
  378. /* If no context is available then all necessary
  379. * processing has been done. */
  380. if (ctx == NULL)
  381. return;
  382. dev = ctx->dev;
  383. mfc_err("Interrupt Error: %08x\n", err);
  384. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  385. wake_up_dev(dev, reason, err);
  386. /* Error recovery is dependent on the state of context */
  387. switch (ctx->state) {
  388. case MFCINST_INIT:
  389. /* This error had to happen while acquireing instance */
  390. case MFCINST_GOT_INST:
  391. /* This error had to happen while parsing the header */
  392. case MFCINST_HEAD_PARSED:
  393. /* This error had to happen while setting dst buffers */
  394. case MFCINST_RETURN_INST:
  395. /* This error had to happen while releasing instance */
  396. clear_work_bit(ctx);
  397. wake_up_ctx(ctx, reason, err);
  398. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  399. BUG();
  400. s5p_mfc_clock_off();
  401. ctx->state = MFCINST_ERROR;
  402. break;
  403. case MFCINST_FINISHING:
  404. case MFCINST_FINISHED:
  405. case MFCINST_RUNNING:
  406. /* It is higly probable that an error occured
  407. * while decoding a frame */
  408. clear_work_bit(ctx);
  409. ctx->state = MFCINST_ERROR;
  410. /* Mark all dst buffers as having an error */
  411. spin_lock_irqsave(&dev->irqlock, flags);
  412. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
  413. &ctx->vq_dst);
  414. /* Mark all src buffers as having an error */
  415. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
  416. &ctx->vq_src);
  417. spin_unlock_irqrestore(&dev->irqlock, flags);
  418. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  419. BUG();
  420. s5p_mfc_clock_off();
  421. break;
  422. default:
  423. mfc_err("Encountered an error interrupt which had not been handled\n");
  424. break;
  425. }
  426. return;
  427. }
  428. /* Header parsing interrupt handling */
  429. static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
  430. unsigned int reason, unsigned int err)
  431. {
  432. struct s5p_mfc_dev *dev;
  433. if (ctx == NULL)
  434. return;
  435. dev = ctx->dev;
  436. if (ctx->c_ops->post_seq_start) {
  437. if (ctx->c_ops->post_seq_start(ctx))
  438. mfc_err("post_seq_start() failed\n");
  439. } else {
  440. ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
  441. dev);
  442. ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
  443. dev);
  444. s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
  445. ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
  446. dev);
  447. ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
  448. dev);
  449. if (ctx->img_width == 0 || ctx->img_height == 0)
  450. ctx->state = MFCINST_ERROR;
  451. else
  452. ctx->state = MFCINST_HEAD_PARSED;
  453. if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
  454. ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
  455. !list_empty(&ctx->src_queue)) {
  456. struct s5p_mfc_buf *src_buf;
  457. src_buf = list_entry(ctx->src_queue.next,
  458. struct s5p_mfc_buf, list);
  459. if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
  460. dev) <
  461. src_buf->b->v4l2_planes[0].bytesused)
  462. ctx->head_processed = 0;
  463. else
  464. ctx->head_processed = 1;
  465. } else {
  466. ctx->head_processed = 1;
  467. }
  468. }
  469. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  470. clear_work_bit(ctx);
  471. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  472. BUG();
  473. s5p_mfc_clock_off();
  474. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  475. wake_up_ctx(ctx, reason, err);
  476. }
  477. /* Header parsing interrupt handling */
  478. static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
  479. unsigned int reason, unsigned int err)
  480. {
  481. struct s5p_mfc_buf *src_buf;
  482. struct s5p_mfc_dev *dev;
  483. unsigned long flags;
  484. if (ctx == NULL)
  485. return;
  486. dev = ctx->dev;
  487. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  488. ctx->int_type = reason;
  489. ctx->int_err = err;
  490. ctx->int_cond = 1;
  491. clear_work_bit(ctx);
  492. if (err == 0) {
  493. ctx->state = MFCINST_RUNNING;
  494. if (!ctx->dpb_flush_flag && ctx->head_processed) {
  495. spin_lock_irqsave(&dev->irqlock, flags);
  496. if (!list_empty(&ctx->src_queue)) {
  497. src_buf = list_entry(ctx->src_queue.next,
  498. struct s5p_mfc_buf, list);
  499. list_del(&src_buf->list);
  500. ctx->src_queue_cnt--;
  501. vb2_buffer_done(src_buf->b,
  502. VB2_BUF_STATE_DONE);
  503. }
  504. spin_unlock_irqrestore(&dev->irqlock, flags);
  505. } else {
  506. ctx->dpb_flush_flag = 0;
  507. }
  508. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  509. BUG();
  510. s5p_mfc_clock_off();
  511. wake_up(&ctx->queue);
  512. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  513. } else {
  514. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  515. BUG();
  516. s5p_mfc_clock_off();
  517. wake_up(&ctx->queue);
  518. }
  519. }
  520. static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
  521. unsigned int reason, unsigned int err)
  522. {
  523. struct s5p_mfc_dev *dev = ctx->dev;
  524. struct s5p_mfc_buf *mb_entry;
  525. mfc_debug(2, "Stream completed");
  526. s5p_mfc_clear_int_flags(dev);
  527. ctx->int_type = reason;
  528. ctx->int_err = err;
  529. ctx->state = MFCINST_FINISHED;
  530. spin_lock(&dev->irqlock);
  531. if (!list_empty(&ctx->dst_queue)) {
  532. mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
  533. list);
  534. list_del(&mb_entry->list);
  535. ctx->dst_queue_cnt--;
  536. vb2_set_plane_payload(mb_entry->b, 0, 0);
  537. vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
  538. }
  539. spin_unlock(&dev->irqlock);
  540. clear_work_bit(ctx);
  541. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  542. WARN_ON(1);
  543. s5p_mfc_clock_off();
  544. wake_up(&ctx->queue);
  545. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  546. }
  547. /* Interrupt processing */
  548. static irqreturn_t s5p_mfc_irq(int irq, void *priv)
  549. {
  550. struct s5p_mfc_dev *dev = priv;
  551. struct s5p_mfc_ctx *ctx;
  552. unsigned int reason;
  553. unsigned int err;
  554. mfc_debug_enter();
  555. /* Reset the timeout watchdog */
  556. atomic_set(&dev->watchdog_cnt, 0);
  557. ctx = dev->ctx[dev->curr_ctx];
  558. /* Get the reason of interrupt and the error code */
  559. reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
  560. err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
  561. mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
  562. switch (reason) {
  563. case S5P_MFC_R2H_CMD_ERR_RET:
  564. /* An error has occured */
  565. if (ctx->state == MFCINST_RUNNING &&
  566. s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
  567. dev->warn_start)
  568. s5p_mfc_handle_frame(ctx, reason, err);
  569. else
  570. s5p_mfc_handle_error(ctx, reason, err);
  571. clear_bit(0, &dev->enter_suspend);
  572. break;
  573. case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
  574. case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
  575. case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
  576. if (ctx->c_ops->post_frame_start) {
  577. if (ctx->c_ops->post_frame_start(ctx))
  578. mfc_err("post_frame_start() failed\n");
  579. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  580. wake_up_ctx(ctx, reason, err);
  581. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  582. BUG();
  583. s5p_mfc_clock_off();
  584. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  585. } else {
  586. s5p_mfc_handle_frame(ctx, reason, err);
  587. }
  588. break;
  589. case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
  590. s5p_mfc_handle_seq_done(ctx, reason, err);
  591. break;
  592. case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
  593. ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
  594. ctx->state = MFCINST_GOT_INST;
  595. clear_work_bit(ctx);
  596. wake_up(&ctx->queue);
  597. goto irq_cleanup_hw;
  598. case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
  599. clear_work_bit(ctx);
  600. ctx->state = MFCINST_FREE;
  601. wake_up(&ctx->queue);
  602. goto irq_cleanup_hw;
  603. case S5P_MFC_R2H_CMD_SYS_INIT_RET:
  604. case S5P_MFC_R2H_CMD_FW_STATUS_RET:
  605. case S5P_MFC_R2H_CMD_SLEEP_RET:
  606. case S5P_MFC_R2H_CMD_WAKEUP_RET:
  607. if (ctx)
  608. clear_work_bit(ctx);
  609. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  610. wake_up_dev(dev, reason, err);
  611. clear_bit(0, &dev->hw_lock);
  612. clear_bit(0, &dev->enter_suspend);
  613. break;
  614. case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
  615. s5p_mfc_handle_init_buffers(ctx, reason, err);
  616. break;
  617. case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
  618. s5p_mfc_handle_stream_complete(ctx, reason, err);
  619. break;
  620. default:
  621. mfc_debug(2, "Unknown int reason\n");
  622. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  623. }
  624. mfc_debug_leave();
  625. return IRQ_HANDLED;
  626. irq_cleanup_hw:
  627. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  628. ctx->int_type = reason;
  629. ctx->int_err = err;
  630. ctx->int_cond = 1;
  631. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  632. mfc_err("Failed to unlock hw\n");
  633. s5p_mfc_clock_off();
  634. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  635. mfc_debug(2, "Exit via irq_cleanup_hw\n");
  636. return IRQ_HANDLED;
  637. }
  638. /* Open an MFC node */
  639. static int s5p_mfc_open(struct file *file)
  640. {
  641. struct s5p_mfc_dev *dev = video_drvdata(file);
  642. struct s5p_mfc_ctx *ctx = NULL;
  643. struct vb2_queue *q;
  644. int ret = 0;
  645. mfc_debug_enter();
  646. if (mutex_lock_interruptible(&dev->mfc_mutex))
  647. return -ERESTARTSYS;
  648. dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
  649. /* Allocate memory for context */
  650. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  651. if (!ctx) {
  652. mfc_err("Not enough memory\n");
  653. ret = -ENOMEM;
  654. goto err_alloc;
  655. }
  656. v4l2_fh_init(&ctx->fh, video_devdata(file));
  657. file->private_data = &ctx->fh;
  658. v4l2_fh_add(&ctx->fh);
  659. ctx->dev = dev;
  660. INIT_LIST_HEAD(&ctx->src_queue);
  661. INIT_LIST_HEAD(&ctx->dst_queue);
  662. ctx->src_queue_cnt = 0;
  663. ctx->dst_queue_cnt = 0;
  664. /* Get context number */
  665. ctx->num = 0;
  666. while (dev->ctx[ctx->num]) {
  667. ctx->num++;
  668. if (ctx->num >= MFC_NUM_CONTEXTS) {
  669. mfc_err("Too many open contexts\n");
  670. ret = -EBUSY;
  671. goto err_no_ctx;
  672. }
  673. }
  674. /* Mark context as idle */
  675. clear_work_bit_irqsave(ctx);
  676. dev->ctx[ctx->num] = ctx;
  677. if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
  678. ctx->type = MFCINST_DECODER;
  679. ctx->c_ops = get_dec_codec_ops();
  680. s5p_mfc_dec_init(ctx);
  681. /* Setup ctrl handler */
  682. ret = s5p_mfc_dec_ctrls_setup(ctx);
  683. if (ret) {
  684. mfc_err("Failed to setup mfc controls\n");
  685. goto err_ctrls_setup;
  686. }
  687. } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
  688. ctx->type = MFCINST_ENCODER;
  689. ctx->c_ops = get_enc_codec_ops();
  690. /* only for encoder */
  691. INIT_LIST_HEAD(&ctx->ref_queue);
  692. ctx->ref_queue_cnt = 0;
  693. s5p_mfc_enc_init(ctx);
  694. /* Setup ctrl handler */
  695. ret = s5p_mfc_enc_ctrls_setup(ctx);
  696. if (ret) {
  697. mfc_err("Failed to setup mfc controls\n");
  698. goto err_ctrls_setup;
  699. }
  700. } else {
  701. ret = -ENOENT;
  702. goto err_bad_node;
  703. }
  704. ctx->fh.ctrl_handler = &ctx->ctrl_handler;
  705. ctx->inst_no = -1;
  706. /* Load firmware if this is the first instance */
  707. if (dev->num_inst == 1) {
  708. dev->watchdog_timer.expires = jiffies +
  709. msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
  710. add_timer(&dev->watchdog_timer);
  711. ret = s5p_mfc_power_on();
  712. if (ret < 0) {
  713. mfc_err("power on failed\n");
  714. goto err_pwr_enable;
  715. }
  716. s5p_mfc_clock_on();
  717. ret = s5p_mfc_alloc_and_load_firmware(dev);
  718. if (ret)
  719. goto err_alloc_fw;
  720. /* Init the FW */
  721. ret = s5p_mfc_init_hw(dev);
  722. if (ret)
  723. goto err_init_hw;
  724. s5p_mfc_clock_off();
  725. }
  726. /* Init videobuf2 queue for CAPTURE */
  727. q = &ctx->vq_dst;
  728. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  729. q->drv_priv = &ctx->fh;
  730. if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
  731. q->io_modes = VB2_MMAP;
  732. q->ops = get_dec_queue_ops();
  733. } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
  734. q->io_modes = VB2_MMAP | VB2_USERPTR;
  735. q->ops = get_enc_queue_ops();
  736. } else {
  737. ret = -ENOENT;
  738. goto err_queue_init;
  739. }
  740. q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
  741. ret = vb2_queue_init(q);
  742. if (ret) {
  743. mfc_err("Failed to initialize videobuf2 queue(capture)\n");
  744. goto err_queue_init;
  745. }
  746. /* Init videobuf2 queue for OUTPUT */
  747. q = &ctx->vq_src;
  748. q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
  749. q->io_modes = VB2_MMAP;
  750. q->drv_priv = &ctx->fh;
  751. if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
  752. q->io_modes = VB2_MMAP;
  753. q->ops = get_dec_queue_ops();
  754. } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
  755. q->io_modes = VB2_MMAP | VB2_USERPTR;
  756. q->ops = get_enc_queue_ops();
  757. } else {
  758. ret = -ENOENT;
  759. goto err_queue_init;
  760. }
  761. q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
  762. ret = vb2_queue_init(q);
  763. if (ret) {
  764. mfc_err("Failed to initialize videobuf2 queue(output)\n");
  765. goto err_queue_init;
  766. }
  767. init_waitqueue_head(&ctx->queue);
  768. mutex_unlock(&dev->mfc_mutex);
  769. mfc_debug_leave();
  770. return ret;
  771. /* Deinit when failure occured */
  772. err_queue_init:
  773. err_init_hw:
  774. s5p_mfc_release_firmware(dev);
  775. err_alloc_fw:
  776. dev->ctx[ctx->num] = NULL;
  777. del_timer_sync(&dev->watchdog_timer);
  778. s5p_mfc_clock_off();
  779. err_pwr_enable:
  780. if (dev->num_inst == 1) {
  781. if (s5p_mfc_power_off() < 0)
  782. mfc_err("power off failed\n");
  783. s5p_mfc_release_firmware(dev);
  784. }
  785. err_ctrls_setup:
  786. s5p_mfc_dec_ctrls_delete(ctx);
  787. err_bad_node:
  788. err_no_ctx:
  789. v4l2_fh_del(&ctx->fh);
  790. v4l2_fh_exit(&ctx->fh);
  791. kfree(ctx);
  792. err_alloc:
  793. dev->num_inst--;
  794. mutex_unlock(&dev->mfc_mutex);
  795. mfc_debug_leave();
  796. return ret;
  797. }
  798. /* Release MFC context */
  799. static int s5p_mfc_release(struct file *file)
  800. {
  801. struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
  802. struct s5p_mfc_dev *dev = ctx->dev;
  803. mfc_debug_enter();
  804. mutex_lock(&dev->mfc_mutex);
  805. s5p_mfc_clock_on();
  806. vb2_queue_release(&ctx->vq_src);
  807. vb2_queue_release(&ctx->vq_dst);
  808. /* Mark context as idle */
  809. clear_work_bit_irqsave(ctx);
  810. /* If instance was initialised then
  811. * return instance and free reosurces */
  812. if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
  813. mfc_debug(2, "Has to free instance\n");
  814. ctx->state = MFCINST_RETURN_INST;
  815. set_work_bit_irqsave(ctx);
  816. s5p_mfc_clean_ctx_int_flags(ctx);
  817. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  818. /* Wait until instance is returned or timeout occured */
  819. if (s5p_mfc_wait_for_done_ctx
  820. (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
  821. s5p_mfc_clock_off();
  822. mfc_err("Err returning instance\n");
  823. }
  824. mfc_debug(2, "After free instance\n");
  825. /* Free resources */
  826. s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
  827. s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
  828. if (ctx->type == MFCINST_DECODER)
  829. s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer,
  830. ctx);
  831. ctx->inst_no = MFC_NO_INSTANCE_SET;
  832. }
  833. /* hardware locking scheme */
  834. if (dev->curr_ctx == ctx->num)
  835. clear_bit(0, &dev->hw_lock);
  836. dev->num_inst--;
  837. if (dev->num_inst == 0) {
  838. mfc_debug(2, "Last instance - release firmware\n");
  839. /* reset <-> F/W release */
  840. s5p_mfc_reset(dev);
  841. s5p_mfc_deinit_hw(dev);
  842. s5p_mfc_release_firmware(dev);
  843. del_timer_sync(&dev->watchdog_timer);
  844. if (s5p_mfc_power_off() < 0)
  845. mfc_err("Power off failed\n");
  846. }
  847. mfc_debug(2, "Shutting down clock\n");
  848. s5p_mfc_clock_off();
  849. dev->ctx[ctx->num] = NULL;
  850. s5p_mfc_dec_ctrls_delete(ctx);
  851. v4l2_fh_del(&ctx->fh);
  852. v4l2_fh_exit(&ctx->fh);
  853. kfree(ctx);
  854. mfc_debug_leave();
  855. mutex_unlock(&dev->mfc_mutex);
  856. return 0;
  857. }
  858. /* Poll */
  859. static unsigned int s5p_mfc_poll(struct file *file,
  860. struct poll_table_struct *wait)
  861. {
  862. struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
  863. struct s5p_mfc_dev *dev = ctx->dev;
  864. struct vb2_queue *src_q, *dst_q;
  865. struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
  866. unsigned int rc = 0;
  867. unsigned long flags;
  868. mutex_lock(&dev->mfc_mutex);
  869. src_q = &ctx->vq_src;
  870. dst_q = &ctx->vq_dst;
  871. /*
  872. * There has to be at least one buffer queued on each queued_list, which
  873. * means either in driver already or waiting for driver to claim it
  874. * and start processing.
  875. */
  876. if ((!src_q->streaming || list_empty(&src_q->queued_list))
  877. && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
  878. rc = POLLERR;
  879. goto end;
  880. }
  881. mutex_unlock(&dev->mfc_mutex);
  882. poll_wait(file, &ctx->fh.wait, wait);
  883. poll_wait(file, &src_q->done_wq, wait);
  884. poll_wait(file, &dst_q->done_wq, wait);
  885. mutex_lock(&dev->mfc_mutex);
  886. if (v4l2_event_pending(&ctx->fh))
  887. rc |= POLLPRI;
  888. spin_lock_irqsave(&src_q->done_lock, flags);
  889. if (!list_empty(&src_q->done_list))
  890. src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
  891. done_entry);
  892. if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
  893. || src_vb->state == VB2_BUF_STATE_ERROR))
  894. rc |= POLLOUT | POLLWRNORM;
  895. spin_unlock_irqrestore(&src_q->done_lock, flags);
  896. spin_lock_irqsave(&dst_q->done_lock, flags);
  897. if (!list_empty(&dst_q->done_list))
  898. dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
  899. done_entry);
  900. if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
  901. || dst_vb->state == VB2_BUF_STATE_ERROR))
  902. rc |= POLLIN | POLLRDNORM;
  903. spin_unlock_irqrestore(&dst_q->done_lock, flags);
  904. end:
  905. mutex_unlock(&dev->mfc_mutex);
  906. return rc;
  907. }
  908. /* Mmap */
  909. static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
  910. {
  911. struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
  912. struct s5p_mfc_dev *dev = ctx->dev;
  913. unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
  914. int ret;
  915. if (mutex_lock_interruptible(&dev->mfc_mutex))
  916. return -ERESTARTSYS;
  917. if (offset < DST_QUEUE_OFF_BASE) {
  918. mfc_debug(2, "mmaping source\n");
  919. ret = vb2_mmap(&ctx->vq_src, vma);
  920. } else { /* capture */
  921. mfc_debug(2, "mmaping destination\n");
  922. vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
  923. ret = vb2_mmap(&ctx->vq_dst, vma);
  924. }
  925. mutex_unlock(&dev->mfc_mutex);
  926. return ret;
  927. }
  928. /* v4l2 ops */
  929. static const struct v4l2_file_operations s5p_mfc_fops = {
  930. .owner = THIS_MODULE,
  931. .open = s5p_mfc_open,
  932. .release = s5p_mfc_release,
  933. .poll = s5p_mfc_poll,
  934. .unlocked_ioctl = video_ioctl2,
  935. .mmap = s5p_mfc_mmap,
  936. };
  937. static int match_child(struct device *dev, void *data)
  938. {
  939. if (!dev_name(dev))
  940. return 0;
  941. return !strcmp(dev_name(dev), (char *)data);
  942. }
  943. static void *mfc_get_drv_data(struct platform_device *pdev);
  944. /* MFC probe function */
  945. static int s5p_mfc_probe(struct platform_device *pdev)
  946. {
  947. struct s5p_mfc_dev *dev;
  948. struct video_device *vfd;
  949. struct resource *res;
  950. int ret;
  951. unsigned int mem_info[2];
  952. pr_debug("%s++\n", __func__);
  953. dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
  954. if (!dev) {
  955. dev_err(&pdev->dev, "Not enough memory for MFC device\n");
  956. return -ENOMEM;
  957. }
  958. spin_lock_init(&dev->irqlock);
  959. spin_lock_init(&dev->condlock);
  960. dev->plat_dev = pdev;
  961. if (!dev->plat_dev) {
  962. dev_err(&pdev->dev, "No platform data specified\n");
  963. return -ENODEV;
  964. }
  965. dev->variant = mfc_get_drv_data(pdev);
  966. ret = s5p_mfc_init_pm(dev);
  967. if (ret < 0) {
  968. dev_err(&pdev->dev, "failed to get mfc clock source\n");
  969. return ret;
  970. }
  971. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  972. dev->regs_base = devm_request_and_ioremap(&pdev->dev, res);
  973. if (dev->regs_base == NULL) {
  974. dev_err(&pdev->dev, "Failed to obtain io memory\n");
  975. return -ENOENT;
  976. }
  977. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  978. if (res == NULL) {
  979. dev_err(&pdev->dev, "failed to get irq resource\n");
  980. ret = -ENOENT;
  981. goto err_res;
  982. }
  983. dev->irq = res->start;
  984. ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
  985. IRQF_DISABLED, pdev->name, dev);
  986. if (ret) {
  987. dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
  988. goto err_res;
  989. }
  990. if (pdev->dev.of_node) {
  991. dev->mem_dev_l = kzalloc(sizeof(struct device), GFP_KERNEL);
  992. if (!dev->mem_dev_l) {
  993. mfc_err("Not enough memory\n");
  994. ret = -ENOMEM;
  995. goto err_res;
  996. }
  997. of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-l",
  998. mem_info, 2);
  999. if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
  1000. mem_info[0], mem_info[1],
  1001. DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
  1002. mfc_err("Failed to declare coherent memory for\n"
  1003. "MFC device\n");
  1004. ret = -ENOMEM;
  1005. goto err_res;
  1006. }
  1007. dev->mem_dev_r = kzalloc(sizeof(struct device), GFP_KERNEL);
  1008. if (!dev->mem_dev_r) {
  1009. mfc_err("Not enough memory\n");
  1010. ret = -ENOMEM;
  1011. goto err_res;
  1012. }
  1013. of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-r",
  1014. mem_info, 2);
  1015. if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
  1016. mem_info[0], mem_info[1],
  1017. DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
  1018. pr_err("Failed to declare coherent memory for\n"
  1019. "MFC device\n");
  1020. ret = -ENOMEM;
  1021. goto err_res;
  1022. }
  1023. } else {
  1024. dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
  1025. "s5p-mfc-l", match_child);
  1026. if (!dev->mem_dev_l) {
  1027. mfc_err("Mem child (L) device get failed\n");
  1028. ret = -ENODEV;
  1029. goto err_res;
  1030. }
  1031. dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
  1032. "s5p-mfc-r", match_child);
  1033. if (!dev->mem_dev_r) {
  1034. mfc_err("Mem child (R) device get failed\n");
  1035. ret = -ENODEV;
  1036. goto err_res;
  1037. }
  1038. }
  1039. dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
  1040. if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) {
  1041. ret = PTR_ERR(dev->alloc_ctx[0]);
  1042. goto err_res;
  1043. }
  1044. dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
  1045. if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) {
  1046. ret = PTR_ERR(dev->alloc_ctx[1]);
  1047. goto err_mem_init_ctx_1;
  1048. }
  1049. mutex_init(&dev->mfc_mutex);
  1050. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1051. if (ret)
  1052. goto err_v4l2_dev_reg;
  1053. init_waitqueue_head(&dev->queue);
  1054. /* decoder */
  1055. vfd = video_device_alloc();
  1056. if (!vfd) {
  1057. v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
  1058. ret = -ENOMEM;
  1059. goto err_dec_alloc;
  1060. }
  1061. vfd->fops = &s5p_mfc_fops,
  1062. vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
  1063. vfd->release = video_device_release,
  1064. vfd->lock = &dev->mfc_mutex;
  1065. vfd->v4l2_dev = &dev->v4l2_dev;
  1066. vfd->vfl_dir = VFL_DIR_M2M;
  1067. snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
  1068. dev->vfd_dec = vfd;
  1069. ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
  1070. if (ret) {
  1071. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1072. video_device_release(vfd);
  1073. goto err_dec_reg;
  1074. }
  1075. v4l2_info(&dev->v4l2_dev,
  1076. "decoder registered as /dev/video%d\n", vfd->num);
  1077. video_set_drvdata(vfd, dev);
  1078. /* encoder */
  1079. vfd = video_device_alloc();
  1080. if (!vfd) {
  1081. v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
  1082. ret = -ENOMEM;
  1083. goto err_enc_alloc;
  1084. }
  1085. vfd->fops = &s5p_mfc_fops,
  1086. vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
  1087. vfd->release = video_device_release,
  1088. vfd->lock = &dev->mfc_mutex;
  1089. vfd->v4l2_dev = &dev->v4l2_dev;
  1090. vfd->vfl_dir = VFL_DIR_M2M;
  1091. snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
  1092. dev->vfd_enc = vfd;
  1093. ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
  1094. if (ret) {
  1095. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1096. video_device_release(vfd);
  1097. goto err_enc_reg;
  1098. }
  1099. v4l2_info(&dev->v4l2_dev,
  1100. "encoder registered as /dev/video%d\n", vfd->num);
  1101. video_set_drvdata(vfd, dev);
  1102. platform_set_drvdata(pdev, dev);
  1103. dev->hw_lock = 0;
  1104. dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
  1105. INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
  1106. atomic_set(&dev->watchdog_cnt, 0);
  1107. init_timer(&dev->watchdog_timer);
  1108. dev->watchdog_timer.data = (unsigned long)dev;
  1109. dev->watchdog_timer.function = s5p_mfc_watchdog;
  1110. /* Initialize HW ops and commands based on MFC version */
  1111. s5p_mfc_init_hw_ops(dev);
  1112. s5p_mfc_init_hw_cmds(dev);
  1113. pr_debug("%s--\n", __func__);
  1114. return 0;
  1115. /* Deinit MFC if probe had failed */
  1116. err_enc_reg:
  1117. video_device_release(dev->vfd_enc);
  1118. err_enc_alloc:
  1119. video_unregister_device(dev->vfd_dec);
  1120. err_dec_reg:
  1121. video_device_release(dev->vfd_dec);
  1122. err_dec_alloc:
  1123. v4l2_device_unregister(&dev->v4l2_dev);
  1124. err_v4l2_dev_reg:
  1125. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
  1126. err_mem_init_ctx_1:
  1127. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
  1128. err_res:
  1129. s5p_mfc_final_pm(dev);
  1130. pr_debug("%s-- with error\n", __func__);
  1131. return ret;
  1132. }
  1133. /* Remove the driver */
  1134. static int __devexit s5p_mfc_remove(struct platform_device *pdev)
  1135. {
  1136. struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
  1137. v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
  1138. del_timer_sync(&dev->watchdog_timer);
  1139. flush_workqueue(dev->watchdog_workqueue);
  1140. destroy_workqueue(dev->watchdog_workqueue);
  1141. video_unregister_device(dev->vfd_enc);
  1142. video_unregister_device(dev->vfd_dec);
  1143. v4l2_device_unregister(&dev->v4l2_dev);
  1144. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
  1145. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
  1146. s5p_mfc_final_pm(dev);
  1147. return 0;
  1148. }
  1149. #ifdef CONFIG_PM_SLEEP
  1150. static int s5p_mfc_suspend(struct device *dev)
  1151. {
  1152. struct platform_device *pdev = to_platform_device(dev);
  1153. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1154. int ret;
  1155. if (m_dev->num_inst == 0)
  1156. return 0;
  1157. if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
  1158. mfc_err("Error: going to suspend for a second time\n");
  1159. return -EIO;
  1160. }
  1161. /* Check if we're processing then wait if it necessary. */
  1162. while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
  1163. /* Try and lock the HW */
  1164. /* Wait on the interrupt waitqueue */
  1165. ret = wait_event_interruptible_timeout(m_dev->queue,
  1166. m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond,
  1167. msecs_to_jiffies(MFC_INT_TIMEOUT));
  1168. if (ret == 0) {
  1169. mfc_err("Waiting for hardware to finish timed out\n");
  1170. return -EIO;
  1171. }
  1172. }
  1173. return s5p_mfc_sleep(m_dev);
  1174. }
  1175. static int s5p_mfc_resume(struct device *dev)
  1176. {
  1177. struct platform_device *pdev = to_platform_device(dev);
  1178. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1179. if (m_dev->num_inst == 0)
  1180. return 0;
  1181. return s5p_mfc_wakeup(m_dev);
  1182. }
  1183. #endif
  1184. #ifdef CONFIG_PM_RUNTIME
  1185. static int s5p_mfc_runtime_suspend(struct device *dev)
  1186. {
  1187. struct platform_device *pdev = to_platform_device(dev);
  1188. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1189. atomic_set(&m_dev->pm.power, 0);
  1190. return 0;
  1191. }
  1192. static int s5p_mfc_runtime_resume(struct device *dev)
  1193. {
  1194. struct platform_device *pdev = to_platform_device(dev);
  1195. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1196. int pre_power;
  1197. if (!m_dev->alloc_ctx)
  1198. return 0;
  1199. pre_power = atomic_read(&m_dev->pm.power);
  1200. atomic_set(&m_dev->pm.power, 1);
  1201. return 0;
  1202. }
  1203. #endif
  1204. /* Power management */
  1205. static const struct dev_pm_ops s5p_mfc_pm_ops = {
  1206. SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
  1207. SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
  1208. NULL)
  1209. };
  1210. struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
  1211. .h264_ctx = MFC_H264_CTX_BUF_SIZE,
  1212. .non_h264_ctx = MFC_CTX_BUF_SIZE,
  1213. .dsc = DESC_BUF_SIZE,
  1214. .shm = SHARED_BUF_SIZE,
  1215. };
  1216. struct s5p_mfc_buf_size buf_size_v5 = {
  1217. .fw = MAX_FW_SIZE,
  1218. .cpb = MAX_CPB_SIZE,
  1219. .priv = &mfc_buf_size_v5,
  1220. };
  1221. struct s5p_mfc_buf_align mfc_buf_align_v5 = {
  1222. .base = MFC_BASE_ALIGN_ORDER,
  1223. };
  1224. static struct s5p_mfc_variant mfc_drvdata_v5 = {
  1225. .version = MFC_VERSION,
  1226. .port_num = MFC_NUM_PORTS,
  1227. .buf_size = &buf_size_v5,
  1228. .buf_align = &mfc_buf_align_v5,
  1229. .mclk_name = "sclk_mfc",
  1230. .fw_name = "s5p-mfc.fw",
  1231. };
  1232. struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
  1233. .dev_ctx = MFC_CTX_BUF_SIZE_V6,
  1234. .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
  1235. .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
  1236. .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
  1237. .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
  1238. };
  1239. struct s5p_mfc_buf_size buf_size_v6 = {
  1240. .fw = MAX_FW_SIZE_V6,
  1241. .cpb = MAX_CPB_SIZE_V6,
  1242. .priv = &mfc_buf_size_v6,
  1243. };
  1244. struct s5p_mfc_buf_align mfc_buf_align_v6 = {
  1245. .base = 0,
  1246. };
  1247. static struct s5p_mfc_variant mfc_drvdata_v6 = {
  1248. .version = MFC_VERSION_V6,
  1249. .port_num = MFC_NUM_PORTS_V6,
  1250. .buf_size = &buf_size_v6,
  1251. .buf_align = &mfc_buf_align_v6,
  1252. .mclk_name = "aclk_333",
  1253. .fw_name = "s5p-mfc-v6.fw",
  1254. };
  1255. static struct platform_device_id mfc_driver_ids[] = {
  1256. {
  1257. .name = "s5p-mfc",
  1258. .driver_data = (unsigned long)&mfc_drvdata_v5,
  1259. }, {
  1260. .name = "s5p-mfc-v5",
  1261. .driver_data = (unsigned long)&mfc_drvdata_v5,
  1262. }, {
  1263. .name = "s5p-mfc-v6",
  1264. .driver_data = (unsigned long)&mfc_drvdata_v6,
  1265. },
  1266. {},
  1267. };
  1268. MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
  1269. static const struct of_device_id exynos_mfc_match[] = {
  1270. {
  1271. .compatible = "samsung,mfc-v5",
  1272. .data = &mfc_drvdata_v5,
  1273. }, {
  1274. .compatible = "samsung,mfc-v6",
  1275. .data = &mfc_drvdata_v6,
  1276. },
  1277. {},
  1278. };
  1279. MODULE_DEVICE_TABLE(of, exynos_mfc_match);
  1280. static void *mfc_get_drv_data(struct platform_device *pdev)
  1281. {
  1282. struct s5p_mfc_variant *driver_data = NULL;
  1283. if (pdev->dev.of_node) {
  1284. const struct of_device_id *match;
  1285. match = of_match_node(of_match_ptr(exynos_mfc_match),
  1286. pdev->dev.of_node);
  1287. if (match)
  1288. driver_data = (struct s5p_mfc_variant *)match->data;
  1289. } else {
  1290. driver_data = (struct s5p_mfc_variant *)
  1291. platform_get_device_id(pdev)->driver_data;
  1292. }
  1293. return driver_data;
  1294. }
  1295. static struct platform_driver s5p_mfc_driver = {
  1296. .probe = s5p_mfc_probe,
  1297. .remove = __devexit_p(s5p_mfc_remove),
  1298. .id_table = mfc_driver_ids,
  1299. .driver = {
  1300. .name = S5P_MFC_NAME,
  1301. .owner = THIS_MODULE,
  1302. .pm = &s5p_mfc_pm_ops,
  1303. .of_match_table = exynos_mfc_match,
  1304. },
  1305. };
  1306. module_platform_driver(s5p_mfc_driver);
  1307. MODULE_LICENSE("GPL");
  1308. MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
  1309. MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");