mce_amd_64.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680
  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kobject.h>
  21. #include <linux/notifier.h>
  22. #include <linux/sched.h>
  23. #include <linux/smp.h>
  24. #include <linux/sysdev.h>
  25. #include <linux/sysfs.h>
  26. #include <asm/apic.h>
  27. #include <asm/mce.h>
  28. #include <asm/msr.h>
  29. #include <asm/percpu.h>
  30. #include <asm/idle.h>
  31. #define PFX "mce_threshold: "
  32. #define VERSION "version 1.1.1"
  33. #define NR_BANKS 6
  34. #define NR_BLOCKS 9
  35. #define THRESHOLD_MAX 0xFFF
  36. #define INT_TYPE_APIC 0x00020000
  37. #define MASK_VALID_HI 0x80000000
  38. #define MASK_CNTP_HI 0x40000000
  39. #define MASK_LOCKED_HI 0x20000000
  40. #define MASK_LVTOFF_HI 0x00F00000
  41. #define MASK_COUNT_EN_HI 0x00080000
  42. #define MASK_INT_TYPE_HI 0x00060000
  43. #define MASK_OVERFLOW_HI 0x00010000
  44. #define MASK_ERR_COUNT_HI 0x00000FFF
  45. #define MASK_BLKPTR_LO 0xFF000000
  46. #define MCG_XBLK_ADDR 0xC0000400
  47. struct threshold_block {
  48. unsigned int block;
  49. unsigned int bank;
  50. unsigned int cpu;
  51. u32 address;
  52. u16 interrupt_enable;
  53. u16 threshold_limit;
  54. struct kobject kobj;
  55. struct list_head miscj;
  56. };
  57. /* defaults used early on boot */
  58. static struct threshold_block threshold_defaults = {
  59. .interrupt_enable = 0,
  60. .threshold_limit = THRESHOLD_MAX,
  61. };
  62. struct threshold_bank {
  63. struct kobject *kobj;
  64. struct threshold_block *blocks;
  65. cpumask_t cpus;
  66. };
  67. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  68. #ifdef CONFIG_SMP
  69. static unsigned char shared_bank[NR_BANKS] = {
  70. 0, 0, 0, 0, 1
  71. };
  72. #endif
  73. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  74. static void amd_threshold_interrupt(void);
  75. /*
  76. * CPU Initialization
  77. */
  78. struct thresh_restart {
  79. struct threshold_block *b;
  80. int reset;
  81. u16 old_limit;
  82. };
  83. /* must be called with correct cpu affinity */
  84. static long threshold_restart_bank(void *_tr)
  85. {
  86. struct thresh_restart *tr = _tr;
  87. u32 mci_misc_hi, mci_misc_lo;
  88. rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
  89. if (tr->b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  90. tr->reset = 1; /* limit cannot be lower than err count */
  91. if (tr->reset) { /* reset err count and overflow bit */
  92. mci_misc_hi =
  93. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  94. (THRESHOLD_MAX - tr->b->threshold_limit);
  95. } else if (tr->old_limit) { /* change limit w/o reset */
  96. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  97. (tr->old_limit - tr->b->threshold_limit);
  98. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  99. (new_count & THRESHOLD_MAX);
  100. }
  101. tr->b->interrupt_enable ?
  102. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  103. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  104. mci_misc_hi |= MASK_COUNT_EN_HI;
  105. wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
  106. return 0;
  107. }
  108. /* cpu init entry point, called from mce.c with preempt off */
  109. void mce_amd_feature_init(struct cpuinfo_x86 *c)
  110. {
  111. unsigned int bank, block;
  112. unsigned int cpu = smp_processor_id();
  113. u8 lvt_off;
  114. u32 low = 0, high = 0, address = 0;
  115. struct thresh_restart tr;
  116. for (bank = 0; bank < NR_BANKS; ++bank) {
  117. for (block = 0; block < NR_BLOCKS; ++block) {
  118. if (block == 0)
  119. address = MSR_IA32_MC0_MISC + bank * 4;
  120. else if (block == 1) {
  121. address = (low & MASK_BLKPTR_LO) >> 21;
  122. if (!address)
  123. break;
  124. address += MCG_XBLK_ADDR;
  125. }
  126. else
  127. ++address;
  128. if (rdmsr_safe(address, &low, &high))
  129. break;
  130. if (!(high & MASK_VALID_HI)) {
  131. if (block)
  132. continue;
  133. else
  134. break;
  135. }
  136. if (!(high & MASK_CNTP_HI) ||
  137. (high & MASK_LOCKED_HI))
  138. continue;
  139. if (!block)
  140. per_cpu(bank_map, cpu) |= (1 << bank);
  141. #ifdef CONFIG_SMP
  142. if (shared_bank[bank] && c->cpu_core_id)
  143. break;
  144. #endif
  145. lvt_off = setup_APIC_eilvt_mce(THRESHOLD_APIC_VECTOR,
  146. APIC_EILVT_MSG_FIX, 0);
  147. high &= ~MASK_LVTOFF_HI;
  148. high |= lvt_off << 20;
  149. wrmsr(address, low, high);
  150. threshold_defaults.address = address;
  151. tr.b = &threshold_defaults;
  152. tr.reset = 0;
  153. tr.old_limit = 0;
  154. threshold_restart_bank(&tr);
  155. mce_threshold_vector = amd_threshold_interrupt;
  156. }
  157. }
  158. }
  159. /*
  160. * APIC Interrupt Handler
  161. */
  162. /*
  163. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  164. * the interrupt goes off when error_count reaches threshold_limit.
  165. * the handler will simply log mcelog w/ software defined bank number.
  166. */
  167. static void amd_threshold_interrupt(void)
  168. {
  169. unsigned int bank, block;
  170. struct mce m;
  171. u32 low = 0, high = 0, address = 0;
  172. mce_setup(&m);
  173. /* assume first bank caused it */
  174. for (bank = 0; bank < NR_BANKS; ++bank) {
  175. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  176. continue;
  177. for (block = 0; block < NR_BLOCKS; ++block) {
  178. if (block == 0)
  179. address = MSR_IA32_MC0_MISC + bank * 4;
  180. else if (block == 1) {
  181. address = (low & MASK_BLKPTR_LO) >> 21;
  182. if (!address)
  183. break;
  184. address += MCG_XBLK_ADDR;
  185. }
  186. else
  187. ++address;
  188. if (rdmsr_safe(address, &low, &high))
  189. break;
  190. if (!(high & MASK_VALID_HI)) {
  191. if (block)
  192. continue;
  193. else
  194. break;
  195. }
  196. if (!(high & MASK_CNTP_HI) ||
  197. (high & MASK_LOCKED_HI))
  198. continue;
  199. /* Log the machine check that caused the threshold
  200. event. */
  201. machine_check_poll(MCP_TIMESTAMP);
  202. if (high & MASK_OVERFLOW_HI) {
  203. rdmsrl(address, m.misc);
  204. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  205. m.status);
  206. m.bank = K8_MCE_THRESHOLD_BASE
  207. + bank * NR_BLOCKS
  208. + block;
  209. mce_log(&m);
  210. return;
  211. }
  212. }
  213. }
  214. }
  215. /*
  216. * Sysfs Interface
  217. */
  218. struct threshold_attr {
  219. struct attribute attr;
  220. ssize_t(*show) (struct threshold_block *, char *);
  221. ssize_t(*store) (struct threshold_block *, const char *, size_t count);
  222. };
  223. #define SHOW_FIELDS(name) \
  224. static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
  225. { \
  226. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  227. }
  228. SHOW_FIELDS(interrupt_enable)
  229. SHOW_FIELDS(threshold_limit)
  230. static ssize_t store_interrupt_enable(struct threshold_block *b,
  231. const char *buf, size_t count)
  232. {
  233. char *end;
  234. struct thresh_restart tr;
  235. unsigned long new = simple_strtoul(buf, &end, 0);
  236. if (end == buf)
  237. return -EINVAL;
  238. b->interrupt_enable = !!new;
  239. tr.b = b;
  240. tr.reset = 0;
  241. tr.old_limit = 0;
  242. work_on_cpu(b->cpu, threshold_restart_bank, &tr);
  243. return end - buf;
  244. }
  245. static ssize_t store_threshold_limit(struct threshold_block *b,
  246. const char *buf, size_t count)
  247. {
  248. char *end;
  249. struct thresh_restart tr;
  250. unsigned long new = simple_strtoul(buf, &end, 0);
  251. if (end == buf)
  252. return -EINVAL;
  253. if (new > THRESHOLD_MAX)
  254. new = THRESHOLD_MAX;
  255. if (new < 1)
  256. new = 1;
  257. tr.old_limit = b->threshold_limit;
  258. b->threshold_limit = new;
  259. tr.b = b;
  260. tr.reset = 0;
  261. work_on_cpu(b->cpu, threshold_restart_bank, &tr);
  262. return end - buf;
  263. }
  264. static long local_error_count(void *_b)
  265. {
  266. struct threshold_block *b = _b;
  267. u32 low, high;
  268. rdmsr(b->address, low, high);
  269. return (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
  270. }
  271. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  272. {
  273. return sprintf(buf, "%lx\n", work_on_cpu(b->cpu, local_error_count, b));
  274. }
  275. static ssize_t store_error_count(struct threshold_block *b,
  276. const char *buf, size_t count)
  277. {
  278. struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
  279. work_on_cpu(b->cpu, threshold_restart_bank, &tr);
  280. return 1;
  281. }
  282. #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
  283. .attr = {.name = __stringify(_name), .mode = _mode }, \
  284. .show = _show, \
  285. .store = _store, \
  286. };
  287. #define RW_ATTR(name) \
  288. static struct threshold_attr name = \
  289. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  290. RW_ATTR(interrupt_enable);
  291. RW_ATTR(threshold_limit);
  292. RW_ATTR(error_count);
  293. static struct attribute *default_attrs[] = {
  294. &interrupt_enable.attr,
  295. &threshold_limit.attr,
  296. &error_count.attr,
  297. NULL
  298. };
  299. #define to_block(k) container_of(k, struct threshold_block, kobj)
  300. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  301. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  302. {
  303. struct threshold_block *b = to_block(kobj);
  304. struct threshold_attr *a = to_attr(attr);
  305. ssize_t ret;
  306. ret = a->show ? a->show(b, buf) : -EIO;
  307. return ret;
  308. }
  309. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  310. const char *buf, size_t count)
  311. {
  312. struct threshold_block *b = to_block(kobj);
  313. struct threshold_attr *a = to_attr(attr);
  314. ssize_t ret;
  315. ret = a->store ? a->store(b, buf, count) : -EIO;
  316. return ret;
  317. }
  318. static struct sysfs_ops threshold_ops = {
  319. .show = show,
  320. .store = store,
  321. };
  322. static struct kobj_type threshold_ktype = {
  323. .sysfs_ops = &threshold_ops,
  324. .default_attrs = default_attrs,
  325. };
  326. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  327. unsigned int bank,
  328. unsigned int block,
  329. u32 address)
  330. {
  331. int err;
  332. u32 low, high;
  333. struct threshold_block *b = NULL;
  334. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  335. return 0;
  336. if (rdmsr_safe(address, &low, &high))
  337. return 0;
  338. if (!(high & MASK_VALID_HI)) {
  339. if (block)
  340. goto recurse;
  341. else
  342. return 0;
  343. }
  344. if (!(high & MASK_CNTP_HI) ||
  345. (high & MASK_LOCKED_HI))
  346. goto recurse;
  347. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  348. if (!b)
  349. return -ENOMEM;
  350. b->block = block;
  351. b->bank = bank;
  352. b->cpu = cpu;
  353. b->address = address;
  354. b->interrupt_enable = 0;
  355. b->threshold_limit = THRESHOLD_MAX;
  356. INIT_LIST_HEAD(&b->miscj);
  357. if (per_cpu(threshold_banks, cpu)[bank]->blocks)
  358. list_add(&b->miscj,
  359. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  360. else
  361. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  362. err = kobject_init_and_add(&b->kobj, &threshold_ktype,
  363. per_cpu(threshold_banks, cpu)[bank]->kobj,
  364. "misc%i", block);
  365. if (err)
  366. goto out_free;
  367. recurse:
  368. if (!block) {
  369. address = (low & MASK_BLKPTR_LO) >> 21;
  370. if (!address)
  371. return 0;
  372. address += MCG_XBLK_ADDR;
  373. } else
  374. ++address;
  375. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  376. if (err)
  377. goto out_free;
  378. if (b)
  379. kobject_uevent(&b->kobj, KOBJ_ADD);
  380. return err;
  381. out_free:
  382. if (b) {
  383. kobject_put(&b->kobj);
  384. kfree(b);
  385. }
  386. return err;
  387. }
  388. static __cpuinit long local_allocate_threshold_blocks(void *_bank)
  389. {
  390. unsigned int *bank = _bank;
  391. return allocate_threshold_blocks(smp_processor_id(), *bank, 0,
  392. MSR_IA32_MC0_MISC + *bank * 4);
  393. }
  394. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  395. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  396. {
  397. int i, err = 0;
  398. struct threshold_bank *b = NULL;
  399. char name[32];
  400. sprintf(name, "threshold_bank%i", bank);
  401. #ifdef CONFIG_SMP
  402. if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
  403. i = first_cpu(per_cpu(cpu_core_map, cpu));
  404. /* first core not up yet */
  405. if (cpu_data(i).cpu_core_id)
  406. goto out;
  407. /* already linked */
  408. if (per_cpu(threshold_banks, cpu)[bank])
  409. goto out;
  410. b = per_cpu(threshold_banks, i)[bank];
  411. if (!b)
  412. goto out;
  413. err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
  414. b->kobj, name);
  415. if (err)
  416. goto out;
  417. b->cpus = per_cpu(cpu_core_map, cpu);
  418. per_cpu(threshold_banks, cpu)[bank] = b;
  419. goto out;
  420. }
  421. #endif
  422. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  423. if (!b) {
  424. err = -ENOMEM;
  425. goto out;
  426. }
  427. b->kobj = kobject_create_and_add(name, &per_cpu(device_mce, cpu).kobj);
  428. if (!b->kobj)
  429. goto out_free;
  430. #ifndef CONFIG_SMP
  431. b->cpus = CPU_MASK_ALL;
  432. #else
  433. b->cpus = per_cpu(cpu_core_map, cpu);
  434. #endif
  435. per_cpu(threshold_banks, cpu)[bank] = b;
  436. err = work_on_cpu(cpu, local_allocate_threshold_blocks, &bank);
  437. if (err)
  438. goto out_free;
  439. for_each_cpu_mask_nr(i, b->cpus) {
  440. if (i == cpu)
  441. continue;
  442. err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
  443. b->kobj, name);
  444. if (err)
  445. goto out;
  446. per_cpu(threshold_banks, i)[bank] = b;
  447. }
  448. goto out;
  449. out_free:
  450. per_cpu(threshold_banks, cpu)[bank] = NULL;
  451. kfree(b);
  452. out:
  453. return err;
  454. }
  455. /* create dir/files for all valid threshold banks */
  456. static __cpuinit int threshold_create_device(unsigned int cpu)
  457. {
  458. unsigned int bank;
  459. int err = 0;
  460. for (bank = 0; bank < NR_BANKS; ++bank) {
  461. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  462. continue;
  463. err = threshold_create_bank(cpu, bank);
  464. if (err)
  465. goto out;
  466. }
  467. out:
  468. return err;
  469. }
  470. /*
  471. * let's be hotplug friendly.
  472. * in case of multiple core processors, the first core always takes ownership
  473. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  474. */
  475. static void deallocate_threshold_block(unsigned int cpu,
  476. unsigned int bank)
  477. {
  478. struct threshold_block *pos = NULL;
  479. struct threshold_block *tmp = NULL;
  480. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  481. if (!head)
  482. return;
  483. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  484. kobject_put(&pos->kobj);
  485. list_del(&pos->miscj);
  486. kfree(pos);
  487. }
  488. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  489. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  490. }
  491. static void threshold_remove_bank(unsigned int cpu, int bank)
  492. {
  493. int i = 0;
  494. struct threshold_bank *b;
  495. char name[32];
  496. b = per_cpu(threshold_banks, cpu)[bank];
  497. if (!b)
  498. return;
  499. if (!b->blocks)
  500. goto free_out;
  501. sprintf(name, "threshold_bank%i", bank);
  502. #ifdef CONFIG_SMP
  503. /* sibling symlink */
  504. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  505. sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
  506. per_cpu(threshold_banks, cpu)[bank] = NULL;
  507. return;
  508. }
  509. #endif
  510. /* remove all sibling symlinks before unregistering */
  511. for_each_cpu_mask_nr(i, b->cpus) {
  512. if (i == cpu)
  513. continue;
  514. sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
  515. per_cpu(threshold_banks, i)[bank] = NULL;
  516. }
  517. deallocate_threshold_block(cpu, bank);
  518. free_out:
  519. kobject_del(b->kobj);
  520. kobject_put(b->kobj);
  521. kfree(b);
  522. per_cpu(threshold_banks, cpu)[bank] = NULL;
  523. }
  524. static void threshold_remove_device(unsigned int cpu)
  525. {
  526. unsigned int bank;
  527. for (bank = 0; bank < NR_BANKS; ++bank) {
  528. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  529. continue;
  530. threshold_remove_bank(cpu, bank);
  531. }
  532. }
  533. /* get notified when a cpu comes on/off */
  534. static void __cpuinit amd_64_threshold_cpu_callback(unsigned long action,
  535. unsigned int cpu)
  536. {
  537. if (cpu >= NR_CPUS)
  538. return;
  539. switch (action) {
  540. case CPU_ONLINE:
  541. case CPU_ONLINE_FROZEN:
  542. threshold_create_device(cpu);
  543. break;
  544. case CPU_DEAD:
  545. case CPU_DEAD_FROZEN:
  546. threshold_remove_device(cpu);
  547. break;
  548. default:
  549. break;
  550. }
  551. }
  552. static __init int threshold_init_device(void)
  553. {
  554. unsigned lcpu = 0;
  555. /* to hit CPUs online before the notifier is up */
  556. for_each_online_cpu(lcpu) {
  557. int err = threshold_create_device(lcpu);
  558. if (err)
  559. return err;
  560. }
  561. threshold_cpu_callback = amd_64_threshold_cpu_callback;
  562. return 0;
  563. }
  564. device_initcall(threshold_init_device);