eeprom_4k.c 34 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211
  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. #include "ar9002_phy.h"
  18. static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  19. {
  20. return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  21. }
  22. static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  23. {
  24. return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  25. }
  26. static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  27. {
  28. #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  29. struct ath_common *common = ath9k_hw_common(ah);
  30. u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  31. int addr, eep_start_loc = 0;
  32. eep_start_loc = 64;
  33. if (!ath9k_hw_use_flash(ah)) {
  34. ath_print(common, ATH_DBG_EEPROM,
  35. "Reading from EEPROM, not flash\n");
  36. }
  37. for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  38. if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  39. ath_print(common, ATH_DBG_EEPROM,
  40. "Unable to read eeprom region\n");
  41. return false;
  42. }
  43. eep_data++;
  44. }
  45. return true;
  46. #undef SIZE_EEPROM_4K
  47. }
  48. static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
  49. {
  50. #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  51. struct ath_common *common = ath9k_hw_common(ah);
  52. struct ar5416_eeprom_4k *eep =
  53. (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
  54. u16 *eepdata, temp, magic, magic2;
  55. u32 sum = 0, el;
  56. bool need_swap = false;
  57. int i, addr;
  58. if (!ath9k_hw_use_flash(ah)) {
  59. if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
  60. &magic)) {
  61. ath_print(common, ATH_DBG_FATAL,
  62. "Reading Magic # failed\n");
  63. return false;
  64. }
  65. ath_print(common, ATH_DBG_EEPROM,
  66. "Read Magic = 0x%04X\n", magic);
  67. if (magic != AR5416_EEPROM_MAGIC) {
  68. magic2 = swab16(magic);
  69. if (magic2 == AR5416_EEPROM_MAGIC) {
  70. need_swap = true;
  71. eepdata = (u16 *) (&ah->eeprom);
  72. for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
  73. temp = swab16(*eepdata);
  74. *eepdata = temp;
  75. eepdata++;
  76. }
  77. } else {
  78. ath_print(common, ATH_DBG_FATAL,
  79. "Invalid EEPROM Magic. "
  80. "endianness mismatch.\n");
  81. return -EINVAL;
  82. }
  83. }
  84. }
  85. ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
  86. need_swap ? "True" : "False");
  87. if (need_swap)
  88. el = swab16(ah->eeprom.map4k.baseEepHeader.length);
  89. else
  90. el = ah->eeprom.map4k.baseEepHeader.length;
  91. if (el > sizeof(struct ar5416_eeprom_4k))
  92. el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
  93. else
  94. el = el / sizeof(u16);
  95. eepdata = (u16 *)(&ah->eeprom);
  96. for (i = 0; i < el; i++)
  97. sum ^= *eepdata++;
  98. if (need_swap) {
  99. u32 integer;
  100. u16 word;
  101. ath_print(common, ATH_DBG_EEPROM,
  102. "EEPROM Endianness is not native.. Changing\n");
  103. word = swab16(eep->baseEepHeader.length);
  104. eep->baseEepHeader.length = word;
  105. word = swab16(eep->baseEepHeader.checksum);
  106. eep->baseEepHeader.checksum = word;
  107. word = swab16(eep->baseEepHeader.version);
  108. eep->baseEepHeader.version = word;
  109. word = swab16(eep->baseEepHeader.regDmn[0]);
  110. eep->baseEepHeader.regDmn[0] = word;
  111. word = swab16(eep->baseEepHeader.regDmn[1]);
  112. eep->baseEepHeader.regDmn[1] = word;
  113. word = swab16(eep->baseEepHeader.rfSilent);
  114. eep->baseEepHeader.rfSilent = word;
  115. word = swab16(eep->baseEepHeader.blueToothOptions);
  116. eep->baseEepHeader.blueToothOptions = word;
  117. word = swab16(eep->baseEepHeader.deviceCap);
  118. eep->baseEepHeader.deviceCap = word;
  119. integer = swab32(eep->modalHeader.antCtrlCommon);
  120. eep->modalHeader.antCtrlCommon = integer;
  121. for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
  122. integer = swab32(eep->modalHeader.antCtrlChain[i]);
  123. eep->modalHeader.antCtrlChain[i] = integer;
  124. }
  125. for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
  126. word = swab16(eep->modalHeader.spurChans[i].spurChan);
  127. eep->modalHeader.spurChans[i].spurChan = word;
  128. }
  129. }
  130. if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
  131. ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
  132. ath_print(common, ATH_DBG_FATAL,
  133. "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
  134. sum, ah->eep_ops->get_eeprom_ver(ah));
  135. return -EINVAL;
  136. }
  137. return 0;
  138. #undef EEPROM_4K_SIZE
  139. }
  140. static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
  141. enum eeprom_param param)
  142. {
  143. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  144. struct modal_eep_4k_header *pModal = &eep->modalHeader;
  145. struct base_eep_header_4k *pBase = &eep->baseEepHeader;
  146. u16 ver_minor;
  147. ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
  148. switch (param) {
  149. case EEP_NFTHRESH_2:
  150. return pModal->noiseFloorThreshCh[0];
  151. case EEP_MAC_LSW:
  152. return pBase->macAddr[0] << 8 | pBase->macAddr[1];
  153. case EEP_MAC_MID:
  154. return pBase->macAddr[2] << 8 | pBase->macAddr[3];
  155. case EEP_MAC_MSW:
  156. return pBase->macAddr[4] << 8 | pBase->macAddr[5];
  157. case EEP_REG_0:
  158. return pBase->regDmn[0];
  159. case EEP_REG_1:
  160. return pBase->regDmn[1];
  161. case EEP_OP_CAP:
  162. return pBase->deviceCap;
  163. case EEP_OP_MODE:
  164. return pBase->opCapFlags;
  165. case EEP_RF_SILENT:
  166. return pBase->rfSilent;
  167. case EEP_OB_2:
  168. return pModal->ob_0;
  169. case EEP_DB_2:
  170. return pModal->db1_1;
  171. case EEP_MINOR_REV:
  172. return ver_minor;
  173. case EEP_TX_MASK:
  174. return pBase->txMask;
  175. case EEP_RX_MASK:
  176. return pBase->rxMask;
  177. case EEP_FRAC_N_5G:
  178. return 0;
  179. case EEP_PWR_TABLE_OFFSET:
  180. return AR5416_PWR_TABLE_OFFSET_DB;
  181. case EEP_MODAL_VER:
  182. return pModal->version;
  183. case EEP_ANT_DIV_CTL1:
  184. return pModal->antdiv_ctl1;
  185. case EEP_TXGAIN_TYPE:
  186. if (ver_minor >= AR5416_EEP_MINOR_VER_19)
  187. return pBase->txGainType;
  188. else
  189. return AR5416_EEP_TXGAIN_ORIGINAL;
  190. default:
  191. return 0;
  192. }
  193. }
  194. static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
  195. struct ath9k_channel *chan,
  196. struct cal_data_per_freq_4k *pRawDataSet,
  197. u8 *bChans, u16 availPiers,
  198. u16 tPdGainOverlap,
  199. u16 *pPdGainBoundaries, u8 *pPDADCValues,
  200. u16 numXpdGains)
  201. {
  202. #define TMP_VAL_VPD_TABLE \
  203. ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
  204. int i, j, k;
  205. int16_t ss;
  206. u16 idxL = 0, idxR = 0, numPiers;
  207. static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
  208. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  209. static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
  210. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  211. static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
  212. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  213. u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
  214. u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
  215. u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
  216. int16_t vpdStep;
  217. int16_t tmpVal;
  218. u16 sizeCurrVpdTable, maxIndex, tgtIndex;
  219. bool match;
  220. int16_t minDelta = 0;
  221. struct chan_centers centers;
  222. #define PD_GAIN_BOUNDARY_DEFAULT 58;
  223. memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
  224. ath9k_hw_get_channel_centers(ah, chan, &centers);
  225. for (numPiers = 0; numPiers < availPiers; numPiers++) {
  226. if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
  227. break;
  228. }
  229. match = ath9k_hw_get_lower_upper_index(
  230. (u8)FREQ2FBIN(centers.synth_center,
  231. IS_CHAN_2GHZ(chan)), bChans, numPiers,
  232. &idxL, &idxR);
  233. if (match) {
  234. for (i = 0; i < numXpdGains; i++) {
  235. minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
  236. maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
  237. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  238. pRawDataSet[idxL].pwrPdg[i],
  239. pRawDataSet[idxL].vpdPdg[i],
  240. AR5416_EEP4K_PD_GAIN_ICEPTS,
  241. vpdTableI[i]);
  242. }
  243. } else {
  244. for (i = 0; i < numXpdGains; i++) {
  245. pVpdL = pRawDataSet[idxL].vpdPdg[i];
  246. pPwrL = pRawDataSet[idxL].pwrPdg[i];
  247. pVpdR = pRawDataSet[idxR].vpdPdg[i];
  248. pPwrR = pRawDataSet[idxR].pwrPdg[i];
  249. minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
  250. maxPwrT4[i] =
  251. min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
  252. pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
  253. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  254. pPwrL, pVpdL,
  255. AR5416_EEP4K_PD_GAIN_ICEPTS,
  256. vpdTableL[i]);
  257. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  258. pPwrR, pVpdR,
  259. AR5416_EEP4K_PD_GAIN_ICEPTS,
  260. vpdTableR[i]);
  261. for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
  262. vpdTableI[i][j] =
  263. (u8)(ath9k_hw_interpolate((u16)
  264. FREQ2FBIN(centers.
  265. synth_center,
  266. IS_CHAN_2GHZ
  267. (chan)),
  268. bChans[idxL], bChans[idxR],
  269. vpdTableL[i][j], vpdTableR[i][j]));
  270. }
  271. }
  272. }
  273. k = 0;
  274. for (i = 0; i < numXpdGains; i++) {
  275. if (i == (numXpdGains - 1))
  276. pPdGainBoundaries[i] =
  277. (u16)(maxPwrT4[i] / 2);
  278. else
  279. pPdGainBoundaries[i] =
  280. (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
  281. pPdGainBoundaries[i] =
  282. min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
  283. if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
  284. minDelta = pPdGainBoundaries[0] - 23;
  285. pPdGainBoundaries[0] = 23;
  286. } else {
  287. minDelta = 0;
  288. }
  289. if (i == 0) {
  290. if (AR_SREV_9280_20_OR_LATER(ah))
  291. ss = (int16_t)(0 - (minPwrT4[i] / 2));
  292. else
  293. ss = 0;
  294. } else {
  295. ss = (int16_t)((pPdGainBoundaries[i - 1] -
  296. (minPwrT4[i] / 2)) -
  297. tPdGainOverlap + 1 + minDelta);
  298. }
  299. vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
  300. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  301. while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  302. tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
  303. pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
  304. ss++;
  305. }
  306. sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
  307. tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
  308. (minPwrT4[i] / 2));
  309. maxIndex = (tgtIndex < sizeCurrVpdTable) ?
  310. tgtIndex : sizeCurrVpdTable;
  311. while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
  312. pPDADCValues[k++] = vpdTableI[i][ss++];
  313. vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
  314. vpdTableI[i][sizeCurrVpdTable - 2]);
  315. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  316. if (tgtIndex >= maxIndex) {
  317. while ((ss <= tgtIndex) &&
  318. (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  319. tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
  320. pPDADCValues[k++] = (u8)((tmpVal > 255) ?
  321. 255 : tmpVal);
  322. ss++;
  323. }
  324. }
  325. }
  326. while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
  327. pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
  328. i++;
  329. }
  330. while (k < AR5416_NUM_PDADC_VALUES) {
  331. pPDADCValues[k] = pPDADCValues[k - 1];
  332. k++;
  333. }
  334. return;
  335. #undef TMP_VAL_VPD_TABLE
  336. }
  337. static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
  338. struct ath9k_channel *chan,
  339. int16_t *pTxPowerIndexOffset)
  340. {
  341. struct ath_common *common = ath9k_hw_common(ah);
  342. struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
  343. struct cal_data_per_freq_4k *pRawDataset;
  344. u8 *pCalBChans = NULL;
  345. u16 pdGainOverlap_t2;
  346. static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
  347. u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
  348. u16 numPiers, i, j;
  349. u16 numXpdGain, xpdMask;
  350. u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
  351. u32 reg32, regOffset, regChainOffset;
  352. xpdMask = pEepData->modalHeader.xpdGain;
  353. if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  354. AR5416_EEP_MINOR_VER_2) {
  355. pdGainOverlap_t2 =
  356. pEepData->modalHeader.pdGainOverlap;
  357. } else {
  358. pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
  359. AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
  360. }
  361. pCalBChans = pEepData->calFreqPier2G;
  362. numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
  363. numXpdGain = 0;
  364. for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
  365. if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
  366. if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
  367. break;
  368. xpdGainValues[numXpdGain] =
  369. (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
  370. numXpdGain++;
  371. }
  372. }
  373. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
  374. (numXpdGain - 1) & 0x3);
  375. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
  376. xpdGainValues[0]);
  377. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
  378. xpdGainValues[1]);
  379. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
  380. for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
  381. if (AR_SREV_5416_20_OR_LATER(ah) &&
  382. (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
  383. (i != 0)) {
  384. regChainOffset = (i == 1) ? 0x2000 : 0x1000;
  385. } else
  386. regChainOffset = i * 0x1000;
  387. if (pEepData->baseEepHeader.txMask & (1 << i)) {
  388. pRawDataset = pEepData->calPierData2G[i];
  389. ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
  390. pRawDataset, pCalBChans,
  391. numPiers, pdGainOverlap_t2,
  392. gainBoundaries,
  393. pdadcValues, numXpdGain);
  394. ENABLE_REGWRITE_BUFFER(ah);
  395. if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
  396. REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
  397. SM(pdGainOverlap_t2,
  398. AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
  399. | SM(gainBoundaries[0],
  400. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
  401. | SM(gainBoundaries[1],
  402. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
  403. | SM(gainBoundaries[2],
  404. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
  405. | SM(gainBoundaries[3],
  406. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
  407. }
  408. regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
  409. for (j = 0; j < 32; j++) {
  410. reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
  411. ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
  412. ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
  413. ((pdadcValues[4 * j + 3] & 0xFF) << 24);
  414. REG_WRITE(ah, regOffset, reg32);
  415. ath_print(common, ATH_DBG_EEPROM,
  416. "PDADC (%d,%4x): %4.4x %8.8x\n",
  417. i, regChainOffset, regOffset,
  418. reg32);
  419. ath_print(common, ATH_DBG_EEPROM,
  420. "PDADC: Chain %d | "
  421. "PDADC %3d Value %3d | "
  422. "PDADC %3d Value %3d | "
  423. "PDADC %3d Value %3d | "
  424. "PDADC %3d Value %3d |\n",
  425. i, 4 * j, pdadcValues[4 * j],
  426. 4 * j + 1, pdadcValues[4 * j + 1],
  427. 4 * j + 2, pdadcValues[4 * j + 2],
  428. 4 * j + 3,
  429. pdadcValues[4 * j + 3]);
  430. regOffset += 4;
  431. }
  432. REGWRITE_BUFFER_FLUSH(ah);
  433. }
  434. }
  435. *pTxPowerIndexOffset = 0;
  436. }
  437. static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
  438. struct ath9k_channel *chan,
  439. int16_t *ratesArray,
  440. u16 cfgCtl,
  441. u16 AntennaReduction,
  442. u16 twiceMaxRegulatoryPower,
  443. u16 powerLimit)
  444. {
  445. #define CMP_TEST_GRP \
  446. (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
  447. pEepData->ctlIndex[i]) \
  448. || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
  449. ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
  450. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  451. int i;
  452. int16_t twiceLargestAntenna;
  453. u16 twiceMinEdgePower;
  454. u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
  455. u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
  456. u16 numCtlModes, *pCtlMode, ctlMode, freq;
  457. struct chan_centers centers;
  458. struct cal_ctl_data_4k *rep;
  459. struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
  460. static const u16 tpScaleReductionTable[5] =
  461. { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
  462. struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
  463. 0, { 0, 0, 0, 0}
  464. };
  465. struct cal_target_power_leg targetPowerOfdmExt = {
  466. 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
  467. 0, { 0, 0, 0, 0 }
  468. };
  469. struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
  470. 0, {0, 0, 0, 0}
  471. };
  472. u16 ctlModesFor11g[] =
  473. { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
  474. CTL_2GHT40
  475. };
  476. ath9k_hw_get_channel_centers(ah, chan, &centers);
  477. twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
  478. twiceLargestAntenna = (int16_t)min(AntennaReduction -
  479. twiceLargestAntenna, 0);
  480. maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
  481. if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
  482. maxRegAllowedPower -=
  483. (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
  484. }
  485. scaledPower = min(powerLimit, maxRegAllowedPower);
  486. scaledPower = max((u16)0, scaledPower);
  487. numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
  488. pCtlMode = ctlModesFor11g;
  489. ath9k_hw_get_legacy_target_powers(ah, chan,
  490. pEepData->calTargetPowerCck,
  491. AR5416_NUM_2G_CCK_TARGET_POWERS,
  492. &targetPowerCck, 4, false);
  493. ath9k_hw_get_legacy_target_powers(ah, chan,
  494. pEepData->calTargetPower2G,
  495. AR5416_NUM_2G_20_TARGET_POWERS,
  496. &targetPowerOfdm, 4, false);
  497. ath9k_hw_get_target_powers(ah, chan,
  498. pEepData->calTargetPower2GHT20,
  499. AR5416_NUM_2G_20_TARGET_POWERS,
  500. &targetPowerHt20, 8, false);
  501. if (IS_CHAN_HT40(chan)) {
  502. numCtlModes = ARRAY_SIZE(ctlModesFor11g);
  503. ath9k_hw_get_target_powers(ah, chan,
  504. pEepData->calTargetPower2GHT40,
  505. AR5416_NUM_2G_40_TARGET_POWERS,
  506. &targetPowerHt40, 8, true);
  507. ath9k_hw_get_legacy_target_powers(ah, chan,
  508. pEepData->calTargetPowerCck,
  509. AR5416_NUM_2G_CCK_TARGET_POWERS,
  510. &targetPowerCckExt, 4, true);
  511. ath9k_hw_get_legacy_target_powers(ah, chan,
  512. pEepData->calTargetPower2G,
  513. AR5416_NUM_2G_20_TARGET_POWERS,
  514. &targetPowerOfdmExt, 4, true);
  515. }
  516. for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
  517. bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
  518. (pCtlMode[ctlMode] == CTL_2GHT40);
  519. if (isHt40CtlMode)
  520. freq = centers.synth_center;
  521. else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
  522. freq = centers.ext_center;
  523. else
  524. freq = centers.ctl_center;
  525. if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
  526. ah->eep_ops->get_eeprom_rev(ah) <= 2)
  527. twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
  528. for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
  529. pEepData->ctlIndex[i]; i++) {
  530. if (CMP_TEST_GRP) {
  531. rep = &(pEepData->ctlData[i]);
  532. twiceMinEdgePower = ath9k_hw_get_max_edge_power(
  533. freq,
  534. rep->ctlEdges[
  535. ar5416_get_ntxchains(ah->txchainmask) - 1],
  536. IS_CHAN_2GHZ(chan),
  537. AR5416_EEP4K_NUM_BAND_EDGES);
  538. if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
  539. twiceMaxEdgePower =
  540. min(twiceMaxEdgePower,
  541. twiceMinEdgePower);
  542. } else {
  543. twiceMaxEdgePower = twiceMinEdgePower;
  544. break;
  545. }
  546. }
  547. }
  548. minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
  549. switch (pCtlMode[ctlMode]) {
  550. case CTL_11B:
  551. for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
  552. targetPowerCck.tPow2x[i] =
  553. min((u16)targetPowerCck.tPow2x[i],
  554. minCtlPower);
  555. }
  556. break;
  557. case CTL_11G:
  558. for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
  559. targetPowerOfdm.tPow2x[i] =
  560. min((u16)targetPowerOfdm.tPow2x[i],
  561. minCtlPower);
  562. }
  563. break;
  564. case CTL_2GHT20:
  565. for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
  566. targetPowerHt20.tPow2x[i] =
  567. min((u16)targetPowerHt20.tPow2x[i],
  568. minCtlPower);
  569. }
  570. break;
  571. case CTL_11B_EXT:
  572. targetPowerCckExt.tPow2x[0] =
  573. min((u16)targetPowerCckExt.tPow2x[0],
  574. minCtlPower);
  575. break;
  576. case CTL_11G_EXT:
  577. targetPowerOfdmExt.tPow2x[0] =
  578. min((u16)targetPowerOfdmExt.tPow2x[0],
  579. minCtlPower);
  580. break;
  581. case CTL_2GHT40:
  582. for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
  583. targetPowerHt40.tPow2x[i] =
  584. min((u16)targetPowerHt40.tPow2x[i],
  585. minCtlPower);
  586. }
  587. break;
  588. default:
  589. break;
  590. }
  591. }
  592. ratesArray[rate6mb] =
  593. ratesArray[rate9mb] =
  594. ratesArray[rate12mb] =
  595. ratesArray[rate18mb] =
  596. ratesArray[rate24mb] =
  597. targetPowerOfdm.tPow2x[0];
  598. ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
  599. ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
  600. ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
  601. ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
  602. for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
  603. ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
  604. ratesArray[rate1l] = targetPowerCck.tPow2x[0];
  605. ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
  606. ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
  607. ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
  608. if (IS_CHAN_HT40(chan)) {
  609. for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
  610. ratesArray[rateHt40_0 + i] =
  611. targetPowerHt40.tPow2x[i];
  612. }
  613. ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
  614. ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
  615. ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
  616. ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
  617. }
  618. #undef CMP_TEST_GRP
  619. }
  620. static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
  621. struct ath9k_channel *chan,
  622. u16 cfgCtl,
  623. u8 twiceAntennaReduction,
  624. u8 twiceMaxRegulatoryPower,
  625. u8 powerLimit)
  626. {
  627. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  628. struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
  629. struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
  630. int16_t ratesArray[Ar5416RateSize];
  631. int16_t txPowerIndexOffset = 0;
  632. u8 ht40PowerIncForPdadc = 2;
  633. int i;
  634. memset(ratesArray, 0, sizeof(ratesArray));
  635. if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  636. AR5416_EEP_MINOR_VER_2) {
  637. ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
  638. }
  639. ath9k_hw_set_4k_power_per_rate_table(ah, chan,
  640. &ratesArray[0], cfgCtl,
  641. twiceAntennaReduction,
  642. twiceMaxRegulatoryPower,
  643. powerLimit);
  644. ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
  645. for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
  646. ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
  647. if (ratesArray[i] > AR5416_MAX_RATE_POWER)
  648. ratesArray[i] = AR5416_MAX_RATE_POWER;
  649. }
  650. /* Update regulatory */
  651. i = rate6mb;
  652. if (IS_CHAN_HT40(chan))
  653. i = rateHt40_0;
  654. else if (IS_CHAN_HT20(chan))
  655. i = rateHt20_0;
  656. regulatory->max_power_level = ratesArray[i];
  657. if (AR_SREV_9280_20_OR_LATER(ah)) {
  658. for (i = 0; i < Ar5416RateSize; i++)
  659. ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
  660. }
  661. ENABLE_REGWRITE_BUFFER(ah);
  662. /* OFDM power per rate */
  663. REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
  664. ATH9K_POW_SM(ratesArray[rate18mb], 24)
  665. | ATH9K_POW_SM(ratesArray[rate12mb], 16)
  666. | ATH9K_POW_SM(ratesArray[rate9mb], 8)
  667. | ATH9K_POW_SM(ratesArray[rate6mb], 0));
  668. REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
  669. ATH9K_POW_SM(ratesArray[rate54mb], 24)
  670. | ATH9K_POW_SM(ratesArray[rate48mb], 16)
  671. | ATH9K_POW_SM(ratesArray[rate36mb], 8)
  672. | ATH9K_POW_SM(ratesArray[rate24mb], 0));
  673. /* CCK power per rate */
  674. REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
  675. ATH9K_POW_SM(ratesArray[rate2s], 24)
  676. | ATH9K_POW_SM(ratesArray[rate2l], 16)
  677. | ATH9K_POW_SM(ratesArray[rateXr], 8)
  678. | ATH9K_POW_SM(ratesArray[rate1l], 0));
  679. REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
  680. ATH9K_POW_SM(ratesArray[rate11s], 24)
  681. | ATH9K_POW_SM(ratesArray[rate11l], 16)
  682. | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
  683. | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
  684. /* HT20 power per rate */
  685. REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
  686. ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
  687. | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
  688. | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
  689. | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
  690. REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
  691. ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
  692. | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
  693. | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
  694. | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
  695. /* HT40 power per rate */
  696. if (IS_CHAN_HT40(chan)) {
  697. REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
  698. ATH9K_POW_SM(ratesArray[rateHt40_3] +
  699. ht40PowerIncForPdadc, 24)
  700. | ATH9K_POW_SM(ratesArray[rateHt40_2] +
  701. ht40PowerIncForPdadc, 16)
  702. | ATH9K_POW_SM(ratesArray[rateHt40_1] +
  703. ht40PowerIncForPdadc, 8)
  704. | ATH9K_POW_SM(ratesArray[rateHt40_0] +
  705. ht40PowerIncForPdadc, 0));
  706. REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
  707. ATH9K_POW_SM(ratesArray[rateHt40_7] +
  708. ht40PowerIncForPdadc, 24)
  709. | ATH9K_POW_SM(ratesArray[rateHt40_6] +
  710. ht40PowerIncForPdadc, 16)
  711. | ATH9K_POW_SM(ratesArray[rateHt40_5] +
  712. ht40PowerIncForPdadc, 8)
  713. | ATH9K_POW_SM(ratesArray[rateHt40_4] +
  714. ht40PowerIncForPdadc, 0));
  715. REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
  716. ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
  717. | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
  718. | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
  719. | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
  720. }
  721. REGWRITE_BUFFER_FLUSH(ah);
  722. }
  723. static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
  724. struct ath9k_channel *chan)
  725. {
  726. struct modal_eep_4k_header *pModal;
  727. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  728. u8 biaslevel;
  729. if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
  730. return;
  731. if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
  732. return;
  733. pModal = &eep->modalHeader;
  734. if (pModal->xpaBiasLvl != 0xff) {
  735. biaslevel = pModal->xpaBiasLvl;
  736. INI_RA(&ah->iniAddac, 7, 1) =
  737. (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
  738. }
  739. }
  740. static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
  741. struct modal_eep_4k_header *pModal,
  742. struct ar5416_eeprom_4k *eep,
  743. u8 txRxAttenLocal)
  744. {
  745. REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
  746. pModal->antCtrlChain[0]);
  747. REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
  748. (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
  749. ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
  750. AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
  751. SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
  752. SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
  753. if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  754. AR5416_EEP_MINOR_VER_3) {
  755. txRxAttenLocal = pModal->txRxAttenCh[0];
  756. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  757. AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
  758. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  759. AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
  760. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  761. AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
  762. pModal->xatten2Margin[0]);
  763. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  764. AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
  765. /* Set the block 1 value to block 0 value */
  766. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  767. AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
  768. pModal->bswMargin[0]);
  769. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  770. AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
  771. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  772. AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
  773. pModal->xatten2Margin[0]);
  774. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  775. AR_PHY_GAIN_2GHZ_XATTEN2_DB,
  776. pModal->xatten2Db[0]);
  777. }
  778. REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
  779. AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
  780. REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
  781. AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
  782. REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
  783. AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
  784. REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
  785. AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
  786. }
  787. /*
  788. * Read EEPROM header info and program the device for correct operation
  789. * given the channel value.
  790. */
  791. static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
  792. struct ath9k_channel *chan)
  793. {
  794. struct modal_eep_4k_header *pModal;
  795. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  796. u8 txRxAttenLocal;
  797. u8 ob[5], db1[5], db2[5];
  798. u8 ant_div_control1, ant_div_control2;
  799. u32 regVal;
  800. pModal = &eep->modalHeader;
  801. txRxAttenLocal = 23;
  802. REG_WRITE(ah, AR_PHY_SWITCH_COM,
  803. ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
  804. /* Single chain for 4K EEPROM*/
  805. ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
  806. /* Initialize Ant Diversity settings from EEPROM */
  807. if (pModal->version >= 3) {
  808. ant_div_control1 = pModal->antdiv_ctl1;
  809. ant_div_control2 = pModal->antdiv_ctl2;
  810. regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
  811. regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
  812. regVal |= SM(ant_div_control1,
  813. AR_PHY_9285_ANT_DIV_CTL);
  814. regVal |= SM(ant_div_control2,
  815. AR_PHY_9285_ANT_DIV_ALT_LNACONF);
  816. regVal |= SM((ant_div_control2 >> 2),
  817. AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
  818. regVal |= SM((ant_div_control1 >> 1),
  819. AR_PHY_9285_ANT_DIV_ALT_GAINTB);
  820. regVal |= SM((ant_div_control1 >> 2),
  821. AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
  822. REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
  823. regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
  824. regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
  825. regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
  826. regVal |= SM((ant_div_control1 >> 3),
  827. AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
  828. REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
  829. regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
  830. }
  831. if (pModal->version >= 2) {
  832. ob[0] = pModal->ob_0;
  833. ob[1] = pModal->ob_1;
  834. ob[2] = pModal->ob_2;
  835. ob[3] = pModal->ob_3;
  836. ob[4] = pModal->ob_4;
  837. db1[0] = pModal->db1_0;
  838. db1[1] = pModal->db1_1;
  839. db1[2] = pModal->db1_2;
  840. db1[3] = pModal->db1_3;
  841. db1[4] = pModal->db1_4;
  842. db2[0] = pModal->db2_0;
  843. db2[1] = pModal->db2_1;
  844. db2[2] = pModal->db2_2;
  845. db2[3] = pModal->db2_3;
  846. db2[4] = pModal->db2_4;
  847. } else if (pModal->version == 1) {
  848. ob[0] = pModal->ob_0;
  849. ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
  850. db1[0] = pModal->db1_0;
  851. db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
  852. db2[0] = pModal->db2_0;
  853. db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
  854. } else {
  855. int i;
  856. for (i = 0; i < 5; i++) {
  857. ob[i] = pModal->ob_0;
  858. db1[i] = pModal->db1_0;
  859. db2[i] = pModal->db1_0;
  860. }
  861. }
  862. if (AR_SREV_9271(ah)) {
  863. ath9k_hw_analog_shift_rmw(ah,
  864. AR9285_AN_RF2G3,
  865. AR9271_AN_RF2G3_OB_cck,
  866. AR9271_AN_RF2G3_OB_cck_S,
  867. ob[0]);
  868. ath9k_hw_analog_shift_rmw(ah,
  869. AR9285_AN_RF2G3,
  870. AR9271_AN_RF2G3_OB_psk,
  871. AR9271_AN_RF2G3_OB_psk_S,
  872. ob[1]);
  873. ath9k_hw_analog_shift_rmw(ah,
  874. AR9285_AN_RF2G3,
  875. AR9271_AN_RF2G3_OB_qam,
  876. AR9271_AN_RF2G3_OB_qam_S,
  877. ob[2]);
  878. ath9k_hw_analog_shift_rmw(ah,
  879. AR9285_AN_RF2G3,
  880. AR9271_AN_RF2G3_DB_1,
  881. AR9271_AN_RF2G3_DB_1_S,
  882. db1[0]);
  883. ath9k_hw_analog_shift_rmw(ah,
  884. AR9285_AN_RF2G4,
  885. AR9271_AN_RF2G4_DB_2,
  886. AR9271_AN_RF2G4_DB_2_S,
  887. db2[0]);
  888. } else {
  889. ath9k_hw_analog_shift_rmw(ah,
  890. AR9285_AN_RF2G3,
  891. AR9285_AN_RF2G3_OB_0,
  892. AR9285_AN_RF2G3_OB_0_S,
  893. ob[0]);
  894. ath9k_hw_analog_shift_rmw(ah,
  895. AR9285_AN_RF2G3,
  896. AR9285_AN_RF2G3_OB_1,
  897. AR9285_AN_RF2G3_OB_1_S,
  898. ob[1]);
  899. ath9k_hw_analog_shift_rmw(ah,
  900. AR9285_AN_RF2G3,
  901. AR9285_AN_RF2G3_OB_2,
  902. AR9285_AN_RF2G3_OB_2_S,
  903. ob[2]);
  904. ath9k_hw_analog_shift_rmw(ah,
  905. AR9285_AN_RF2G3,
  906. AR9285_AN_RF2G3_OB_3,
  907. AR9285_AN_RF2G3_OB_3_S,
  908. ob[3]);
  909. ath9k_hw_analog_shift_rmw(ah,
  910. AR9285_AN_RF2G3,
  911. AR9285_AN_RF2G3_OB_4,
  912. AR9285_AN_RF2G3_OB_4_S,
  913. ob[4]);
  914. ath9k_hw_analog_shift_rmw(ah,
  915. AR9285_AN_RF2G3,
  916. AR9285_AN_RF2G3_DB1_0,
  917. AR9285_AN_RF2G3_DB1_0_S,
  918. db1[0]);
  919. ath9k_hw_analog_shift_rmw(ah,
  920. AR9285_AN_RF2G3,
  921. AR9285_AN_RF2G3_DB1_1,
  922. AR9285_AN_RF2G3_DB1_1_S,
  923. db1[1]);
  924. ath9k_hw_analog_shift_rmw(ah,
  925. AR9285_AN_RF2G3,
  926. AR9285_AN_RF2G3_DB1_2,
  927. AR9285_AN_RF2G3_DB1_2_S,
  928. db1[2]);
  929. ath9k_hw_analog_shift_rmw(ah,
  930. AR9285_AN_RF2G4,
  931. AR9285_AN_RF2G4_DB1_3,
  932. AR9285_AN_RF2G4_DB1_3_S,
  933. db1[3]);
  934. ath9k_hw_analog_shift_rmw(ah,
  935. AR9285_AN_RF2G4,
  936. AR9285_AN_RF2G4_DB1_4,
  937. AR9285_AN_RF2G4_DB1_4_S, db1[4]);
  938. ath9k_hw_analog_shift_rmw(ah,
  939. AR9285_AN_RF2G4,
  940. AR9285_AN_RF2G4_DB2_0,
  941. AR9285_AN_RF2G4_DB2_0_S,
  942. db2[0]);
  943. ath9k_hw_analog_shift_rmw(ah,
  944. AR9285_AN_RF2G4,
  945. AR9285_AN_RF2G4_DB2_1,
  946. AR9285_AN_RF2G4_DB2_1_S,
  947. db2[1]);
  948. ath9k_hw_analog_shift_rmw(ah,
  949. AR9285_AN_RF2G4,
  950. AR9285_AN_RF2G4_DB2_2,
  951. AR9285_AN_RF2G4_DB2_2_S,
  952. db2[2]);
  953. ath9k_hw_analog_shift_rmw(ah,
  954. AR9285_AN_RF2G4,
  955. AR9285_AN_RF2G4_DB2_3,
  956. AR9285_AN_RF2G4_DB2_3_S,
  957. db2[3]);
  958. ath9k_hw_analog_shift_rmw(ah,
  959. AR9285_AN_RF2G4,
  960. AR9285_AN_RF2G4_DB2_4,
  961. AR9285_AN_RF2G4_DB2_4_S,
  962. db2[4]);
  963. }
  964. REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
  965. pModal->switchSettling);
  966. REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
  967. pModal->adcDesiredSize);
  968. REG_WRITE(ah, AR_PHY_RF_CTL4,
  969. SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
  970. SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
  971. SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
  972. SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
  973. REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
  974. pModal->txEndToRxOn);
  975. if (AR_SREV_9271_10(ah))
  976. REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
  977. pModal->txEndToRxOn);
  978. REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
  979. pModal->thresh62);
  980. REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
  981. pModal->thresh62);
  982. if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  983. AR5416_EEP_MINOR_VER_2) {
  984. REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
  985. pModal->txFrameToDataStart);
  986. REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
  987. pModal->txFrameToPaOn);
  988. }
  989. if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  990. AR5416_EEP_MINOR_VER_3) {
  991. if (IS_CHAN_HT40(chan))
  992. REG_RMW_FIELD(ah, AR_PHY_SETTLING,
  993. AR_PHY_SETTLING_SWITCH,
  994. pModal->swSettleHt40);
  995. }
  996. }
  997. static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
  998. struct ath9k_channel *chan)
  999. {
  1000. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  1001. struct modal_eep_4k_header *pModal = &eep->modalHeader;
  1002. return pModal->antCtrlCommon;
  1003. }
  1004. static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
  1005. enum ath9k_hal_freq_band freq_band)
  1006. {
  1007. return 1;
  1008. }
  1009. static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
  1010. {
  1011. #define EEP_MAP4K_SPURCHAN \
  1012. (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
  1013. struct ath_common *common = ath9k_hw_common(ah);
  1014. u16 spur_val = AR_NO_SPUR;
  1015. ath_print(common, ATH_DBG_ANI,
  1016. "Getting spur idx %d is2Ghz. %d val %x\n",
  1017. i, is2GHz, ah->config.spurchans[i][is2GHz]);
  1018. switch (ah->config.spurmode) {
  1019. case SPUR_DISABLE:
  1020. break;
  1021. case SPUR_ENABLE_IOCTL:
  1022. spur_val = ah->config.spurchans[i][is2GHz];
  1023. ath_print(common, ATH_DBG_ANI,
  1024. "Getting spur val from new loc. %d\n", spur_val);
  1025. break;
  1026. case SPUR_ENABLE_EEPROM:
  1027. spur_val = EEP_MAP4K_SPURCHAN;
  1028. break;
  1029. }
  1030. return spur_val;
  1031. #undef EEP_MAP4K_SPURCHAN
  1032. }
  1033. const struct eeprom_ops eep_4k_ops = {
  1034. .check_eeprom = ath9k_hw_4k_check_eeprom,
  1035. .get_eeprom = ath9k_hw_4k_get_eeprom,
  1036. .fill_eeprom = ath9k_hw_4k_fill_eeprom,
  1037. .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
  1038. .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
  1039. .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
  1040. .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
  1041. .set_board_values = ath9k_hw_4k_set_board_values,
  1042. .set_addac = ath9k_hw_4k_set_addac,
  1043. .set_txpower = ath9k_hw_4k_set_txpower,
  1044. .get_spur_channel = ath9k_hw_4k_get_spur_channel
  1045. };