esas2r_init.c 46 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771
  1. /*
  2. * linux/drivers/scsi/esas2r/esas2r_init.c
  3. * For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers
  4. *
  5. * Copyright (c) 2001-2013 ATTO Technology, Inc.
  6. * (mailto:linuxdrivers@attotech.com)mpt3sas/mpt3sas_trigger_diag.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * NO WARRANTY
  19. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  20. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  21. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  22. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  23. * solely responsible for determining the appropriateness of using and
  24. * distributing the Program and assumes all risks associated with its
  25. * exercise of rights under this Agreement, including but not limited to
  26. * the risks and costs of program errors, damage to or loss of data,
  27. * programs or equipment, and unavailability or interruption of operations.
  28. *
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. *
  38. * You should have received a copy of the GNU General Public License
  39. * along with this program; if not, write to the Free Software
  40. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  41. * USA.
  42. */
  43. #include "esas2r.h"
  44. static bool esas2r_initmem_alloc(struct esas2r_adapter *a,
  45. struct esas2r_mem_desc *mem_desc,
  46. u32 align)
  47. {
  48. mem_desc->esas2r_param = mem_desc->size + align;
  49. mem_desc->virt_addr = NULL;
  50. mem_desc->phys_addr = 0;
  51. mem_desc->esas2r_data = dma_alloc_coherent(&a->pcid->dev,
  52. (size_t)mem_desc->
  53. esas2r_param,
  54. (dma_addr_t *)&mem_desc->
  55. phys_addr,
  56. GFP_KERNEL);
  57. if (mem_desc->esas2r_data == NULL) {
  58. esas2r_log(ESAS2R_LOG_CRIT,
  59. "failed to allocate %lu bytes of consistent memory!",
  60. (long
  61. unsigned
  62. int)mem_desc->esas2r_param);
  63. return false;
  64. }
  65. mem_desc->virt_addr = PTR_ALIGN(mem_desc->esas2r_data, align);
  66. mem_desc->phys_addr = ALIGN(mem_desc->phys_addr, align);
  67. memset(mem_desc->virt_addr, 0, mem_desc->size);
  68. return true;
  69. }
  70. static void esas2r_initmem_free(struct esas2r_adapter *a,
  71. struct esas2r_mem_desc *mem_desc)
  72. {
  73. if (mem_desc->virt_addr == NULL)
  74. return;
  75. /*
  76. * Careful! phys_addr and virt_addr may have been adjusted from the
  77. * original allocation in order to return the desired alignment. That
  78. * means we have to use the original address (in esas2r_data) and size
  79. * (esas2r_param) and calculate the original physical address based on
  80. * the difference between the requested and actual allocation size.
  81. */
  82. if (mem_desc->phys_addr) {
  83. int unalign = ((u8 *)mem_desc->virt_addr) -
  84. ((u8 *)mem_desc->esas2r_data);
  85. dma_free_coherent(&a->pcid->dev,
  86. (size_t)mem_desc->esas2r_param,
  87. mem_desc->esas2r_data,
  88. (dma_addr_t)(mem_desc->phys_addr - unalign));
  89. } else {
  90. kfree(mem_desc->esas2r_data);
  91. }
  92. mem_desc->virt_addr = NULL;
  93. }
  94. static bool alloc_vda_req(struct esas2r_adapter *a,
  95. struct esas2r_request *rq)
  96. {
  97. struct esas2r_mem_desc *memdesc = kzalloc(
  98. sizeof(struct esas2r_mem_desc), GFP_KERNEL);
  99. if (memdesc == NULL) {
  100. esas2r_hdebug("could not alloc mem for vda request memdesc\n");
  101. return false;
  102. }
  103. memdesc->size = sizeof(union atto_vda_req) +
  104. ESAS2R_DATA_BUF_LEN;
  105. if (!esas2r_initmem_alloc(a, memdesc, 256)) {
  106. esas2r_hdebug("could not alloc mem for vda request\n");
  107. kfree(memdesc);
  108. return false;
  109. }
  110. a->num_vrqs++;
  111. list_add(&memdesc->next_desc, &a->vrq_mds_head);
  112. rq->vrq_md = memdesc;
  113. rq->vrq = (union atto_vda_req *)memdesc->virt_addr;
  114. rq->vrq->scsi.handle = a->num_vrqs;
  115. return true;
  116. }
  117. static void esas2r_unmap_regions(struct esas2r_adapter *a)
  118. {
  119. if (a->regs)
  120. iounmap((void __iomem *)a->regs);
  121. a->regs = NULL;
  122. pci_release_region(a->pcid, 2);
  123. if (a->data_window)
  124. iounmap((void __iomem *)a->data_window);
  125. a->data_window = NULL;
  126. pci_release_region(a->pcid, 0);
  127. }
  128. static int esas2r_map_regions(struct esas2r_adapter *a)
  129. {
  130. int error;
  131. a->regs = NULL;
  132. a->data_window = NULL;
  133. error = pci_request_region(a->pcid, 2, a->name);
  134. if (error != 0) {
  135. esas2r_log(ESAS2R_LOG_CRIT,
  136. "pci_request_region(2) failed, error %d",
  137. error);
  138. return error;
  139. }
  140. a->regs = (void __force *)ioremap(pci_resource_start(a->pcid, 2),
  141. pci_resource_len(a->pcid, 2));
  142. if (a->regs == NULL) {
  143. esas2r_log(ESAS2R_LOG_CRIT,
  144. "ioremap failed for regs mem region\n");
  145. pci_release_region(a->pcid, 2);
  146. return -EFAULT;
  147. }
  148. error = pci_request_region(a->pcid, 0, a->name);
  149. if (error != 0) {
  150. esas2r_log(ESAS2R_LOG_CRIT,
  151. "pci_request_region(2) failed, error %d",
  152. error);
  153. esas2r_unmap_regions(a);
  154. return error;
  155. }
  156. a->data_window = (void __force *)ioremap(pci_resource_start(a->pcid,
  157. 0),
  158. pci_resource_len(a->pcid, 0));
  159. if (a->data_window == NULL) {
  160. esas2r_log(ESAS2R_LOG_CRIT,
  161. "ioremap failed for data_window mem region\n");
  162. esas2r_unmap_regions(a);
  163. return -EFAULT;
  164. }
  165. return 0;
  166. }
  167. static void esas2r_setup_interrupts(struct esas2r_adapter *a, int intr_mode)
  168. {
  169. int i;
  170. /* Set up interrupt mode based on the requested value */
  171. switch (intr_mode) {
  172. case INTR_MODE_LEGACY:
  173. use_legacy_interrupts:
  174. a->intr_mode = INTR_MODE_LEGACY;
  175. break;
  176. case INTR_MODE_MSI:
  177. i = pci_enable_msi(a->pcid);
  178. if (i != 0) {
  179. esas2r_log(ESAS2R_LOG_WARN,
  180. "failed to enable MSI for adapter %d, "
  181. "falling back to legacy interrupts "
  182. "(err=%d)", a->index,
  183. i);
  184. goto use_legacy_interrupts;
  185. }
  186. a->intr_mode = INTR_MODE_MSI;
  187. set_bit(AF2_MSI_ENABLED, &a->flags2);
  188. break;
  189. default:
  190. esas2r_log(ESAS2R_LOG_WARN,
  191. "unknown interrupt_mode %d requested, "
  192. "falling back to legacy interrupt",
  193. interrupt_mode);
  194. goto use_legacy_interrupts;
  195. }
  196. }
  197. static void esas2r_claim_interrupts(struct esas2r_adapter *a)
  198. {
  199. unsigned long flags = IRQF_DISABLED;
  200. if (a->intr_mode == INTR_MODE_LEGACY)
  201. flags |= IRQF_SHARED;
  202. esas2r_log(ESAS2R_LOG_INFO,
  203. "esas2r_claim_interrupts irq=%d (%p, %s, %x)",
  204. a->pcid->irq, a, a->name, flags);
  205. if (request_irq(a->pcid->irq,
  206. (a->intr_mode ==
  207. INTR_MODE_LEGACY) ? esas2r_interrupt :
  208. esas2r_msi_interrupt,
  209. flags,
  210. a->name,
  211. a)) {
  212. esas2r_log(ESAS2R_LOG_CRIT, "unable to request IRQ %02X",
  213. a->pcid->irq);
  214. return;
  215. }
  216. set_bit(AF2_IRQ_CLAIMED, &a->flags2);
  217. esas2r_log(ESAS2R_LOG_INFO,
  218. "claimed IRQ %d flags: 0x%lx",
  219. a->pcid->irq, flags);
  220. }
  221. int esas2r_init_adapter(struct Scsi_Host *host, struct pci_dev *pcid,
  222. int index)
  223. {
  224. struct esas2r_adapter *a;
  225. u64 bus_addr = 0;
  226. int i;
  227. void *next_uncached;
  228. struct esas2r_request *first_request, *last_request;
  229. if (index >= MAX_ADAPTERS) {
  230. esas2r_log(ESAS2R_LOG_CRIT,
  231. "tried to init invalid adapter index %u!",
  232. index);
  233. return 0;
  234. }
  235. if (esas2r_adapters[index]) {
  236. esas2r_log(ESAS2R_LOG_CRIT,
  237. "tried to init existing adapter index %u!",
  238. index);
  239. return 0;
  240. }
  241. a = (struct esas2r_adapter *)host->hostdata;
  242. memset(a, 0, sizeof(struct esas2r_adapter));
  243. a->pcid = pcid;
  244. a->host = host;
  245. if (sizeof(dma_addr_t) > 4) {
  246. const uint64_t required_mask = dma_get_required_mask
  247. (&pcid->dev);
  248. if (required_mask > DMA_BIT_MASK(32)
  249. && !pci_set_dma_mask(pcid, DMA_BIT_MASK(64))
  250. && !pci_set_consistent_dma_mask(pcid,
  251. DMA_BIT_MASK(64))) {
  252. esas2r_log_dev(ESAS2R_LOG_INFO,
  253. &(a->pcid->dev),
  254. "64-bit PCI addressing enabled\n");
  255. } else if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
  256. && !pci_set_consistent_dma_mask(pcid,
  257. DMA_BIT_MASK(32))) {
  258. esas2r_log_dev(ESAS2R_LOG_INFO,
  259. &(a->pcid->dev),
  260. "32-bit PCI addressing enabled\n");
  261. } else {
  262. esas2r_log(ESAS2R_LOG_CRIT,
  263. "failed to set DMA mask");
  264. esas2r_kill_adapter(index);
  265. return 0;
  266. }
  267. } else {
  268. if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
  269. && !pci_set_consistent_dma_mask(pcid,
  270. DMA_BIT_MASK(32))) {
  271. esas2r_log_dev(ESAS2R_LOG_INFO,
  272. &(a->pcid->dev),
  273. "32-bit PCI addressing enabled\n");
  274. } else {
  275. esas2r_log(ESAS2R_LOG_CRIT,
  276. "failed to set DMA mask");
  277. esas2r_kill_adapter(index);
  278. return 0;
  279. }
  280. }
  281. esas2r_adapters[index] = a;
  282. sprintf(a->name, ESAS2R_DRVR_NAME "_%02d", index);
  283. esas2r_debug("new adapter %p, name %s", a, a->name);
  284. spin_lock_init(&a->request_lock);
  285. spin_lock_init(&a->fw_event_lock);
  286. sema_init(&a->fm_api_semaphore, 1);
  287. sema_init(&a->fs_api_semaphore, 1);
  288. sema_init(&a->nvram_semaphore, 1);
  289. esas2r_fw_event_off(a);
  290. snprintf(a->fw_event_q_name, ESAS2R_KOBJ_NAME_LEN, "esas2r/%d",
  291. a->index);
  292. a->fw_event_q = create_singlethread_workqueue(a->fw_event_q_name);
  293. init_waitqueue_head(&a->buffered_ioctl_waiter);
  294. init_waitqueue_head(&a->nvram_waiter);
  295. init_waitqueue_head(&a->fm_api_waiter);
  296. init_waitqueue_head(&a->fs_api_waiter);
  297. init_waitqueue_head(&a->vda_waiter);
  298. INIT_LIST_HEAD(&a->general_req.req_list);
  299. INIT_LIST_HEAD(&a->active_list);
  300. INIT_LIST_HEAD(&a->defer_list);
  301. INIT_LIST_HEAD(&a->free_sg_list_head);
  302. INIT_LIST_HEAD(&a->avail_request);
  303. INIT_LIST_HEAD(&a->vrq_mds_head);
  304. INIT_LIST_HEAD(&a->fw_event_list);
  305. first_request = (struct esas2r_request *)((u8 *)(a + 1));
  306. for (last_request = first_request, i = 1; i < num_requests;
  307. last_request++, i++) {
  308. INIT_LIST_HEAD(&last_request->req_list);
  309. list_add_tail(&last_request->comp_list, &a->avail_request);
  310. if (!alloc_vda_req(a, last_request)) {
  311. esas2r_log(ESAS2R_LOG_CRIT,
  312. "failed to allocate a VDA request!");
  313. esas2r_kill_adapter(index);
  314. return 0;
  315. }
  316. }
  317. esas2r_debug("requests: %p to %p (%d, %d)", first_request,
  318. last_request,
  319. sizeof(*first_request),
  320. num_requests);
  321. if (esas2r_map_regions(a) != 0) {
  322. esas2r_log(ESAS2R_LOG_CRIT, "could not map PCI regions!");
  323. esas2r_kill_adapter(index);
  324. return 0;
  325. }
  326. a->index = index;
  327. /* interrupts will be disabled until we are done with init */
  328. atomic_inc(&a->dis_ints_cnt);
  329. atomic_inc(&a->disable_cnt);
  330. set_bit(AF_CHPRST_PENDING, &a->flags);
  331. set_bit(AF_DISC_PENDING, &a->flags);
  332. set_bit(AF_FIRST_INIT, &a->flags);
  333. set_bit(AF_LEGACY_SGE_MODE, &a->flags);
  334. a->init_msg = ESAS2R_INIT_MSG_START;
  335. a->max_vdareq_size = 128;
  336. a->build_sgl = esas2r_build_sg_list_sge;
  337. esas2r_setup_interrupts(a, interrupt_mode);
  338. a->uncached_size = esas2r_get_uncached_size(a);
  339. a->uncached = dma_alloc_coherent(&pcid->dev,
  340. (size_t)a->uncached_size,
  341. (dma_addr_t *)&bus_addr,
  342. GFP_KERNEL);
  343. if (a->uncached == NULL) {
  344. esas2r_log(ESAS2R_LOG_CRIT,
  345. "failed to allocate %d bytes of consistent memory!",
  346. a->uncached_size);
  347. esas2r_kill_adapter(index);
  348. return 0;
  349. }
  350. a->uncached_phys = bus_addr;
  351. esas2r_debug("%d bytes uncached memory allocated @ %p (%x:%x)",
  352. a->uncached_size,
  353. a->uncached,
  354. upper_32_bits(bus_addr),
  355. lower_32_bits(bus_addr));
  356. memset(a->uncached, 0, a->uncached_size);
  357. next_uncached = a->uncached;
  358. if (!esas2r_init_adapter_struct(a,
  359. &next_uncached)) {
  360. esas2r_log(ESAS2R_LOG_CRIT,
  361. "failed to initialize adapter structure (2)!");
  362. esas2r_kill_adapter(index);
  363. return 0;
  364. }
  365. tasklet_init(&a->tasklet,
  366. esas2r_adapter_tasklet,
  367. (unsigned long)a);
  368. /*
  369. * Disable chip interrupts to prevent spurious interrupts
  370. * until we claim the IRQ.
  371. */
  372. esas2r_disable_chip_interrupts(a);
  373. esas2r_check_adapter(a);
  374. if (!esas2r_init_adapter_hw(a, true))
  375. esas2r_log(ESAS2R_LOG_CRIT, "failed to initialize hardware!");
  376. else
  377. esas2r_debug("esas2r_init_adapter ok");
  378. esas2r_claim_interrupts(a);
  379. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2))
  380. esas2r_enable_chip_interrupts(a);
  381. set_bit(AF2_INIT_DONE, &a->flags2);
  382. if (!test_bit(AF_DEGRADED_MODE, &a->flags))
  383. esas2r_kickoff_timer(a);
  384. esas2r_debug("esas2r_init_adapter done for %p (%d)",
  385. a, a->disable_cnt);
  386. return 1;
  387. }
  388. static void esas2r_adapter_power_down(struct esas2r_adapter *a,
  389. int power_management)
  390. {
  391. struct esas2r_mem_desc *memdesc, *next;
  392. if ((test_bit(AF2_INIT_DONE, &a->flags2))
  393. && (!test_bit(AF_DEGRADED_MODE, &a->flags))) {
  394. if (!power_management) {
  395. del_timer_sync(&a->timer);
  396. tasklet_kill(&a->tasklet);
  397. }
  398. esas2r_power_down(a);
  399. /*
  400. * There are versions of firmware that do not handle the sync
  401. * cache command correctly. Stall here to ensure that the
  402. * cache is lazily flushed.
  403. */
  404. mdelay(500);
  405. esas2r_debug("chip halted");
  406. }
  407. /* Remove sysfs binary files */
  408. if (a->sysfs_fw_created) {
  409. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fw);
  410. a->sysfs_fw_created = 0;
  411. }
  412. if (a->sysfs_fs_created) {
  413. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fs);
  414. a->sysfs_fs_created = 0;
  415. }
  416. if (a->sysfs_vda_created) {
  417. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_vda);
  418. a->sysfs_vda_created = 0;
  419. }
  420. if (a->sysfs_hw_created) {
  421. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_hw);
  422. a->sysfs_hw_created = 0;
  423. }
  424. if (a->sysfs_live_nvram_created) {
  425. sysfs_remove_bin_file(&a->host->shost_dev.kobj,
  426. &bin_attr_live_nvram);
  427. a->sysfs_live_nvram_created = 0;
  428. }
  429. if (a->sysfs_default_nvram_created) {
  430. sysfs_remove_bin_file(&a->host->shost_dev.kobj,
  431. &bin_attr_default_nvram);
  432. a->sysfs_default_nvram_created = 0;
  433. }
  434. /* Clean up interrupts */
  435. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
  436. esas2r_log_dev(ESAS2R_LOG_INFO,
  437. &(a->pcid->dev),
  438. "free_irq(%d) called", a->pcid->irq);
  439. free_irq(a->pcid->irq, a);
  440. esas2r_debug("IRQ released");
  441. clear_bit(AF2_IRQ_CLAIMED, &a->flags2);
  442. }
  443. if (test_bit(AF2_MSI_ENABLED, &a->flags2)) {
  444. pci_disable_msi(a->pcid);
  445. clear_bit(AF2_MSI_ENABLED, &a->flags2);
  446. esas2r_debug("MSI disabled");
  447. }
  448. if (a->inbound_list_md.virt_addr)
  449. esas2r_initmem_free(a, &a->inbound_list_md);
  450. if (a->outbound_list_md.virt_addr)
  451. esas2r_initmem_free(a, &a->outbound_list_md);
  452. list_for_each_entry_safe(memdesc, next, &a->free_sg_list_head,
  453. next_desc) {
  454. esas2r_initmem_free(a, memdesc);
  455. }
  456. /* Following frees everything allocated via alloc_vda_req */
  457. list_for_each_entry_safe(memdesc, next, &a->vrq_mds_head, next_desc) {
  458. esas2r_initmem_free(a, memdesc);
  459. list_del(&memdesc->next_desc);
  460. kfree(memdesc);
  461. }
  462. kfree(a->first_ae_req);
  463. a->first_ae_req = NULL;
  464. kfree(a->sg_list_mds);
  465. a->sg_list_mds = NULL;
  466. kfree(a->req_table);
  467. a->req_table = NULL;
  468. if (a->regs) {
  469. esas2r_unmap_regions(a);
  470. a->regs = NULL;
  471. a->data_window = NULL;
  472. esas2r_debug("regions unmapped");
  473. }
  474. }
  475. /* Release/free allocated resources for specified adapters. */
  476. void esas2r_kill_adapter(int i)
  477. {
  478. struct esas2r_adapter *a = esas2r_adapters[i];
  479. if (a) {
  480. unsigned long flags;
  481. struct workqueue_struct *wq;
  482. esas2r_debug("killing adapter %p [%d] ", a, i);
  483. esas2r_fw_event_off(a);
  484. esas2r_adapter_power_down(a, 0);
  485. if (esas2r_buffered_ioctl &&
  486. (a->pcid == esas2r_buffered_ioctl_pcid)) {
  487. dma_free_coherent(&a->pcid->dev,
  488. (size_t)esas2r_buffered_ioctl_size,
  489. esas2r_buffered_ioctl,
  490. esas2r_buffered_ioctl_addr);
  491. esas2r_buffered_ioctl = NULL;
  492. }
  493. if (a->vda_buffer) {
  494. dma_free_coherent(&a->pcid->dev,
  495. (size_t)VDA_MAX_BUFFER_SIZE,
  496. a->vda_buffer,
  497. (dma_addr_t)a->ppvda_buffer);
  498. a->vda_buffer = NULL;
  499. }
  500. if (a->fs_api_buffer) {
  501. dma_free_coherent(&a->pcid->dev,
  502. (size_t)a->fs_api_buffer_size,
  503. a->fs_api_buffer,
  504. (dma_addr_t)a->ppfs_api_buffer);
  505. a->fs_api_buffer = NULL;
  506. }
  507. kfree(a->local_atto_ioctl);
  508. a->local_atto_ioctl = NULL;
  509. spin_lock_irqsave(&a->fw_event_lock, flags);
  510. wq = a->fw_event_q;
  511. a->fw_event_q = NULL;
  512. spin_unlock_irqrestore(&a->fw_event_lock, flags);
  513. if (wq)
  514. destroy_workqueue(wq);
  515. if (a->uncached) {
  516. dma_free_coherent(&a->pcid->dev,
  517. (size_t)a->uncached_size,
  518. a->uncached,
  519. (dma_addr_t)a->uncached_phys);
  520. a->uncached = NULL;
  521. esas2r_debug("uncached area freed");
  522. }
  523. esas2r_log_dev(ESAS2R_LOG_INFO,
  524. &(a->pcid->dev),
  525. "pci_disable_device() called. msix_enabled: %d "
  526. "msi_enabled: %d irq: %d pin: %d",
  527. a->pcid->msix_enabled,
  528. a->pcid->msi_enabled,
  529. a->pcid->irq,
  530. a->pcid->pin);
  531. esas2r_log_dev(ESAS2R_LOG_INFO,
  532. &(a->pcid->dev),
  533. "before pci_disable_device() enable_cnt: %d",
  534. a->pcid->enable_cnt.counter);
  535. pci_disable_device(a->pcid);
  536. esas2r_log_dev(ESAS2R_LOG_INFO,
  537. &(a->pcid->dev),
  538. "after pci_disable_device() enable_cnt: %d",
  539. a->pcid->enable_cnt.counter);
  540. esas2r_log_dev(ESAS2R_LOG_INFO,
  541. &(a->pcid->dev),
  542. "pci_set_drv_data(%p, NULL) called",
  543. a->pcid);
  544. pci_set_drvdata(a->pcid, NULL);
  545. esas2r_adapters[i] = NULL;
  546. if (test_bit(AF2_INIT_DONE, &a->flags2)) {
  547. clear_bit(AF2_INIT_DONE, &a->flags2);
  548. set_bit(AF_DEGRADED_MODE, &a->flags);
  549. esas2r_log_dev(ESAS2R_LOG_INFO,
  550. &(a->host->shost_gendev),
  551. "scsi_remove_host() called");
  552. scsi_remove_host(a->host);
  553. esas2r_log_dev(ESAS2R_LOG_INFO,
  554. &(a->host->shost_gendev),
  555. "scsi_host_put() called");
  556. scsi_host_put(a->host);
  557. }
  558. }
  559. }
  560. int esas2r_cleanup(struct Scsi_Host *host)
  561. {
  562. struct esas2r_adapter *a;
  563. int index;
  564. if (host == NULL) {
  565. int i;
  566. esas2r_debug("esas2r_cleanup everything");
  567. for (i = 0; i < MAX_ADAPTERS; i++)
  568. esas2r_kill_adapter(i);
  569. return -1;
  570. }
  571. esas2r_debug("esas2r_cleanup called for host %p", host);
  572. a = (struct esas2r_adapter *)host->hostdata;
  573. index = a->index;
  574. esas2r_kill_adapter(index);
  575. return index;
  576. }
  577. int esas2r_suspend(struct pci_dev *pdev, pm_message_t state)
  578. {
  579. struct Scsi_Host *host = pci_get_drvdata(pdev);
  580. u32 device_state;
  581. struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
  582. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "suspending adapter()");
  583. if (!a)
  584. return -ENODEV;
  585. esas2r_adapter_power_down(a, 1);
  586. device_state = pci_choose_state(pdev, state);
  587. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  588. "pci_save_state() called");
  589. pci_save_state(pdev);
  590. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  591. "pci_disable_device() called");
  592. pci_disable_device(pdev);
  593. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  594. "pci_set_power_state() called");
  595. pci_set_power_state(pdev, device_state);
  596. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "esas2r_suspend(): 0");
  597. return 0;
  598. }
  599. int esas2r_resume(struct pci_dev *pdev)
  600. {
  601. struct Scsi_Host *host = pci_get_drvdata(pdev);
  602. struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
  603. int rez;
  604. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "resuming adapter()");
  605. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  606. "pci_set_power_state(PCI_D0) "
  607. "called");
  608. pci_set_power_state(pdev, PCI_D0);
  609. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  610. "pci_enable_wake(PCI_D0, 0) "
  611. "called");
  612. pci_enable_wake(pdev, PCI_D0, 0);
  613. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  614. "pci_restore_state() called");
  615. pci_restore_state(pdev);
  616. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  617. "pci_enable_device() called");
  618. rez = pci_enable_device(pdev);
  619. pci_set_master(pdev);
  620. if (!a) {
  621. rez = -ENODEV;
  622. goto error_exit;
  623. }
  624. if (esas2r_map_regions(a) != 0) {
  625. esas2r_log(ESAS2R_LOG_CRIT, "could not re-map PCI regions!");
  626. rez = -ENOMEM;
  627. goto error_exit;
  628. }
  629. /* Set up interupt mode */
  630. esas2r_setup_interrupts(a, a->intr_mode);
  631. /*
  632. * Disable chip interrupts to prevent spurious interrupts until we
  633. * claim the IRQ.
  634. */
  635. esas2r_disable_chip_interrupts(a);
  636. if (!esas2r_power_up(a, true)) {
  637. esas2r_debug("yikes, esas2r_power_up failed");
  638. rez = -ENOMEM;
  639. goto error_exit;
  640. }
  641. esas2r_claim_interrupts(a);
  642. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
  643. /*
  644. * Now that system interrupt(s) are claimed, we can enable
  645. * chip interrupts.
  646. */
  647. esas2r_enable_chip_interrupts(a);
  648. esas2r_kickoff_timer(a);
  649. } else {
  650. esas2r_debug("yikes, unable to claim IRQ");
  651. esas2r_log(ESAS2R_LOG_CRIT, "could not re-claim IRQ!");
  652. rez = -ENOMEM;
  653. goto error_exit;
  654. }
  655. error_exit:
  656. esas2r_log_dev(ESAS2R_LOG_CRIT, &(pdev->dev), "esas2r_resume(): %d",
  657. rez);
  658. return rez;
  659. }
  660. bool esas2r_set_degraded_mode(struct esas2r_adapter *a, char *error_str)
  661. {
  662. set_bit(AF_DEGRADED_MODE, &a->flags);
  663. esas2r_log(ESAS2R_LOG_CRIT,
  664. "setting adapter to degraded mode: %s\n", error_str);
  665. return false;
  666. }
  667. u32 esas2r_get_uncached_size(struct esas2r_adapter *a)
  668. {
  669. return sizeof(struct esas2r_sas_nvram)
  670. + ALIGN(ESAS2R_DISC_BUF_LEN, 8)
  671. + ALIGN(sizeof(u32), 8) /* outbound list copy pointer */
  672. + 8
  673. + (num_sg_lists * (u16)sgl_page_size)
  674. + ALIGN((num_requests + num_ae_requests + 1 +
  675. ESAS2R_LIST_EXTRA) *
  676. sizeof(struct esas2r_inbound_list_source_entry),
  677. 8)
  678. + ALIGN((num_requests + num_ae_requests + 1 +
  679. ESAS2R_LIST_EXTRA) *
  680. sizeof(struct atto_vda_ob_rsp), 8)
  681. + 256; /* VDA request and buffer align */
  682. }
  683. static void esas2r_init_pci_cfg_space(struct esas2r_adapter *a)
  684. {
  685. int pcie_cap_reg;
  686. pcie_cap_reg = pci_find_capability(a->pcid, PCI_CAP_ID_EXP);
  687. if (pcie_cap_reg) {
  688. u16 devcontrol;
  689. pci_read_config_word(a->pcid, pcie_cap_reg + PCI_EXP_DEVCTL,
  690. &devcontrol);
  691. if ((devcontrol & PCI_EXP_DEVCTL_READRQ) > 0x2000) {
  692. esas2r_log(ESAS2R_LOG_INFO,
  693. "max read request size > 512B");
  694. devcontrol &= ~PCI_EXP_DEVCTL_READRQ;
  695. devcontrol |= 0x2000;
  696. pci_write_config_word(a->pcid,
  697. pcie_cap_reg + PCI_EXP_DEVCTL,
  698. devcontrol);
  699. }
  700. }
  701. }
  702. /*
  703. * Determine the organization of the uncached data area and
  704. * finish initializing the adapter structure
  705. */
  706. bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
  707. void **uncached_area)
  708. {
  709. u32 i;
  710. u8 *high;
  711. struct esas2r_inbound_list_source_entry *element;
  712. struct esas2r_request *rq;
  713. struct esas2r_mem_desc *sgl;
  714. spin_lock_init(&a->sg_list_lock);
  715. spin_lock_init(&a->mem_lock);
  716. spin_lock_init(&a->queue_lock);
  717. a->targetdb_end = &a->targetdb[ESAS2R_MAX_TARGETS];
  718. if (!alloc_vda_req(a, &a->general_req)) {
  719. esas2r_hdebug(
  720. "failed to allocate a VDA request for the general req!");
  721. return false;
  722. }
  723. /* allocate requests for asynchronous events */
  724. a->first_ae_req =
  725. kzalloc(num_ae_requests * sizeof(struct esas2r_request),
  726. GFP_KERNEL);
  727. if (a->first_ae_req == NULL) {
  728. esas2r_log(ESAS2R_LOG_CRIT,
  729. "failed to allocate memory for asynchronous events");
  730. return false;
  731. }
  732. /* allocate the S/G list memory descriptors */
  733. a->sg_list_mds = kzalloc(
  734. num_sg_lists * sizeof(struct esas2r_mem_desc), GFP_KERNEL);
  735. if (a->sg_list_mds == NULL) {
  736. esas2r_log(ESAS2R_LOG_CRIT,
  737. "failed to allocate memory for s/g list descriptors");
  738. return false;
  739. }
  740. /* allocate the request table */
  741. a->req_table =
  742. kzalloc((num_requests + num_ae_requests +
  743. 1) * sizeof(struct esas2r_request *), GFP_KERNEL);
  744. if (a->req_table == NULL) {
  745. esas2r_log(ESAS2R_LOG_CRIT,
  746. "failed to allocate memory for the request table");
  747. return false;
  748. }
  749. /* initialize PCI configuration space */
  750. esas2r_init_pci_cfg_space(a);
  751. /*
  752. * the thunder_stream boards all have a serial flash part that has a
  753. * different base address on the AHB bus.
  754. */
  755. if ((a->pcid->subsystem_vendor == ATTO_VENDOR_ID)
  756. && (a->pcid->subsystem_device & ATTO_SSDID_TBT))
  757. a->flags2 |= AF2_THUNDERBOLT;
  758. if (test_bit(AF2_THUNDERBOLT, &a->flags2))
  759. a->flags2 |= AF2_SERIAL_FLASH;
  760. if (a->pcid->subsystem_device == ATTO_TLSH_1068)
  761. a->flags2 |= AF2_THUNDERLINK;
  762. /* Uncached Area */
  763. high = (u8 *)*uncached_area;
  764. /* initialize the scatter/gather table pages */
  765. for (i = 0, sgl = a->sg_list_mds; i < num_sg_lists; i++, sgl++) {
  766. sgl->size = sgl_page_size;
  767. list_add_tail(&sgl->next_desc, &a->free_sg_list_head);
  768. if (!esas2r_initmem_alloc(a, sgl, ESAS2R_SGL_ALIGN)) {
  769. /* Allow the driver to load if the minimum count met. */
  770. if (i < NUM_SGL_MIN)
  771. return false;
  772. break;
  773. }
  774. }
  775. /* compute the size of the lists */
  776. a->list_size = num_requests + ESAS2R_LIST_EXTRA;
  777. /* allocate the inbound list */
  778. a->inbound_list_md.size = a->list_size *
  779. sizeof(struct
  780. esas2r_inbound_list_source_entry);
  781. if (!esas2r_initmem_alloc(a, &a->inbound_list_md, ESAS2R_LIST_ALIGN)) {
  782. esas2r_hdebug("failed to allocate IB list");
  783. return false;
  784. }
  785. /* allocate the outbound list */
  786. a->outbound_list_md.size = a->list_size *
  787. sizeof(struct atto_vda_ob_rsp);
  788. if (!esas2r_initmem_alloc(a, &a->outbound_list_md,
  789. ESAS2R_LIST_ALIGN)) {
  790. esas2r_hdebug("failed to allocate IB list");
  791. return false;
  792. }
  793. /* allocate the NVRAM structure */
  794. a->nvram = (struct esas2r_sas_nvram *)high;
  795. high += sizeof(struct esas2r_sas_nvram);
  796. /* allocate the discovery buffer */
  797. a->disc_buffer = high;
  798. high += ESAS2R_DISC_BUF_LEN;
  799. high = PTR_ALIGN(high, 8);
  800. /* allocate the outbound list copy pointer */
  801. a->outbound_copy = (u32 volatile *)high;
  802. high += sizeof(u32);
  803. if (!test_bit(AF_NVR_VALID, &a->flags))
  804. esas2r_nvram_set_defaults(a);
  805. /* update the caller's uncached memory area pointer */
  806. *uncached_area = (void *)high;
  807. /* initialize the allocated memory */
  808. if (test_bit(AF_FIRST_INIT, &a->flags)) {
  809. memset(a->req_table, 0,
  810. (num_requests + num_ae_requests +
  811. 1) * sizeof(struct esas2r_request *));
  812. esas2r_targ_db_initialize(a);
  813. /* prime parts of the inbound list */
  814. element =
  815. (struct esas2r_inbound_list_source_entry *)a->
  816. inbound_list_md.
  817. virt_addr;
  818. for (i = 0; i < a->list_size; i++) {
  819. element->address = 0;
  820. element->reserved = 0;
  821. element->length = cpu_to_le32(HWILSE_INTERFACE_F0
  822. | (sizeof(union
  823. atto_vda_req)
  824. /
  825. sizeof(u32)));
  826. element++;
  827. }
  828. /* init the AE requests */
  829. for (rq = a->first_ae_req, i = 0; i < num_ae_requests; rq++,
  830. i++) {
  831. INIT_LIST_HEAD(&rq->req_list);
  832. if (!alloc_vda_req(a, rq)) {
  833. esas2r_hdebug(
  834. "failed to allocate a VDA request!");
  835. return false;
  836. }
  837. esas2r_rq_init_request(rq, a);
  838. /* override the completion function */
  839. rq->comp_cb = esas2r_ae_complete;
  840. }
  841. }
  842. return true;
  843. }
  844. /* This code will verify that the chip is operational. */
  845. bool esas2r_check_adapter(struct esas2r_adapter *a)
  846. {
  847. u32 starttime;
  848. u32 doorbell;
  849. u64 ppaddr;
  850. u32 dw;
  851. /*
  852. * if the chip reset detected flag is set, we can bypass a bunch of
  853. * stuff.
  854. */
  855. if (test_bit(AF_CHPRST_DETECTED, &a->flags))
  856. goto skip_chip_reset;
  857. /*
  858. * BEFORE WE DO ANYTHING, disable the chip interrupts! the boot driver
  859. * may have left them enabled or we may be recovering from a fault.
  860. */
  861. esas2r_write_register_dword(a, MU_INT_MASK_OUT, ESAS2R_INT_DIS_MASK);
  862. esas2r_flush_register_dword(a, MU_INT_MASK_OUT);
  863. /*
  864. * wait for the firmware to become ready by forcing an interrupt and
  865. * waiting for a response.
  866. */
  867. starttime = jiffies_to_msecs(jiffies);
  868. while (true) {
  869. esas2r_force_interrupt(a);
  870. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  871. if (doorbell == 0xFFFFFFFF) {
  872. /*
  873. * Give the firmware up to two seconds to enable
  874. * register access after a reset.
  875. */
  876. if ((jiffies_to_msecs(jiffies) - starttime) > 2000)
  877. return esas2r_set_degraded_mode(a,
  878. "unable to access registers");
  879. } else if (doorbell & DRBL_FORCE_INT) {
  880. u32 ver = (doorbell & DRBL_FW_VER_MSK);
  881. /*
  882. * This driver supports version 0 and version 1 of
  883. * the API
  884. */
  885. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  886. doorbell);
  887. if (ver == DRBL_FW_VER_0) {
  888. set_bit(AF_LEGACY_SGE_MODE, &a->flags);
  889. a->max_vdareq_size = 128;
  890. a->build_sgl = esas2r_build_sg_list_sge;
  891. } else if (ver == DRBL_FW_VER_1) {
  892. clear_bit(AF_LEGACY_SGE_MODE, &a->flags);
  893. a->max_vdareq_size = 1024;
  894. a->build_sgl = esas2r_build_sg_list_prd;
  895. } else {
  896. return esas2r_set_degraded_mode(a,
  897. "unknown firmware version");
  898. }
  899. break;
  900. }
  901. schedule_timeout_interruptible(msecs_to_jiffies(100));
  902. if ((jiffies_to_msecs(jiffies) - starttime) > 180000) {
  903. esas2r_hdebug("FW ready TMO");
  904. esas2r_bugon();
  905. return esas2r_set_degraded_mode(a,
  906. "firmware start has timed out");
  907. }
  908. }
  909. /* purge any asynchronous events since we will repost them later */
  910. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_DOWN);
  911. starttime = jiffies_to_msecs(jiffies);
  912. while (true) {
  913. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  914. if (doorbell & DRBL_MSG_IFC_DOWN) {
  915. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  916. doorbell);
  917. break;
  918. }
  919. schedule_timeout_interruptible(msecs_to_jiffies(50));
  920. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  921. esas2r_hdebug("timeout waiting for interface down");
  922. break;
  923. }
  924. }
  925. skip_chip_reset:
  926. /*
  927. * first things first, before we go changing any of these registers
  928. * disable the communication lists.
  929. */
  930. dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
  931. dw &= ~MU_ILC_ENABLE;
  932. esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
  933. dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
  934. dw &= ~MU_OLC_ENABLE;
  935. esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
  936. /* configure the communication list addresses */
  937. ppaddr = a->inbound_list_md.phys_addr;
  938. esas2r_write_register_dword(a, MU_IN_LIST_ADDR_LO,
  939. lower_32_bits(ppaddr));
  940. esas2r_write_register_dword(a, MU_IN_LIST_ADDR_HI,
  941. upper_32_bits(ppaddr));
  942. ppaddr = a->outbound_list_md.phys_addr;
  943. esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_LO,
  944. lower_32_bits(ppaddr));
  945. esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_HI,
  946. upper_32_bits(ppaddr));
  947. ppaddr = a->uncached_phys +
  948. ((u8 *)a->outbound_copy - a->uncached);
  949. esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_LO,
  950. lower_32_bits(ppaddr));
  951. esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_HI,
  952. upper_32_bits(ppaddr));
  953. /* reset the read and write pointers */
  954. *a->outbound_copy =
  955. a->last_write =
  956. a->last_read = a->list_size - 1;
  957. set_bit(AF_COMM_LIST_TOGGLE, &a->flags);
  958. esas2r_write_register_dword(a, MU_IN_LIST_WRITE, MU_ILW_TOGGLE |
  959. a->last_write);
  960. esas2r_write_register_dword(a, MU_OUT_LIST_COPY, MU_OLC_TOGGLE |
  961. a->last_write);
  962. esas2r_write_register_dword(a, MU_IN_LIST_READ, MU_ILR_TOGGLE |
  963. a->last_write);
  964. esas2r_write_register_dword(a, MU_OUT_LIST_WRITE,
  965. MU_OLW_TOGGLE | a->last_write);
  966. /* configure the interface select fields */
  967. dw = esas2r_read_register_dword(a, MU_IN_LIST_IFC_CONFIG);
  968. dw &= ~(MU_ILIC_LIST | MU_ILIC_DEST);
  969. esas2r_write_register_dword(a, MU_IN_LIST_IFC_CONFIG,
  970. (dw | MU_ILIC_LIST_F0 | MU_ILIC_DEST_DDR));
  971. dw = esas2r_read_register_dword(a, MU_OUT_LIST_IFC_CONFIG);
  972. dw &= ~(MU_OLIC_LIST | MU_OLIC_SOURCE);
  973. esas2r_write_register_dword(a, MU_OUT_LIST_IFC_CONFIG,
  974. (dw | MU_OLIC_LIST_F0 |
  975. MU_OLIC_SOURCE_DDR));
  976. /* finish configuring the communication lists */
  977. dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
  978. dw &= ~(MU_ILC_ENTRY_MASK | MU_ILC_NUMBER_MASK);
  979. dw |= MU_ILC_ENTRY_4_DW | MU_ILC_DYNAMIC_SRC
  980. | (a->list_size << MU_ILC_NUMBER_SHIFT);
  981. esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
  982. dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
  983. dw &= ~(MU_OLC_ENTRY_MASK | MU_OLC_NUMBER_MASK);
  984. dw |= MU_OLC_ENTRY_4_DW | (a->list_size << MU_OLC_NUMBER_SHIFT);
  985. esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
  986. /*
  987. * notify the firmware that we're done setting up the communication
  988. * list registers. wait here until the firmware is done configuring
  989. * its lists. it will signal that it is done by enabling the lists.
  990. */
  991. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_INIT);
  992. starttime = jiffies_to_msecs(jiffies);
  993. while (true) {
  994. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  995. if (doorbell & DRBL_MSG_IFC_INIT) {
  996. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  997. doorbell);
  998. break;
  999. }
  1000. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1001. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  1002. esas2r_hdebug(
  1003. "timeout waiting for communication list init");
  1004. esas2r_bugon();
  1005. return esas2r_set_degraded_mode(a,
  1006. "timeout waiting for communication list init");
  1007. }
  1008. }
  1009. /*
  1010. * flag whether the firmware supports the power down doorbell. we
  1011. * determine this by reading the inbound doorbell enable mask.
  1012. */
  1013. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_IN_ENB);
  1014. if (doorbell & DRBL_POWER_DOWN)
  1015. set_bit(AF2_VDA_POWER_DOWN, &a->flags2);
  1016. else
  1017. clear_bit(AF2_VDA_POWER_DOWN, &a->flags2);
  1018. /*
  1019. * enable assertion of outbound queue and doorbell interrupts in the
  1020. * main interrupt cause register.
  1021. */
  1022. esas2r_write_register_dword(a, MU_OUT_LIST_INT_MASK, MU_OLIS_MASK);
  1023. esas2r_write_register_dword(a, MU_DOORBELL_OUT_ENB, DRBL_ENB_MASK);
  1024. return true;
  1025. }
  1026. /* Process the initialization message just completed and format the next one. */
  1027. static bool esas2r_format_init_msg(struct esas2r_adapter *a,
  1028. struct esas2r_request *rq)
  1029. {
  1030. u32 msg = a->init_msg;
  1031. struct atto_vda_cfg_init *ci;
  1032. a->init_msg = 0;
  1033. switch (msg) {
  1034. case ESAS2R_INIT_MSG_START:
  1035. case ESAS2R_INIT_MSG_REINIT:
  1036. {
  1037. struct timeval now;
  1038. do_gettimeofday(&now);
  1039. esas2r_hdebug("CFG init");
  1040. esas2r_build_cfg_req(a,
  1041. rq,
  1042. VDA_CFG_INIT,
  1043. 0,
  1044. NULL);
  1045. ci = (struct atto_vda_cfg_init *)&rq->vrq->cfg.data.init;
  1046. ci->sgl_page_size = cpu_to_le32(sgl_page_size);
  1047. ci->epoch_time = cpu_to_le32(now.tv_sec);
  1048. rq->flags |= RF_FAILURE_OK;
  1049. a->init_msg = ESAS2R_INIT_MSG_INIT;
  1050. break;
  1051. }
  1052. case ESAS2R_INIT_MSG_INIT:
  1053. if (rq->req_stat == RS_SUCCESS) {
  1054. u32 major;
  1055. u32 minor;
  1056. u16 fw_release;
  1057. a->fw_version = le16_to_cpu(
  1058. rq->func_rsp.cfg_rsp.vda_version);
  1059. a->fw_build = rq->func_rsp.cfg_rsp.fw_build;
  1060. fw_release = le16_to_cpu(
  1061. rq->func_rsp.cfg_rsp.fw_release);
  1062. major = LOBYTE(fw_release);
  1063. minor = HIBYTE(fw_release);
  1064. a->fw_version += (major << 16) + (minor << 24);
  1065. } else {
  1066. esas2r_hdebug("FAILED");
  1067. }
  1068. /*
  1069. * the 2.71 and earlier releases of R6xx firmware did not error
  1070. * unsupported config requests correctly.
  1071. */
  1072. if ((test_bit(AF2_THUNDERBOLT, &a->flags2))
  1073. || (be32_to_cpu(a->fw_version) > 0x00524702)) {
  1074. esas2r_hdebug("CFG get init");
  1075. esas2r_build_cfg_req(a,
  1076. rq,
  1077. VDA_CFG_GET_INIT2,
  1078. sizeof(struct atto_vda_cfg_init),
  1079. NULL);
  1080. rq->vrq->cfg.sg_list_offset = offsetof(
  1081. struct atto_vda_cfg_req,
  1082. data.sge);
  1083. rq->vrq->cfg.data.prde.ctl_len =
  1084. cpu_to_le32(sizeof(struct atto_vda_cfg_init));
  1085. rq->vrq->cfg.data.prde.address = cpu_to_le64(
  1086. rq->vrq_md->phys_addr +
  1087. sizeof(union atto_vda_req));
  1088. rq->flags |= RF_FAILURE_OK;
  1089. a->init_msg = ESAS2R_INIT_MSG_GET_INIT;
  1090. break;
  1091. }
  1092. case ESAS2R_INIT_MSG_GET_INIT:
  1093. if (msg == ESAS2R_INIT_MSG_GET_INIT) {
  1094. ci = (struct atto_vda_cfg_init *)rq->data_buf;
  1095. if (rq->req_stat == RS_SUCCESS) {
  1096. a->num_targets_backend =
  1097. le32_to_cpu(ci->num_targets_backend);
  1098. a->ioctl_tunnel =
  1099. le32_to_cpu(ci->ioctl_tunnel);
  1100. } else {
  1101. esas2r_hdebug("FAILED");
  1102. }
  1103. }
  1104. /* fall through */
  1105. default:
  1106. rq->req_stat = RS_SUCCESS;
  1107. return false;
  1108. }
  1109. return true;
  1110. }
  1111. /*
  1112. * Perform initialization messages via the request queue. Messages are
  1113. * performed with interrupts disabled.
  1114. */
  1115. bool esas2r_init_msgs(struct esas2r_adapter *a)
  1116. {
  1117. bool success = true;
  1118. struct esas2r_request *rq = &a->general_req;
  1119. esas2r_rq_init_request(rq, a);
  1120. rq->comp_cb = esas2r_dummy_complete;
  1121. if (a->init_msg == 0)
  1122. a->init_msg = ESAS2R_INIT_MSG_REINIT;
  1123. while (a->init_msg) {
  1124. if (esas2r_format_init_msg(a, rq)) {
  1125. unsigned long flags;
  1126. while (true) {
  1127. spin_lock_irqsave(&a->queue_lock, flags);
  1128. esas2r_start_vda_request(a, rq);
  1129. spin_unlock_irqrestore(&a->queue_lock, flags);
  1130. esas2r_wait_request(a, rq);
  1131. if (rq->req_stat != RS_PENDING)
  1132. break;
  1133. }
  1134. }
  1135. if (rq->req_stat == RS_SUCCESS
  1136. || ((rq->flags & RF_FAILURE_OK)
  1137. && rq->req_stat != RS_TIMEOUT))
  1138. continue;
  1139. esas2r_log(ESAS2R_LOG_CRIT, "init message %x failed (%x, %x)",
  1140. a->init_msg, rq->req_stat, rq->flags);
  1141. a->init_msg = ESAS2R_INIT_MSG_START;
  1142. success = false;
  1143. break;
  1144. }
  1145. esas2r_rq_destroy_request(rq, a);
  1146. return success;
  1147. }
  1148. /* Initialize the adapter chip */
  1149. bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll)
  1150. {
  1151. bool rslt = false;
  1152. struct esas2r_request *rq;
  1153. u32 i;
  1154. if (test_bit(AF_DEGRADED_MODE, &a->flags))
  1155. goto exit;
  1156. if (!test_bit(AF_NVR_VALID, &a->flags)) {
  1157. if (!esas2r_nvram_read_direct(a))
  1158. esas2r_log(ESAS2R_LOG_WARN,
  1159. "invalid/missing NVRAM parameters");
  1160. }
  1161. if (!esas2r_init_msgs(a)) {
  1162. esas2r_set_degraded_mode(a, "init messages failed");
  1163. goto exit;
  1164. }
  1165. /* The firmware is ready. */
  1166. clear_bit(AF_DEGRADED_MODE, &a->flags);
  1167. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1168. /* Post all the async event requests */
  1169. for (i = 0, rq = a->first_ae_req; i < num_ae_requests; i++, rq++)
  1170. esas2r_start_ae_request(a, rq);
  1171. if (!a->flash_rev[0])
  1172. esas2r_read_flash_rev(a);
  1173. if (!a->image_type[0])
  1174. esas2r_read_image_type(a);
  1175. if (a->fw_version == 0)
  1176. a->fw_rev[0] = 0;
  1177. else
  1178. sprintf(a->fw_rev, "%1d.%02d",
  1179. (int)LOBYTE(HIWORD(a->fw_version)),
  1180. (int)HIBYTE(HIWORD(a->fw_version)));
  1181. esas2r_hdebug("firmware revision: %s", a->fw_rev);
  1182. if (test_bit(AF_CHPRST_DETECTED, &a->flags)
  1183. && (test_bit(AF_FIRST_INIT, &a->flags))) {
  1184. esas2r_enable_chip_interrupts(a);
  1185. return true;
  1186. }
  1187. /* initialize discovery */
  1188. esas2r_disc_initialize(a);
  1189. /*
  1190. * wait for the device wait time to expire here if requested. this is
  1191. * usually requested during initial driver load and possibly when
  1192. * resuming from a low power state. deferred device waiting will use
  1193. * interrupts. chip reset recovery always defers device waiting to
  1194. * avoid being in a TASKLET too long.
  1195. */
  1196. if (init_poll) {
  1197. u32 currtime = a->disc_start_time;
  1198. u32 nexttick = 100;
  1199. u32 deltatime;
  1200. /*
  1201. * Block Tasklets from getting scheduled and indicate this is
  1202. * polled discovery.
  1203. */
  1204. set_bit(AF_TASKLET_SCHEDULED, &a->flags);
  1205. set_bit(AF_DISC_POLLED, &a->flags);
  1206. /*
  1207. * Temporarily bring the disable count to zero to enable
  1208. * deferred processing. Note that the count is already zero
  1209. * after the first initialization.
  1210. */
  1211. if (test_bit(AF_FIRST_INIT, &a->flags))
  1212. atomic_dec(&a->disable_cnt);
  1213. while (test_bit(AF_DISC_PENDING, &a->flags)) {
  1214. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1215. /*
  1216. * Determine the need for a timer tick based on the
  1217. * delta time between this and the last iteration of
  1218. * this loop. We don't use the absolute time because
  1219. * then we would have to worry about when nexttick
  1220. * wraps and currtime hasn't yet.
  1221. */
  1222. deltatime = jiffies_to_msecs(jiffies) - currtime;
  1223. currtime += deltatime;
  1224. /*
  1225. * Process any waiting discovery as long as the chip is
  1226. * up. If a chip reset happens during initial polling,
  1227. * we have to make sure the timer tick processes the
  1228. * doorbell indicating the firmware is ready.
  1229. */
  1230. if (!test_bit(AF_CHPRST_PENDING, &a->flags))
  1231. esas2r_disc_check_for_work(a);
  1232. /* Simulate a timer tick. */
  1233. if (nexttick <= deltatime) {
  1234. /* Time for a timer tick */
  1235. nexttick += 100;
  1236. esas2r_timer_tick(a);
  1237. }
  1238. if (nexttick > deltatime)
  1239. nexttick -= deltatime;
  1240. /* Do any deferred processing */
  1241. if (esas2r_is_tasklet_pending(a))
  1242. esas2r_do_tasklet_tasks(a);
  1243. }
  1244. if (test_bit(AF_FIRST_INIT, &a->flags))
  1245. atomic_inc(&a->disable_cnt);
  1246. clear_bit(AF_DISC_POLLED, &a->flags);
  1247. clear_bit(AF_TASKLET_SCHEDULED, &a->flags);
  1248. }
  1249. esas2r_targ_db_report_changes(a);
  1250. /*
  1251. * For cases where (a) the initialization messages processing may
  1252. * handle an interrupt for a port event and a discovery is waiting, but
  1253. * we are not waiting for devices, or (b) the device wait time has been
  1254. * exhausted but there is still discovery pending, start any leftover
  1255. * discovery in interrupt driven mode.
  1256. */
  1257. esas2r_disc_start_waiting(a);
  1258. /* Enable chip interrupts */
  1259. a->int_mask = ESAS2R_INT_STS_MASK;
  1260. esas2r_enable_chip_interrupts(a);
  1261. esas2r_enable_heartbeat(a);
  1262. rslt = true;
  1263. exit:
  1264. /*
  1265. * Regardless of whether initialization was successful, certain things
  1266. * need to get done before we exit.
  1267. */
  1268. if (test_bit(AF_CHPRST_DETECTED, &a->flags) &&
  1269. test_bit(AF_FIRST_INIT, &a->flags)) {
  1270. /*
  1271. * Reinitialization was performed during the first
  1272. * initialization. Only clear the chip reset flag so the
  1273. * original device polling is not cancelled.
  1274. */
  1275. if (!rslt)
  1276. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1277. } else {
  1278. /* First initialization or a subsequent re-init is complete. */
  1279. if (!rslt) {
  1280. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1281. clear_bit(AF_DISC_PENDING, &a->flags);
  1282. }
  1283. /* Enable deferred processing after the first initialization. */
  1284. if (test_bit(AF_FIRST_INIT, &a->flags)) {
  1285. clear_bit(AF_FIRST_INIT, &a->flags);
  1286. if (atomic_dec_return(&a->disable_cnt) == 0)
  1287. esas2r_do_deferred_processes(a);
  1288. }
  1289. }
  1290. return rslt;
  1291. }
  1292. void esas2r_reset_adapter(struct esas2r_adapter *a)
  1293. {
  1294. set_bit(AF_OS_RESET, &a->flags);
  1295. esas2r_local_reset_adapter(a);
  1296. esas2r_schedule_tasklet(a);
  1297. }
  1298. void esas2r_reset_chip(struct esas2r_adapter *a)
  1299. {
  1300. if (!esas2r_is_adapter_present(a))
  1301. return;
  1302. /*
  1303. * Before we reset the chip, save off the VDA core dump. The VDA core
  1304. * dump is located in the upper 512KB of the onchip SRAM. Make sure
  1305. * to not overwrite a previous crash that was saved.
  1306. */
  1307. if (test_bit(AF2_COREDUMP_AVAIL, &a->flags2) &&
  1308. !test_bit(AF2_COREDUMP_SAVED, &a->flags2)) {
  1309. esas2r_read_mem_block(a,
  1310. a->fw_coredump_buff,
  1311. MW_DATA_ADDR_SRAM + 0x80000,
  1312. ESAS2R_FWCOREDUMP_SZ);
  1313. set_bit(AF2_COREDUMP_SAVED, &a->flags2);
  1314. }
  1315. clear_bit(AF2_COREDUMP_AVAIL, &a->flags2);
  1316. /* Reset the chip */
  1317. if (a->pcid->revision == MVR_FREY_B2)
  1318. esas2r_write_register_dword(a, MU_CTL_STATUS_IN_B2,
  1319. MU_CTL_IN_FULL_RST2);
  1320. else
  1321. esas2r_write_register_dword(a, MU_CTL_STATUS_IN,
  1322. MU_CTL_IN_FULL_RST);
  1323. /* Stall a little while to let the reset condition clear */
  1324. mdelay(10);
  1325. }
  1326. static void esas2r_power_down_notify_firmware(struct esas2r_adapter *a)
  1327. {
  1328. u32 starttime;
  1329. u32 doorbell;
  1330. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_POWER_DOWN);
  1331. starttime = jiffies_to_msecs(jiffies);
  1332. while (true) {
  1333. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  1334. if (doorbell & DRBL_POWER_DOWN) {
  1335. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  1336. doorbell);
  1337. break;
  1338. }
  1339. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1340. if ((jiffies_to_msecs(jiffies) - starttime) > 30000) {
  1341. esas2r_hdebug("Timeout waiting for power down");
  1342. break;
  1343. }
  1344. }
  1345. }
  1346. /*
  1347. * Perform power management processing including managing device states, adapter
  1348. * states, interrupts, and I/O.
  1349. */
  1350. void esas2r_power_down(struct esas2r_adapter *a)
  1351. {
  1352. set_bit(AF_POWER_MGT, &a->flags);
  1353. set_bit(AF_POWER_DOWN, &a->flags);
  1354. if (!test_bit(AF_DEGRADED_MODE, &a->flags)) {
  1355. u32 starttime;
  1356. u32 doorbell;
  1357. /*
  1358. * We are currently running OK and will be reinitializing later.
  1359. * increment the disable count to coordinate with
  1360. * esas2r_init_adapter. We don't have to do this in degraded
  1361. * mode since we never enabled interrupts in the first place.
  1362. */
  1363. esas2r_disable_chip_interrupts(a);
  1364. esas2r_disable_heartbeat(a);
  1365. /* wait for any VDA activity to clear before continuing */
  1366. esas2r_write_register_dword(a, MU_DOORBELL_IN,
  1367. DRBL_MSG_IFC_DOWN);
  1368. starttime = jiffies_to_msecs(jiffies);
  1369. while (true) {
  1370. doorbell =
  1371. esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  1372. if (doorbell & DRBL_MSG_IFC_DOWN) {
  1373. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  1374. doorbell);
  1375. break;
  1376. }
  1377. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1378. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  1379. esas2r_hdebug(
  1380. "timeout waiting for interface down");
  1381. break;
  1382. }
  1383. }
  1384. /*
  1385. * For versions of firmware that support it tell them the driver
  1386. * is powering down.
  1387. */
  1388. if (test_bit(AF2_VDA_POWER_DOWN, &a->flags2))
  1389. esas2r_power_down_notify_firmware(a);
  1390. }
  1391. /* Suspend I/O processing. */
  1392. set_bit(AF_OS_RESET, &a->flags);
  1393. set_bit(AF_DISC_PENDING, &a->flags);
  1394. set_bit(AF_CHPRST_PENDING, &a->flags);
  1395. esas2r_process_adapter_reset(a);
  1396. /* Remove devices now that I/O is cleaned up. */
  1397. a->prev_dev_cnt = esas2r_targ_db_get_tgt_cnt(a);
  1398. esas2r_targ_db_remove_all(a, false);
  1399. }
  1400. /*
  1401. * Perform power management processing including managing device states, adapter
  1402. * states, interrupts, and I/O.
  1403. */
  1404. bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll)
  1405. {
  1406. bool ret;
  1407. clear_bit(AF_POWER_DOWN, &a->flags);
  1408. esas2r_init_pci_cfg_space(a);
  1409. set_bit(AF_FIRST_INIT, &a->flags);
  1410. atomic_inc(&a->disable_cnt);
  1411. /* reinitialize the adapter */
  1412. ret = esas2r_check_adapter(a);
  1413. if (!esas2r_init_adapter_hw(a, init_poll))
  1414. ret = false;
  1415. /* send the reset asynchronous event */
  1416. esas2r_send_reset_ae(a, true);
  1417. /* clear this flag after initialization. */
  1418. clear_bit(AF_POWER_MGT, &a->flags);
  1419. return ret;
  1420. }
  1421. bool esas2r_is_adapter_present(struct esas2r_adapter *a)
  1422. {
  1423. if (test_bit(AF_NOT_PRESENT, &a->flags))
  1424. return false;
  1425. if (esas2r_read_register_dword(a, MU_DOORBELL_OUT) == 0xFFFFFFFF) {
  1426. set_bit(AF_NOT_PRESENT, &a->flags);
  1427. return false;
  1428. }
  1429. return true;
  1430. }
  1431. const char *esas2r_get_model_name(struct esas2r_adapter *a)
  1432. {
  1433. switch (a->pcid->subsystem_device) {
  1434. case ATTO_ESAS_R680:
  1435. return "ATTO ExpressSAS R680";
  1436. case ATTO_ESAS_R608:
  1437. return "ATTO ExpressSAS R608";
  1438. case ATTO_ESAS_R60F:
  1439. return "ATTO ExpressSAS R60F";
  1440. case ATTO_ESAS_R6F0:
  1441. return "ATTO ExpressSAS R6F0";
  1442. case ATTO_ESAS_R644:
  1443. return "ATTO ExpressSAS R644";
  1444. case ATTO_ESAS_R648:
  1445. return "ATTO ExpressSAS R648";
  1446. case ATTO_TSSC_3808:
  1447. return "ATTO ThunderStream SC 3808D";
  1448. case ATTO_TSSC_3808E:
  1449. return "ATTO ThunderStream SC 3808E";
  1450. case ATTO_TLSH_1068:
  1451. return "ATTO ThunderLink SH 1068";
  1452. }
  1453. return "ATTO SAS Controller";
  1454. }
  1455. const char *esas2r_get_model_name_short(struct esas2r_adapter *a)
  1456. {
  1457. switch (a->pcid->subsystem_device) {
  1458. case ATTO_ESAS_R680:
  1459. return "R680";
  1460. case ATTO_ESAS_R608:
  1461. return "R608";
  1462. case ATTO_ESAS_R60F:
  1463. return "R60F";
  1464. case ATTO_ESAS_R6F0:
  1465. return "R6F0";
  1466. case ATTO_ESAS_R644:
  1467. return "R644";
  1468. case ATTO_ESAS_R648:
  1469. return "R648";
  1470. case ATTO_TSSC_3808:
  1471. return "SC 3808D";
  1472. case ATTO_TSSC_3808E:
  1473. return "SC 3808E";
  1474. case ATTO_TLSH_1068:
  1475. return "SH 1068";
  1476. }
  1477. return "unknown";
  1478. }