cpu-probe.c 17 KB

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  1. /*
  2. * Processor capabilities determination functions.
  3. *
  4. * Copyright (C) xxxx the Anonymous
  5. * Copyright (C) 1994 - 2006 Ralf Baechle
  6. * Copyright (C) 2003, 2004 Maciej W. Rozycki
  7. * Copyright (C) 2001, 2004 MIPS Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. #include <linux/config.h>
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ptrace.h>
  18. #include <linux/stddef.h>
  19. #include <asm/cpu.h>
  20. #include <asm/fpu.h>
  21. #include <asm/mipsregs.h>
  22. #include <asm/system.h>
  23. /*
  24. * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  25. * the implementation of the "wait" feature differs between CPU families. This
  26. * points to the function that implements CPU specific wait.
  27. * The wait instruction stops the pipeline and reduces the power consumption of
  28. * the CPU very much.
  29. */
  30. void (*cpu_wait)(void) = NULL;
  31. static void r3081_wait(void)
  32. {
  33. unsigned long cfg = read_c0_conf();
  34. write_c0_conf(cfg | R30XX_CONF_HALT);
  35. }
  36. static void r39xx_wait(void)
  37. {
  38. unsigned long cfg = read_c0_conf();
  39. write_c0_conf(cfg | TX39_CONF_HALT);
  40. }
  41. static void r4k_wait(void)
  42. {
  43. __asm__(".set\tmips3\n\t"
  44. "wait\n\t"
  45. ".set\tmips0");
  46. }
  47. /* The Au1xxx wait is available only if using 32khz counter or
  48. * external timer source, but specifically not CP0 Counter. */
  49. int allow_au1k_wait;
  50. static void au1k_wait(void)
  51. {
  52. /* using the wait instruction makes CP0 counter unusable */
  53. __asm__(".set mips3\n\t"
  54. "cache 0x14, 0(%0)\n\t"
  55. "cache 0x14, 32(%0)\n\t"
  56. "sync\n\t"
  57. "nop\n\t"
  58. "wait\n\t"
  59. "nop\n\t"
  60. "nop\n\t"
  61. "nop\n\t"
  62. "nop\n\t"
  63. ".set mips0\n\t"
  64. : : "r" (au1k_wait));
  65. }
  66. static int __initdata nowait = 0;
  67. int __init wait_disable(char *s)
  68. {
  69. nowait = 1;
  70. return 1;
  71. }
  72. __setup("nowait", wait_disable);
  73. static inline void check_wait(void)
  74. {
  75. struct cpuinfo_mips *c = &current_cpu_data;
  76. printk("Checking for 'wait' instruction... ");
  77. if (nowait) {
  78. printk (" disabled.\n");
  79. return;
  80. }
  81. switch (c->cputype) {
  82. case CPU_R3081:
  83. case CPU_R3081E:
  84. cpu_wait = r3081_wait;
  85. printk(" available.\n");
  86. break;
  87. case CPU_TX3927:
  88. cpu_wait = r39xx_wait;
  89. printk(" available.\n");
  90. break;
  91. case CPU_R4200:
  92. /* case CPU_R4300: */
  93. case CPU_R4600:
  94. case CPU_R4640:
  95. case CPU_R4650:
  96. case CPU_R4700:
  97. case CPU_R5000:
  98. case CPU_NEVADA:
  99. case CPU_RM7000:
  100. case CPU_RM9000:
  101. case CPU_TX49XX:
  102. case CPU_4KC:
  103. case CPU_4KEC:
  104. case CPU_4KSC:
  105. case CPU_5KC:
  106. /* case CPU_20KC:*/
  107. case CPU_24K:
  108. case CPU_25KF:
  109. case CPU_34K:
  110. case CPU_74K:
  111. case CPU_PR4450:
  112. cpu_wait = r4k_wait;
  113. printk(" available.\n");
  114. break;
  115. case CPU_AU1000:
  116. case CPU_AU1100:
  117. case CPU_AU1500:
  118. case CPU_AU1550:
  119. case CPU_AU1200:
  120. if (allow_au1k_wait) {
  121. cpu_wait = au1k_wait;
  122. printk(" available.\n");
  123. } else
  124. printk(" unavailable.\n");
  125. break;
  126. default:
  127. printk(" unavailable.\n");
  128. break;
  129. }
  130. }
  131. void __init check_bugs32(void)
  132. {
  133. check_wait();
  134. }
  135. /*
  136. * Probe whether cpu has config register by trying to play with
  137. * alternate cache bit and see whether it matters.
  138. * It's used by cpu_probe to distinguish between R3000A and R3081.
  139. */
  140. static inline int cpu_has_confreg(void)
  141. {
  142. #ifdef CONFIG_CPU_R3000
  143. extern unsigned long r3k_cache_size(unsigned long);
  144. unsigned long size1, size2;
  145. unsigned long cfg = read_c0_conf();
  146. size1 = r3k_cache_size(ST0_ISC);
  147. write_c0_conf(cfg ^ R30XX_CONF_AC);
  148. size2 = r3k_cache_size(ST0_ISC);
  149. write_c0_conf(cfg);
  150. return size1 != size2;
  151. #else
  152. return 0;
  153. #endif
  154. }
  155. /*
  156. * Get the FPU Implementation/Revision.
  157. */
  158. static inline unsigned long cpu_get_fpu_id(void)
  159. {
  160. unsigned long tmp, fpu_id;
  161. tmp = read_c0_status();
  162. __enable_fpu();
  163. fpu_id = read_32bit_cp1_register(CP1_REVISION);
  164. write_c0_status(tmp);
  165. return fpu_id;
  166. }
  167. /*
  168. * Check the CPU has an FPU the official way.
  169. */
  170. static inline int __cpu_has_fpu(void)
  171. {
  172. return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
  173. }
  174. #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
  175. | MIPS_CPU_COUNTER)
  176. static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
  177. {
  178. switch (c->processor_id & 0xff00) {
  179. case PRID_IMP_R2000:
  180. c->cputype = CPU_R2000;
  181. c->isa_level = MIPS_CPU_ISA_I;
  182. c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
  183. MIPS_CPU_NOFPUEX;
  184. if (__cpu_has_fpu())
  185. c->options |= MIPS_CPU_FPU;
  186. c->tlbsize = 64;
  187. break;
  188. case PRID_IMP_R3000:
  189. if ((c->processor_id & 0xff) == PRID_REV_R3000A)
  190. if (cpu_has_confreg())
  191. c->cputype = CPU_R3081E;
  192. else
  193. c->cputype = CPU_R3000A;
  194. else
  195. c->cputype = CPU_R3000;
  196. c->isa_level = MIPS_CPU_ISA_I;
  197. c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
  198. MIPS_CPU_NOFPUEX;
  199. if (__cpu_has_fpu())
  200. c->options |= MIPS_CPU_FPU;
  201. c->tlbsize = 64;
  202. break;
  203. case PRID_IMP_R4000:
  204. if (read_c0_config() & CONF_SC) {
  205. if ((c->processor_id & 0xff) >= PRID_REV_R4400)
  206. c->cputype = CPU_R4400PC;
  207. else
  208. c->cputype = CPU_R4000PC;
  209. } else {
  210. if ((c->processor_id & 0xff) >= PRID_REV_R4400)
  211. c->cputype = CPU_R4400SC;
  212. else
  213. c->cputype = CPU_R4000SC;
  214. }
  215. c->isa_level = MIPS_CPU_ISA_III;
  216. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  217. MIPS_CPU_WATCH | MIPS_CPU_VCE |
  218. MIPS_CPU_LLSC;
  219. c->tlbsize = 48;
  220. break;
  221. case PRID_IMP_VR41XX:
  222. switch (c->processor_id & 0xf0) {
  223. case PRID_REV_VR4111:
  224. c->cputype = CPU_VR4111;
  225. break;
  226. case PRID_REV_VR4121:
  227. c->cputype = CPU_VR4121;
  228. break;
  229. case PRID_REV_VR4122:
  230. if ((c->processor_id & 0xf) < 0x3)
  231. c->cputype = CPU_VR4122;
  232. else
  233. c->cputype = CPU_VR4181A;
  234. break;
  235. case PRID_REV_VR4130:
  236. if ((c->processor_id & 0xf) < 0x4)
  237. c->cputype = CPU_VR4131;
  238. else
  239. c->cputype = CPU_VR4133;
  240. break;
  241. default:
  242. printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
  243. c->cputype = CPU_VR41XX;
  244. break;
  245. }
  246. c->isa_level = MIPS_CPU_ISA_III;
  247. c->options = R4K_OPTS;
  248. c->tlbsize = 32;
  249. break;
  250. case PRID_IMP_R4300:
  251. c->cputype = CPU_R4300;
  252. c->isa_level = MIPS_CPU_ISA_III;
  253. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  254. MIPS_CPU_LLSC;
  255. c->tlbsize = 32;
  256. break;
  257. case PRID_IMP_R4600:
  258. c->cputype = CPU_R4600;
  259. c->isa_level = MIPS_CPU_ISA_III;
  260. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  261. MIPS_CPU_LLSC;
  262. c->tlbsize = 48;
  263. break;
  264. #if 0
  265. case PRID_IMP_R4650:
  266. /*
  267. * This processor doesn't have an MMU, so it's not
  268. * "real easy" to run Linux on it. It is left purely
  269. * for documentation. Commented out because it shares
  270. * it's c0_prid id number with the TX3900.
  271. */
  272. c->cputype = CPU_R4650;
  273. c->isa_level = MIPS_CPU_ISA_III;
  274. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
  275. c->tlbsize = 48;
  276. break;
  277. #endif
  278. case PRID_IMP_TX39:
  279. c->isa_level = MIPS_CPU_ISA_I;
  280. c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
  281. if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
  282. c->cputype = CPU_TX3927;
  283. c->tlbsize = 64;
  284. } else {
  285. switch (c->processor_id & 0xff) {
  286. case PRID_REV_TX3912:
  287. c->cputype = CPU_TX3912;
  288. c->tlbsize = 32;
  289. break;
  290. case PRID_REV_TX3922:
  291. c->cputype = CPU_TX3922;
  292. c->tlbsize = 64;
  293. break;
  294. default:
  295. c->cputype = CPU_UNKNOWN;
  296. break;
  297. }
  298. }
  299. break;
  300. case PRID_IMP_R4700:
  301. c->cputype = CPU_R4700;
  302. c->isa_level = MIPS_CPU_ISA_III;
  303. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  304. MIPS_CPU_LLSC;
  305. c->tlbsize = 48;
  306. break;
  307. case PRID_IMP_TX49:
  308. c->cputype = CPU_TX49XX;
  309. c->isa_level = MIPS_CPU_ISA_III;
  310. c->options = R4K_OPTS | MIPS_CPU_LLSC;
  311. if (!(c->processor_id & 0x08))
  312. c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
  313. c->tlbsize = 48;
  314. break;
  315. case PRID_IMP_R5000:
  316. c->cputype = CPU_R5000;
  317. c->isa_level = MIPS_CPU_ISA_IV;
  318. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  319. MIPS_CPU_LLSC;
  320. c->tlbsize = 48;
  321. break;
  322. case PRID_IMP_R5432:
  323. c->cputype = CPU_R5432;
  324. c->isa_level = MIPS_CPU_ISA_IV;
  325. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  326. MIPS_CPU_WATCH | MIPS_CPU_LLSC;
  327. c->tlbsize = 48;
  328. break;
  329. case PRID_IMP_R5500:
  330. c->cputype = CPU_R5500;
  331. c->isa_level = MIPS_CPU_ISA_IV;
  332. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  333. MIPS_CPU_WATCH | MIPS_CPU_LLSC;
  334. c->tlbsize = 48;
  335. break;
  336. case PRID_IMP_NEVADA:
  337. c->cputype = CPU_NEVADA;
  338. c->isa_level = MIPS_CPU_ISA_IV;
  339. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  340. MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
  341. c->tlbsize = 48;
  342. break;
  343. case PRID_IMP_R6000:
  344. c->cputype = CPU_R6000;
  345. c->isa_level = MIPS_CPU_ISA_II;
  346. c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
  347. MIPS_CPU_LLSC;
  348. c->tlbsize = 32;
  349. break;
  350. case PRID_IMP_R6000A:
  351. c->cputype = CPU_R6000A;
  352. c->isa_level = MIPS_CPU_ISA_II;
  353. c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
  354. MIPS_CPU_LLSC;
  355. c->tlbsize = 32;
  356. break;
  357. case PRID_IMP_RM7000:
  358. c->cputype = CPU_RM7000;
  359. c->isa_level = MIPS_CPU_ISA_IV;
  360. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  361. MIPS_CPU_LLSC;
  362. /*
  363. * Undocumented RM7000: Bit 29 in the info register of
  364. * the RM7000 v2.0 indicates if the TLB has 48 or 64
  365. * entries.
  366. *
  367. * 29 1 => 64 entry JTLB
  368. * 0 => 48 entry JTLB
  369. */
  370. c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
  371. break;
  372. case PRID_IMP_RM9000:
  373. c->cputype = CPU_RM9000;
  374. c->isa_level = MIPS_CPU_ISA_IV;
  375. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  376. MIPS_CPU_LLSC;
  377. /*
  378. * Bit 29 in the info register of the RM9000
  379. * indicates if the TLB has 48 or 64 entries.
  380. *
  381. * 29 1 => 64 entry JTLB
  382. * 0 => 48 entry JTLB
  383. */
  384. c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
  385. break;
  386. case PRID_IMP_R8000:
  387. c->cputype = CPU_R8000;
  388. c->isa_level = MIPS_CPU_ISA_IV;
  389. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  390. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  391. MIPS_CPU_LLSC;
  392. c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
  393. break;
  394. case PRID_IMP_R10000:
  395. c->cputype = CPU_R10000;
  396. c->isa_level = MIPS_CPU_ISA_IV;
  397. c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
  398. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  399. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  400. MIPS_CPU_LLSC;
  401. c->tlbsize = 64;
  402. break;
  403. case PRID_IMP_R12000:
  404. c->cputype = CPU_R12000;
  405. c->isa_level = MIPS_CPU_ISA_IV;
  406. c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
  407. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  408. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  409. MIPS_CPU_LLSC;
  410. c->tlbsize = 64;
  411. break;
  412. case PRID_IMP_R14000:
  413. c->cputype = CPU_R14000;
  414. c->isa_level = MIPS_CPU_ISA_IV;
  415. c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
  416. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  417. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  418. MIPS_CPU_LLSC;
  419. c->tlbsize = 64;
  420. break;
  421. }
  422. }
  423. static char unknown_isa[] __initdata = KERN_ERR \
  424. "Unsupported ISA type, c0.config0: %d.";
  425. static inline unsigned int decode_config0(struct cpuinfo_mips *c)
  426. {
  427. unsigned int config0;
  428. int isa;
  429. config0 = read_c0_config();
  430. if (((config0 & MIPS_CONF_MT) >> 7) == 1)
  431. c->options |= MIPS_CPU_TLB;
  432. isa = (config0 & MIPS_CONF_AT) >> 13;
  433. switch (isa) {
  434. case 0:
  435. switch ((config0 >> 10) & 7) {
  436. case 0:
  437. c->isa_level = MIPS_CPU_ISA_M32R1;
  438. break;
  439. case 1:
  440. c->isa_level = MIPS_CPU_ISA_M32R2;
  441. break;
  442. default:
  443. goto unknown;
  444. }
  445. break;
  446. case 2:
  447. switch ((config0 >> 10) & 7) {
  448. case 0:
  449. c->isa_level = MIPS_CPU_ISA_M64R1;
  450. break;
  451. case 1:
  452. c->isa_level = MIPS_CPU_ISA_M64R2;
  453. break;
  454. default:
  455. goto unknown;
  456. }
  457. break;
  458. default:
  459. goto unknown;
  460. }
  461. return config0 & MIPS_CONF_M;
  462. unknown:
  463. panic(unknown_isa, config0);
  464. }
  465. static inline unsigned int decode_config1(struct cpuinfo_mips *c)
  466. {
  467. unsigned int config1;
  468. config1 = read_c0_config1();
  469. if (config1 & MIPS_CONF1_MD)
  470. c->ases |= MIPS_ASE_MDMX;
  471. if (config1 & MIPS_CONF1_WR)
  472. c->options |= MIPS_CPU_WATCH;
  473. if (config1 & MIPS_CONF1_CA)
  474. c->ases |= MIPS_ASE_MIPS16;
  475. if (config1 & MIPS_CONF1_EP)
  476. c->options |= MIPS_CPU_EJTAG;
  477. if (config1 & MIPS_CONF1_FP) {
  478. c->options |= MIPS_CPU_FPU;
  479. c->options |= MIPS_CPU_32FPR;
  480. }
  481. if (cpu_has_tlb)
  482. c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
  483. return config1 & MIPS_CONF_M;
  484. }
  485. static inline unsigned int decode_config2(struct cpuinfo_mips *c)
  486. {
  487. unsigned int config2;
  488. config2 = read_c0_config2();
  489. if (config2 & MIPS_CONF2_SL)
  490. c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  491. return config2 & MIPS_CONF_M;
  492. }
  493. static inline unsigned int decode_config3(struct cpuinfo_mips *c)
  494. {
  495. unsigned int config3;
  496. config3 = read_c0_config3();
  497. if (config3 & MIPS_CONF3_SM)
  498. c->ases |= MIPS_ASE_SMARTMIPS;
  499. if (config3 & MIPS_CONF3_DSP)
  500. c->ases |= MIPS_ASE_DSP;
  501. if (config3 & MIPS_CONF3_VINT)
  502. c->options |= MIPS_CPU_VINT;
  503. if (config3 & MIPS_CONF3_VEIC)
  504. c->options |= MIPS_CPU_VEIC;
  505. if (config3 & MIPS_CONF3_MT)
  506. c->ases |= MIPS_ASE_MIPSMT;
  507. return config3 & MIPS_CONF_M;
  508. }
  509. static inline void decode_configs(struct cpuinfo_mips *c)
  510. {
  511. /* MIPS32 or MIPS64 compliant CPU. */
  512. c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
  513. MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
  514. c->scache.flags = MIPS_CACHE_NOT_PRESENT;
  515. /* Read Config registers. */
  516. if (!decode_config0(c))
  517. return; /* actually worth a panic() */
  518. if (!decode_config1(c))
  519. return;
  520. if (!decode_config2(c))
  521. return;
  522. if (!decode_config3(c))
  523. return;
  524. }
  525. static inline void cpu_probe_mips(struct cpuinfo_mips *c)
  526. {
  527. decode_configs(c);
  528. switch (c->processor_id & 0xff00) {
  529. case PRID_IMP_4KC:
  530. c->cputype = CPU_4KC;
  531. break;
  532. case PRID_IMP_4KEC:
  533. c->cputype = CPU_4KEC;
  534. break;
  535. case PRID_IMP_4KECR2:
  536. c->cputype = CPU_4KEC;
  537. break;
  538. case PRID_IMP_4KSC:
  539. case PRID_IMP_4KSD:
  540. c->cputype = CPU_4KSC;
  541. break;
  542. case PRID_IMP_5KC:
  543. c->cputype = CPU_5KC;
  544. break;
  545. case PRID_IMP_20KC:
  546. c->cputype = CPU_20KC;
  547. break;
  548. case PRID_IMP_24K:
  549. case PRID_IMP_24KE:
  550. c->cputype = CPU_24K;
  551. break;
  552. case PRID_IMP_25KF:
  553. c->cputype = CPU_25KF;
  554. /* Probe for L2 cache */
  555. c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  556. break;
  557. case PRID_IMP_34K:
  558. c->cputype = CPU_34K;
  559. break;
  560. case PRID_IMP_74K:
  561. c->cputype = CPU_74K;
  562. break;
  563. }
  564. }
  565. static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
  566. {
  567. decode_configs(c);
  568. switch (c->processor_id & 0xff00) {
  569. case PRID_IMP_AU1_REV1:
  570. case PRID_IMP_AU1_REV2:
  571. switch ((c->processor_id >> 24) & 0xff) {
  572. case 0:
  573. c->cputype = CPU_AU1000;
  574. break;
  575. case 1:
  576. c->cputype = CPU_AU1500;
  577. break;
  578. case 2:
  579. c->cputype = CPU_AU1100;
  580. break;
  581. case 3:
  582. c->cputype = CPU_AU1550;
  583. break;
  584. case 4:
  585. c->cputype = CPU_AU1200;
  586. break;
  587. default:
  588. panic("Unknown Au Core!");
  589. break;
  590. }
  591. break;
  592. }
  593. }
  594. static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
  595. {
  596. decode_configs(c);
  597. /*
  598. * For historical reasons the SB1 comes with it's own variant of
  599. * cache code which eventually will be folded into c-r4k.c. Until
  600. * then we pretend it's got it's own cache architecture.
  601. */
  602. c->options &= ~MIPS_CPU_4K_CACHE;
  603. c->options |= MIPS_CPU_SB1_CACHE;
  604. switch (c->processor_id & 0xff00) {
  605. case PRID_IMP_SB1:
  606. c->cputype = CPU_SB1;
  607. /* FPU in pass1 is known to have issues. */
  608. if ((c->processor_id & 0xff) < 0x02)
  609. c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
  610. break;
  611. case PRID_IMP_SB1A:
  612. c->cputype = CPU_SB1A;
  613. break;
  614. }
  615. }
  616. static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
  617. {
  618. decode_configs(c);
  619. switch (c->processor_id & 0xff00) {
  620. case PRID_IMP_SR71000:
  621. c->cputype = CPU_SR71000;
  622. c->scache.ways = 8;
  623. c->tlbsize = 64;
  624. break;
  625. }
  626. }
  627. static inline void cpu_probe_philips(struct cpuinfo_mips *c)
  628. {
  629. decode_configs(c);
  630. switch (c->processor_id & 0xff00) {
  631. case PRID_IMP_PR4450:
  632. c->cputype = CPU_PR4450;
  633. c->isa_level = MIPS_CPU_ISA_M32R1;
  634. break;
  635. default:
  636. panic("Unknown Philips Core!"); /* REVISIT: die? */
  637. break;
  638. }
  639. }
  640. __init void cpu_probe(void)
  641. {
  642. struct cpuinfo_mips *c = &current_cpu_data;
  643. c->processor_id = PRID_IMP_UNKNOWN;
  644. c->fpu_id = FPIR_IMP_NONE;
  645. c->cputype = CPU_UNKNOWN;
  646. c->processor_id = read_c0_prid();
  647. switch (c->processor_id & 0xff0000) {
  648. case PRID_COMP_LEGACY:
  649. cpu_probe_legacy(c);
  650. break;
  651. case PRID_COMP_MIPS:
  652. cpu_probe_mips(c);
  653. break;
  654. case PRID_COMP_ALCHEMY:
  655. cpu_probe_alchemy(c);
  656. break;
  657. case PRID_COMP_SIBYTE:
  658. cpu_probe_sibyte(c);
  659. break;
  660. case PRID_COMP_SANDCRAFT:
  661. cpu_probe_sandcraft(c);
  662. break;
  663. case PRID_COMP_PHILIPS:
  664. cpu_probe_philips(c);
  665. break;
  666. default:
  667. c->cputype = CPU_UNKNOWN;
  668. }
  669. if (c->options & MIPS_CPU_FPU) {
  670. c->fpu_id = cpu_get_fpu_id();
  671. if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
  672. c->isa_level == MIPS_CPU_ISA_M32R2 ||
  673. c->isa_level == MIPS_CPU_ISA_M64R1 ||
  674. c->isa_level == MIPS_CPU_ISA_M64R2) {
  675. if (c->fpu_id & MIPS_FPIR_3D)
  676. c->ases |= MIPS_ASE_MIPS3D;
  677. }
  678. }
  679. }
  680. __init void cpu_report(void)
  681. {
  682. struct cpuinfo_mips *c = &current_cpu_data;
  683. printk("CPU revision is: %08x\n", c->processor_id);
  684. if (c->options & MIPS_CPU_FPU)
  685. printk("FPU revision is: %08x\n", c->fpu_id);
  686. }