ipath_intr.c 28 KB

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  1. /*
  2. * Copyright (c) 2006 QLogic, Inc. All rights reserved.
  3. * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/pci.h>
  34. #include "ipath_kernel.h"
  35. #include "ipath_layer.h"
  36. #include "ipath_verbs.h"
  37. #include "ipath_common.h"
  38. /* These are all rcv-related errors which we want to count for stats */
  39. #define E_SUM_PKTERRS \
  40. (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
  41. INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
  42. INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
  43. INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  44. INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
  45. INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
  46. /* These are all send-related errors which we want to count for stats */
  47. #define E_SUM_ERRS \
  48. (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
  49. INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  50. INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
  51. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  52. INFINIPATH_E_INVALIDADDR)
  53. /*
  54. * these are errors that can occur when the link changes state while
  55. * a packet is being sent or received. This doesn't cover things
  56. * like EBP or VCRC that can be the result of a sending having the
  57. * link change state, so we receive a "known bad" packet.
  58. */
  59. #define E_SUM_LINK_PKTERRS \
  60. (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  61. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  62. INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  63. INFINIPATH_E_RUNEXPCHAR)
  64. static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
  65. {
  66. unsigned long sbuf[4];
  67. u64 ignore_this_time = 0;
  68. u32 piobcnt;
  69. /* if possible that sendbuffererror could be valid */
  70. piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
  71. /* read these before writing errorclear */
  72. sbuf[0] = ipath_read_kreg64(
  73. dd, dd->ipath_kregs->kr_sendbuffererror);
  74. sbuf[1] = ipath_read_kreg64(
  75. dd, dd->ipath_kregs->kr_sendbuffererror + 1);
  76. if (piobcnt > 128) {
  77. sbuf[2] = ipath_read_kreg64(
  78. dd, dd->ipath_kregs->kr_sendbuffererror + 2);
  79. sbuf[3] = ipath_read_kreg64(
  80. dd, dd->ipath_kregs->kr_sendbuffererror + 3);
  81. }
  82. if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
  83. int i;
  84. ipath_cdbg(PKT, "SendbufErrs %lx %lx ", sbuf[0], sbuf[1]);
  85. if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
  86. printk("%lx %lx ", sbuf[2], sbuf[3]);
  87. for (i = 0; i < piobcnt; i++) {
  88. if (test_bit(i, sbuf)) {
  89. u32 __iomem *piobuf;
  90. if (i < dd->ipath_piobcnt2k)
  91. piobuf = (u32 __iomem *)
  92. (dd->ipath_pio2kbase +
  93. i * dd->ipath_palign);
  94. else
  95. piobuf = (u32 __iomem *)
  96. (dd->ipath_pio4kbase +
  97. (i - dd->ipath_piobcnt2k) *
  98. dd->ipath_4kalign);
  99. ipath_cdbg(PKT,
  100. "PIObuf[%u] @%p pbc is %x; ",
  101. i, piobuf, readl(piobuf));
  102. ipath_disarm_piobufs(dd, i, 1);
  103. }
  104. }
  105. if (ipath_debug & __IPATH_PKTDBG)
  106. printk("\n");
  107. }
  108. if ((errs & E_SUM_LINK_PKTERRS) &&
  109. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  110. /*
  111. * This can happen when SMA is trying to bring the link
  112. * up, but the IB link changes state at the "wrong" time.
  113. * The IB logic then complains that the packet isn't
  114. * valid. We don't want to confuse people, so we just
  115. * don't print them, except at debug
  116. */
  117. ipath_dbg("Ignoring packet errors %llx, because link not "
  118. "ACTIVE\n", (unsigned long long) errs);
  119. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  120. }
  121. return ignore_this_time;
  122. }
  123. /* return the strings for the most common link states */
  124. static char *ib_linkstate(u32 linkstate)
  125. {
  126. char *ret;
  127. switch (linkstate) {
  128. case IPATH_IBSTATE_INIT:
  129. ret = "Init";
  130. break;
  131. case IPATH_IBSTATE_ARM:
  132. ret = "Arm";
  133. break;
  134. case IPATH_IBSTATE_ACTIVE:
  135. ret = "Active";
  136. break;
  137. default:
  138. ret = "Down";
  139. }
  140. return ret;
  141. }
  142. static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
  143. ipath_err_t errs, int noprint)
  144. {
  145. u64 val;
  146. u32 ltstate, lstate;
  147. /*
  148. * even if diags are enabled, we want to notice LINKINIT, etc.
  149. * We just don't want to change the LED state, or
  150. * dd->ipath_kregs->kr_ibcctrl
  151. */
  152. val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
  153. lstate = val & IPATH_IBSTATE_MASK;
  154. /*
  155. * this is confusing enough when it happens that I want to always put it
  156. * on the console and in the logs. If it was a requested state change,
  157. * we'll have already cleared the flags, so we won't print this warning
  158. */
  159. if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE)
  160. && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
  161. dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n",
  162. (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE",
  163. ib_linkstate(lstate));
  164. /*
  165. * Flush all queued sends when link went to DOWN or INIT,
  166. * to be sure that they don't block SMA and other MAD packets
  167. */
  168. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  169. INFINIPATH_S_ABORT);
  170. ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
  171. (unsigned)(dd->ipath_piobcnt2k +
  172. dd->ipath_piobcnt4k) -
  173. dd->ipath_lastport_piobuf);
  174. }
  175. else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
  176. lstate == IPATH_IBSTATE_ACTIVE) {
  177. /*
  178. * only print at SMA if there is a change, debug if not
  179. * (sometimes we want to know that, usually not).
  180. */
  181. if (lstate == ((unsigned) dd->ipath_lastibcstat
  182. & IPATH_IBSTATE_MASK)) {
  183. ipath_dbg("Status change intr but no change (%s)\n",
  184. ib_linkstate(lstate));
  185. }
  186. else
  187. ipath_cdbg(SMA, "Unit %u link state %s, last "
  188. "was %s\n", dd->ipath_unit,
  189. ib_linkstate(lstate),
  190. ib_linkstate((unsigned)
  191. dd->ipath_lastibcstat
  192. & IPATH_IBSTATE_MASK));
  193. }
  194. else {
  195. lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK;
  196. if (lstate == IPATH_IBSTATE_INIT ||
  197. lstate == IPATH_IBSTATE_ARM ||
  198. lstate == IPATH_IBSTATE_ACTIVE)
  199. ipath_cdbg(SMA, "Unit %u link state down"
  200. " (state 0x%x), from %s\n",
  201. dd->ipath_unit,
  202. (u32)val & IPATH_IBSTATE_MASK,
  203. ib_linkstate(lstate));
  204. else
  205. ipath_cdbg(VERBOSE, "Unit %u link state changed "
  206. "to 0x%x from down (%x)\n",
  207. dd->ipath_unit, (u32) val, lstate);
  208. }
  209. ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
  210. INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  211. lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  212. INFINIPATH_IBCS_LINKSTATE_MASK;
  213. if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
  214. ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  215. u32 last_ltstate;
  216. /*
  217. * Ignore cycling back and forth from Polling.Active
  218. * to Polling.Quiet while waiting for the other end of
  219. * the link to come up. We will cycle back and forth
  220. * between them if no cable is plugged in,
  221. * the other device is powered off or disabled, etc.
  222. */
  223. last_ltstate = (dd->ipath_lastibcstat >>
  224. INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)
  225. & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  226. if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE
  227. || last_ltstate ==
  228. INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  229. if (dd->ipath_ibpollcnt > 40) {
  230. dd->ipath_flags |= IPATH_NOCABLE;
  231. *dd->ipath_statusp |=
  232. IPATH_STATUS_IB_NOCABLE;
  233. } else
  234. dd->ipath_ibpollcnt++;
  235. goto skip_ibchange;
  236. }
  237. }
  238. dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */
  239. ipath_stats.sps_iblink++;
  240. if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
  241. dd->ipath_flags |= IPATH_LINKDOWN;
  242. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  243. | IPATH_LINKACTIVE |
  244. IPATH_LINKARMED);
  245. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  246. dd->ipath_lli_counter = 0;
  247. if (!noprint) {
  248. if (((dd->ipath_lastibcstat >>
  249. INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  250. INFINIPATH_IBCS_LINKSTATE_MASK)
  251. == INFINIPATH_IBCS_L_STATE_ACTIVE)
  252. /* if from up to down be more vocal */
  253. ipath_cdbg(SMA,
  254. "Unit %u link now down (%s)\n",
  255. dd->ipath_unit,
  256. ipath_ibcstatus_str[ltstate]);
  257. else
  258. ipath_cdbg(VERBOSE, "Unit %u link is "
  259. "down (%s)\n", dd->ipath_unit,
  260. ipath_ibcstatus_str[ltstate]);
  261. }
  262. dd->ipath_f_setextled(dd, lstate, ltstate);
  263. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) {
  264. dd->ipath_flags |= IPATH_LINKACTIVE;
  265. dd->ipath_flags &=
  266. ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN |
  267. IPATH_LINKARMED | IPATH_NOCABLE);
  268. *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
  269. *dd->ipath_statusp |=
  270. IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
  271. dd->ipath_f_setextled(dd, lstate, ltstate);
  272. __ipath_layer_intr(dd, IPATH_LAYER_INT_IF_UP);
  273. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) {
  274. /*
  275. * set INIT and DOWN. Down is checked by most of the other
  276. * code, but INIT is useful to know in a few places.
  277. */
  278. dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN;
  279. dd->ipath_flags &=
  280. ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED
  281. | IPATH_NOCABLE);
  282. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  283. | IPATH_STATUS_IB_READY);
  284. dd->ipath_f_setextled(dd, lstate, ltstate);
  285. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) {
  286. dd->ipath_flags |= IPATH_LINKARMED;
  287. dd->ipath_flags &=
  288. ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT |
  289. IPATH_LINKACTIVE | IPATH_NOCABLE);
  290. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  291. | IPATH_STATUS_IB_READY);
  292. dd->ipath_f_setextled(dd, lstate, ltstate);
  293. } else {
  294. if (!noprint)
  295. ipath_dbg("IBstatuschange unit %u: %s (%x)\n",
  296. dd->ipath_unit,
  297. ipath_ibcstatus_str[ltstate], ltstate);
  298. }
  299. skip_ibchange:
  300. dd->ipath_lastibcstat = val;
  301. }
  302. static void handle_supp_msgs(struct ipath_devdata *dd,
  303. unsigned supp_msgs, char msg[512])
  304. {
  305. /*
  306. * Print the message unless it's ibc status change only, which
  307. * happens so often we never want to count it.
  308. */
  309. if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
  310. ipath_decode_err(msg, sizeof msg, dd->ipath_lasterror &
  311. ~INFINIPATH_E_IBSTATUSCHANGED);
  312. if (dd->ipath_lasterror &
  313. ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
  314. ipath_dev_err(dd, "Suppressed %u messages for "
  315. "fast-repeating errors (%s) (%llx)\n",
  316. supp_msgs, msg,
  317. (unsigned long long)
  318. dd->ipath_lasterror);
  319. else {
  320. /*
  321. * rcvegrfull and rcvhdrqfull are "normal", for some
  322. * types of processes (mostly benchmarks) that send
  323. * huge numbers of messages, while not processing
  324. * them. So only complain about these at debug
  325. * level.
  326. */
  327. ipath_dbg("Suppressed %u messages for %s\n",
  328. supp_msgs, msg);
  329. }
  330. }
  331. }
  332. static unsigned handle_frequent_errors(struct ipath_devdata *dd,
  333. ipath_err_t errs, char msg[512],
  334. int *noprint)
  335. {
  336. unsigned long nc;
  337. static unsigned long nextmsg_time;
  338. static unsigned nmsgs, supp_msgs;
  339. /*
  340. * Throttle back "fast" messages to no more than 10 per 5 seconds.
  341. * This isn't perfect, but it's a reasonable heuristic. If we get
  342. * more than 10, give a 6x longer delay.
  343. */
  344. nc = jiffies;
  345. if (nmsgs > 10) {
  346. if (time_before(nc, nextmsg_time)) {
  347. *noprint = 1;
  348. if (!supp_msgs++)
  349. nextmsg_time = nc + HZ * 3;
  350. }
  351. else if (supp_msgs) {
  352. handle_supp_msgs(dd, supp_msgs, msg);
  353. supp_msgs = 0;
  354. nmsgs = 0;
  355. }
  356. }
  357. else if (!nmsgs++ || time_after(nc, nextmsg_time))
  358. nextmsg_time = nc + HZ / 2;
  359. return supp_msgs;
  360. }
  361. static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
  362. {
  363. char msg[512];
  364. u64 ignore_this_time = 0;
  365. int i;
  366. int chkerrpkts = 0, noprint = 0;
  367. unsigned supp_msgs;
  368. supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint);
  369. /*
  370. * don't report errors that are masked (includes those always
  371. * ignored)
  372. */
  373. errs &= ~dd->ipath_maskederrs;
  374. /* do these first, they are most important */
  375. if (errs & INFINIPATH_E_HARDWARE) {
  376. /* reuse same msg buf */
  377. dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
  378. }
  379. if (!noprint && (errs & ~infinipath_e_bitsextant))
  380. ipath_dev_err(dd, "error interrupt with unknown errors "
  381. "%llx set\n", (unsigned long long)
  382. (errs & ~infinipath_e_bitsextant));
  383. if (errs & E_SUM_ERRS)
  384. ignore_this_time = handle_e_sum_errs(dd, errs);
  385. else if ((errs & E_SUM_LINK_PKTERRS) &&
  386. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  387. /*
  388. * This can happen when SMA is trying to bring the link
  389. * up, but the IB link changes state at the "wrong" time.
  390. * The IB logic then complains that the packet isn't
  391. * valid. We don't want to confuse people, so we just
  392. * don't print them, except at debug
  393. */
  394. ipath_dbg("Ignoring packet errors %llx, because link not "
  395. "ACTIVE\n", (unsigned long long) errs);
  396. ignore_this_time = errs & E_SUM_LINK_PKTERRS;
  397. }
  398. if (supp_msgs == 250000) {
  399. /*
  400. * It's not entirely reasonable assuming that the errors set
  401. * in the last clear period are all responsible for the
  402. * problem, but the alternative is to assume it's the only
  403. * ones on this particular interrupt, which also isn't great
  404. */
  405. dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
  406. ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
  407. ~dd->ipath_maskederrs);
  408. ipath_decode_err(msg, sizeof msg,
  409. (dd->ipath_maskederrs & ~dd->
  410. ipath_ignorederrs));
  411. if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) &
  412. ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
  413. ipath_dev_err(dd, "Disabling error(s) %llx because "
  414. "occurring too frequently (%s)\n",
  415. (unsigned long long)
  416. (dd->ipath_maskederrs &
  417. ~dd->ipath_ignorederrs), msg);
  418. else {
  419. /*
  420. * rcvegrfull and rcvhdrqfull are "normal",
  421. * for some types of processes (mostly benchmarks)
  422. * that send huge numbers of messages, while not
  423. * processing them. So only complain about
  424. * these at debug level.
  425. */
  426. ipath_dbg("Disabling frequent queue full errors "
  427. "(%s)\n", msg);
  428. }
  429. /*
  430. * Re-enable the masked errors after around 3 minutes. in
  431. * ipath_get_faststats(). If we have a series of fast
  432. * repeating but different errors, the interval will keep
  433. * stretching out, but that's OK, as that's pretty
  434. * catastrophic.
  435. */
  436. dd->ipath_unmasktime = jiffies + HZ * 180;
  437. }
  438. ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
  439. if (ignore_this_time)
  440. errs &= ~ignore_this_time;
  441. if (errs & ~dd->ipath_lasterror) {
  442. errs &= ~dd->ipath_lasterror;
  443. /* never suppress duplicate hwerrors or ibstatuschange */
  444. dd->ipath_lasterror |= errs &
  445. ~(INFINIPATH_E_HARDWARE |
  446. INFINIPATH_E_IBSTATUSCHANGED);
  447. }
  448. if (!errs)
  449. return 0;
  450. if (!noprint)
  451. /*
  452. * the ones we mask off are handled specially below or above
  453. */
  454. ipath_decode_err(msg, sizeof msg,
  455. errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
  456. INFINIPATH_E_RRCVEGRFULL |
  457. INFINIPATH_E_RRCVHDRFULL |
  458. INFINIPATH_E_HARDWARE));
  459. else
  460. /* so we don't need if (!noprint) at strlcat's below */
  461. *msg = 0;
  462. if (errs & E_SUM_PKTERRS) {
  463. ipath_stats.sps_pkterrs++;
  464. chkerrpkts = 1;
  465. }
  466. if (errs & E_SUM_ERRS)
  467. ipath_stats.sps_errs++;
  468. if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
  469. ipath_stats.sps_crcerrs++;
  470. chkerrpkts = 1;
  471. }
  472. /*
  473. * We don't want to print these two as they happen, or we can make
  474. * the situation even worse, because it takes so long to print
  475. * messages to serial consoles. Kernel ports get printed from
  476. * fast_stats, no more than every 5 seconds, user ports get printed
  477. * on close
  478. */
  479. if (errs & INFINIPATH_E_RRCVHDRFULL) {
  480. int any;
  481. u32 hd, tl;
  482. ipath_stats.sps_hdrqfull++;
  483. for (any = i = 0; i < dd->ipath_cfgports; i++) {
  484. struct ipath_portdata *pd = dd->ipath_pd[i];
  485. if (i == 0) {
  486. hd = dd->ipath_port0head;
  487. tl = (u32) le64_to_cpu(
  488. *dd->ipath_hdrqtailptr);
  489. } else if (pd && pd->port_cnt &&
  490. pd->port_rcvhdrtail_kvaddr) {
  491. /*
  492. * don't report same point multiple times,
  493. * except kernel
  494. */
  495. tl = (u32) * pd->port_rcvhdrtail_kvaddr;
  496. if (tl == dd->ipath_lastrcvhdrqtails[i])
  497. continue;
  498. hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
  499. i);
  500. } else
  501. continue;
  502. if (hd == (tl + 1) ||
  503. (!hd && tl == dd->ipath_hdrqlast)) {
  504. if (i == 0)
  505. chkerrpkts = 1;
  506. dd->ipath_lastrcvhdrqtails[i] = tl;
  507. pd->port_hdrqfull++;
  508. }
  509. }
  510. }
  511. if (errs & INFINIPATH_E_RRCVEGRFULL) {
  512. /*
  513. * since this is of less importance and not likely to
  514. * happen without also getting hdrfull, only count
  515. * occurrences; don't check each port (or even the kernel
  516. * vs user)
  517. */
  518. ipath_stats.sps_etidfull++;
  519. if (dd->ipath_port0head !=
  520. (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
  521. chkerrpkts = 1;
  522. }
  523. /*
  524. * do this before IBSTATUSCHANGED, in case both bits set in a single
  525. * interrupt; we want the STATUSCHANGE to "win", so we do our
  526. * internal copy of state machine correctly
  527. */
  528. if (errs & INFINIPATH_E_RIBLOSTLINK) {
  529. /*
  530. * force through block below
  531. */
  532. errs |= INFINIPATH_E_IBSTATUSCHANGED;
  533. ipath_stats.sps_iblink++;
  534. dd->ipath_flags |= IPATH_LINKDOWN;
  535. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  536. | IPATH_LINKARMED | IPATH_LINKACTIVE);
  537. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  538. if (!noprint) {
  539. u64 st = ipath_read_kreg64(
  540. dd, dd->ipath_kregs->kr_ibcstatus);
  541. ipath_dbg("Lost link, link now down (%s)\n",
  542. ipath_ibcstatus_str[st & 0xf]);
  543. }
  544. }
  545. if (errs & INFINIPATH_E_IBSTATUSCHANGED)
  546. handle_e_ibstatuschanged(dd, errs, noprint);
  547. if (errs & INFINIPATH_E_RESET) {
  548. if (!noprint)
  549. ipath_dev_err(dd, "Got reset, requires re-init "
  550. "(unload and reload driver)\n");
  551. dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
  552. /* mark as having had error */
  553. *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
  554. *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
  555. }
  556. if (!noprint && *msg)
  557. ipath_dev_err(dd, "%s error\n", msg);
  558. if (dd->ipath_sma_state_wanted & dd->ipath_flags) {
  559. ipath_cdbg(VERBOSE, "sma wanted state %x, iflags now %x, "
  560. "waking\n", dd->ipath_sma_state_wanted,
  561. dd->ipath_flags);
  562. wake_up_interruptible(&ipath_sma_state_wait);
  563. }
  564. return chkerrpkts;
  565. }
  566. /* this is separate to allow for better optimization of ipath_intr() */
  567. static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp)
  568. {
  569. /*
  570. * sometimes happen during driver init and unload, don't want
  571. * to process any interrupts at that point
  572. */
  573. /* this is just a bandaid, not a fix, if something goes badly
  574. * wrong */
  575. if (++*unexpectp > 100) {
  576. if (++*unexpectp > 105) {
  577. /*
  578. * ok, we must be taking somebody else's interrupts,
  579. * due to a messed up mptable and/or PIRQ table, so
  580. * unregister the interrupt. We've seen this during
  581. * linuxbios development work, and it may happen in
  582. * the future again.
  583. */
  584. if (dd->pcidev && dd->pcidev->irq) {
  585. ipath_dev_err(dd, "Now %u unexpected "
  586. "interrupts, unregistering "
  587. "interrupt handler\n",
  588. *unexpectp);
  589. ipath_dbg("free_irq of irq %x\n",
  590. dd->pcidev->irq);
  591. free_irq(dd->pcidev->irq, dd);
  592. }
  593. }
  594. if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) {
  595. ipath_dev_err(dd, "%u unexpected interrupts, "
  596. "disabling interrupts completely\n",
  597. *unexpectp);
  598. /*
  599. * disable all interrupts, something is very wrong
  600. */
  601. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
  602. 0ULL);
  603. }
  604. } else if (*unexpectp > 1)
  605. ipath_dbg("Interrupt when not ready, should not happen, "
  606. "ignoring\n");
  607. }
  608. static void ipath_bad_regread(struct ipath_devdata *dd)
  609. {
  610. static int allbits;
  611. /* separate routine, for better optimization of ipath_intr() */
  612. /*
  613. * We print the message and disable interrupts, in hope of
  614. * having a better chance of debugging the problem.
  615. */
  616. ipath_dev_err(dd,
  617. "Read of interrupt status failed (all bits set)\n");
  618. if (allbits++) {
  619. /* disable all interrupts, something is very wrong */
  620. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
  621. if (allbits == 2) {
  622. ipath_dev_err(dd, "Still bad interrupt status, "
  623. "unregistering interrupt\n");
  624. free_irq(dd->pcidev->irq, dd);
  625. } else if (allbits > 2) {
  626. if ((allbits % 10000) == 0)
  627. printk(".");
  628. } else
  629. ipath_dev_err(dd, "Disabling interrupts, "
  630. "multiple errors\n");
  631. }
  632. }
  633. static void handle_port_pioavail(struct ipath_devdata *dd)
  634. {
  635. u32 i;
  636. /*
  637. * start from port 1, since for now port 0 is never using
  638. * wait_event for PIO
  639. */
  640. for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) {
  641. struct ipath_portdata *pd = dd->ipath_pd[i];
  642. if (pd && pd->port_cnt &&
  643. dd->ipath_portpiowait & (1U << i)) {
  644. clear_bit(i, &dd->ipath_portpiowait);
  645. if (test_bit(IPATH_PORT_WAITING_PIO,
  646. &pd->port_flag)) {
  647. clear_bit(IPATH_PORT_WAITING_PIO,
  648. &pd->port_flag);
  649. wake_up_interruptible(&pd->port_wait);
  650. }
  651. }
  652. }
  653. }
  654. static void handle_layer_pioavail(struct ipath_devdata *dd)
  655. {
  656. int ret;
  657. ret = __ipath_layer_intr(dd, IPATH_LAYER_INT_SEND_CONTINUE);
  658. if (ret > 0)
  659. goto set;
  660. ret = ipath_ib_piobufavail(dd->verbs_dev);
  661. if (ret > 0)
  662. goto set;
  663. return;
  664. set:
  665. set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  666. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  667. dd->ipath_sendctrl);
  668. }
  669. /*
  670. * Handle receive interrupts for user ports; this means a user
  671. * process was waiting for a packet to arrive, and didn't want
  672. * to poll
  673. */
  674. static void handle_urcv(struct ipath_devdata *dd, u32 istat)
  675. {
  676. u64 portr;
  677. int i;
  678. int rcvdint = 0;
  679. portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
  680. infinipath_i_rcvavail_mask)
  681. | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
  682. infinipath_i_rcvurg_mask);
  683. for (i = 1; i < dd->ipath_cfgports; i++) {
  684. struct ipath_portdata *pd = dd->ipath_pd[i];
  685. if (portr & (1 << i) && pd && pd->port_cnt &&
  686. test_bit(IPATH_PORT_WAITING_RCV, &pd->port_flag)) {
  687. int rcbit;
  688. clear_bit(IPATH_PORT_WAITING_RCV,
  689. &pd->port_flag);
  690. rcbit = i + INFINIPATH_R_INTRAVAIL_SHIFT;
  691. clear_bit(1UL << rcbit, &dd->ipath_rcvctrl);
  692. wake_up_interruptible(&pd->port_wait);
  693. rcvdint = 1;
  694. }
  695. }
  696. if (rcvdint) {
  697. /* only want to take one interrupt, so turn off the rcv
  698. * interrupt for all the ports that we did the wakeup on
  699. * (but never for kernel port)
  700. */
  701. ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
  702. dd->ipath_rcvctrl);
  703. }
  704. }
  705. irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
  706. {
  707. struct ipath_devdata *dd = data;
  708. u32 istat, chk0rcv = 0;
  709. ipath_err_t estat = 0;
  710. irqreturn_t ret;
  711. u32 oldhead, curtail;
  712. static unsigned unexpected = 0;
  713. static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
  714. (1U<<INFINIPATH_I_RCVURG_SHIFT);
  715. ipath_stats.sps_ints++;
  716. if (!(dd->ipath_flags & IPATH_PRESENT)) {
  717. /*
  718. * This return value is not great, but we do not want the
  719. * interrupt core code to remove our interrupt handler
  720. * because we don't appear to be handling an interrupt
  721. * during a chip reset.
  722. */
  723. return IRQ_HANDLED;
  724. }
  725. /*
  726. * this needs to be flags&initted, not statusp, so we keep
  727. * taking interrupts even after link goes down, etc.
  728. * Also, we *must* clear the interrupt at some point, or we won't
  729. * take it again, which can be real bad for errors, etc...
  730. */
  731. if (!(dd->ipath_flags & IPATH_INITTED)) {
  732. ipath_bad_intr(dd, &unexpected);
  733. ret = IRQ_NONE;
  734. goto bail;
  735. }
  736. /*
  737. * We try to avoid reading the interrupt status register, since
  738. * that's a PIO read, and stalls the processor for up to about
  739. * ~0.25 usec. The idea is that if we processed a port0 packet,
  740. * we blindly clear the port 0 receive interrupt bits, and nothing
  741. * else, then return. If other interrupts are pending, the chip
  742. * will re-interrupt us as soon as we write the intclear register.
  743. * We then won't process any more kernel packets (if not the 2nd
  744. * time, then the 3rd or 4th) and we'll then handle the other
  745. * interrupts. We clear the interrupts first so that we don't
  746. * lose intr for later packets that arrive while we are processing.
  747. */
  748. oldhead = dd->ipath_port0head;
  749. curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
  750. if (oldhead != curtail) {
  751. if (dd->ipath_flags & IPATH_GPIO_INTR) {
  752. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  753. (u64) (1 << 2));
  754. istat = port0rbits | INFINIPATH_I_GPIO;
  755. }
  756. else
  757. istat = port0rbits;
  758. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  759. ipath_kreceive(dd);
  760. if (oldhead != dd->ipath_port0head) {
  761. ipath_stats.sps_fastrcvint++;
  762. goto done;
  763. }
  764. }
  765. istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
  766. if (unlikely(!istat)) {
  767. ipath_stats.sps_nullintr++;
  768. ret = IRQ_NONE; /* not our interrupt, or already handled */
  769. goto bail;
  770. }
  771. if (unlikely(istat == -1)) {
  772. ipath_bad_regread(dd);
  773. /* don't know if it was our interrupt or not */
  774. ret = IRQ_NONE;
  775. goto bail;
  776. }
  777. if (unexpected)
  778. unexpected = 0;
  779. if (unlikely(istat & ~infinipath_i_bitsextant))
  780. ipath_dev_err(dd,
  781. "interrupt with unknown interrupts %x set\n",
  782. istat & (u32) ~ infinipath_i_bitsextant);
  783. else
  784. ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
  785. if (unlikely(istat & INFINIPATH_I_ERROR)) {
  786. ipath_stats.sps_errints++;
  787. estat = ipath_read_kreg64(dd,
  788. dd->ipath_kregs->kr_errorstatus);
  789. if (!estat)
  790. dev_info(&dd->pcidev->dev, "error interrupt (%x), "
  791. "but no error bits set!\n", istat);
  792. else if (estat == -1LL)
  793. /*
  794. * should we try clearing all, or hope next read
  795. * works?
  796. */
  797. ipath_dev_err(dd, "Read of error status failed "
  798. "(all bits set); ignoring\n");
  799. else
  800. if (handle_errors(dd, estat))
  801. /* force calling ipath_kreceive() */
  802. chk0rcv = 1;
  803. }
  804. if (istat & INFINIPATH_I_GPIO) {
  805. /*
  806. * Packets are available in the port 0 rcv queue.
  807. * Eventually this needs to be generalized to check
  808. * IPATH_GPIO_INTR, and the specific GPIO bit, if
  809. * GPIO interrupts are used for anything else.
  810. */
  811. if (unlikely(!(dd->ipath_flags & IPATH_GPIO_INTR))) {
  812. u32 gpiostatus;
  813. gpiostatus = ipath_read_kreg32(
  814. dd, dd->ipath_kregs->kr_gpio_status);
  815. ipath_dbg("Unexpected GPIO interrupt bits %x\n",
  816. gpiostatus);
  817. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  818. gpiostatus);
  819. }
  820. else {
  821. /* Clear GPIO status bit 2 */
  822. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  823. (u64) (1 << 2));
  824. chk0rcv = 1;
  825. }
  826. }
  827. chk0rcv |= istat & port0rbits;
  828. /*
  829. * Clear the interrupt bits we found set, unless they are receive
  830. * related, in which case we already cleared them above, and don't
  831. * want to clear them again, because we might lose an interrupt.
  832. * Clear it early, so we "know" know the chip will have seen this by
  833. * the time we process the queue, and will re-interrupt if necessary.
  834. * The processor itself won't take the interrupt again until we return.
  835. */
  836. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  837. /*
  838. * handle port0 receive before checking for pio buffers available,
  839. * since receives can overflow; piobuf waiters can afford a few
  840. * extra cycles, since they were waiting anyway, and user's waiting
  841. * for receive are at the bottom.
  842. */
  843. if (chk0rcv) {
  844. ipath_kreceive(dd);
  845. istat &= ~port0rbits;
  846. }
  847. if (istat & ((infinipath_i_rcvavail_mask <<
  848. INFINIPATH_I_RCVAVAIL_SHIFT)
  849. | (infinipath_i_rcvurg_mask <<
  850. INFINIPATH_I_RCVURG_SHIFT)))
  851. handle_urcv(dd, istat);
  852. if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
  853. clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  854. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  855. dd->ipath_sendctrl);
  856. if (dd->ipath_portpiowait)
  857. handle_port_pioavail(dd);
  858. handle_layer_pioavail(dd);
  859. }
  860. done:
  861. ret = IRQ_HANDLED;
  862. bail:
  863. return ret;
  864. }