iwl-agn.c 87 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. iwl_clear_stations_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->meta[index], mapping),
  366. pci_unmap_len(&txq->meta[index], len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int txq_id = txq->q.id;
  416. /* Circular buffer (TFD queue in DRAM) physical base address */
  417. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  418. txq->q.dma_addr >> 8);
  419. return 0;
  420. }
  421. /******************************************************************************
  422. *
  423. * Generic RX handler implementations
  424. *
  425. ******************************************************************************/
  426. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  427. struct iwl_rx_mem_buffer *rxb)
  428. {
  429. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  430. struct iwl_alive_resp *palive;
  431. struct delayed_work *pwork;
  432. palive = &pkt->u.alive_frame;
  433. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  434. "0x%01X 0x%01X\n",
  435. palive->is_valid, palive->ver_type,
  436. palive->ver_subtype);
  437. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  438. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  439. set_bit(STATUS_INIT_UCODE_ALIVE, &priv->status);
  440. wake_up_interruptible(&priv->wait_command_queue);
  441. memcpy(&priv->card_alive_init,
  442. &pkt->u.alive_frame,
  443. sizeof(struct iwl_init_alive_resp));
  444. pwork = &priv->init_alive_start;
  445. } else {
  446. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  447. set_bit(STATUS_RT_UCODE_ALIVE, &priv->status);
  448. wake_up_interruptible(&priv->wait_command_queue);
  449. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  450. sizeof(struct iwl_alive_resp));
  451. pwork = &priv->alive_start;
  452. }
  453. /* We delay the ALIVE response by 5ms to
  454. * give the HW RF Kill time to activate... */
  455. if (palive->is_valid == UCODE_VALID_OK)
  456. queue_delayed_work(priv->workqueue, pwork,
  457. msecs_to_jiffies(5));
  458. else
  459. IWL_WARN(priv, "uCode did not respond OK.\n");
  460. }
  461. static void iwl_bg_beacon_update(struct work_struct *work)
  462. {
  463. struct iwl_priv *priv =
  464. container_of(work, struct iwl_priv, beacon_update);
  465. struct sk_buff *beacon;
  466. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  467. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  468. if (!beacon) {
  469. IWL_ERR(priv, "update beacon failed\n");
  470. return;
  471. }
  472. mutex_lock(&priv->mutex);
  473. /* new beacon skb is allocated every time; dispose previous.*/
  474. if (priv->ibss_beacon)
  475. dev_kfree_skb(priv->ibss_beacon);
  476. priv->ibss_beacon = beacon;
  477. mutex_unlock(&priv->mutex);
  478. iwl_send_beacon_cmd(priv);
  479. }
  480. /**
  481. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  482. *
  483. * This callback is provided in order to send a statistics request.
  484. *
  485. * This timer function is continually reset to execute within
  486. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  487. * was received. We need to ensure we receive the statistics in order
  488. * to update the temperature used for calibrating the TXPOWER.
  489. */
  490. static void iwl_bg_statistics_periodic(unsigned long data)
  491. {
  492. struct iwl_priv *priv = (struct iwl_priv *)data;
  493. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  494. return;
  495. /* dont send host command if rf-kill is on */
  496. if (!iwl_is_ready_rf(priv))
  497. return;
  498. iwl_send_statistics_request(priv, CMD_ASYNC);
  499. }
  500. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  501. struct iwl_rx_mem_buffer *rxb)
  502. {
  503. #ifdef CONFIG_IWLWIFI_DEBUG
  504. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  505. struct iwl4965_beacon_notif *beacon =
  506. (struct iwl4965_beacon_notif *)pkt->u.raw;
  507. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  508. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  509. "tsf %d %d rate %d\n",
  510. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  511. beacon->beacon_notify_hdr.failure_frame,
  512. le32_to_cpu(beacon->ibss_mgr_status),
  513. le32_to_cpu(beacon->high_tsf),
  514. le32_to_cpu(beacon->low_tsf), rate);
  515. #endif
  516. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  517. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  518. queue_work(priv->workqueue, &priv->beacon_update);
  519. }
  520. /* Handle notification from uCode that card's power state is changing
  521. * due to software, hardware, or critical temperature RFKILL */
  522. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  523. struct iwl_rx_mem_buffer *rxb)
  524. {
  525. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  526. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  527. unsigned long status = priv->status;
  528. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  529. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  530. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  531. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  532. RF_CARD_DISABLED)) {
  533. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  534. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  535. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  536. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  537. if (!(flags & RXON_CARD_DISABLED)) {
  538. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  539. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  540. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  541. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  542. }
  543. if (flags & RF_CARD_DISABLED)
  544. iwl_tt_enter_ct_kill(priv);
  545. }
  546. if (!(flags & RF_CARD_DISABLED))
  547. iwl_tt_exit_ct_kill(priv);
  548. if (flags & HW_CARD_DISABLED)
  549. set_bit(STATUS_RF_KILL_HW, &priv->status);
  550. else
  551. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  552. if (!(flags & RXON_CARD_DISABLED))
  553. iwl_scan_cancel(priv);
  554. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  555. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  556. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  557. test_bit(STATUS_RF_KILL_HW, &priv->status));
  558. else
  559. wake_up_interruptible(&priv->wait_command_queue);
  560. }
  561. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  562. {
  563. if (src == IWL_PWR_SRC_VAUX) {
  564. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  565. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  566. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  567. ~APMG_PS_CTRL_MSK_PWR_SRC);
  568. } else {
  569. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  570. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  571. ~APMG_PS_CTRL_MSK_PWR_SRC);
  572. }
  573. return 0;
  574. }
  575. /**
  576. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  577. *
  578. * Setup the RX handlers for each of the reply types sent from the uCode
  579. * to the host.
  580. *
  581. * This function chains into the hardware specific files for them to setup
  582. * any hardware specific handlers as well.
  583. */
  584. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  585. {
  586. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  587. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  588. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  589. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  590. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  591. iwl_rx_pm_debug_statistics_notif;
  592. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  593. /*
  594. * The same handler is used for both the REPLY to a discrete
  595. * statistics request from the host as well as for the periodic
  596. * statistics notifications (after received beacons) from the uCode.
  597. */
  598. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  599. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  600. iwl_setup_spectrum_handlers(priv);
  601. iwl_setup_rx_scan_handlers(priv);
  602. /* status change handler */
  603. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  604. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  605. iwl_rx_missed_beacon_notif;
  606. /* Rx handlers */
  607. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  608. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  609. /* block ack */
  610. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  611. /* Set up hardware specific Rx handlers */
  612. priv->cfg->ops->lib->rx_handler_setup(priv);
  613. }
  614. /**
  615. * iwl_rx_handle - Main entry function for receiving responses from uCode
  616. *
  617. * Uses the priv->rx_handlers callback function array to invoke
  618. * the appropriate handlers, including command responses,
  619. * frame-received notifications, and other notifications.
  620. */
  621. void iwl_rx_handle(struct iwl_priv *priv)
  622. {
  623. struct iwl_rx_mem_buffer *rxb;
  624. struct iwl_rx_packet *pkt;
  625. struct iwl_rx_queue *rxq = &priv->rxq;
  626. u32 r, i;
  627. int reclaim;
  628. unsigned long flags;
  629. u8 fill_rx = 0;
  630. u32 count = 8;
  631. int total_empty;
  632. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  633. * buffer that the driver may process (last buffer filled by ucode). */
  634. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  635. i = rxq->read;
  636. /* Rx interrupt, but nothing sent from uCode */
  637. if (i == r)
  638. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  639. /* calculate total frames need to be restock after handling RX */
  640. total_empty = r - priv->rxq.write_actual;
  641. if (total_empty < 0)
  642. total_empty += RX_QUEUE_SIZE;
  643. if (total_empty > (RX_QUEUE_SIZE / 2))
  644. fill_rx = 1;
  645. while (i != r) {
  646. rxb = rxq->queue[i];
  647. /* If an RXB doesn't have a Rx queue slot associated with it,
  648. * then a bug has been introduced in the queue refilling
  649. * routines -- catch it here */
  650. BUG_ON(rxb == NULL);
  651. rxq->queue[i] = NULL;
  652. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  653. priv->hw_params.rx_buf_size + 256,
  654. PCI_DMA_FROMDEVICE);
  655. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  656. /* Reclaim a command buffer only if this packet is a response
  657. * to a (driver-originated) command.
  658. * If the packet (e.g. Rx frame) originated from uCode,
  659. * there is no command buffer to reclaim.
  660. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  661. * but apparently a few don't get set; catch them here. */
  662. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  663. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  664. (pkt->hdr.cmd != REPLY_RX) &&
  665. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  666. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  667. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  668. (pkt->hdr.cmd != REPLY_TX);
  669. /* Based on type of command response or notification,
  670. * handle those that need handling via function in
  671. * rx_handlers table. See iwl_setup_rx_handlers() */
  672. if (priv->rx_handlers[pkt->hdr.cmd]) {
  673. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  674. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  675. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  676. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  677. } else {
  678. /* No handling needed */
  679. IWL_DEBUG_RX(priv,
  680. "r %d i %d No handler needed for %s, 0x%02x\n",
  681. r, i, get_cmd_string(pkt->hdr.cmd),
  682. pkt->hdr.cmd);
  683. }
  684. if (reclaim) {
  685. /* Invoke any callbacks, transfer the skb to caller, and
  686. * fire off the (possibly) blocking iwl_send_cmd()
  687. * as we reclaim the driver command queue */
  688. if (rxb && rxb->skb)
  689. iwl_tx_cmd_complete(priv, rxb);
  690. else
  691. IWL_WARN(priv, "Claim null rxb?\n");
  692. }
  693. /* For now we just don't re-use anything. We can tweak this
  694. * later to try and re-use notification packets and SKBs that
  695. * fail to Rx correctly */
  696. if (rxb->skb != NULL) {
  697. priv->alloc_rxb_skb--;
  698. dev_kfree_skb_any(rxb->skb);
  699. rxb->skb = NULL;
  700. }
  701. spin_lock_irqsave(&rxq->lock, flags);
  702. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  703. spin_unlock_irqrestore(&rxq->lock, flags);
  704. i = (i + 1) & RX_QUEUE_MASK;
  705. /* If there are a lot of unused frames,
  706. * restock the Rx queue so ucode wont assert. */
  707. if (fill_rx) {
  708. count++;
  709. if (count >= 8) {
  710. priv->rxq.read = i;
  711. iwl_rx_replenish_now(priv);
  712. count = 0;
  713. }
  714. }
  715. }
  716. /* Backtrack one entry */
  717. priv->rxq.read = i;
  718. if (fill_rx)
  719. iwl_rx_replenish_now(priv);
  720. else
  721. iwl_rx_queue_restock(priv);
  722. }
  723. /* call this function to flush any scheduled tasklet */
  724. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  725. {
  726. /* wait to make sure we flush pending tasklet*/
  727. synchronize_irq(priv->pci_dev->irq);
  728. tasklet_kill(&priv->irq_tasklet);
  729. }
  730. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  731. {
  732. u32 inta, handled = 0;
  733. u32 inta_fh;
  734. unsigned long flags;
  735. #ifdef CONFIG_IWLWIFI_DEBUG
  736. u32 inta_mask;
  737. #endif
  738. spin_lock_irqsave(&priv->lock, flags);
  739. /* Ack/clear/reset pending uCode interrupts.
  740. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  741. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  742. inta = iwl_read32(priv, CSR_INT);
  743. iwl_write32(priv, CSR_INT, inta);
  744. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  745. * Any new interrupts that happen after this, either while we're
  746. * in this tasklet, or later, will show up in next ISR/tasklet. */
  747. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  748. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  749. #ifdef CONFIG_IWLWIFI_DEBUG
  750. if (iwl_debug_level & IWL_DL_ISR) {
  751. /* just for debug */
  752. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  753. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  754. inta, inta_mask, inta_fh);
  755. }
  756. #endif
  757. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  758. * atomic, make sure that inta covers all the interrupts that
  759. * we've discovered, even if FH interrupt came in just after
  760. * reading CSR_INT. */
  761. if (inta_fh & CSR49_FH_INT_RX_MASK)
  762. inta |= CSR_INT_BIT_FH_RX;
  763. if (inta_fh & CSR49_FH_INT_TX_MASK)
  764. inta |= CSR_INT_BIT_FH_TX;
  765. /* Now service all interrupt bits discovered above. */
  766. if (inta & CSR_INT_BIT_HW_ERR) {
  767. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  768. /* Tell the device to stop sending interrupts */
  769. iwl_disable_interrupts(priv);
  770. priv->isr_stats.hw++;
  771. iwl_irq_handle_error(priv);
  772. handled |= CSR_INT_BIT_HW_ERR;
  773. spin_unlock_irqrestore(&priv->lock, flags);
  774. return;
  775. }
  776. #ifdef CONFIG_IWLWIFI_DEBUG
  777. if (iwl_debug_level & (IWL_DL_ISR)) {
  778. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  779. if (inta & CSR_INT_BIT_SCD) {
  780. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  781. "the frame/frames.\n");
  782. priv->isr_stats.sch++;
  783. }
  784. /* Alive notification via Rx interrupt will do the real work */
  785. if (inta & CSR_INT_BIT_ALIVE) {
  786. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  787. priv->isr_stats.alive++;
  788. }
  789. }
  790. #endif
  791. /* Safely ignore these bits for debug checks below */
  792. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  793. /* HW RF KILL switch toggled */
  794. if (inta & CSR_INT_BIT_RF_KILL) {
  795. int hw_rf_kill = 0;
  796. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  797. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  798. hw_rf_kill = 1;
  799. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  800. hw_rf_kill ? "disable radio" : "enable radio");
  801. priv->isr_stats.rfkill++;
  802. /* driver only loads ucode once setting the interface up.
  803. * the driver allows loading the ucode even if the radio
  804. * is killed. Hence update the killswitch state here. The
  805. * rfkill handler will care about restarting if needed.
  806. */
  807. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  808. if (hw_rf_kill)
  809. set_bit(STATUS_RF_KILL_HW, &priv->status);
  810. else
  811. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  812. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  813. }
  814. handled |= CSR_INT_BIT_RF_KILL;
  815. }
  816. /* Chip got too hot and stopped itself */
  817. if (inta & CSR_INT_BIT_CT_KILL) {
  818. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  819. priv->isr_stats.ctkill++;
  820. handled |= CSR_INT_BIT_CT_KILL;
  821. }
  822. /* Error detected by uCode */
  823. if (inta & CSR_INT_BIT_SW_ERR) {
  824. IWL_ERR(priv, "Microcode SW error detected. "
  825. " Restarting 0x%X.\n", inta);
  826. priv->isr_stats.sw++;
  827. priv->isr_stats.sw_err = inta;
  828. iwl_irq_handle_error(priv);
  829. handled |= CSR_INT_BIT_SW_ERR;
  830. }
  831. /* uCode wakes up after power-down sleep */
  832. if (inta & CSR_INT_BIT_WAKEUP) {
  833. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  834. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  835. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  836. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  837. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  838. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  839. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  840. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  841. priv->isr_stats.wakeup++;
  842. handled |= CSR_INT_BIT_WAKEUP;
  843. }
  844. /* All uCode command responses, including Tx command responses,
  845. * Rx "responses" (frame-received notification), and other
  846. * notifications from uCode come through here*/
  847. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  848. iwl_rx_handle(priv);
  849. priv->isr_stats.rx++;
  850. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  851. }
  852. if (inta & CSR_INT_BIT_FH_TX) {
  853. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  854. priv->isr_stats.tx++;
  855. handled |= CSR_INT_BIT_FH_TX;
  856. /* FH finished to write, send event */
  857. priv->ucode_write_complete = 1;
  858. wake_up_interruptible(&priv->wait_command_queue);
  859. }
  860. if (inta & ~handled) {
  861. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  862. priv->isr_stats.unhandled++;
  863. }
  864. if (inta & ~(priv->inta_mask)) {
  865. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  866. inta & ~priv->inta_mask);
  867. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  868. }
  869. /* Re-enable all interrupts */
  870. /* only Re-enable if diabled by irq */
  871. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  872. iwl_enable_interrupts(priv);
  873. #ifdef CONFIG_IWLWIFI_DEBUG
  874. if (iwl_debug_level & (IWL_DL_ISR)) {
  875. inta = iwl_read32(priv, CSR_INT);
  876. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  877. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  878. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  879. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  880. }
  881. #endif
  882. spin_unlock_irqrestore(&priv->lock, flags);
  883. }
  884. /* tasklet for iwlagn interrupt */
  885. static void iwl_irq_tasklet(struct iwl_priv *priv)
  886. {
  887. u32 inta = 0;
  888. u32 handled = 0;
  889. unsigned long flags;
  890. #ifdef CONFIG_IWLWIFI_DEBUG
  891. u32 inta_mask;
  892. #endif
  893. spin_lock_irqsave(&priv->lock, flags);
  894. /* Ack/clear/reset pending uCode interrupts.
  895. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  896. */
  897. iwl_write32(priv, CSR_INT, priv->inta);
  898. inta = priv->inta;
  899. #ifdef CONFIG_IWLWIFI_DEBUG
  900. if (iwl_debug_level & IWL_DL_ISR) {
  901. /* just for debug */
  902. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  903. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  904. inta, inta_mask);
  905. }
  906. #endif
  907. /* saved interrupt in inta variable now we can reset priv->inta */
  908. priv->inta = 0;
  909. /* Now service all interrupt bits discovered above. */
  910. if (inta & CSR_INT_BIT_HW_ERR) {
  911. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  912. /* Tell the device to stop sending interrupts */
  913. iwl_disable_interrupts(priv);
  914. priv->isr_stats.hw++;
  915. iwl_irq_handle_error(priv);
  916. handled |= CSR_INT_BIT_HW_ERR;
  917. spin_unlock_irqrestore(&priv->lock, flags);
  918. return;
  919. }
  920. #ifdef CONFIG_IWLWIFI_DEBUG
  921. if (iwl_debug_level & (IWL_DL_ISR)) {
  922. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  923. if (inta & CSR_INT_BIT_SCD) {
  924. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  925. "the frame/frames.\n");
  926. priv->isr_stats.sch++;
  927. }
  928. /* Alive notification via Rx interrupt will do the real work */
  929. if (inta & CSR_INT_BIT_ALIVE) {
  930. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  931. priv->isr_stats.alive++;
  932. }
  933. }
  934. #endif
  935. /* Safely ignore these bits for debug checks below */
  936. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  937. /* HW RF KILL switch toggled */
  938. if (inta & CSR_INT_BIT_RF_KILL) {
  939. int hw_rf_kill = 0;
  940. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  941. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  942. hw_rf_kill = 1;
  943. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  944. hw_rf_kill ? "disable radio" : "enable radio");
  945. priv->isr_stats.rfkill++;
  946. /* driver only loads ucode once setting the interface up.
  947. * the driver allows loading the ucode even if the radio
  948. * is killed. Hence update the killswitch state here. The
  949. * rfkill handler will care about restarting if needed.
  950. */
  951. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  952. if (hw_rf_kill)
  953. set_bit(STATUS_RF_KILL_HW, &priv->status);
  954. else
  955. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  956. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  957. }
  958. handled |= CSR_INT_BIT_RF_KILL;
  959. }
  960. /* Chip got too hot and stopped itself */
  961. if (inta & CSR_INT_BIT_CT_KILL) {
  962. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  963. priv->isr_stats.ctkill++;
  964. handled |= CSR_INT_BIT_CT_KILL;
  965. }
  966. /* Error detected by uCode */
  967. if (inta & CSR_INT_BIT_SW_ERR) {
  968. IWL_ERR(priv, "Microcode SW error detected. "
  969. " Restarting 0x%X.\n", inta);
  970. priv->isr_stats.sw++;
  971. priv->isr_stats.sw_err = inta;
  972. iwl_irq_handle_error(priv);
  973. handled |= CSR_INT_BIT_SW_ERR;
  974. }
  975. /* uCode wakes up after power-down sleep */
  976. if (inta & CSR_INT_BIT_WAKEUP) {
  977. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  978. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  979. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  980. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  981. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  982. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  983. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  984. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  985. priv->isr_stats.wakeup++;
  986. handled |= CSR_INT_BIT_WAKEUP;
  987. }
  988. /* All uCode command responses, including Tx command responses,
  989. * Rx "responses" (frame-received notification), and other
  990. * notifications from uCode come through here*/
  991. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  992. CSR_INT_BIT_RX_PERIODIC)) {
  993. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  994. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  995. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  996. iwl_write32(priv, CSR_FH_INT_STATUS,
  997. CSR49_FH_INT_RX_MASK);
  998. }
  999. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1000. handled |= CSR_INT_BIT_RX_PERIODIC;
  1001. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1002. }
  1003. /* Sending RX interrupt require many steps to be done in the
  1004. * the device:
  1005. * 1- write interrupt to current index in ICT table.
  1006. * 2- dma RX frame.
  1007. * 3- update RX shared data to indicate last write index.
  1008. * 4- send interrupt.
  1009. * This could lead to RX race, driver could receive RX interrupt
  1010. * but the shared data changes does not reflect this.
  1011. * this could lead to RX race, RX periodic will solve this race
  1012. */
  1013. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1014. CSR_INT_PERIODIC_DIS);
  1015. iwl_rx_handle(priv);
  1016. /* Only set RX periodic if real RX is received. */
  1017. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1018. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1019. CSR_INT_PERIODIC_ENA);
  1020. priv->isr_stats.rx++;
  1021. }
  1022. if (inta & CSR_INT_BIT_FH_TX) {
  1023. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1024. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1025. priv->isr_stats.tx++;
  1026. handled |= CSR_INT_BIT_FH_TX;
  1027. /* FH finished to write, send event */
  1028. priv->ucode_write_complete = 1;
  1029. wake_up_interruptible(&priv->wait_command_queue);
  1030. }
  1031. if (inta & ~handled) {
  1032. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1033. priv->isr_stats.unhandled++;
  1034. }
  1035. if (inta & ~(priv->inta_mask)) {
  1036. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1037. inta & ~priv->inta_mask);
  1038. }
  1039. /* Re-enable all interrupts */
  1040. /* only Re-enable if diabled by irq */
  1041. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1042. iwl_enable_interrupts(priv);
  1043. spin_unlock_irqrestore(&priv->lock, flags);
  1044. }
  1045. /******************************************************************************
  1046. *
  1047. * uCode download functions
  1048. *
  1049. ******************************************************************************/
  1050. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1051. {
  1052. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1053. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1054. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1055. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1056. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1057. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1058. }
  1059. static void iwl_nic_start(struct iwl_priv *priv)
  1060. {
  1061. /* Remove all resets to allow NIC to operate */
  1062. iwl_write32(priv, CSR_RESET, 0);
  1063. }
  1064. /**
  1065. * iwl_read_ucode - Read uCode images from disk file.
  1066. *
  1067. * Copy into buffers for card to fetch via bus-mastering
  1068. */
  1069. static int iwl_read_ucode(struct iwl_priv *priv)
  1070. {
  1071. struct iwl_ucode_header *ucode;
  1072. int ret = -EINVAL, index;
  1073. const struct firmware *ucode_raw;
  1074. const char *name_pre = priv->cfg->fw_name_pre;
  1075. const unsigned int api_max = priv->cfg->ucode_api_max;
  1076. const unsigned int api_min = priv->cfg->ucode_api_min;
  1077. char buf[25];
  1078. u8 *src;
  1079. size_t len;
  1080. u32 api_ver, build;
  1081. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1082. u16 eeprom_ver;
  1083. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1084. * request_firmware() is synchronous, file is in memory on return. */
  1085. for (index = api_max; index >= api_min; index--) {
  1086. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1087. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1088. if (ret < 0) {
  1089. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1090. buf, ret);
  1091. if (ret == -ENOENT)
  1092. continue;
  1093. else
  1094. goto error;
  1095. } else {
  1096. if (index < api_max)
  1097. IWL_ERR(priv, "Loaded firmware %s, "
  1098. "which is deprecated. "
  1099. "Please use API v%u instead.\n",
  1100. buf, api_max);
  1101. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1102. buf, ucode_raw->size);
  1103. break;
  1104. }
  1105. }
  1106. if (ret < 0)
  1107. goto error;
  1108. /* Make sure that we got at least the v1 header! */
  1109. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1110. IWL_ERR(priv, "File size way too small!\n");
  1111. ret = -EINVAL;
  1112. goto err_release;
  1113. }
  1114. /* Data from ucode file: header followed by uCode images */
  1115. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1116. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1117. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1118. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1119. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1120. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1121. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1122. init_data_size =
  1123. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1124. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1125. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1126. /* api_ver should match the api version forming part of the
  1127. * firmware filename ... but we don't check for that and only rely
  1128. * on the API version read from firmware header from here on forward */
  1129. if (api_ver < api_min || api_ver > api_max) {
  1130. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1131. "Driver supports v%u, firmware is v%u.\n",
  1132. api_max, api_ver);
  1133. priv->ucode_ver = 0;
  1134. ret = -EINVAL;
  1135. goto err_release;
  1136. }
  1137. if (api_ver != api_max)
  1138. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1139. "got v%u. New firmware can be obtained "
  1140. "from http://www.intellinuxwireless.org.\n",
  1141. api_max, api_ver);
  1142. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1143. IWL_UCODE_MAJOR(priv->ucode_ver),
  1144. IWL_UCODE_MINOR(priv->ucode_ver),
  1145. IWL_UCODE_API(priv->ucode_ver),
  1146. IWL_UCODE_SERIAL(priv->ucode_ver));
  1147. if (build)
  1148. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1149. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1150. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1151. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1152. ? "OTP" : "EEPROM", eeprom_ver);
  1153. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1154. priv->ucode_ver);
  1155. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1156. inst_size);
  1157. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1158. data_size);
  1159. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1160. init_size);
  1161. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1162. init_data_size);
  1163. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1164. boot_size);
  1165. /* Verify size of file vs. image size info in file's header */
  1166. if (ucode_raw->size !=
  1167. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1168. inst_size + data_size + init_size +
  1169. init_data_size + boot_size) {
  1170. IWL_DEBUG_INFO(priv,
  1171. "uCode file size %d does not match expected size\n",
  1172. (int)ucode_raw->size);
  1173. ret = -EINVAL;
  1174. goto err_release;
  1175. }
  1176. /* Verify that uCode images will fit in card's SRAM */
  1177. if (inst_size > priv->hw_params.max_inst_size) {
  1178. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1179. inst_size);
  1180. ret = -EINVAL;
  1181. goto err_release;
  1182. }
  1183. if (data_size > priv->hw_params.max_data_size) {
  1184. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1185. data_size);
  1186. ret = -EINVAL;
  1187. goto err_release;
  1188. }
  1189. if (init_size > priv->hw_params.max_inst_size) {
  1190. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1191. init_size);
  1192. ret = -EINVAL;
  1193. goto err_release;
  1194. }
  1195. if (init_data_size > priv->hw_params.max_data_size) {
  1196. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1197. init_data_size);
  1198. ret = -EINVAL;
  1199. goto err_release;
  1200. }
  1201. if (boot_size > priv->hw_params.max_bsm_size) {
  1202. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1203. boot_size);
  1204. ret = -EINVAL;
  1205. goto err_release;
  1206. }
  1207. /* Allocate ucode buffers for card's bus-master loading ... */
  1208. /* Runtime instructions and 2 copies of data:
  1209. * 1) unmodified from disk
  1210. * 2) backup cache for save/restore during power-downs */
  1211. priv->ucode_code.len = inst_size;
  1212. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1213. priv->ucode_data.len = data_size;
  1214. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1215. priv->ucode_data_backup.len = data_size;
  1216. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1217. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1218. !priv->ucode_data_backup.v_addr)
  1219. goto err_pci_alloc;
  1220. /* Initialization instructions and data */
  1221. if (init_size && init_data_size) {
  1222. priv->ucode_init.len = init_size;
  1223. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1224. priv->ucode_init_data.len = init_data_size;
  1225. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1226. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1227. goto err_pci_alloc;
  1228. }
  1229. /* Bootstrap (instructions only, no data) */
  1230. if (boot_size) {
  1231. priv->ucode_boot.len = boot_size;
  1232. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1233. if (!priv->ucode_boot.v_addr)
  1234. goto err_pci_alloc;
  1235. }
  1236. /* Copy images into buffers for card's bus-master reads ... */
  1237. /* Runtime instructions (first block of data in file) */
  1238. len = inst_size;
  1239. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1240. memcpy(priv->ucode_code.v_addr, src, len);
  1241. src += len;
  1242. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1243. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1244. /* Runtime data (2nd block)
  1245. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1246. len = data_size;
  1247. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1248. memcpy(priv->ucode_data.v_addr, src, len);
  1249. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1250. src += len;
  1251. /* Initialization instructions (3rd block) */
  1252. if (init_size) {
  1253. len = init_size;
  1254. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1255. len);
  1256. memcpy(priv->ucode_init.v_addr, src, len);
  1257. src += len;
  1258. }
  1259. /* Initialization data (4th block) */
  1260. if (init_data_size) {
  1261. len = init_data_size;
  1262. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1263. len);
  1264. memcpy(priv->ucode_init_data.v_addr, src, len);
  1265. src += len;
  1266. }
  1267. /* Bootstrap instructions (5th block) */
  1268. len = boot_size;
  1269. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1270. memcpy(priv->ucode_boot.v_addr, src, len);
  1271. /* We have our copies now, allow OS release its copies */
  1272. release_firmware(ucode_raw);
  1273. return 0;
  1274. err_pci_alloc:
  1275. IWL_ERR(priv, "failed to allocate pci memory\n");
  1276. ret = -ENOMEM;
  1277. iwl_dealloc_ucode_pci(priv);
  1278. err_release:
  1279. release_firmware(ucode_raw);
  1280. error:
  1281. return ret;
  1282. }
  1283. /**
  1284. * iwl_alive_start - called after REPLY_ALIVE notification received
  1285. * from protocol/runtime uCode (initialization uCode's
  1286. * Alive gets handled by iwl_init_alive_start()).
  1287. */
  1288. static void iwl_alive_start(struct iwl_priv *priv)
  1289. {
  1290. int ret = 0;
  1291. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1292. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1293. /* We had an error bringing up the hardware, so take it
  1294. * all the way back down so we can try again */
  1295. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1296. goto restart;
  1297. }
  1298. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1299. * This is a paranoid check, because we would not have gotten the
  1300. * "runtime" alive if code weren't properly loaded. */
  1301. if (iwl_verify_ucode(priv)) {
  1302. /* Runtime instruction load was bad;
  1303. * take it all the way back down so we can try again */
  1304. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1305. goto restart;
  1306. }
  1307. iwl_clear_stations_table(priv);
  1308. ret = priv->cfg->ops->lib->alive_notify(priv);
  1309. if (ret) {
  1310. IWL_WARN(priv,
  1311. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1312. goto restart;
  1313. }
  1314. /* After the ALIVE response, we can send host commands to the uCode */
  1315. set_bit(STATUS_ALIVE, &priv->status);
  1316. if (iwl_is_rfkill(priv))
  1317. return;
  1318. ieee80211_wake_queues(priv->hw);
  1319. priv->active_rate = priv->rates_mask;
  1320. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1321. if (iwl_is_associated(priv)) {
  1322. struct iwl_rxon_cmd *active_rxon =
  1323. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1324. /* apply any changes in staging */
  1325. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1326. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1327. } else {
  1328. /* Initialize our rx_config data */
  1329. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1330. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1331. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1332. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1333. }
  1334. /* Configure Bluetooth device coexistence support */
  1335. iwl_send_bt_config(priv);
  1336. iwl_reset_run_time_calib(priv);
  1337. /* Configure the adapter for unassociated operation */
  1338. iwlcore_commit_rxon(priv);
  1339. /* At this point, the NIC is initialized and operational */
  1340. iwl_rf_kill_ct_config(priv);
  1341. iwl_leds_register(priv);
  1342. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1343. set_bit(STATUS_READY, &priv->status);
  1344. wake_up_interruptible(&priv->wait_command_queue);
  1345. iwl_power_update_mode(priv, 1);
  1346. /* reassociate for ADHOC mode */
  1347. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1348. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1349. priv->vif);
  1350. if (beacon)
  1351. iwl_mac_beacon_update(priv->hw, beacon);
  1352. }
  1353. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1354. iwl_set_mode(priv, priv->iw_mode);
  1355. return;
  1356. restart:
  1357. queue_work(priv->workqueue, &priv->restart);
  1358. }
  1359. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1360. static void __iwl_down(struct iwl_priv *priv)
  1361. {
  1362. unsigned long flags;
  1363. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1364. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1365. if (!exit_pending)
  1366. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1367. iwl_leds_unregister(priv);
  1368. iwl_clear_stations_table(priv);
  1369. /* Unblock any waiting calls */
  1370. wake_up_interruptible_all(&priv->wait_command_queue);
  1371. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1372. * exiting the module */
  1373. if (!exit_pending)
  1374. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1375. /* stop and reset the on-board processor */
  1376. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1377. /* tell the device to stop sending interrupts */
  1378. spin_lock_irqsave(&priv->lock, flags);
  1379. iwl_disable_interrupts(priv);
  1380. spin_unlock_irqrestore(&priv->lock, flags);
  1381. iwl_synchronize_irq(priv);
  1382. if (priv->mac80211_registered)
  1383. ieee80211_stop_queues(priv->hw);
  1384. /* If we have not previously called iwl_init() then
  1385. * clear all bits but the RF Kill bit and return */
  1386. if (!iwl_is_init(priv)) {
  1387. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1388. STATUS_RF_KILL_HW |
  1389. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1390. STATUS_GEO_CONFIGURED |
  1391. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1392. STATUS_EXIT_PENDING;
  1393. goto exit;
  1394. }
  1395. /* ...otherwise clear out all the status bits but the RF Kill
  1396. * bit and continue taking the NIC down. */
  1397. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1398. STATUS_RF_KILL_HW |
  1399. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1400. STATUS_GEO_CONFIGURED |
  1401. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1402. STATUS_FW_ERROR |
  1403. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1404. STATUS_EXIT_PENDING;
  1405. /* device going down, Stop using ICT table */
  1406. iwl_disable_ict(priv);
  1407. spin_lock_irqsave(&priv->lock, flags);
  1408. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1409. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1410. spin_unlock_irqrestore(&priv->lock, flags);
  1411. iwl_txq_ctx_stop(priv);
  1412. iwl_rxq_stop(priv);
  1413. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1414. APMG_CLK_VAL_DMA_CLK_RQT);
  1415. udelay(5);
  1416. /* FIXME: apm_ops.suspend(priv) */
  1417. if (exit_pending)
  1418. priv->cfg->ops->lib->apm_ops.stop(priv);
  1419. else
  1420. priv->cfg->ops->lib->apm_ops.reset(priv);
  1421. exit:
  1422. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1423. if (priv->ibss_beacon)
  1424. dev_kfree_skb(priv->ibss_beacon);
  1425. priv->ibss_beacon = NULL;
  1426. /* clear out any free frames */
  1427. iwl_clear_free_frames(priv);
  1428. }
  1429. static void iwl_down(struct iwl_priv *priv)
  1430. {
  1431. mutex_lock(&priv->mutex);
  1432. __iwl_down(priv);
  1433. mutex_unlock(&priv->mutex);
  1434. iwl_cancel_deferred_work(priv);
  1435. }
  1436. #define HW_READY_TIMEOUT (50)
  1437. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1438. {
  1439. int ret = 0;
  1440. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1441. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1442. /* See if we got it */
  1443. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1444. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1445. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1446. HW_READY_TIMEOUT);
  1447. if (ret != -ETIMEDOUT)
  1448. priv->hw_ready = true;
  1449. else
  1450. priv->hw_ready = false;
  1451. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1452. (priv->hw_ready == 1) ? "ready" : "not ready");
  1453. return ret;
  1454. }
  1455. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1456. {
  1457. int ret = 0;
  1458. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1459. ret = iwl_set_hw_ready(priv);
  1460. if (priv->hw_ready)
  1461. return ret;
  1462. /* If HW is not ready, prepare the conditions to check again */
  1463. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1464. CSR_HW_IF_CONFIG_REG_PREPARE);
  1465. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1466. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1467. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1468. /* HW should be ready by now, check again. */
  1469. if (ret != -ETIMEDOUT)
  1470. iwl_set_hw_ready(priv);
  1471. return ret;
  1472. }
  1473. #define MAX_HW_RESTARTS 5
  1474. static int __iwl_up(struct iwl_priv *priv)
  1475. {
  1476. int i;
  1477. int ret;
  1478. unsigned long status;
  1479. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1480. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1481. return -EIO;
  1482. }
  1483. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1484. IWL_ERR(priv, "ucode not available for device bringup\n");
  1485. return -EIO;
  1486. }
  1487. iwl_prepare_card_hw(priv);
  1488. if (!priv->hw_ready) {
  1489. IWL_WARN(priv, "Exit HW not ready\n");
  1490. return -EIO;
  1491. }
  1492. /* If platform's RF_KILL switch is NOT set to KILL */
  1493. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1494. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1495. else
  1496. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1497. if (iwl_is_rfkill(priv)) {
  1498. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1499. iwl_enable_interrupts(priv);
  1500. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1501. return 0;
  1502. }
  1503. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1504. ret = iwl_hw_nic_init(priv);
  1505. if (ret) {
  1506. IWL_ERR(priv, "Unable to init nic\n");
  1507. return ret;
  1508. }
  1509. /* make sure rfkill handshake bits are cleared */
  1510. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1511. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1512. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1513. /* clear (again), then enable host interrupts */
  1514. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1515. iwl_enable_interrupts(priv);
  1516. /* really make sure rfkill handshake bits are cleared */
  1517. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1518. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1519. /* Copy original ucode data image from disk into backup cache.
  1520. * This will be used to initialize the on-board processor's
  1521. * data SRAM for a clean start when the runtime program first loads. */
  1522. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1523. priv->ucode_data.len);
  1524. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1525. iwl_clear_stations_table(priv);
  1526. /* load bootstrap state machine,
  1527. * load bootstrap program into processor's memory,
  1528. * prepare to load the "initialize" uCode */
  1529. ret = priv->cfg->ops->lib->load_ucode(priv);
  1530. if (ret) {
  1531. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1532. ret);
  1533. continue;
  1534. }
  1535. /* start card; "initialize" will load runtime ucode */
  1536. iwl_nic_start(priv);
  1537. /* Just finish download Init or Runtime uCode image to device
  1538. * now we wait here for uCode send REPLY_ALIVE notification
  1539. * to indicate uCode is ready.
  1540. * 1) For Init uCode image, all iwlagn devices should wait here
  1541. * on STATUS_INIT_UCODE_ALIVE status bit; if timeout before
  1542. * receive the REPLY_ALIVE notification, go back and try to
  1543. * download the Init uCode image again.
  1544. * 2) For Runtime uCode image, all iwlagn devices except 4965
  1545. * wait here on STATUS_RT_UCODE_ALIVE status bit; if
  1546. * timeout before receive the REPLY_ALIVE notification, go back
  1547. * and download the Runtime uCode image again.
  1548. * 3) For 4965 Runtime uCode, it will not go through this path,
  1549. * need to wait for STATUS_RT_UCODE_ALIVE status bit in
  1550. * iwl4965_init_alive_start() function; if timeout, need to
  1551. * restart and download Init uCode image.
  1552. */
  1553. if (priv->ucode_type == UCODE_INIT)
  1554. status = STATUS_INIT_UCODE_ALIVE;
  1555. else
  1556. status = STATUS_RT_UCODE_ALIVE;
  1557. if (test_bit(status, &priv->status)) {
  1558. IWL_WARN(priv,
  1559. "%s uCode already alive? "
  1560. "Waiting for alive anyway\n",
  1561. (status == STATUS_INIT_UCODE_ALIVE)
  1562. ? "INIT" : "Runtime");
  1563. clear_bit(status, &priv->status);
  1564. }
  1565. ret = wait_event_interruptible_timeout(
  1566. priv->wait_command_queue,
  1567. test_bit(status, &priv->status),
  1568. UCODE_ALIVE_TIMEOUT);
  1569. if (!ret) {
  1570. if (!test_bit(status, &priv->status)) {
  1571. priv->ucode_type =
  1572. (status == STATUS_INIT_UCODE_ALIVE)
  1573. ? UCODE_NONE : UCODE_INIT;
  1574. IWL_ERR(priv,
  1575. "%s timeout after %dms\n",
  1576. (status == STATUS_INIT_UCODE_ALIVE)
  1577. ? "INIT" : "Runtime",
  1578. jiffies_to_msecs(UCODE_ALIVE_TIMEOUT));
  1579. continue;
  1580. }
  1581. }
  1582. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1583. return 0;
  1584. }
  1585. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1586. __iwl_down(priv);
  1587. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1588. /* tried to restart and config the device for as long as our
  1589. * patience could withstand */
  1590. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1591. return -EIO;
  1592. }
  1593. /*****************************************************************************
  1594. *
  1595. * Workqueue callbacks
  1596. *
  1597. *****************************************************************************/
  1598. static void iwl_bg_init_alive_start(struct work_struct *data)
  1599. {
  1600. struct iwl_priv *priv =
  1601. container_of(data, struct iwl_priv, init_alive_start.work);
  1602. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1603. return;
  1604. mutex_lock(&priv->mutex);
  1605. priv->cfg->ops->lib->init_alive_start(priv);
  1606. mutex_unlock(&priv->mutex);
  1607. }
  1608. static void iwl_bg_alive_start(struct work_struct *data)
  1609. {
  1610. struct iwl_priv *priv =
  1611. container_of(data, struct iwl_priv, alive_start.work);
  1612. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1613. return;
  1614. /* enable dram interrupt */
  1615. iwl_reset_ict(priv);
  1616. mutex_lock(&priv->mutex);
  1617. iwl_alive_start(priv);
  1618. mutex_unlock(&priv->mutex);
  1619. }
  1620. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1621. {
  1622. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1623. run_time_calib_work);
  1624. mutex_lock(&priv->mutex);
  1625. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1626. test_bit(STATUS_SCANNING, &priv->status)) {
  1627. mutex_unlock(&priv->mutex);
  1628. return;
  1629. }
  1630. if (priv->start_calib) {
  1631. iwl_chain_noise_calibration(priv, &priv->statistics);
  1632. iwl_sensitivity_calibration(priv, &priv->statistics);
  1633. }
  1634. mutex_unlock(&priv->mutex);
  1635. return;
  1636. }
  1637. static void iwl_bg_up(struct work_struct *data)
  1638. {
  1639. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1640. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1641. return;
  1642. mutex_lock(&priv->mutex);
  1643. __iwl_up(priv);
  1644. mutex_unlock(&priv->mutex);
  1645. }
  1646. static void iwl_bg_restart(struct work_struct *data)
  1647. {
  1648. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1649. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1650. return;
  1651. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1652. mutex_lock(&priv->mutex);
  1653. priv->vif = NULL;
  1654. priv->is_open = 0;
  1655. mutex_unlock(&priv->mutex);
  1656. iwl_down(priv);
  1657. ieee80211_restart_hw(priv->hw);
  1658. } else {
  1659. iwl_down(priv);
  1660. queue_work(priv->workqueue, &priv->up);
  1661. }
  1662. }
  1663. static void iwl_bg_rx_replenish(struct work_struct *data)
  1664. {
  1665. struct iwl_priv *priv =
  1666. container_of(data, struct iwl_priv, rx_replenish);
  1667. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1668. return;
  1669. mutex_lock(&priv->mutex);
  1670. iwl_rx_replenish(priv);
  1671. mutex_unlock(&priv->mutex);
  1672. }
  1673. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1674. void iwl_post_associate(struct iwl_priv *priv)
  1675. {
  1676. struct ieee80211_conf *conf = NULL;
  1677. int ret = 0;
  1678. unsigned long flags;
  1679. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1680. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1681. return;
  1682. }
  1683. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1684. priv->assoc_id, priv->active_rxon.bssid_addr);
  1685. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1686. return;
  1687. if (!priv->vif || !priv->is_open)
  1688. return;
  1689. iwl_scan_cancel_timeout(priv, 200);
  1690. conf = ieee80211_get_hw_conf(priv->hw);
  1691. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1692. iwlcore_commit_rxon(priv);
  1693. iwl_setup_rxon_timing(priv);
  1694. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1695. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1696. if (ret)
  1697. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1698. "Attempting to continue.\n");
  1699. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1700. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1701. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1702. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1703. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1704. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1705. priv->assoc_id, priv->beacon_int);
  1706. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1707. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1708. else
  1709. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1710. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1711. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1712. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1713. else
  1714. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1715. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1716. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1717. }
  1718. iwlcore_commit_rxon(priv);
  1719. switch (priv->iw_mode) {
  1720. case NL80211_IFTYPE_STATION:
  1721. break;
  1722. case NL80211_IFTYPE_ADHOC:
  1723. /* assume default assoc id */
  1724. priv->assoc_id = 1;
  1725. iwl_rxon_add_station(priv, priv->bssid, 0);
  1726. iwl_send_beacon_cmd(priv);
  1727. break;
  1728. default:
  1729. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1730. __func__, priv->iw_mode);
  1731. break;
  1732. }
  1733. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1734. priv->assoc_station_added = 1;
  1735. spin_lock_irqsave(&priv->lock, flags);
  1736. iwl_activate_qos(priv, 0);
  1737. spin_unlock_irqrestore(&priv->lock, flags);
  1738. /* the chain noise calibration will enabled PM upon completion
  1739. * If chain noise has already been run, then we need to enable
  1740. * power management here */
  1741. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1742. iwl_power_update_mode(priv, 0);
  1743. /* Enable Rx differential gain and sensitivity calibrations */
  1744. iwl_chain_noise_reset(priv);
  1745. priv->start_calib = 1;
  1746. }
  1747. /*****************************************************************************
  1748. *
  1749. * mac80211 entry point functions
  1750. *
  1751. *****************************************************************************/
  1752. #define UCODE_READY_TIMEOUT (4 * HZ)
  1753. static int iwl_mac_start(struct ieee80211_hw *hw)
  1754. {
  1755. struct iwl_priv *priv = hw->priv;
  1756. int ret;
  1757. IWL_DEBUG_MAC80211(priv, "enter\n");
  1758. /* we should be verifying the device is ready to be opened */
  1759. mutex_lock(&priv->mutex);
  1760. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1761. * ucode filename and max sizes are card-specific. */
  1762. if (!priv->ucode_code.len) {
  1763. ret = iwl_read_ucode(priv);
  1764. if (ret) {
  1765. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1766. mutex_unlock(&priv->mutex);
  1767. return ret;
  1768. }
  1769. }
  1770. ret = __iwl_up(priv);
  1771. mutex_unlock(&priv->mutex);
  1772. if (ret)
  1773. return ret;
  1774. if (iwl_is_rfkill(priv))
  1775. goto out;
  1776. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1777. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1778. * mac80211 will not be run successfully. */
  1779. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1780. test_bit(STATUS_READY, &priv->status),
  1781. UCODE_READY_TIMEOUT);
  1782. if (!ret) {
  1783. if (!test_bit(STATUS_READY, &priv->status)) {
  1784. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1785. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1786. return -ETIMEDOUT;
  1787. }
  1788. }
  1789. out:
  1790. priv->is_open = 1;
  1791. IWL_DEBUG_MAC80211(priv, "leave\n");
  1792. return 0;
  1793. }
  1794. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1795. {
  1796. struct iwl_priv *priv = hw->priv;
  1797. IWL_DEBUG_MAC80211(priv, "enter\n");
  1798. if (!priv->is_open)
  1799. return;
  1800. priv->is_open = 0;
  1801. if (iwl_is_ready_rf(priv)) {
  1802. /* stop mac, cancel any scan request and clear
  1803. * RXON_FILTER_ASSOC_MSK BIT
  1804. */
  1805. mutex_lock(&priv->mutex);
  1806. iwl_scan_cancel_timeout(priv, 100);
  1807. mutex_unlock(&priv->mutex);
  1808. }
  1809. iwl_down(priv);
  1810. flush_workqueue(priv->workqueue);
  1811. /* enable interrupts again in order to receive rfkill changes */
  1812. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1813. iwl_enable_interrupts(priv);
  1814. IWL_DEBUG_MAC80211(priv, "leave\n");
  1815. }
  1816. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1817. {
  1818. struct iwl_priv *priv = hw->priv;
  1819. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1820. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1821. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1822. if (iwl_tx_skb(priv, skb))
  1823. dev_kfree_skb_any(skb);
  1824. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1825. return NETDEV_TX_OK;
  1826. }
  1827. void iwl_config_ap(struct iwl_priv *priv)
  1828. {
  1829. int ret = 0;
  1830. unsigned long flags;
  1831. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1832. return;
  1833. /* The following should be done only at AP bring up */
  1834. if (!iwl_is_associated(priv)) {
  1835. /* RXON - unassoc (to set timing command) */
  1836. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1837. iwlcore_commit_rxon(priv);
  1838. /* RXON Timing */
  1839. iwl_setup_rxon_timing(priv);
  1840. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1841. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1842. if (ret)
  1843. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1844. "Attempting to continue.\n");
  1845. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1846. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1847. /* FIXME: what should be the assoc_id for AP? */
  1848. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1849. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1850. priv->staging_rxon.flags |=
  1851. RXON_FLG_SHORT_PREAMBLE_MSK;
  1852. else
  1853. priv->staging_rxon.flags &=
  1854. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1855. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1856. if (priv->assoc_capability &
  1857. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1858. priv->staging_rxon.flags |=
  1859. RXON_FLG_SHORT_SLOT_MSK;
  1860. else
  1861. priv->staging_rxon.flags &=
  1862. ~RXON_FLG_SHORT_SLOT_MSK;
  1863. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1864. priv->staging_rxon.flags &=
  1865. ~RXON_FLG_SHORT_SLOT_MSK;
  1866. }
  1867. /* restore RXON assoc */
  1868. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1869. iwlcore_commit_rxon(priv);
  1870. spin_lock_irqsave(&priv->lock, flags);
  1871. iwl_activate_qos(priv, 1);
  1872. spin_unlock_irqrestore(&priv->lock, flags);
  1873. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1874. }
  1875. iwl_send_beacon_cmd(priv);
  1876. /* FIXME - we need to add code here to detect a totally new
  1877. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1878. * clear sta table, add BCAST sta... */
  1879. }
  1880. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1881. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1882. u32 iv32, u16 *phase1key)
  1883. {
  1884. struct iwl_priv *priv = hw->priv;
  1885. IWL_DEBUG_MAC80211(priv, "enter\n");
  1886. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1887. IWL_DEBUG_MAC80211(priv, "leave\n");
  1888. }
  1889. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1890. struct ieee80211_vif *vif,
  1891. struct ieee80211_sta *sta,
  1892. struct ieee80211_key_conf *key)
  1893. {
  1894. struct iwl_priv *priv = hw->priv;
  1895. const u8 *addr;
  1896. int ret;
  1897. u8 sta_id;
  1898. bool is_default_wep_key = false;
  1899. IWL_DEBUG_MAC80211(priv, "enter\n");
  1900. if (priv->cfg->mod_params->sw_crypto) {
  1901. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1902. return -EOPNOTSUPP;
  1903. }
  1904. addr = sta ? sta->addr : iwl_bcast_addr;
  1905. sta_id = iwl_find_station(priv, addr);
  1906. if (sta_id == IWL_INVALID_STATION) {
  1907. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1908. addr);
  1909. return -EINVAL;
  1910. }
  1911. mutex_lock(&priv->mutex);
  1912. iwl_scan_cancel_timeout(priv, 100);
  1913. mutex_unlock(&priv->mutex);
  1914. /* If we are getting WEP group key and we didn't receive any key mapping
  1915. * so far, we are in legacy wep mode (group key only), otherwise we are
  1916. * in 1X mode.
  1917. * In legacy wep mode, we use another host command to the uCode */
  1918. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1919. priv->iw_mode != NL80211_IFTYPE_AP) {
  1920. if (cmd == SET_KEY)
  1921. is_default_wep_key = !priv->key_mapping_key;
  1922. else
  1923. is_default_wep_key =
  1924. (key->hw_key_idx == HW_KEY_DEFAULT);
  1925. }
  1926. switch (cmd) {
  1927. case SET_KEY:
  1928. if (is_default_wep_key)
  1929. ret = iwl_set_default_wep_key(priv, key);
  1930. else
  1931. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1932. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1933. break;
  1934. case DISABLE_KEY:
  1935. if (is_default_wep_key)
  1936. ret = iwl_remove_default_wep_key(priv, key);
  1937. else
  1938. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1939. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1940. break;
  1941. default:
  1942. ret = -EINVAL;
  1943. }
  1944. IWL_DEBUG_MAC80211(priv, "leave\n");
  1945. return ret;
  1946. }
  1947. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1948. enum ieee80211_ampdu_mlme_action action,
  1949. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1950. {
  1951. struct iwl_priv *priv = hw->priv;
  1952. int ret;
  1953. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1954. sta->addr, tid);
  1955. if (!(priv->cfg->sku & IWL_SKU_N))
  1956. return -EACCES;
  1957. switch (action) {
  1958. case IEEE80211_AMPDU_RX_START:
  1959. IWL_DEBUG_HT(priv, "start Rx\n");
  1960. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1961. case IEEE80211_AMPDU_RX_STOP:
  1962. IWL_DEBUG_HT(priv, "stop Rx\n");
  1963. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1964. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1965. return 0;
  1966. else
  1967. return ret;
  1968. case IEEE80211_AMPDU_TX_START:
  1969. IWL_DEBUG_HT(priv, "start Tx\n");
  1970. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1971. case IEEE80211_AMPDU_TX_STOP:
  1972. IWL_DEBUG_HT(priv, "stop Tx\n");
  1973. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1974. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1975. return 0;
  1976. else
  1977. return ret;
  1978. default:
  1979. IWL_DEBUG_HT(priv, "unknown\n");
  1980. return -EINVAL;
  1981. break;
  1982. }
  1983. return 0;
  1984. }
  1985. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1986. struct ieee80211_low_level_stats *stats)
  1987. {
  1988. struct iwl_priv *priv = hw->priv;
  1989. priv = hw->priv;
  1990. IWL_DEBUG_MAC80211(priv, "enter\n");
  1991. IWL_DEBUG_MAC80211(priv, "leave\n");
  1992. return 0;
  1993. }
  1994. /*****************************************************************************
  1995. *
  1996. * sysfs attributes
  1997. *
  1998. *****************************************************************************/
  1999. #ifdef CONFIG_IWLWIFI_DEBUG
  2000. /*
  2001. * The following adds a new attribute to the sysfs representation
  2002. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2003. * used for controlling the debug level.
  2004. *
  2005. * See the level definitions in iwl for details.
  2006. *
  2007. * FIXME This file can be deprecated as the module parameter is
  2008. * writable and users can thus also change the debug level
  2009. * using the /sys/module/iwl3945/parameters/debug file.
  2010. */
  2011. static ssize_t show_debug_level(struct device *d,
  2012. struct device_attribute *attr, char *buf)
  2013. {
  2014. return sprintf(buf, "0x%08X\n", iwl_debug_level);
  2015. }
  2016. static ssize_t store_debug_level(struct device *d,
  2017. struct device_attribute *attr,
  2018. const char *buf, size_t count)
  2019. {
  2020. struct iwl_priv *priv = dev_get_drvdata(d);
  2021. unsigned long val;
  2022. int ret;
  2023. ret = strict_strtoul(buf, 0, &val);
  2024. if (ret)
  2025. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2026. else
  2027. iwl_debug_level = val;
  2028. return strnlen(buf, count);
  2029. }
  2030. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2031. show_debug_level, store_debug_level);
  2032. #endif /* CONFIG_IWLWIFI_DEBUG */
  2033. static ssize_t show_temperature(struct device *d,
  2034. struct device_attribute *attr, char *buf)
  2035. {
  2036. struct iwl_priv *priv = dev_get_drvdata(d);
  2037. if (!iwl_is_alive(priv))
  2038. return -EAGAIN;
  2039. return sprintf(buf, "%d\n", priv->temperature);
  2040. }
  2041. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2042. static ssize_t show_tx_power(struct device *d,
  2043. struct device_attribute *attr, char *buf)
  2044. {
  2045. struct iwl_priv *priv = dev_get_drvdata(d);
  2046. if (!iwl_is_ready_rf(priv))
  2047. return sprintf(buf, "off\n");
  2048. else
  2049. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2050. }
  2051. static ssize_t store_tx_power(struct device *d,
  2052. struct device_attribute *attr,
  2053. const char *buf, size_t count)
  2054. {
  2055. struct iwl_priv *priv = dev_get_drvdata(d);
  2056. unsigned long val;
  2057. int ret;
  2058. ret = strict_strtoul(buf, 10, &val);
  2059. if (ret)
  2060. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2061. else
  2062. iwl_set_tx_power(priv, val, false);
  2063. return count;
  2064. }
  2065. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2066. static ssize_t show_flags(struct device *d,
  2067. struct device_attribute *attr, char *buf)
  2068. {
  2069. struct iwl_priv *priv = dev_get_drvdata(d);
  2070. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2071. }
  2072. static ssize_t store_flags(struct device *d,
  2073. struct device_attribute *attr,
  2074. const char *buf, size_t count)
  2075. {
  2076. struct iwl_priv *priv = dev_get_drvdata(d);
  2077. unsigned long val;
  2078. u32 flags;
  2079. int ret = strict_strtoul(buf, 0, &val);
  2080. if (ret)
  2081. return ret;
  2082. flags = (u32)val;
  2083. mutex_lock(&priv->mutex);
  2084. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2085. /* Cancel any currently running scans... */
  2086. if (iwl_scan_cancel_timeout(priv, 100))
  2087. IWL_WARN(priv, "Could not cancel scan.\n");
  2088. else {
  2089. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2090. priv->staging_rxon.flags = cpu_to_le32(flags);
  2091. iwlcore_commit_rxon(priv);
  2092. }
  2093. }
  2094. mutex_unlock(&priv->mutex);
  2095. return count;
  2096. }
  2097. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2098. static ssize_t show_filter_flags(struct device *d,
  2099. struct device_attribute *attr, char *buf)
  2100. {
  2101. struct iwl_priv *priv = dev_get_drvdata(d);
  2102. return sprintf(buf, "0x%04X\n",
  2103. le32_to_cpu(priv->active_rxon.filter_flags));
  2104. }
  2105. static ssize_t store_filter_flags(struct device *d,
  2106. struct device_attribute *attr,
  2107. const char *buf, size_t count)
  2108. {
  2109. struct iwl_priv *priv = dev_get_drvdata(d);
  2110. unsigned long val;
  2111. u32 filter_flags;
  2112. int ret = strict_strtoul(buf, 0, &val);
  2113. if (ret)
  2114. return ret;
  2115. filter_flags = (u32)val;
  2116. mutex_lock(&priv->mutex);
  2117. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2118. /* Cancel any currently running scans... */
  2119. if (iwl_scan_cancel_timeout(priv, 100))
  2120. IWL_WARN(priv, "Could not cancel scan.\n");
  2121. else {
  2122. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2123. "0x%04X\n", filter_flags);
  2124. priv->staging_rxon.filter_flags =
  2125. cpu_to_le32(filter_flags);
  2126. iwlcore_commit_rxon(priv);
  2127. }
  2128. }
  2129. mutex_unlock(&priv->mutex);
  2130. return count;
  2131. }
  2132. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2133. store_filter_flags);
  2134. static ssize_t store_power_level(struct device *d,
  2135. struct device_attribute *attr,
  2136. const char *buf, size_t count)
  2137. {
  2138. struct iwl_priv *priv = dev_get_drvdata(d);
  2139. int ret;
  2140. unsigned long mode;
  2141. mutex_lock(&priv->mutex);
  2142. ret = strict_strtoul(buf, 10, &mode);
  2143. if (ret)
  2144. goto out;
  2145. ret = iwl_power_set_user_mode(priv, mode);
  2146. if (ret) {
  2147. IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
  2148. goto out;
  2149. }
  2150. ret = count;
  2151. out:
  2152. mutex_unlock(&priv->mutex);
  2153. return ret;
  2154. }
  2155. static ssize_t show_power_level(struct device *d,
  2156. struct device_attribute *attr, char *buf)
  2157. {
  2158. struct iwl_priv *priv = dev_get_drvdata(d);
  2159. int level = priv->power_data.power_mode;
  2160. char *p = buf;
  2161. p += sprintf(p, "%d\n", level);
  2162. return p - buf + 1;
  2163. }
  2164. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  2165. store_power_level);
  2166. static ssize_t show_statistics(struct device *d,
  2167. struct device_attribute *attr, char *buf)
  2168. {
  2169. struct iwl_priv *priv = dev_get_drvdata(d);
  2170. u32 size = sizeof(struct iwl_notif_statistics);
  2171. u32 len = 0, ofs = 0;
  2172. u8 *data = (u8 *)&priv->statistics;
  2173. int rc = 0;
  2174. if (!iwl_is_alive(priv))
  2175. return -EAGAIN;
  2176. mutex_lock(&priv->mutex);
  2177. rc = iwl_send_statistics_request(priv, 0);
  2178. mutex_unlock(&priv->mutex);
  2179. if (rc) {
  2180. len = sprintf(buf,
  2181. "Error sending statistics request: 0x%08X\n", rc);
  2182. return len;
  2183. }
  2184. while (size && (PAGE_SIZE - len)) {
  2185. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2186. PAGE_SIZE - len, 1);
  2187. len = strlen(buf);
  2188. if (PAGE_SIZE - len)
  2189. buf[len++] = '\n';
  2190. ofs += 16;
  2191. size -= min(size, 16U);
  2192. }
  2193. return len;
  2194. }
  2195. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2196. /*****************************************************************************
  2197. *
  2198. * driver setup and teardown
  2199. *
  2200. *****************************************************************************/
  2201. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2202. {
  2203. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2204. init_waitqueue_head(&priv->wait_command_queue);
  2205. INIT_WORK(&priv->up, iwl_bg_up);
  2206. INIT_WORK(&priv->restart, iwl_bg_restart);
  2207. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2208. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2209. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2210. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2211. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2212. iwl_setup_scan_deferred_work(priv);
  2213. if (priv->cfg->ops->lib->setup_deferred_work)
  2214. priv->cfg->ops->lib->setup_deferred_work(priv);
  2215. init_timer(&priv->statistics_periodic);
  2216. priv->statistics_periodic.data = (unsigned long)priv;
  2217. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2218. if (!priv->cfg->use_isr_legacy)
  2219. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2220. iwl_irq_tasklet, (unsigned long)priv);
  2221. else
  2222. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2223. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2224. }
  2225. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2226. {
  2227. if (priv->cfg->ops->lib->cancel_deferred_work)
  2228. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2229. cancel_delayed_work_sync(&priv->init_alive_start);
  2230. cancel_delayed_work(&priv->scan_check);
  2231. cancel_delayed_work(&priv->alive_start);
  2232. cancel_work_sync(&priv->beacon_update);
  2233. del_timer_sync(&priv->statistics_periodic);
  2234. }
  2235. static struct attribute *iwl_sysfs_entries[] = {
  2236. &dev_attr_flags.attr,
  2237. &dev_attr_filter_flags.attr,
  2238. &dev_attr_power_level.attr,
  2239. &dev_attr_statistics.attr,
  2240. &dev_attr_temperature.attr,
  2241. &dev_attr_tx_power.attr,
  2242. #ifdef CONFIG_IWLWIFI_DEBUG
  2243. &dev_attr_debug_level.attr,
  2244. #endif
  2245. NULL
  2246. };
  2247. static struct attribute_group iwl_attribute_group = {
  2248. .name = NULL, /* put in device directory */
  2249. .attrs = iwl_sysfs_entries,
  2250. };
  2251. static struct ieee80211_ops iwl_hw_ops = {
  2252. .tx = iwl_mac_tx,
  2253. .start = iwl_mac_start,
  2254. .stop = iwl_mac_stop,
  2255. .add_interface = iwl_mac_add_interface,
  2256. .remove_interface = iwl_mac_remove_interface,
  2257. .config = iwl_mac_config,
  2258. .configure_filter = iwl_configure_filter,
  2259. .set_key = iwl_mac_set_key,
  2260. .update_tkip_key = iwl_mac_update_tkip_key,
  2261. .get_stats = iwl_mac_get_stats,
  2262. .get_tx_stats = iwl_mac_get_tx_stats,
  2263. .conf_tx = iwl_mac_conf_tx,
  2264. .reset_tsf = iwl_mac_reset_tsf,
  2265. .bss_info_changed = iwl_bss_info_changed,
  2266. .ampdu_action = iwl_mac_ampdu_action,
  2267. .hw_scan = iwl_mac_hw_scan
  2268. };
  2269. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2270. {
  2271. int err = 0;
  2272. struct iwl_priv *priv;
  2273. struct ieee80211_hw *hw;
  2274. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2275. unsigned long flags;
  2276. u16 pci_cmd;
  2277. /************************
  2278. * 1. Allocating HW data
  2279. ************************/
  2280. /* Disabling hardware scan means that mac80211 will perform scans
  2281. * "the hard way", rather than using device's scan. */
  2282. if (cfg->mod_params->disable_hw_scan) {
  2283. if (iwl_debug_level & IWL_DL_INFO)
  2284. dev_printk(KERN_DEBUG, &(pdev->dev),
  2285. "Disabling hw_scan\n");
  2286. iwl_hw_ops.hw_scan = NULL;
  2287. }
  2288. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2289. if (!hw) {
  2290. err = -ENOMEM;
  2291. goto out;
  2292. }
  2293. priv = hw->priv;
  2294. /* At this point both hw and priv are allocated. */
  2295. SET_IEEE80211_DEV(hw, &pdev->dev);
  2296. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2297. priv->cfg = cfg;
  2298. priv->pci_dev = pdev;
  2299. priv->inta_mask = CSR_INI_SET_MASK;
  2300. #ifdef CONFIG_IWLWIFI_DEBUG
  2301. atomic_set(&priv->restrict_refcnt, 0);
  2302. #endif
  2303. /**************************
  2304. * 2. Initializing PCI bus
  2305. **************************/
  2306. if (pci_enable_device(pdev)) {
  2307. err = -ENODEV;
  2308. goto out_ieee80211_free_hw;
  2309. }
  2310. pci_set_master(pdev);
  2311. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2312. if (!err)
  2313. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2314. if (err) {
  2315. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2316. if (!err)
  2317. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2318. /* both attempts failed: */
  2319. if (err) {
  2320. IWL_WARN(priv, "No suitable DMA available.\n");
  2321. goto out_pci_disable_device;
  2322. }
  2323. }
  2324. err = pci_request_regions(pdev, DRV_NAME);
  2325. if (err)
  2326. goto out_pci_disable_device;
  2327. pci_set_drvdata(pdev, priv);
  2328. /***********************
  2329. * 3. Read REV register
  2330. ***********************/
  2331. priv->hw_base = pci_iomap(pdev, 0, 0);
  2332. if (!priv->hw_base) {
  2333. err = -ENODEV;
  2334. goto out_pci_release_regions;
  2335. }
  2336. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2337. (unsigned long long) pci_resource_len(pdev, 0));
  2338. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2339. /* this spin lock will be used in apm_ops.init and EEPROM access
  2340. * we should init now
  2341. */
  2342. spin_lock_init(&priv->reg_lock);
  2343. iwl_hw_detect(priv);
  2344. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2345. priv->cfg->name, priv->hw_rev);
  2346. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2347. * PCI Tx retries from interfering with C3 CPU state */
  2348. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2349. iwl_prepare_card_hw(priv);
  2350. if (!priv->hw_ready) {
  2351. IWL_WARN(priv, "Failed, HW not ready\n");
  2352. goto out_iounmap;
  2353. }
  2354. /* amp init */
  2355. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2356. if (err < 0) {
  2357. IWL_ERR(priv, "Failed to init APMG\n");
  2358. goto out_iounmap;
  2359. }
  2360. /*****************
  2361. * 4. Read EEPROM
  2362. *****************/
  2363. /* Read the EEPROM */
  2364. err = iwl_eeprom_init(priv);
  2365. if (err) {
  2366. IWL_ERR(priv, "Unable to init EEPROM\n");
  2367. goto out_iounmap;
  2368. }
  2369. err = iwl_eeprom_check_version(priv);
  2370. if (err)
  2371. goto out_free_eeprom;
  2372. /* extract MAC Address */
  2373. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2374. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2375. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2376. /************************
  2377. * 5. Setup HW constants
  2378. ************************/
  2379. if (iwl_set_hw_params(priv)) {
  2380. IWL_ERR(priv, "failed to set hw parameters\n");
  2381. goto out_free_eeprom;
  2382. }
  2383. /*******************
  2384. * 6. Setup priv
  2385. *******************/
  2386. err = iwl_init_drv(priv);
  2387. if (err)
  2388. goto out_free_eeprom;
  2389. /* At this point both hw and priv are initialized. */
  2390. /********************
  2391. * 7. Setup services
  2392. ********************/
  2393. spin_lock_irqsave(&priv->lock, flags);
  2394. iwl_disable_interrupts(priv);
  2395. spin_unlock_irqrestore(&priv->lock, flags);
  2396. pci_enable_msi(priv->pci_dev);
  2397. iwl_alloc_isr_ict(priv);
  2398. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2399. IRQF_SHARED, DRV_NAME, priv);
  2400. if (err) {
  2401. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2402. goto out_disable_msi;
  2403. }
  2404. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2405. if (err) {
  2406. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2407. goto out_free_irq;
  2408. }
  2409. iwl_setup_deferred_work(priv);
  2410. iwl_setup_rx_handlers(priv);
  2411. /**********************************
  2412. * 8. Setup and register mac80211
  2413. **********************************/
  2414. /* enable interrupts if needed: hw bug w/a */
  2415. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2416. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2417. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2418. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2419. }
  2420. iwl_enable_interrupts(priv);
  2421. err = iwl_setup_mac(priv);
  2422. if (err)
  2423. goto out_remove_sysfs;
  2424. err = iwl_dbgfs_register(priv, DRV_NAME);
  2425. if (err)
  2426. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2427. /* If platform's RF_KILL switch is NOT set to KILL */
  2428. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2429. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2430. else
  2431. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2432. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2433. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2434. iwl_power_initialize(priv);
  2435. iwl_tt_initialize(priv);
  2436. return 0;
  2437. out_remove_sysfs:
  2438. destroy_workqueue(priv->workqueue);
  2439. priv->workqueue = NULL;
  2440. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2441. out_free_irq:
  2442. free_irq(priv->pci_dev->irq, priv);
  2443. iwl_free_isr_ict(priv);
  2444. out_disable_msi:
  2445. pci_disable_msi(priv->pci_dev);
  2446. iwl_uninit_drv(priv);
  2447. out_free_eeprom:
  2448. iwl_eeprom_free(priv);
  2449. out_iounmap:
  2450. pci_iounmap(pdev, priv->hw_base);
  2451. out_pci_release_regions:
  2452. pci_set_drvdata(pdev, NULL);
  2453. pci_release_regions(pdev);
  2454. out_pci_disable_device:
  2455. pci_disable_device(pdev);
  2456. out_ieee80211_free_hw:
  2457. ieee80211_free_hw(priv->hw);
  2458. out:
  2459. return err;
  2460. }
  2461. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2462. {
  2463. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2464. unsigned long flags;
  2465. if (!priv)
  2466. return;
  2467. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2468. iwl_dbgfs_unregister(priv);
  2469. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2470. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2471. * to be called and iwl_down since we are removing the device
  2472. * we need to set STATUS_EXIT_PENDING bit.
  2473. */
  2474. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2475. if (priv->mac80211_registered) {
  2476. ieee80211_unregister_hw(priv->hw);
  2477. priv->mac80211_registered = 0;
  2478. } else {
  2479. iwl_down(priv);
  2480. }
  2481. iwl_tt_exit(priv);
  2482. /* make sure we flush any pending irq or
  2483. * tasklet for the driver
  2484. */
  2485. spin_lock_irqsave(&priv->lock, flags);
  2486. iwl_disable_interrupts(priv);
  2487. spin_unlock_irqrestore(&priv->lock, flags);
  2488. iwl_synchronize_irq(priv);
  2489. iwl_dealloc_ucode_pci(priv);
  2490. if (priv->rxq.bd)
  2491. iwl_rx_queue_free(priv, &priv->rxq);
  2492. iwl_hw_txq_ctx_free(priv);
  2493. iwl_clear_stations_table(priv);
  2494. iwl_eeprom_free(priv);
  2495. /*netif_stop_queue(dev); */
  2496. flush_workqueue(priv->workqueue);
  2497. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2498. * priv->workqueue... so we can't take down the workqueue
  2499. * until now... */
  2500. destroy_workqueue(priv->workqueue);
  2501. priv->workqueue = NULL;
  2502. free_irq(priv->pci_dev->irq, priv);
  2503. pci_disable_msi(priv->pci_dev);
  2504. pci_iounmap(pdev, priv->hw_base);
  2505. pci_release_regions(pdev);
  2506. pci_disable_device(pdev);
  2507. pci_set_drvdata(pdev, NULL);
  2508. iwl_uninit_drv(priv);
  2509. iwl_free_isr_ict(priv);
  2510. if (priv->ibss_beacon)
  2511. dev_kfree_skb(priv->ibss_beacon);
  2512. ieee80211_free_hw(priv->hw);
  2513. }
  2514. /*****************************************************************************
  2515. *
  2516. * driver and module entry point
  2517. *
  2518. *****************************************************************************/
  2519. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2520. static struct pci_device_id iwl_hw_card_ids[] = {
  2521. #ifdef CONFIG_IWL4965
  2522. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2523. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2524. #endif /* CONFIG_IWL4965 */
  2525. #ifdef CONFIG_IWL5000
  2526. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2527. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2528. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2529. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2530. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2531. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2532. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2533. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2534. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2535. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2536. /* 5350 WiFi/WiMax */
  2537. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2538. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2539. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2540. /* 5150 Wifi/WiMax */
  2541. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2542. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2543. /* 6000/6050 Series */
  2544. {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2545. {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2546. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2547. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2548. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2549. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2550. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2551. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2552. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2553. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2554. /* 1000 Series WiFi */
  2555. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2556. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2557. #endif /* CONFIG_IWL5000 */
  2558. {0}
  2559. };
  2560. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2561. static struct pci_driver iwl_driver = {
  2562. .name = DRV_NAME,
  2563. .id_table = iwl_hw_card_ids,
  2564. .probe = iwl_pci_probe,
  2565. .remove = __devexit_p(iwl_pci_remove),
  2566. #ifdef CONFIG_PM
  2567. .suspend = iwl_pci_suspend,
  2568. .resume = iwl_pci_resume,
  2569. #endif
  2570. };
  2571. static int __init iwl_init(void)
  2572. {
  2573. int ret;
  2574. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2575. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2576. ret = iwlagn_rate_control_register();
  2577. if (ret) {
  2578. printk(KERN_ERR DRV_NAME
  2579. "Unable to register rate control algorithm: %d\n", ret);
  2580. return ret;
  2581. }
  2582. ret = pci_register_driver(&iwl_driver);
  2583. if (ret) {
  2584. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2585. goto error_register;
  2586. }
  2587. return ret;
  2588. error_register:
  2589. iwlagn_rate_control_unregister();
  2590. return ret;
  2591. }
  2592. static void __exit iwl_exit(void)
  2593. {
  2594. pci_unregister_driver(&iwl_driver);
  2595. iwlagn_rate_control_unregister();
  2596. }
  2597. module_exit(iwl_exit);
  2598. module_init(iwl_init);
  2599. #ifdef CONFIG_IWLWIFI_DEBUG
  2600. module_param_named(debug50, iwl_debug_level, uint, 0444);
  2601. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2602. module_param_named(debug, iwl_debug_level, uint, 0644);
  2603. MODULE_PARM_DESC(debug, "debug output mask");
  2604. #endif