recv.c 24 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "ath9k.h"
  17. static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
  18. struct ieee80211_hdr *hdr)
  19. {
  20. struct ieee80211_hw *hw = sc->pri_wiphy->hw;
  21. int i;
  22. spin_lock_bh(&sc->wiphy_lock);
  23. for (i = 0; i < sc->num_sec_wiphy; i++) {
  24. struct ath_wiphy *aphy = sc->sec_wiphy[i];
  25. if (aphy == NULL)
  26. continue;
  27. if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
  28. == 0) {
  29. hw = aphy->hw;
  30. break;
  31. }
  32. }
  33. spin_unlock_bh(&sc->wiphy_lock);
  34. return hw;
  35. }
  36. /*
  37. * Setup and link descriptors.
  38. *
  39. * 11N: we can no longer afford to self link the last descriptor.
  40. * MAC acknowledges BA status as long as it copies frames to host
  41. * buffer (or rx fifo). This can incorrectly acknowledge packets
  42. * to a sender if last desc is self-linked.
  43. */
  44. static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  45. {
  46. struct ath_hw *ah = sc->sc_ah;
  47. struct ath_desc *ds;
  48. struct sk_buff *skb;
  49. ATH_RXBUF_RESET(bf);
  50. ds = bf->bf_desc;
  51. ds->ds_link = 0; /* link to null */
  52. ds->ds_data = bf->bf_buf_addr;
  53. /* virtual addr of the beginning of the buffer. */
  54. skb = bf->bf_mpdu;
  55. ASSERT(skb != NULL);
  56. ds->ds_vdata = skb->data;
  57. /* setup rx descriptors. The rx.bufsize here tells the harware
  58. * how much data it can DMA to us and that we are prepared
  59. * to process */
  60. ath9k_hw_setuprxdesc(ah, ds,
  61. sc->rx.bufsize,
  62. 0);
  63. if (sc->rx.rxlink == NULL)
  64. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  65. else
  66. *sc->rx.rxlink = bf->bf_daddr;
  67. sc->rx.rxlink = &ds->ds_link;
  68. ath9k_hw_rxena(ah);
  69. }
  70. static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  71. {
  72. /* XXX block beacon interrupts */
  73. ath9k_hw_setantenna(sc->sc_ah, antenna);
  74. sc->rx.defant = antenna;
  75. sc->rx.rxotherant = 0;
  76. }
  77. /*
  78. * Extend 15-bit time stamp from rx descriptor to
  79. * a full 64-bit TSF using the current h/w TSF.
  80. */
  81. static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
  82. {
  83. u64 tsf;
  84. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  85. if ((tsf & 0x7fff) < rstamp)
  86. tsf -= 0x8000;
  87. return (tsf & ~0x7fff) | rstamp;
  88. }
  89. static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len, gfp_t gfp_mask)
  90. {
  91. struct sk_buff *skb;
  92. u32 off;
  93. /*
  94. * Cache-line-align. This is important (for the
  95. * 5210 at least) as not doing so causes bogus data
  96. * in rx'd frames.
  97. */
  98. /* Note: the kernel can allocate a value greater than
  99. * what we ask it to give us. We really only need 4 KB as that
  100. * is this hardware supports and in fact we need at least 3849
  101. * as that is the MAX AMSDU size this hardware supports.
  102. * Unfortunately this means we may get 8 KB here from the
  103. * kernel... and that is actually what is observed on some
  104. * systems :( */
  105. skb = __dev_alloc_skb(len + sc->cachelsz - 1, gfp_mask);
  106. if (skb != NULL) {
  107. off = ((unsigned long) skb->data) % sc->cachelsz;
  108. if (off != 0)
  109. skb_reserve(skb, sc->cachelsz - off);
  110. } else {
  111. DPRINTF(sc, ATH_DBG_FATAL,
  112. "skbuff alloc of size %u failed\n", len);
  113. return NULL;
  114. }
  115. return skb;
  116. }
  117. /*
  118. * For Decrypt or Demic errors, we only mark packet status here and always push
  119. * up the frame up to let mac80211 handle the actual error case, be it no
  120. * decryption key or real decryption error. This let us keep statistics there.
  121. */
  122. static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
  123. struct ieee80211_rx_status *rx_status, bool *decrypt_error,
  124. struct ath_softc *sc)
  125. {
  126. struct ieee80211_hdr *hdr;
  127. u8 ratecode;
  128. __le16 fc;
  129. struct ieee80211_hw *hw;
  130. struct ieee80211_sta *sta;
  131. struct ath_node *an;
  132. int last_rssi = ATH_RSSI_DUMMY_MARKER;
  133. hdr = (struct ieee80211_hdr *)skb->data;
  134. fc = hdr->frame_control;
  135. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  136. hw = ath_get_virt_hw(sc, hdr);
  137. if (ds->ds_rxstat.rs_more) {
  138. /*
  139. * Frame spans multiple descriptors; this cannot happen yet
  140. * as we don't support jumbograms. If not in monitor mode,
  141. * discard the frame. Enable this if you want to see
  142. * error frames in Monitor mode.
  143. */
  144. if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR)
  145. goto rx_next;
  146. } else if (ds->ds_rxstat.rs_status != 0) {
  147. if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
  148. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  149. if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY)
  150. goto rx_next;
  151. if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
  152. *decrypt_error = true;
  153. } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
  154. if (ieee80211_is_ctl(fc))
  155. /*
  156. * Sometimes, we get invalid
  157. * MIC failures on valid control frames.
  158. * Remove these mic errors.
  159. */
  160. ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC;
  161. else
  162. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  163. }
  164. /*
  165. * Reject error frames with the exception of
  166. * decryption and MIC failures. For monitor mode,
  167. * we also ignore the CRC error.
  168. */
  169. if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) {
  170. if (ds->ds_rxstat.rs_status &
  171. ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
  172. ATH9K_RXERR_CRC))
  173. goto rx_next;
  174. } else {
  175. if (ds->ds_rxstat.rs_status &
  176. ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
  177. goto rx_next;
  178. }
  179. }
  180. }
  181. ratecode = ds->ds_rxstat.rs_rate;
  182. if (ratecode & 0x80) {
  183. /* HT rate */
  184. rx_status->flag |= RX_FLAG_HT;
  185. if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040)
  186. rx_status->flag |= RX_FLAG_40MHZ;
  187. if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
  188. rx_status->flag |= RX_FLAG_SHORT_GI;
  189. rx_status->rate_idx = ratecode & 0x7f;
  190. } else {
  191. int i = 0, cur_band, n_rates;
  192. cur_band = hw->conf.channel->band;
  193. n_rates = sc->sbands[cur_band].n_bitrates;
  194. for (i = 0; i < n_rates; i++) {
  195. if (sc->sbands[cur_band].bitrates[i].hw_value ==
  196. ratecode) {
  197. rx_status->rate_idx = i;
  198. break;
  199. }
  200. if (sc->sbands[cur_band].bitrates[i].hw_value_short ==
  201. ratecode) {
  202. rx_status->rate_idx = i;
  203. rx_status->flag |= RX_FLAG_SHORTPRE;
  204. break;
  205. }
  206. }
  207. }
  208. rcu_read_lock();
  209. sta = ieee80211_find_sta(sc->hw, hdr->addr2);
  210. if (sta) {
  211. an = (struct ath_node *) sta->drv_priv;
  212. if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD &&
  213. !ds->ds_rxstat.rs_moreaggr)
  214. ATH_RSSI_LPF(an->last_rssi, ds->ds_rxstat.rs_rssi);
  215. last_rssi = an->last_rssi;
  216. }
  217. rcu_read_unlock();
  218. if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
  219. ds->ds_rxstat.rs_rssi = ATH_EP_RND(last_rssi,
  220. ATH_RSSI_EP_MULTIPLIER);
  221. if (ds->ds_rxstat.rs_rssi < 0)
  222. ds->ds_rxstat.rs_rssi = 0;
  223. else if (ds->ds_rxstat.rs_rssi > 127)
  224. ds->ds_rxstat.rs_rssi = 127;
  225. /* Update Beacon RSSI, this is used by ANI. */
  226. if (ieee80211_is_beacon(fc))
  227. sc->nodestats.ns_avgbrssi = ds->ds_rxstat.rs_rssi;
  228. rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
  229. rx_status->band = hw->conf.channel->band;
  230. rx_status->freq = hw->conf.channel->center_freq;
  231. rx_status->noise = sc->ani.noise_floor;
  232. rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + ds->ds_rxstat.rs_rssi;
  233. rx_status->antenna = ds->ds_rxstat.rs_antenna;
  234. /*
  235. * Theory for reporting quality:
  236. *
  237. * At a hardware RSSI of 45 you will be able to use MCS 7 reliably.
  238. * At a hardware RSSI of 45 you will be able to use MCS 15 reliably.
  239. * At a hardware RSSI of 35 you should be able use 54 Mbps reliably.
  240. *
  241. * MCS 7 is the highets MCS index usable by a 1-stream device.
  242. * MCS 15 is the highest MCS index usable by a 2-stream device.
  243. *
  244. * All ath9k devices are either 1-stream or 2-stream.
  245. *
  246. * How many bars you see is derived from the qual reporting.
  247. *
  248. * A more elaborate scheme can be used here but it requires tables
  249. * of SNR/throughput for each possible mode used. For the MCS table
  250. * you can refer to the wireless wiki:
  251. *
  252. * http://wireless.kernel.org/en/developers/Documentation/ieee80211/802.11n
  253. *
  254. */
  255. if (conf_is_ht(&hw->conf))
  256. rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45;
  257. else
  258. rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 35;
  259. /* rssi can be more than 45 though, anything above that
  260. * should be considered at 100% */
  261. if (rx_status->qual > 100)
  262. rx_status->qual = 100;
  263. rx_status->flag |= RX_FLAG_TSFT;
  264. return 1;
  265. rx_next:
  266. return 0;
  267. }
  268. static void ath_opmode_init(struct ath_softc *sc)
  269. {
  270. struct ath_hw *ah = sc->sc_ah;
  271. u32 rfilt, mfilt[2];
  272. /* configure rx filter */
  273. rfilt = ath_calcrxfilter(sc);
  274. ath9k_hw_setrxfilter(ah, rfilt);
  275. /* configure bssid mask */
  276. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  277. ath9k_hw_setbssidmask(sc);
  278. /* configure operational mode */
  279. ath9k_hw_setopmode(ah);
  280. /* Handle any link-level address change. */
  281. ath9k_hw_setmac(ah, sc->sc_ah->macaddr);
  282. /* calculate and install multicast filter */
  283. mfilt[0] = mfilt[1] = ~0;
  284. ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
  285. }
  286. int ath_rx_init(struct ath_softc *sc, int nbufs)
  287. {
  288. struct sk_buff *skb;
  289. struct ath_buf *bf;
  290. int error = 0;
  291. spin_lock_init(&sc->rx.rxflushlock);
  292. sc->sc_flags &= ~SC_OP_RXFLUSH;
  293. spin_lock_init(&sc->rx.rxbuflock);
  294. sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
  295. min(sc->cachelsz, (u16)64));
  296. DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
  297. sc->cachelsz, sc->rx.bufsize);
  298. /* Initialize rx descriptors */
  299. error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
  300. "rx", nbufs, 1);
  301. if (error != 0) {
  302. DPRINTF(sc, ATH_DBG_FATAL,
  303. "failed to allocate rx descriptors: %d\n", error);
  304. goto err;
  305. }
  306. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  307. skb = ath_rxbuf_alloc(sc, sc->rx.bufsize, GFP_KERNEL);
  308. if (skb == NULL) {
  309. error = -ENOMEM;
  310. goto err;
  311. }
  312. bf->bf_mpdu = skb;
  313. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  314. sc->rx.bufsize,
  315. DMA_FROM_DEVICE);
  316. if (unlikely(dma_mapping_error(sc->dev,
  317. bf->bf_buf_addr))) {
  318. dev_kfree_skb_any(skb);
  319. bf->bf_mpdu = NULL;
  320. DPRINTF(sc, ATH_DBG_FATAL,
  321. "dma_mapping_error() on RX init\n");
  322. error = -ENOMEM;
  323. goto err;
  324. }
  325. bf->bf_dmacontext = bf->bf_buf_addr;
  326. }
  327. sc->rx.rxlink = NULL;
  328. err:
  329. if (error)
  330. ath_rx_cleanup(sc);
  331. return error;
  332. }
  333. void ath_rx_cleanup(struct ath_softc *sc)
  334. {
  335. struct sk_buff *skb;
  336. struct ath_buf *bf;
  337. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  338. skb = bf->bf_mpdu;
  339. if (skb) {
  340. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  341. sc->rx.bufsize, DMA_FROM_DEVICE);
  342. dev_kfree_skb(skb);
  343. }
  344. }
  345. if (sc->rx.rxdma.dd_desc_len != 0)
  346. ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
  347. }
  348. /*
  349. * Calculate the receive filter according to the
  350. * operating mode and state:
  351. *
  352. * o always accept unicast, broadcast, and multicast traffic
  353. * o maintain current state of phy error reception (the hal
  354. * may enable phy error frames for noise immunity work)
  355. * o probe request frames are accepted only when operating in
  356. * hostap, adhoc, or monitor modes
  357. * o enable promiscuous mode according to the interface state
  358. * o accept beacons:
  359. * - when operating in adhoc mode so the 802.11 layer creates
  360. * node table entries for peers,
  361. * - when operating in station mode for collecting rssi data when
  362. * the station is otherwise quiet, or
  363. * - when operating as a repeater so we see repeater-sta beacons
  364. * - when scanning
  365. */
  366. u32 ath_calcrxfilter(struct ath_softc *sc)
  367. {
  368. #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
  369. u32 rfilt;
  370. rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
  371. | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
  372. | ATH9K_RX_FILTER_MCAST;
  373. /* If not a STA, enable processing of Probe Requests */
  374. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  375. rfilt |= ATH9K_RX_FILTER_PROBEREQ;
  376. /*
  377. * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
  378. * mode interface or when in monitor mode. AP mode does not need this
  379. * since it receives all in-BSS frames anyway.
  380. */
  381. if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
  382. (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
  383. (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
  384. rfilt |= ATH9K_RX_FILTER_PROM;
  385. if (sc->rx.rxfilter & FIF_CONTROL)
  386. rfilt |= ATH9K_RX_FILTER_CONTROL;
  387. if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
  388. !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
  389. rfilt |= ATH9K_RX_FILTER_MYBEACON;
  390. else
  391. rfilt |= ATH9K_RX_FILTER_BEACON;
  392. if (sc->rx.rxfilter & FIF_PSPOLL)
  393. rfilt |= ATH9K_RX_FILTER_PSPOLL;
  394. if (sc->sec_wiphy) {
  395. /* TODO: only needed if more than one BSSID is in use in
  396. * station/adhoc mode */
  397. /* TODO: for older chips, may need to add ATH9K_RX_FILTER_PROM
  398. */
  399. rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
  400. }
  401. return rfilt;
  402. #undef RX_FILTER_PRESERVE
  403. }
  404. int ath_startrecv(struct ath_softc *sc)
  405. {
  406. struct ath_hw *ah = sc->sc_ah;
  407. struct ath_buf *bf, *tbf;
  408. spin_lock_bh(&sc->rx.rxbuflock);
  409. if (list_empty(&sc->rx.rxbuf))
  410. goto start_recv;
  411. sc->rx.rxlink = NULL;
  412. list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
  413. ath_rx_buf_link(sc, bf);
  414. }
  415. /* We could have deleted elements so the list may be empty now */
  416. if (list_empty(&sc->rx.rxbuf))
  417. goto start_recv;
  418. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  419. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  420. ath9k_hw_rxena(ah);
  421. start_recv:
  422. spin_unlock_bh(&sc->rx.rxbuflock);
  423. ath_opmode_init(sc);
  424. ath9k_hw_startpcureceive(ah);
  425. return 0;
  426. }
  427. bool ath_stoprecv(struct ath_softc *sc)
  428. {
  429. struct ath_hw *ah = sc->sc_ah;
  430. bool stopped;
  431. ath9k_hw_stoppcurecv(ah);
  432. ath9k_hw_setrxfilter(ah, 0);
  433. stopped = ath9k_hw_stopdmarecv(ah);
  434. sc->rx.rxlink = NULL;
  435. return stopped;
  436. }
  437. void ath_flushrecv(struct ath_softc *sc)
  438. {
  439. spin_lock_bh(&sc->rx.rxflushlock);
  440. sc->sc_flags |= SC_OP_RXFLUSH;
  441. ath_rx_tasklet(sc, 1);
  442. sc->sc_flags &= ~SC_OP_RXFLUSH;
  443. spin_unlock_bh(&sc->rx.rxflushlock);
  444. }
  445. static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
  446. {
  447. /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
  448. struct ieee80211_mgmt *mgmt;
  449. u8 *pos, *end, id, elen;
  450. struct ieee80211_tim_ie *tim;
  451. mgmt = (struct ieee80211_mgmt *)skb->data;
  452. pos = mgmt->u.beacon.variable;
  453. end = skb->data + skb->len;
  454. while (pos + 2 < end) {
  455. id = *pos++;
  456. elen = *pos++;
  457. if (pos + elen > end)
  458. break;
  459. if (id == WLAN_EID_TIM) {
  460. if (elen < sizeof(*tim))
  461. break;
  462. tim = (struct ieee80211_tim_ie *) pos;
  463. if (tim->dtim_count != 0)
  464. break;
  465. return tim->bitmap_ctrl & 0x01;
  466. }
  467. pos += elen;
  468. }
  469. return false;
  470. }
  471. static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
  472. {
  473. struct ieee80211_mgmt *mgmt;
  474. if (skb->len < 24 + 8 + 2 + 2)
  475. return;
  476. mgmt = (struct ieee80211_mgmt *)skb->data;
  477. if (memcmp(sc->curbssid, mgmt->bssid, ETH_ALEN) != 0)
  478. return; /* not from our current AP */
  479. sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
  480. if (sc->sc_flags & SC_OP_BEACON_SYNC) {
  481. sc->sc_flags &= ~SC_OP_BEACON_SYNC;
  482. DPRINTF(sc, ATH_DBG_PS, "Reconfigure Beacon timers based on "
  483. "timestamp from the AP\n");
  484. ath_beacon_config(sc, NULL);
  485. }
  486. if (ath_beacon_dtim_pending_cab(skb)) {
  487. /*
  488. * Remain awake waiting for buffered broadcast/multicast
  489. * frames. If the last broadcast/multicast frame is not
  490. * received properly, the next beacon frame will work as
  491. * a backup trigger for returning into NETWORK SLEEP state,
  492. * so we are waiting for it as well.
  493. */
  494. DPRINTF(sc, ATH_DBG_PS, "Received DTIM beacon indicating "
  495. "buffered broadcast/multicast frame(s)\n");
  496. sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON;
  497. return;
  498. }
  499. if (sc->sc_flags & SC_OP_WAIT_FOR_CAB) {
  500. /*
  501. * This can happen if a broadcast frame is dropped or the AP
  502. * fails to send a frame indicating that all CAB frames have
  503. * been delivered.
  504. */
  505. sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
  506. DPRINTF(sc, ATH_DBG_PS, "PS wait for CAB frames timed out\n");
  507. }
  508. }
  509. static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
  510. {
  511. struct ieee80211_hdr *hdr;
  512. hdr = (struct ieee80211_hdr *)skb->data;
  513. /* Process Beacon and CAB receive in PS state */
  514. if ((sc->sc_flags & SC_OP_WAIT_FOR_BEACON) &&
  515. ieee80211_is_beacon(hdr->frame_control))
  516. ath_rx_ps_beacon(sc, skb);
  517. else if ((sc->sc_flags & SC_OP_WAIT_FOR_CAB) &&
  518. (ieee80211_is_data(hdr->frame_control) ||
  519. ieee80211_is_action(hdr->frame_control)) &&
  520. is_multicast_ether_addr(hdr->addr1) &&
  521. !ieee80211_has_moredata(hdr->frame_control)) {
  522. /*
  523. * No more broadcast/multicast frames to be received at this
  524. * point.
  525. */
  526. sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
  527. DPRINTF(sc, ATH_DBG_PS, "All PS CAB frames received, back to "
  528. "sleep\n");
  529. } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) &&
  530. !is_multicast_ether_addr(hdr->addr1) &&
  531. !ieee80211_has_morefrags(hdr->frame_control)) {
  532. sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA;
  533. DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having "
  534. "received PS-Poll data (0x%x)\n",
  535. sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
  536. SC_OP_WAIT_FOR_CAB |
  537. SC_OP_WAIT_FOR_PSPOLL_DATA |
  538. SC_OP_WAIT_FOR_TX_ACK));
  539. }
  540. }
  541. static void ath_rx_send_to_mac80211(struct ath_softc *sc, struct sk_buff *skb,
  542. struct ieee80211_rx_status *rx_status)
  543. {
  544. struct ieee80211_hdr *hdr;
  545. hdr = (struct ieee80211_hdr *)skb->data;
  546. /* Send the frame to mac80211 */
  547. if (is_multicast_ether_addr(hdr->addr1)) {
  548. int i;
  549. /*
  550. * Deliver broadcast/multicast frames to all suitable
  551. * virtual wiphys.
  552. */
  553. /* TODO: filter based on channel configuration */
  554. for (i = 0; i < sc->num_sec_wiphy; i++) {
  555. struct ath_wiphy *aphy = sc->sec_wiphy[i];
  556. struct sk_buff *nskb;
  557. if (aphy == NULL)
  558. continue;
  559. nskb = skb_copy(skb, GFP_ATOMIC);
  560. if (nskb) {
  561. memcpy(IEEE80211_SKB_RXCB(nskb), rx_status,
  562. sizeof(*rx_status));
  563. ieee80211_rx(aphy->hw, nskb);
  564. }
  565. }
  566. memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status));
  567. ieee80211_rx(sc->hw, skb);
  568. } else {
  569. /* Deliver unicast frames based on receiver address */
  570. memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status));
  571. ieee80211_rx(ath_get_virt_hw(sc, hdr), skb);
  572. }
  573. }
  574. int ath_rx_tasklet(struct ath_softc *sc, int flush)
  575. {
  576. #define PA2DESC(_sc, _pa) \
  577. ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
  578. ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
  579. struct ath_buf *bf;
  580. struct ath_desc *ds;
  581. struct sk_buff *skb = NULL, *requeue_skb;
  582. struct ieee80211_rx_status rx_status;
  583. struct ath_hw *ah = sc->sc_ah;
  584. struct ieee80211_hdr *hdr;
  585. int hdrlen, padsize, retval;
  586. bool decrypt_error = false;
  587. u8 keyix;
  588. __le16 fc;
  589. spin_lock_bh(&sc->rx.rxbuflock);
  590. do {
  591. /* If handling rx interrupt and flush is in progress => exit */
  592. if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
  593. break;
  594. if (list_empty(&sc->rx.rxbuf)) {
  595. sc->rx.rxlink = NULL;
  596. break;
  597. }
  598. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  599. ds = bf->bf_desc;
  600. /*
  601. * Must provide the virtual address of the current
  602. * descriptor, the physical address, and the virtual
  603. * address of the next descriptor in the h/w chain.
  604. * This allows the HAL to look ahead to see if the
  605. * hardware is done with a descriptor by checking the
  606. * done bit in the following descriptor and the address
  607. * of the current descriptor the DMA engine is working
  608. * on. All this is necessary because of our use of
  609. * a self-linked list to avoid rx overruns.
  610. */
  611. retval = ath9k_hw_rxprocdesc(ah, ds,
  612. bf->bf_daddr,
  613. PA2DESC(sc, ds->ds_link),
  614. 0);
  615. if (retval == -EINPROGRESS) {
  616. struct ath_buf *tbf;
  617. struct ath_desc *tds;
  618. if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
  619. sc->rx.rxlink = NULL;
  620. break;
  621. }
  622. tbf = list_entry(bf->list.next, struct ath_buf, list);
  623. /*
  624. * On some hardware the descriptor status words could
  625. * get corrupted, including the done bit. Because of
  626. * this, check if the next descriptor's done bit is
  627. * set or not.
  628. *
  629. * If the next descriptor's done bit is set, the current
  630. * descriptor has been corrupted. Force s/w to discard
  631. * this descriptor and continue...
  632. */
  633. tds = tbf->bf_desc;
  634. retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr,
  635. PA2DESC(sc, tds->ds_link), 0);
  636. if (retval == -EINPROGRESS) {
  637. break;
  638. }
  639. }
  640. skb = bf->bf_mpdu;
  641. if (!skb)
  642. continue;
  643. /*
  644. * Synchronize the DMA transfer with CPU before
  645. * 1. accessing the frame
  646. * 2. requeueing the same buffer to h/w
  647. */
  648. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  649. sc->rx.bufsize,
  650. DMA_FROM_DEVICE);
  651. /*
  652. * If we're asked to flush receive queue, directly
  653. * chain it back at the queue without processing it.
  654. */
  655. if (flush)
  656. goto requeue;
  657. if (!ds->ds_rxstat.rs_datalen)
  658. goto requeue;
  659. /* The status portion of the descriptor could get corrupted. */
  660. if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen)
  661. goto requeue;
  662. if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc))
  663. goto requeue;
  664. /* Ensure we always have an skb to requeue once we are done
  665. * processing the current buffer's skb */
  666. requeue_skb = ath_rxbuf_alloc(sc, sc->rx.bufsize, GFP_ATOMIC);
  667. /* If there is no memory we ignore the current RX'd frame,
  668. * tell hardware it can give us a new frame using the old
  669. * skb and put it at the tail of the sc->rx.rxbuf list for
  670. * processing. */
  671. if (!requeue_skb)
  672. goto requeue;
  673. /* Unmap the frame */
  674. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  675. sc->rx.bufsize,
  676. DMA_FROM_DEVICE);
  677. skb_put(skb, ds->ds_rxstat.rs_datalen);
  678. /* see if any padding is done by the hw and remove it */
  679. hdr = (struct ieee80211_hdr *)skb->data;
  680. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  681. fc = hdr->frame_control;
  682. /* The MAC header is padded to have 32-bit boundary if the
  683. * packet payload is non-zero. The general calculation for
  684. * padsize would take into account odd header lengths:
  685. * padsize = (4 - hdrlen % 4) % 4; However, since only
  686. * even-length headers are used, padding can only be 0 or 2
  687. * bytes and we can optimize this a bit. In addition, we must
  688. * not try to remove padding from short control frames that do
  689. * not have payload. */
  690. padsize = hdrlen & 3;
  691. if (padsize && hdrlen >= 24) {
  692. memmove(skb->data + padsize, skb->data, hdrlen);
  693. skb_pull(skb, padsize);
  694. }
  695. keyix = ds->ds_rxstat.rs_keyix;
  696. if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) {
  697. rx_status.flag |= RX_FLAG_DECRYPTED;
  698. } else if (ieee80211_has_protected(fc)
  699. && !decrypt_error && skb->len >= hdrlen + 4) {
  700. keyix = skb->data[hdrlen + 3] >> 6;
  701. if (test_bit(keyix, sc->keymap))
  702. rx_status.flag |= RX_FLAG_DECRYPTED;
  703. }
  704. if (ah->sw_mgmt_crypto &&
  705. (rx_status.flag & RX_FLAG_DECRYPTED) &&
  706. ieee80211_is_mgmt(fc)) {
  707. /* Use software decrypt for management frames. */
  708. rx_status.flag &= ~RX_FLAG_DECRYPTED;
  709. }
  710. /* We will now give hardware our shiny new allocated skb */
  711. bf->bf_mpdu = requeue_skb;
  712. bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
  713. sc->rx.bufsize,
  714. DMA_FROM_DEVICE);
  715. if (unlikely(dma_mapping_error(sc->dev,
  716. bf->bf_buf_addr))) {
  717. dev_kfree_skb_any(requeue_skb);
  718. bf->bf_mpdu = NULL;
  719. DPRINTF(sc, ATH_DBG_FATAL,
  720. "dma_mapping_error() on RX\n");
  721. ath_rx_send_to_mac80211(sc, skb, &rx_status);
  722. break;
  723. }
  724. bf->bf_dmacontext = bf->bf_buf_addr;
  725. /*
  726. * change the default rx antenna if rx diversity chooses the
  727. * other antenna 3 times in a row.
  728. */
  729. if (sc->rx.defant != ds->ds_rxstat.rs_antenna) {
  730. if (++sc->rx.rxotherant >= 3)
  731. ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna);
  732. } else {
  733. sc->rx.rxotherant = 0;
  734. }
  735. if (unlikely(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
  736. SC_OP_WAIT_FOR_CAB |
  737. SC_OP_WAIT_FOR_PSPOLL_DATA)))
  738. ath_rx_ps(sc, skb);
  739. ath_rx_send_to_mac80211(sc, skb, &rx_status);
  740. requeue:
  741. list_move_tail(&bf->list, &sc->rx.rxbuf);
  742. ath_rx_buf_link(sc, bf);
  743. } while (1);
  744. spin_unlock_bh(&sc->rx.rxbuflock);
  745. return 0;
  746. #undef PA2DESC
  747. }