main.c 211 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include <linux/pci_ids.h>
  18. #include <linux/if_ether.h>
  19. #include <net/cfg80211.h>
  20. #include <net/mac80211.h>
  21. #include <brcm_hw_ids.h>
  22. #include <aiutils.h>
  23. #include <chipcommon.h>
  24. #include "rate.h"
  25. #include "scb.h"
  26. #include "phy/phy_hal.h"
  27. #include "channel.h"
  28. #include "antsel.h"
  29. #include "stf.h"
  30. #include "ampdu.h"
  31. #include "mac80211_if.h"
  32. #include "ucode_loader.h"
  33. #include "main.h"
  34. #include "soc.h"
  35. #include "dma.h"
  36. #include "debug.h"
  37. #include "brcms_trace_events.h"
  38. /* watchdog timer, in unit of ms */
  39. #define TIMER_INTERVAL_WATCHDOG 1000
  40. /* radio monitor timer, in unit of ms */
  41. #define TIMER_INTERVAL_RADIOCHK 800
  42. /* beacon interval, in unit of 1024TU */
  43. #define BEACON_INTERVAL_DEFAULT 100
  44. /* n-mode support capability */
  45. /* 2x2 includes both 1x1 & 2x2 devices
  46. * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
  47. * control it independently
  48. */
  49. #define WL_11N_2x2 1
  50. #define WL_11N_3x3 3
  51. #define WL_11N_4x4 4
  52. #define EDCF_ACI_MASK 0x60
  53. #define EDCF_ACI_SHIFT 5
  54. #define EDCF_ECWMIN_MASK 0x0f
  55. #define EDCF_ECWMAX_SHIFT 4
  56. #define EDCF_AIFSN_MASK 0x0f
  57. #define EDCF_AIFSN_MAX 15
  58. #define EDCF_ECWMAX_MASK 0xf0
  59. #define EDCF_AC_BE_TXOP_STA 0x0000
  60. #define EDCF_AC_BK_TXOP_STA 0x0000
  61. #define EDCF_AC_VO_ACI_STA 0x62
  62. #define EDCF_AC_VO_ECW_STA 0x32
  63. #define EDCF_AC_VI_ACI_STA 0x42
  64. #define EDCF_AC_VI_ECW_STA 0x43
  65. #define EDCF_AC_BK_ECW_STA 0xA4
  66. #define EDCF_AC_VI_TXOP_STA 0x005e
  67. #define EDCF_AC_VO_TXOP_STA 0x002f
  68. #define EDCF_AC_BE_ACI_STA 0x03
  69. #define EDCF_AC_BE_ECW_STA 0xA4
  70. #define EDCF_AC_BK_ACI_STA 0x27
  71. #define EDCF_AC_VO_TXOP_AP 0x002f
  72. #define EDCF_TXOP2USEC(txop) ((txop) << 5)
  73. #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
  74. #define APHY_SYMBOL_TIME 4
  75. #define APHY_PREAMBLE_TIME 16
  76. #define APHY_SIGNAL_TIME 4
  77. #define APHY_SIFS_TIME 16
  78. #define APHY_SERVICE_NBITS 16
  79. #define APHY_TAIL_NBITS 6
  80. #define BPHY_SIFS_TIME 10
  81. #define BPHY_PLCP_SHORT_TIME 96
  82. #define PREN_PREAMBLE 24
  83. #define PREN_MM_EXT 12
  84. #define PREN_PREAMBLE_EXT 4
  85. #define DOT11_MAC_HDR_LEN 24
  86. #define DOT11_ACK_LEN 10
  87. #define DOT11_BA_LEN 4
  88. #define DOT11_OFDM_SIGNAL_EXTENSION 6
  89. #define DOT11_MIN_FRAG_LEN 256
  90. #define DOT11_RTS_LEN 16
  91. #define DOT11_CTS_LEN 10
  92. #define DOT11_BA_BITMAP_LEN 128
  93. #define DOT11_MIN_BEACON_PERIOD 1
  94. #define DOT11_MAX_BEACON_PERIOD 0xFFFF
  95. #define DOT11_MAXNUMFRAGS 16
  96. #define DOT11_MAX_FRAG_LEN 2346
  97. #define BPHY_PLCP_TIME 192
  98. #define RIFS_11N_TIME 2
  99. /* length of the BCN template area */
  100. #define BCN_TMPL_LEN 512
  101. /* brcms_bss_info flag bit values */
  102. #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
  103. /* chip rx buffer offset */
  104. #define BRCMS_HWRXOFF 38
  105. /* rfdisable delay timer 500 ms, runs of ALP clock */
  106. #define RFDISABLE_DEFAULT 10000000
  107. #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
  108. /* synthpu_dly times in us */
  109. #define SYNTHPU_DLY_APHY_US 3700
  110. #define SYNTHPU_DLY_BPHY_US 1050
  111. #define SYNTHPU_DLY_NPHY_US 2048
  112. #define SYNTHPU_DLY_LPPHY_US 300
  113. #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
  114. /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
  115. #define EDCF_SHORT_S 0
  116. #define EDCF_SFB_S 4
  117. #define EDCF_LONG_S 8
  118. #define EDCF_LFB_S 12
  119. #define EDCF_SHORT_M BITFIELD_MASK(4)
  120. #define EDCF_SFB_M BITFIELD_MASK(4)
  121. #define EDCF_LONG_M BITFIELD_MASK(4)
  122. #define EDCF_LFB_M BITFIELD_MASK(4)
  123. #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
  124. #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
  125. #define RETRY_LONG_DEF 4 /* Default Long retry count */
  126. #define RETRY_SHORT_FB 3 /* Short count for fb rate */
  127. #define RETRY_LONG_FB 2 /* Long count for fb rate */
  128. #define APHY_CWMIN 15
  129. #define PHY_CWMAX 1023
  130. #define EDCF_AIFSN_MIN 1
  131. #define FRAGNUM_MASK 0xF
  132. #define APHY_SLOT_TIME 9
  133. #define BPHY_SLOT_TIME 20
  134. #define WL_SPURAVOID_OFF 0
  135. #define WL_SPURAVOID_ON1 1
  136. #define WL_SPURAVOID_ON2 2
  137. /* invalid core flags, use the saved coreflags */
  138. #define BRCMS_USE_COREFLAGS 0xffffffff
  139. /* values for PLCPHdr_override */
  140. #define BRCMS_PLCP_AUTO -1
  141. #define BRCMS_PLCP_SHORT 0
  142. #define BRCMS_PLCP_LONG 1
  143. /* values for g_protection_override and n_protection_override */
  144. #define BRCMS_PROTECTION_AUTO -1
  145. #define BRCMS_PROTECTION_OFF 0
  146. #define BRCMS_PROTECTION_ON 1
  147. #define BRCMS_PROTECTION_MMHDR_ONLY 2
  148. #define BRCMS_PROTECTION_CTS_ONLY 3
  149. /* values for g_protection_control and n_protection_control */
  150. #define BRCMS_PROTECTION_CTL_OFF 0
  151. #define BRCMS_PROTECTION_CTL_LOCAL 1
  152. #define BRCMS_PROTECTION_CTL_OVERLAP 2
  153. /* values for n_protection */
  154. #define BRCMS_N_PROTECTION_OFF 0
  155. #define BRCMS_N_PROTECTION_OPTIONAL 1
  156. #define BRCMS_N_PROTECTION_20IN40 2
  157. #define BRCMS_N_PROTECTION_MIXEDMODE 3
  158. /* values for band specific 40MHz capabilities */
  159. #define BRCMS_N_BW_20ALL 0
  160. #define BRCMS_N_BW_40ALL 1
  161. #define BRCMS_N_BW_20IN2G_40IN5G 2
  162. /* bitflags for SGI support (sgi_rx iovar) */
  163. #define BRCMS_N_SGI_20 0x01
  164. #define BRCMS_N_SGI_40 0x02
  165. /* defines used by the nrate iovar */
  166. /* MSC in use,indicates b0-6 holds an mcs */
  167. #define NRATE_MCS_INUSE 0x00000080
  168. /* rate/mcs value */
  169. #define NRATE_RATE_MASK 0x0000007f
  170. /* stf mode mask: siso, cdd, stbc, sdm */
  171. #define NRATE_STF_MASK 0x0000ff00
  172. /* stf mode shift */
  173. #define NRATE_STF_SHIFT 8
  174. /* bit indicate to override mcs only */
  175. #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
  176. #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
  177. #define NRATE_SGI_SHIFT 23 /* sgi mode */
  178. #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
  179. #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
  180. #define NRATE_STF_SISO 0 /* stf mode SISO */
  181. #define NRATE_STF_CDD 1 /* stf mode CDD */
  182. #define NRATE_STF_STBC 2 /* stf mode STBC */
  183. #define NRATE_STF_SDM 3 /* stf mode SDM */
  184. #define MAX_DMA_SEGS 4
  185. /* # of entries in Tx FIFO */
  186. #define NTXD 64
  187. /* Max # of entries in Rx FIFO based on 4kb page size */
  188. #define NRXD 256
  189. /* Amount of headroom to leave in Tx FIFO */
  190. #define TX_HEADROOM 4
  191. /* try to keep this # rbufs posted to the chip */
  192. #define NRXBUFPOST 32
  193. /* max # frames to process in brcms_c_recv() */
  194. #define RXBND 8
  195. /* max # tx status to process in wlc_txstatus() */
  196. #define TXSBND 8
  197. /* brcmu_format_flags() bit description structure */
  198. struct brcms_c_bit_desc {
  199. u32 bit;
  200. const char *name;
  201. };
  202. /*
  203. * The following table lists the buffer memory allocated to xmt fifos in HW.
  204. * the size is in units of 256bytes(one block), total size is HW dependent
  205. * ucode has default fifo partition, sw can overwrite if necessary
  206. *
  207. * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  208. * the twiki is updated before making changes.
  209. */
  210. /* Starting corerev for the fifo size table */
  211. #define XMTFIFOTBL_STARTREV 17
  212. struct d11init {
  213. __le16 addr;
  214. __le16 size;
  215. __le32 value;
  216. };
  217. struct edcf_acparam {
  218. u8 ACI;
  219. u8 ECW;
  220. u16 TXOP;
  221. } __packed;
  222. /* debug/trace */
  223. uint brcm_msg_level;
  224. /* TX FIFO number to WME/802.1E Access Category */
  225. static const u8 wme_fifo2ac[] = {
  226. IEEE80211_AC_BK,
  227. IEEE80211_AC_BE,
  228. IEEE80211_AC_VI,
  229. IEEE80211_AC_VO,
  230. IEEE80211_AC_BE,
  231. IEEE80211_AC_BE
  232. };
  233. /* ieee80211 Access Category to TX FIFO number */
  234. static const u8 wme_ac2fifo[] = {
  235. TX_AC_VO_FIFO,
  236. TX_AC_VI_FIFO,
  237. TX_AC_BE_FIFO,
  238. TX_AC_BK_FIFO
  239. };
  240. static const u16 xmtfifo_sz[][NFIFO] = {
  241. /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
  242. {20, 192, 192, 21, 17, 5},
  243. /* corerev 18: */
  244. {0, 0, 0, 0, 0, 0},
  245. /* corerev 19: */
  246. {0, 0, 0, 0, 0, 0},
  247. /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  248. {20, 192, 192, 21, 17, 5},
  249. /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  250. {9, 58, 22, 14, 14, 5},
  251. /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  252. {20, 192, 192, 21, 17, 5},
  253. /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  254. {20, 192, 192, 21, 17, 5},
  255. /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  256. {9, 58, 22, 14, 14, 5},
  257. /* corerev 25: */
  258. {0, 0, 0, 0, 0, 0},
  259. /* corerev 26: */
  260. {0, 0, 0, 0, 0, 0},
  261. /* corerev 27: */
  262. {0, 0, 0, 0, 0, 0},
  263. /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
  264. {9, 58, 22, 14, 14, 5},
  265. };
  266. #ifdef DEBUG
  267. static const char * const fifo_names[] = {
  268. "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
  269. #else
  270. static const char fifo_names[6][0];
  271. #endif
  272. #ifdef DEBUG
  273. /* pointer to most recently allocated wl/wlc */
  274. static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
  275. #endif
  276. /* Mapping of ieee80211 AC numbers to tx fifos */
  277. static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
  278. [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
  279. [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
  280. [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
  281. [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
  282. };
  283. /* Mapping of tx fifos to ieee80211 AC numbers */
  284. static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
  285. [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
  286. [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
  287. [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
  288. [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
  289. };
  290. static u8 brcms_ac_to_fifo(u8 ac)
  291. {
  292. if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
  293. return TX_AC_BE_FIFO;
  294. return ac_to_fifo_mapping[ac];
  295. }
  296. static u8 brcms_fifo_to_ac(u8 fifo)
  297. {
  298. if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
  299. return IEEE80211_AC_BE;
  300. return fifo_to_ac_mapping[fifo];
  301. }
  302. /* Find basic rate for a given rate */
  303. static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
  304. {
  305. if (is_mcs_rate(rspec))
  306. return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
  307. .leg_ofdm];
  308. return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
  309. }
  310. static u16 frametype(u32 rspec, u8 mimoframe)
  311. {
  312. if (is_mcs_rate(rspec))
  313. return mimoframe;
  314. return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
  315. }
  316. /* currently the best mechanism for determining SIFS is the band in use */
  317. static u16 get_sifs(struct brcms_band *band)
  318. {
  319. return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
  320. BPHY_SIFS_TIME;
  321. }
  322. /*
  323. * Detect Card removed.
  324. * Even checking an sbconfig register read will not false trigger when the core
  325. * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
  326. * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
  327. * reg with fixed 0/1 pattern (some platforms return all 0).
  328. * If clocks are present, call the sb routine which will figure out if the
  329. * device is removed.
  330. */
  331. static bool brcms_deviceremoved(struct brcms_c_info *wlc)
  332. {
  333. u32 macctrl;
  334. if (!wlc->hw->clk)
  335. return ai_deviceremoved(wlc->hw->sih);
  336. macctrl = bcma_read32(wlc->hw->d11core,
  337. D11REGOFFS(maccontrol));
  338. return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
  339. }
  340. /* sum the individual fifo tx pending packet counts */
  341. static int brcms_txpktpendtot(struct brcms_c_info *wlc)
  342. {
  343. int i;
  344. int pending = 0;
  345. for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
  346. if (wlc->hw->di[i])
  347. pending += dma_txpending(wlc->hw->di[i]);
  348. return pending;
  349. }
  350. static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
  351. {
  352. return wlc->pub->_nbands > 1 && !wlc->bandlocked;
  353. }
  354. static int brcms_chspec_bw(u16 chanspec)
  355. {
  356. if (CHSPEC_IS40(chanspec))
  357. return BRCMS_40_MHZ;
  358. if (CHSPEC_IS20(chanspec))
  359. return BRCMS_20_MHZ;
  360. return BRCMS_10_MHZ;
  361. }
  362. static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
  363. {
  364. if (cfg == NULL)
  365. return;
  366. kfree(cfg->current_bss);
  367. kfree(cfg);
  368. }
  369. static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
  370. {
  371. if (wlc == NULL)
  372. return;
  373. brcms_c_bsscfg_mfree(wlc->bsscfg);
  374. kfree(wlc->pub);
  375. kfree(wlc->modulecb);
  376. kfree(wlc->default_bss);
  377. kfree(wlc->protection);
  378. kfree(wlc->stf);
  379. kfree(wlc->bandstate[0]);
  380. kfree(wlc->corestate->macstat_snapshot);
  381. kfree(wlc->corestate);
  382. kfree(wlc->hw->bandstate[0]);
  383. kfree(wlc->hw);
  384. /* free the wlc */
  385. kfree(wlc);
  386. wlc = NULL;
  387. }
  388. static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
  389. {
  390. struct brcms_bss_cfg *cfg;
  391. cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
  392. if (cfg == NULL)
  393. goto fail;
  394. cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  395. if (cfg->current_bss == NULL)
  396. goto fail;
  397. return cfg;
  398. fail:
  399. brcms_c_bsscfg_mfree(cfg);
  400. return NULL;
  401. }
  402. static struct brcms_c_info *
  403. brcms_c_attach_malloc(uint unit, uint *err, uint devid)
  404. {
  405. struct brcms_c_info *wlc;
  406. wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
  407. if (wlc == NULL) {
  408. *err = 1002;
  409. goto fail;
  410. }
  411. /* allocate struct brcms_c_pub state structure */
  412. wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
  413. if (wlc->pub == NULL) {
  414. *err = 1003;
  415. goto fail;
  416. }
  417. wlc->pub->wlc = wlc;
  418. /* allocate struct brcms_hardware state structure */
  419. wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
  420. if (wlc->hw == NULL) {
  421. *err = 1005;
  422. goto fail;
  423. }
  424. wlc->hw->wlc = wlc;
  425. wlc->hw->bandstate[0] =
  426. kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
  427. if (wlc->hw->bandstate[0] == NULL) {
  428. *err = 1006;
  429. goto fail;
  430. } else {
  431. int i;
  432. for (i = 1; i < MAXBANDS; i++)
  433. wlc->hw->bandstate[i] = (struct brcms_hw_band *)
  434. ((unsigned long)wlc->hw->bandstate[0] +
  435. (sizeof(struct brcms_hw_band) * i));
  436. }
  437. wlc->modulecb =
  438. kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
  439. if (wlc->modulecb == NULL) {
  440. *err = 1009;
  441. goto fail;
  442. }
  443. wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  444. if (wlc->default_bss == NULL) {
  445. *err = 1010;
  446. goto fail;
  447. }
  448. wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
  449. if (wlc->bsscfg == NULL) {
  450. *err = 1011;
  451. goto fail;
  452. }
  453. wlc->protection = kzalloc(sizeof(struct brcms_protection),
  454. GFP_ATOMIC);
  455. if (wlc->protection == NULL) {
  456. *err = 1016;
  457. goto fail;
  458. }
  459. wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
  460. if (wlc->stf == NULL) {
  461. *err = 1017;
  462. goto fail;
  463. }
  464. wlc->bandstate[0] =
  465. kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
  466. if (wlc->bandstate[0] == NULL) {
  467. *err = 1025;
  468. goto fail;
  469. } else {
  470. int i;
  471. for (i = 1; i < MAXBANDS; i++)
  472. wlc->bandstate[i] = (struct brcms_band *)
  473. ((unsigned long)wlc->bandstate[0]
  474. + (sizeof(struct brcms_band)*i));
  475. }
  476. wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
  477. if (wlc->corestate == NULL) {
  478. *err = 1026;
  479. goto fail;
  480. }
  481. wlc->corestate->macstat_snapshot =
  482. kzalloc(sizeof(struct macstat), GFP_ATOMIC);
  483. if (wlc->corestate->macstat_snapshot == NULL) {
  484. *err = 1027;
  485. goto fail;
  486. }
  487. return wlc;
  488. fail:
  489. brcms_c_detach_mfree(wlc);
  490. return NULL;
  491. }
  492. /*
  493. * Update the slot timing for standard 11b/g (20us slots)
  494. * or shortslot 11g (9us slots)
  495. * The PSM needs to be suspended for this call.
  496. */
  497. static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
  498. bool shortslot)
  499. {
  500. struct bcma_device *core = wlc_hw->d11core;
  501. if (shortslot) {
  502. /* 11g short slot: 11a timing */
  503. bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
  504. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
  505. } else {
  506. /* 11g long slot: 11b timing */
  507. bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
  508. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
  509. }
  510. }
  511. /*
  512. * calculate frame duration of a given rate and length, return
  513. * time in usec unit
  514. */
  515. static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
  516. u8 preamble_type, uint mac_len)
  517. {
  518. uint nsyms, dur = 0, Ndps, kNdps;
  519. uint rate = rspec2rate(ratespec);
  520. if (rate == 0) {
  521. brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
  522. wlc->pub->unit);
  523. rate = BRCM_RATE_1M;
  524. }
  525. if (is_mcs_rate(ratespec)) {
  526. uint mcs = ratespec & RSPEC_RATE_MASK;
  527. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  528. dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  529. if (preamble_type == BRCMS_MM_PREAMBLE)
  530. dur += PREN_MM_EXT;
  531. /* 1000Ndbps = kbps * 4 */
  532. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  533. rspec_issgi(ratespec)) * 4;
  534. if (rspec_stc(ratespec) == 0)
  535. nsyms =
  536. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  537. APHY_TAIL_NBITS) * 1000, kNdps);
  538. else
  539. /* STBC needs to have even number of symbols */
  540. nsyms =
  541. 2 *
  542. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  543. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  544. dur += APHY_SYMBOL_TIME * nsyms;
  545. if (wlc->band->bandtype == BRCM_BAND_2G)
  546. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  547. } else if (is_ofdm_rate(rate)) {
  548. dur = APHY_PREAMBLE_TIME;
  549. dur += APHY_SIGNAL_TIME;
  550. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  551. Ndps = rate * 2;
  552. /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
  553. nsyms =
  554. CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
  555. Ndps);
  556. dur += APHY_SYMBOL_TIME * nsyms;
  557. if (wlc->band->bandtype == BRCM_BAND_2G)
  558. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  559. } else {
  560. /*
  561. * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
  562. * will divide out
  563. */
  564. mac_len = mac_len * 8 * 2;
  565. /* calc ceiling of bits/rate = microseconds of air time */
  566. dur = (mac_len + rate - 1) / rate;
  567. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  568. dur += BPHY_PLCP_SHORT_TIME;
  569. else
  570. dur += BPHY_PLCP_TIME;
  571. }
  572. return dur;
  573. }
  574. static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
  575. const struct d11init *inits)
  576. {
  577. struct bcma_device *core = wlc_hw->d11core;
  578. int i;
  579. uint offset;
  580. u16 size;
  581. u32 value;
  582. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  583. for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
  584. size = le16_to_cpu(inits[i].size);
  585. offset = le16_to_cpu(inits[i].addr);
  586. value = le32_to_cpu(inits[i].value);
  587. if (size == 2)
  588. bcma_write16(core, offset, value);
  589. else if (size == 4)
  590. bcma_write32(core, offset, value);
  591. else
  592. break;
  593. }
  594. }
  595. static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
  596. {
  597. u8 idx;
  598. u16 addr[] = {
  599. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  600. M_HOST_FLAGS5
  601. };
  602. for (idx = 0; idx < MHFMAX; idx++)
  603. brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
  604. }
  605. static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
  606. {
  607. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  608. /* init microcode host flags */
  609. brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
  610. /* do band-specific ucode IHR, SHM, and SCR inits */
  611. if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
  612. if (BRCMS_ISNPHY(wlc_hw->band))
  613. brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
  614. else
  615. brcms_err(wlc_hw->d11core,
  616. "%s: wl%d: unsupported phy in corerev %d\n",
  617. __func__, wlc_hw->unit,
  618. wlc_hw->corerev);
  619. } else {
  620. if (D11REV_IS(wlc_hw->corerev, 24)) {
  621. if (BRCMS_ISLCNPHY(wlc_hw->band))
  622. brcms_c_write_inits(wlc_hw,
  623. ucode->d11lcn0bsinitvals24);
  624. else
  625. brcms_err(wlc_hw->d11core,
  626. "%s: wl%d: unsupported phy in core rev %d\n",
  627. __func__, wlc_hw->unit,
  628. wlc_hw->corerev);
  629. } else {
  630. brcms_err(wlc_hw->d11core,
  631. "%s: wl%d: unsupported corerev %d\n",
  632. __func__, wlc_hw->unit, wlc_hw->corerev);
  633. }
  634. }
  635. }
  636. static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
  637. {
  638. struct bcma_device *core = wlc_hw->d11core;
  639. u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
  640. bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
  641. }
  642. static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
  643. {
  644. brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
  645. wlc_hw->phyclk = clk;
  646. if (OFF == clk) { /* clear gmode bit, put phy into reset */
  647. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
  648. (SICF_PRST | SICF_FGC));
  649. udelay(1);
  650. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
  651. udelay(1);
  652. } else { /* take phy out of reset */
  653. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
  654. udelay(1);
  655. brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
  656. udelay(1);
  657. }
  658. }
  659. /* low-level band switch utility routine */
  660. static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
  661. {
  662. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
  663. bandunit);
  664. wlc_hw->band = wlc_hw->bandstate[bandunit];
  665. /*
  666. * BMAC_NOTE:
  667. * until we eliminate need for wlc->band refs in low level code
  668. */
  669. wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
  670. /* set gmode core flag */
  671. if (wlc_hw->sbclk && !wlc_hw->noreset) {
  672. u32 gmode = 0;
  673. if (bandunit == 0)
  674. gmode = SICF_GMODE;
  675. brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
  676. }
  677. }
  678. /* switch to new band but leave it inactive */
  679. static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
  680. {
  681. struct brcms_hardware *wlc_hw = wlc->hw;
  682. u32 macintmask;
  683. u32 macctrl;
  684. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  685. macctrl = bcma_read32(wlc_hw->d11core,
  686. D11REGOFFS(maccontrol));
  687. WARN_ON((macctrl & MCTL_EN_MAC) != 0);
  688. /* disable interrupts */
  689. macintmask = brcms_intrsoff(wlc->wl);
  690. /* radio off */
  691. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  692. brcms_b_core_phy_clk(wlc_hw, OFF);
  693. brcms_c_setxband(wlc_hw, bandunit);
  694. return macintmask;
  695. }
  696. /* process an individual struct tx_status */
  697. static bool
  698. brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
  699. {
  700. struct sk_buff *p = NULL;
  701. uint queue = NFIFO;
  702. struct dma_pub *dma = NULL;
  703. struct d11txh *txh = NULL;
  704. struct scb *scb = NULL;
  705. bool free_pdu;
  706. int tx_rts, tx_frame_count, tx_rts_count;
  707. uint totlen, supr_status;
  708. bool lastframe;
  709. struct ieee80211_hdr *h;
  710. u16 mcl;
  711. struct ieee80211_tx_info *tx_info;
  712. struct ieee80211_tx_rate *txrate;
  713. int i;
  714. bool fatal = true;
  715. trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
  716. txs->frameid, txs->status, txs->lasttxtime,
  717. txs->sequence, txs->phyerr, txs->ackphyrxsh);
  718. /* discard intermediate indications for ucode with one legitimate case:
  719. * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
  720. * but the subsequent tx of DATA failed. so it will start rts/cts
  721. * from the beginning (resetting the rts transmission count)
  722. */
  723. if (!(txs->status & TX_STATUS_AMPDU)
  724. && (txs->status & TX_STATUS_INTERMEDIATE)) {
  725. brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
  726. fatal = false;
  727. goto out;
  728. }
  729. queue = txs->frameid & TXFID_QUEUE_MASK;
  730. if (queue >= NFIFO) {
  731. brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
  732. goto out;
  733. }
  734. dma = wlc->hw->di[queue];
  735. p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
  736. if (p == NULL) {
  737. brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
  738. goto out;
  739. }
  740. txh = (struct d11txh *) (p->data);
  741. mcl = le16_to_cpu(txh->MacTxControlLow);
  742. if (txs->phyerr)
  743. brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
  744. txs->phyerr, txh->MainRates);
  745. if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
  746. brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
  747. goto out;
  748. }
  749. tx_info = IEEE80211_SKB_CB(p);
  750. h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
  751. if (tx_info->rate_driver_data[0])
  752. scb = &wlc->pri_scb;
  753. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  754. brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
  755. fatal = false;
  756. goto out;
  757. }
  758. /*
  759. * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
  760. * frames; this traces them for the rest.
  761. */
  762. trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
  763. supr_status = txs->status & TX_STATUS_SUPR_MASK;
  764. if (supr_status == TX_STATUS_SUPR_BADCH) {
  765. unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
  766. brcms_dbg_tx(wlc->hw->d11core,
  767. "Pkt tx suppressed, dest chan %u, current %d\n",
  768. (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
  769. CHSPEC_CHANNEL(wlc->default_bss->chanspec));
  770. }
  771. tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
  772. tx_frame_count =
  773. (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
  774. tx_rts_count =
  775. (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
  776. lastframe = !ieee80211_has_morefrags(h->frame_control);
  777. if (!lastframe) {
  778. brcms_err(wlc->hw->d11core, "Not last frame!\n");
  779. } else {
  780. /*
  781. * Set information to be consumed by Minstrel ht.
  782. *
  783. * The "fallback limit" is the number of tx attempts a given
  784. * MPDU is sent at the "primary" rate. Tx attempts beyond that
  785. * limit are sent at the "secondary" rate.
  786. * A 'short frame' does not exceed RTS treshold.
  787. */
  788. u16 sfbl, /* Short Frame Rate Fallback Limit */
  789. lfbl, /* Long Frame Rate Fallback Limit */
  790. fbl;
  791. if (queue < IEEE80211_NUM_ACS) {
  792. sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  793. EDCF_SFB);
  794. lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  795. EDCF_LFB);
  796. } else {
  797. sfbl = wlc->SFBL;
  798. lfbl = wlc->LFBL;
  799. }
  800. txrate = tx_info->status.rates;
  801. if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
  802. fbl = lfbl;
  803. else
  804. fbl = sfbl;
  805. ieee80211_tx_info_clear_status(tx_info);
  806. if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
  807. /*
  808. * rate selection requested a fallback rate
  809. * and we used it
  810. */
  811. txrate[0].count = fbl;
  812. txrate[1].count = tx_frame_count - fbl;
  813. } else {
  814. /*
  815. * rate selection did not request fallback rate, or
  816. * we didn't need it
  817. */
  818. txrate[0].count = tx_frame_count;
  819. /*
  820. * rc80211_minstrel.c:minstrel_tx_status() expects
  821. * unused rates to be marked with idx = -1
  822. */
  823. txrate[1].idx = -1;
  824. txrate[1].count = 0;
  825. }
  826. /* clear the rest of the rates */
  827. for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
  828. txrate[i].idx = -1;
  829. txrate[i].count = 0;
  830. }
  831. if (txs->status & TX_STATUS_ACK_RCV)
  832. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  833. }
  834. totlen = p->len;
  835. free_pdu = true;
  836. if (lastframe) {
  837. /* remove PLCP & Broadcom tx descriptor header */
  838. skb_pull(p, D11_PHY_HDR_LEN);
  839. skb_pull(p, D11_TXH_LEN);
  840. ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
  841. } else {
  842. brcms_err(wlc->hw->d11core,
  843. "%s: Not last frame => not calling tx_status\n",
  844. __func__);
  845. }
  846. fatal = false;
  847. out:
  848. if (fatal) {
  849. if (txh)
  850. trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
  851. sizeof(*txh));
  852. if (p)
  853. brcmu_pkt_buf_free_skb(p);
  854. }
  855. if (dma && queue < NFIFO) {
  856. u16 ac_queue = brcms_fifo_to_ac(queue);
  857. if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
  858. ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
  859. ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
  860. dma_kick_tx(dma);
  861. }
  862. return fatal;
  863. }
  864. /* process tx completion events in BMAC
  865. * Return true if more tx status need to be processed. false otherwise.
  866. */
  867. static bool
  868. brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
  869. {
  870. bool morepending = false;
  871. struct bcma_device *core;
  872. struct tx_status txstatus, *txs;
  873. u32 s1, s2;
  874. uint n = 0;
  875. /*
  876. * Param 'max_tx_num' indicates max. # tx status to process before
  877. * break out.
  878. */
  879. uint max_tx_num = bound ? TXSBND : -1;
  880. txs = &txstatus;
  881. core = wlc_hw->d11core;
  882. *fatal = false;
  883. s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
  884. while (!(*fatal)
  885. && (s1 & TXS_V)) {
  886. /* !give others some time to run! */
  887. if (n >= max_tx_num) {
  888. morepending = true;
  889. break;
  890. }
  891. if (s1 == 0xffffffff) {
  892. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  893. __func__);
  894. *fatal = true;
  895. return false;
  896. }
  897. s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
  898. txs->status = s1 & TXS_STATUS_MASK;
  899. txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
  900. txs->sequence = s2 & TXS_SEQ_MASK;
  901. txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
  902. txs->lasttxtime = 0;
  903. *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
  904. s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
  905. n++;
  906. }
  907. if (*fatal)
  908. return false;
  909. return morepending;
  910. }
  911. static void brcms_c_tbtt(struct brcms_c_info *wlc)
  912. {
  913. if (!wlc->bsscfg->BSS)
  914. /*
  915. * DirFrmQ is now valid...defer setting until end
  916. * of ATIM window
  917. */
  918. wlc->qvalid |= MCMD_DIRFRMQVAL;
  919. }
  920. /* set initial host flags value */
  921. static void
  922. brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
  923. {
  924. struct brcms_hardware *wlc_hw = wlc->hw;
  925. memset(mhfs, 0, MHFMAX * sizeof(u16));
  926. mhfs[MHF2] |= mhf2_init;
  927. /* prohibit use of slowclock on multifunction boards */
  928. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  929. mhfs[MHF1] |= MHF1_FORCEFASTCLK;
  930. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
  931. mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
  932. mhfs[MHF1] |= MHF1_IQSWAP_WAR;
  933. }
  934. }
  935. static uint
  936. dmareg(uint direction, uint fifonum)
  937. {
  938. if (direction == DMA_TX)
  939. return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
  940. return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
  941. }
  942. static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
  943. {
  944. uint i;
  945. char name[8];
  946. /*
  947. * ucode host flag 2 needed for pio mode, independent of band and fifo
  948. */
  949. u16 pio_mhf2 = 0;
  950. struct brcms_hardware *wlc_hw = wlc->hw;
  951. uint unit = wlc_hw->unit;
  952. /* name and offsets for dma_attach */
  953. snprintf(name, sizeof(name), "wl%d", unit);
  954. if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
  955. int dma_attach_err = 0;
  956. /*
  957. * FIFO 0
  958. * TX: TX_AC_BK_FIFO (TX AC Background data packets)
  959. * RX: RX_FIFO (RX data packets)
  960. */
  961. wlc_hw->di[0] = dma_attach(name, wlc,
  962. (wme ? dmareg(DMA_TX, 0) : 0),
  963. dmareg(DMA_RX, 0),
  964. (wme ? NTXD : 0), NRXD,
  965. RXBUFSZ, -1, NRXBUFPOST,
  966. BRCMS_HWRXOFF);
  967. dma_attach_err |= (NULL == wlc_hw->di[0]);
  968. /*
  969. * FIFO 1
  970. * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
  971. * (legacy) TX_DATA_FIFO (TX data packets)
  972. * RX: UNUSED
  973. */
  974. wlc_hw->di[1] = dma_attach(name, wlc,
  975. dmareg(DMA_TX, 1), 0,
  976. NTXD, 0, 0, -1, 0, 0);
  977. dma_attach_err |= (NULL == wlc_hw->di[1]);
  978. /*
  979. * FIFO 2
  980. * TX: TX_AC_VI_FIFO (TX AC Video data packets)
  981. * RX: UNUSED
  982. */
  983. wlc_hw->di[2] = dma_attach(name, wlc,
  984. dmareg(DMA_TX, 2), 0,
  985. NTXD, 0, 0, -1, 0, 0);
  986. dma_attach_err |= (NULL == wlc_hw->di[2]);
  987. /*
  988. * FIFO 3
  989. * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
  990. * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
  991. */
  992. wlc_hw->di[3] = dma_attach(name, wlc,
  993. dmareg(DMA_TX, 3),
  994. 0, NTXD, 0, 0, -1,
  995. 0, 0);
  996. dma_attach_err |= (NULL == wlc_hw->di[3]);
  997. /* Cleaner to leave this as if with AP defined */
  998. if (dma_attach_err) {
  999. brcms_err(wlc_hw->d11core,
  1000. "wl%d: wlc_attach: dma_attach failed\n",
  1001. unit);
  1002. return false;
  1003. }
  1004. /* get pointer to dma engine tx flow control variable */
  1005. for (i = 0; i < NFIFO; i++)
  1006. if (wlc_hw->di[i])
  1007. wlc_hw->txavail[i] =
  1008. (uint *) dma_getvar(wlc_hw->di[i],
  1009. "&txavail");
  1010. }
  1011. /* initial ucode host flags */
  1012. brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
  1013. return true;
  1014. }
  1015. static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
  1016. {
  1017. uint j;
  1018. for (j = 0; j < NFIFO; j++) {
  1019. if (wlc_hw->di[j]) {
  1020. dma_detach(wlc_hw->di[j]);
  1021. wlc_hw->di[j] = NULL;
  1022. }
  1023. }
  1024. }
  1025. /*
  1026. * Initialize brcms_c_info default values ...
  1027. * may get overrides later in this function
  1028. * BMAC_NOTES, move low out and resolve the dangling ones
  1029. */
  1030. static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
  1031. {
  1032. struct brcms_c_info *wlc = wlc_hw->wlc;
  1033. /* set default sw macintmask value */
  1034. wlc->defmacintmask = DEF_MACINTMASK;
  1035. /* various 802.11g modes */
  1036. wlc_hw->shortslot = false;
  1037. wlc_hw->SFBL = RETRY_SHORT_FB;
  1038. wlc_hw->LFBL = RETRY_LONG_FB;
  1039. /* default mac retry limits */
  1040. wlc_hw->SRL = RETRY_SHORT_DEF;
  1041. wlc_hw->LRL = RETRY_LONG_DEF;
  1042. wlc_hw->chanspec = ch20mhz_chspec(1);
  1043. }
  1044. static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
  1045. {
  1046. /* delay before first read of ucode state */
  1047. udelay(40);
  1048. /* wait until ucode is no longer asleep */
  1049. SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
  1050. DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
  1051. }
  1052. /* control chip clock to save power, enable dynamic clock or force fast clock */
  1053. static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
  1054. {
  1055. if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
  1056. /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
  1057. * on backplane, but mac core will still run on ALP(not HT) when
  1058. * it enters powersave mode, which means the FCA bit may not be
  1059. * set. Should wakeup mac if driver wants it to run on HT.
  1060. */
  1061. if (wlc_hw->clk) {
  1062. if (mode == BCMA_CLKMODE_FAST) {
  1063. bcma_set32(wlc_hw->d11core,
  1064. D11REGOFFS(clk_ctl_st),
  1065. CCS_FORCEHT);
  1066. udelay(64);
  1067. SPINWAIT(
  1068. ((bcma_read32(wlc_hw->d11core,
  1069. D11REGOFFS(clk_ctl_st)) &
  1070. CCS_HTAVAIL) == 0),
  1071. PMU_MAX_TRANSITION_DLY);
  1072. WARN_ON(!(bcma_read32(wlc_hw->d11core,
  1073. D11REGOFFS(clk_ctl_st)) &
  1074. CCS_HTAVAIL));
  1075. } else {
  1076. if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
  1077. (bcma_read32(wlc_hw->d11core,
  1078. D11REGOFFS(clk_ctl_st)) &
  1079. (CCS_FORCEHT | CCS_HTAREQ)))
  1080. SPINWAIT(
  1081. ((bcma_read32(wlc_hw->d11core,
  1082. offsetof(struct d11regs,
  1083. clk_ctl_st)) &
  1084. CCS_HTAVAIL) == 0),
  1085. PMU_MAX_TRANSITION_DLY);
  1086. bcma_mask32(wlc_hw->d11core,
  1087. D11REGOFFS(clk_ctl_st),
  1088. ~CCS_FORCEHT);
  1089. }
  1090. }
  1091. wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
  1092. } else {
  1093. /* old chips w/o PMU, force HT through cc,
  1094. * then use FCA to verify mac is running fast clock
  1095. */
  1096. wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
  1097. /* check fast clock is available (if core is not in reset) */
  1098. if (wlc_hw->forcefastclk && wlc_hw->clk)
  1099. WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
  1100. SISF_FCLKA));
  1101. /*
  1102. * keep the ucode wake bit on if forcefastclk is on since we
  1103. * do not want ucode to put us back to slow clock when it dozes
  1104. * for PM mode. Code below matches the wake override bit with
  1105. * current forcefastclk state. Only setting bit in wake_override
  1106. * instead of waking ucode immediately since old code had this
  1107. * behavior. Older code set wlc->forcefastclk but only had the
  1108. * wake happen if the wakup_ucode work (protected by an up
  1109. * check) was executed just below.
  1110. */
  1111. if (wlc_hw->forcefastclk)
  1112. mboolset(wlc_hw->wake_override,
  1113. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1114. else
  1115. mboolclr(wlc_hw->wake_override,
  1116. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1117. }
  1118. }
  1119. /* set or clear ucode host flag bits
  1120. * it has an optimization for no-change write
  1121. * it only writes through shared memory when the core has clock;
  1122. * pre-CLK changes should use wlc_write_mhf to get around the optimization
  1123. *
  1124. *
  1125. * bands values are: BRCM_BAND_AUTO <--- Current band only
  1126. * BRCM_BAND_5G <--- 5G band only
  1127. * BRCM_BAND_2G <--- 2G band only
  1128. * BRCM_BAND_ALL <--- All bands
  1129. */
  1130. void
  1131. brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
  1132. int bands)
  1133. {
  1134. u16 save;
  1135. u16 addr[MHFMAX] = {
  1136. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  1137. M_HOST_FLAGS5
  1138. };
  1139. struct brcms_hw_band *band;
  1140. if ((val & ~mask) || idx >= MHFMAX)
  1141. return; /* error condition */
  1142. switch (bands) {
  1143. /* Current band only or all bands,
  1144. * then set the band to current band
  1145. */
  1146. case BRCM_BAND_AUTO:
  1147. case BRCM_BAND_ALL:
  1148. band = wlc_hw->band;
  1149. break;
  1150. case BRCM_BAND_5G:
  1151. band = wlc_hw->bandstate[BAND_5G_INDEX];
  1152. break;
  1153. case BRCM_BAND_2G:
  1154. band = wlc_hw->bandstate[BAND_2G_INDEX];
  1155. break;
  1156. default:
  1157. band = NULL; /* error condition */
  1158. }
  1159. if (band) {
  1160. save = band->mhfs[idx];
  1161. band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
  1162. /* optimization: only write through if changed, and
  1163. * changed band is the current band
  1164. */
  1165. if (wlc_hw->clk && (band->mhfs[idx] != save)
  1166. && (band == wlc_hw->band))
  1167. brcms_b_write_shm(wlc_hw, addr[idx],
  1168. (u16) band->mhfs[idx]);
  1169. }
  1170. if (bands == BRCM_BAND_ALL) {
  1171. wlc_hw->bandstate[0]->mhfs[idx] =
  1172. (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
  1173. wlc_hw->bandstate[1]->mhfs[idx] =
  1174. (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
  1175. }
  1176. }
  1177. /* set the maccontrol register to desired reset state and
  1178. * initialize the sw cache of the register
  1179. */
  1180. static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
  1181. {
  1182. /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
  1183. wlc_hw->maccontrol = 0;
  1184. wlc_hw->suspended_fifos = 0;
  1185. wlc_hw->wake_override = 0;
  1186. wlc_hw->mute_override = 0;
  1187. brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
  1188. }
  1189. /*
  1190. * write the software state of maccontrol and
  1191. * overrides to the maccontrol register
  1192. */
  1193. static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
  1194. {
  1195. u32 maccontrol = wlc_hw->maccontrol;
  1196. /* OR in the wake bit if overridden */
  1197. if (wlc_hw->wake_override)
  1198. maccontrol |= MCTL_WAKE;
  1199. /* set AP and INFRA bits for mute if needed */
  1200. if (wlc_hw->mute_override) {
  1201. maccontrol &= ~(MCTL_AP);
  1202. maccontrol |= MCTL_INFRA;
  1203. }
  1204. bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
  1205. maccontrol);
  1206. }
  1207. /* set or clear maccontrol bits */
  1208. void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
  1209. {
  1210. u32 maccontrol;
  1211. u32 new_maccontrol;
  1212. if (val & ~mask)
  1213. return; /* error condition */
  1214. maccontrol = wlc_hw->maccontrol;
  1215. new_maccontrol = (maccontrol & ~mask) | val;
  1216. /* if the new maccontrol value is the same as the old, nothing to do */
  1217. if (new_maccontrol == maccontrol)
  1218. return;
  1219. /* something changed, cache the new value */
  1220. wlc_hw->maccontrol = new_maccontrol;
  1221. /* write the new values with overrides applied */
  1222. brcms_c_mctrl_write(wlc_hw);
  1223. }
  1224. void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
  1225. u32 override_bit)
  1226. {
  1227. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
  1228. mboolset(wlc_hw->wake_override, override_bit);
  1229. return;
  1230. }
  1231. mboolset(wlc_hw->wake_override, override_bit);
  1232. brcms_c_mctrl_write(wlc_hw);
  1233. brcms_b_wait_for_wake(wlc_hw);
  1234. }
  1235. void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
  1236. u32 override_bit)
  1237. {
  1238. mboolclr(wlc_hw->wake_override, override_bit);
  1239. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
  1240. return;
  1241. brcms_c_mctrl_write(wlc_hw);
  1242. }
  1243. /* When driver needs ucode to stop beaconing, it has to make sure that
  1244. * MCTL_AP is clear and MCTL_INFRA is set
  1245. * Mode MCTL_AP MCTL_INFRA
  1246. * AP 1 1
  1247. * STA 0 1 <--- This will ensure no beacons
  1248. * IBSS 0 0
  1249. */
  1250. static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
  1251. {
  1252. wlc_hw->mute_override = 1;
  1253. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1254. * override, then there is no change to write
  1255. */
  1256. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1257. return;
  1258. brcms_c_mctrl_write(wlc_hw);
  1259. }
  1260. /* Clear the override on AP and INFRA bits */
  1261. static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
  1262. {
  1263. if (wlc_hw->mute_override == 0)
  1264. return;
  1265. wlc_hw->mute_override = 0;
  1266. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1267. * override, then there is no change to write
  1268. */
  1269. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1270. return;
  1271. brcms_c_mctrl_write(wlc_hw);
  1272. }
  1273. /*
  1274. * Write a MAC address to the given match reg offset in the RXE match engine.
  1275. */
  1276. static void
  1277. brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
  1278. const u8 *addr)
  1279. {
  1280. struct bcma_device *core = wlc_hw->d11core;
  1281. u16 mac_l;
  1282. u16 mac_m;
  1283. u16 mac_h;
  1284. brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
  1285. mac_l = addr[0] | (addr[1] << 8);
  1286. mac_m = addr[2] | (addr[3] << 8);
  1287. mac_h = addr[4] | (addr[5] << 8);
  1288. /* enter the MAC addr into the RXE match registers */
  1289. bcma_write16(core, D11REGOFFS(rcm_ctl),
  1290. RCM_INC_DATA | match_reg_offset);
  1291. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
  1292. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
  1293. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
  1294. }
  1295. void
  1296. brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
  1297. void *buf)
  1298. {
  1299. struct bcma_device *core = wlc_hw->d11core;
  1300. u32 word;
  1301. __le32 word_le;
  1302. __be32 word_be;
  1303. bool be_bit;
  1304. brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
  1305. bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
  1306. /* if MCTL_BIGEND bit set in mac control register,
  1307. * the chip swaps data in fifo, as well as data in
  1308. * template ram
  1309. */
  1310. be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
  1311. while (len > 0) {
  1312. memcpy(&word, buf, sizeof(u32));
  1313. if (be_bit) {
  1314. word_be = cpu_to_be32(word);
  1315. word = *(u32 *)&word_be;
  1316. } else {
  1317. word_le = cpu_to_le32(word);
  1318. word = *(u32 *)&word_le;
  1319. }
  1320. bcma_write32(core, D11REGOFFS(tplatewrdata), word);
  1321. buf = (u8 *) buf + sizeof(u32);
  1322. len -= sizeof(u32);
  1323. }
  1324. }
  1325. static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
  1326. {
  1327. wlc_hw->band->CWmin = newmin;
  1328. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  1329. OBJADDR_SCR_SEL | S_DOT11_CWMIN);
  1330. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  1331. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
  1332. }
  1333. static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
  1334. {
  1335. wlc_hw->band->CWmax = newmax;
  1336. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  1337. OBJADDR_SCR_SEL | S_DOT11_CWMAX);
  1338. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  1339. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
  1340. }
  1341. void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
  1342. {
  1343. bool fastclk;
  1344. /* request FAST clock if not on */
  1345. fastclk = wlc_hw->forcefastclk;
  1346. if (!fastclk)
  1347. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  1348. wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
  1349. brcms_b_phy_reset(wlc_hw);
  1350. wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
  1351. /* restore the clk */
  1352. if (!fastclk)
  1353. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  1354. }
  1355. static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
  1356. {
  1357. u16 v;
  1358. struct brcms_c_info *wlc = wlc_hw->wlc;
  1359. /* update SYNTHPU_DLY */
  1360. if (BRCMS_ISLCNPHY(wlc->band))
  1361. v = SYNTHPU_DLY_LPPHY_US;
  1362. else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
  1363. v = SYNTHPU_DLY_NPHY_US;
  1364. else
  1365. v = SYNTHPU_DLY_BPHY_US;
  1366. brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
  1367. }
  1368. static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
  1369. {
  1370. u16 phyctl;
  1371. u16 phytxant = wlc_hw->bmac_phytxant;
  1372. u16 mask = PHY_TXC_ANT_MASK;
  1373. /* set the Probe Response frame phy control word */
  1374. phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
  1375. phyctl = (phyctl & ~mask) | phytxant;
  1376. brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
  1377. /* set the Response (ACK/CTS) frame phy control word */
  1378. phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
  1379. phyctl = (phyctl & ~mask) | phytxant;
  1380. brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
  1381. }
  1382. static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
  1383. u8 rate)
  1384. {
  1385. uint i;
  1386. u8 plcp_rate = 0;
  1387. struct plcp_signal_rate_lookup {
  1388. u8 rate;
  1389. u8 signal_rate;
  1390. };
  1391. /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
  1392. const struct plcp_signal_rate_lookup rate_lookup[] = {
  1393. {BRCM_RATE_6M, 0xB},
  1394. {BRCM_RATE_9M, 0xF},
  1395. {BRCM_RATE_12M, 0xA},
  1396. {BRCM_RATE_18M, 0xE},
  1397. {BRCM_RATE_24M, 0x9},
  1398. {BRCM_RATE_36M, 0xD},
  1399. {BRCM_RATE_48M, 0x8},
  1400. {BRCM_RATE_54M, 0xC}
  1401. };
  1402. for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
  1403. if (rate == rate_lookup[i].rate) {
  1404. plcp_rate = rate_lookup[i].signal_rate;
  1405. break;
  1406. }
  1407. }
  1408. /* Find the SHM pointer to the rate table entry by looking in the
  1409. * Direct-map Table
  1410. */
  1411. return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
  1412. }
  1413. static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
  1414. {
  1415. u8 rate;
  1416. u8 rates[8] = {
  1417. BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
  1418. BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
  1419. };
  1420. u16 entry_ptr;
  1421. u16 pctl1;
  1422. uint i;
  1423. if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
  1424. return;
  1425. /* walk the phy rate table and update the entries */
  1426. for (i = 0; i < ARRAY_SIZE(rates); i++) {
  1427. rate = rates[i];
  1428. entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
  1429. /* read the SHM Rate Table entry OFDM PCTL1 values */
  1430. pctl1 =
  1431. brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
  1432. /* modify the value */
  1433. pctl1 &= ~PHY_TXC1_MODE_MASK;
  1434. pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
  1435. /* Update the SHM Rate Table entry OFDM PCTL1 values */
  1436. brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
  1437. pctl1);
  1438. }
  1439. }
  1440. /* band-specific init */
  1441. static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
  1442. {
  1443. struct brcms_hardware *wlc_hw = wlc->hw;
  1444. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
  1445. wlc_hw->band->bandunit);
  1446. brcms_c_ucode_bsinit(wlc_hw);
  1447. wlc_phy_init(wlc_hw->band->pi, chanspec);
  1448. brcms_c_ucode_txant_set(wlc_hw);
  1449. /*
  1450. * cwmin is band-specific, update hardware
  1451. * with value for current band
  1452. */
  1453. brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
  1454. brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
  1455. brcms_b_update_slot_timing(wlc_hw,
  1456. wlc_hw->band->bandtype == BRCM_BAND_5G ?
  1457. true : wlc_hw->shortslot);
  1458. /* write phytype and phyvers */
  1459. brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
  1460. brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
  1461. /*
  1462. * initialize the txphyctl1 rate table since
  1463. * shmem is shared between bands
  1464. */
  1465. brcms_upd_ofdm_pctl1_table(wlc_hw);
  1466. brcms_b_upd_synthpu(wlc_hw);
  1467. }
  1468. /* Perform a soft reset of the PHY PLL */
  1469. void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
  1470. {
  1471. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
  1472. ~0, 0);
  1473. udelay(1);
  1474. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1475. 0x4, 0);
  1476. udelay(1);
  1477. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1478. 0x4, 4);
  1479. udelay(1);
  1480. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1481. 0x4, 0);
  1482. udelay(1);
  1483. }
  1484. /* light way to turn on phy clock without reset for NPHY only
  1485. * refer to brcms_b_core_phy_clk for full version
  1486. */
  1487. void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
  1488. {
  1489. /* support(necessary for NPHY and HYPHY) only */
  1490. if (!BRCMS_ISNPHY(wlc_hw->band))
  1491. return;
  1492. if (ON == clk)
  1493. brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
  1494. else
  1495. brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
  1496. }
  1497. void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
  1498. {
  1499. if (ON == clk)
  1500. brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
  1501. else
  1502. brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
  1503. }
  1504. void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
  1505. {
  1506. struct brcms_phy_pub *pih = wlc_hw->band->pi;
  1507. u32 phy_bw_clkbits;
  1508. bool phy_in_reset = false;
  1509. brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
  1510. if (pih == NULL)
  1511. return;
  1512. phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
  1513. /* Specific reset sequence required for NPHY rev 3 and 4 */
  1514. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
  1515. NREV_LE(wlc_hw->band->phyrev, 4)) {
  1516. /* Set the PHY bandwidth */
  1517. brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
  1518. udelay(1);
  1519. /* Perform a soft reset of the PHY PLL */
  1520. brcms_b_core_phypll_reset(wlc_hw);
  1521. /* reset the PHY */
  1522. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
  1523. (SICF_PRST | SICF_PCLKE));
  1524. phy_in_reset = true;
  1525. } else {
  1526. brcms_b_core_ioctl(wlc_hw,
  1527. (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
  1528. (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
  1529. }
  1530. udelay(2);
  1531. brcms_b_core_phy_clk(wlc_hw, ON);
  1532. if (pih)
  1533. wlc_phy_anacore(pih, ON);
  1534. }
  1535. /* switch to and initialize new band */
  1536. static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
  1537. u16 chanspec) {
  1538. struct brcms_c_info *wlc = wlc_hw->wlc;
  1539. u32 macintmask;
  1540. /* Enable the d11 core before accessing it */
  1541. if (!bcma_core_is_enabled(wlc_hw->d11core)) {
  1542. bcma_core_enable(wlc_hw->d11core, 0);
  1543. brcms_c_mctrl_reset(wlc_hw);
  1544. }
  1545. macintmask = brcms_c_setband_inact(wlc, bandunit);
  1546. if (!wlc_hw->up)
  1547. return;
  1548. brcms_b_core_phy_clk(wlc_hw, ON);
  1549. /* band-specific initializations */
  1550. brcms_b_bsinit(wlc, chanspec);
  1551. /*
  1552. * If there are any pending software interrupt bits,
  1553. * then replace these with a harmless nonzero value
  1554. * so brcms_c_dpc() will re-enable interrupts when done.
  1555. */
  1556. if (wlc->macintstatus)
  1557. wlc->macintstatus = MI_DMAINT;
  1558. /* restore macintmask */
  1559. brcms_intrsrestore(wlc->wl, macintmask);
  1560. /* ucode should still be suspended.. */
  1561. WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
  1562. MCTL_EN_MAC) != 0);
  1563. }
  1564. static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
  1565. {
  1566. /* reject unsupported corerev */
  1567. if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
  1568. wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
  1569. wlc_hw->corerev);
  1570. return false;
  1571. }
  1572. return true;
  1573. }
  1574. /* Validate some board info parameters */
  1575. static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
  1576. {
  1577. uint boardrev = wlc_hw->boardrev;
  1578. /* 4 bits each for board type, major, minor, and tiny version */
  1579. uint brt = (boardrev & 0xf000) >> 12;
  1580. uint b0 = (boardrev & 0xf00) >> 8;
  1581. uint b1 = (boardrev & 0xf0) >> 4;
  1582. uint b2 = boardrev & 0xf;
  1583. /* voards from other vendors are always considered valid */
  1584. if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
  1585. return true;
  1586. /* do some boardrev sanity checks when boardvendor is Broadcom */
  1587. if (boardrev == 0)
  1588. return false;
  1589. if (boardrev <= 0xff)
  1590. return true;
  1591. if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
  1592. || (b2 > 9))
  1593. return false;
  1594. return true;
  1595. }
  1596. static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
  1597. {
  1598. struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
  1599. /* If macaddr exists, use it (Sromrev4, CIS, ...). */
  1600. if (!is_zero_ether_addr(sprom->il0mac)) {
  1601. memcpy(etheraddr, sprom->il0mac, 6);
  1602. return;
  1603. }
  1604. if (wlc_hw->_nbands > 1)
  1605. memcpy(etheraddr, sprom->et1mac, 6);
  1606. else
  1607. memcpy(etheraddr, sprom->il0mac, 6);
  1608. }
  1609. /* power both the pll and external oscillator on/off */
  1610. static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
  1611. {
  1612. brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
  1613. /*
  1614. * dont power down if plldown is false or
  1615. * we must poll hw radio disable
  1616. */
  1617. if (!want && wlc_hw->pllreq)
  1618. return;
  1619. wlc_hw->sbclk = want;
  1620. if (!wlc_hw->sbclk) {
  1621. wlc_hw->clk = false;
  1622. if (wlc_hw->band && wlc_hw->band->pi)
  1623. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  1624. }
  1625. }
  1626. /*
  1627. * Return true if radio is disabled, otherwise false.
  1628. * hw radio disable signal is an external pin, users activate it asynchronously
  1629. * this function could be called when driver is down and w/o clock
  1630. * it operates on different registers depending on corerev and boardflag.
  1631. */
  1632. static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
  1633. {
  1634. bool v, clk, xtal;
  1635. u32 flags = 0;
  1636. xtal = wlc_hw->sbclk;
  1637. if (!xtal)
  1638. brcms_b_xtal(wlc_hw, ON);
  1639. /* may need to take core out of reset first */
  1640. clk = wlc_hw->clk;
  1641. if (!clk) {
  1642. /*
  1643. * mac no longer enables phyclk automatically when driver
  1644. * accesses phyreg throughput mac. This can be skipped since
  1645. * only mac reg is accessed below
  1646. */
  1647. if (D11REV_GE(wlc_hw->corerev, 18))
  1648. flags |= SICF_PCLKE;
  1649. /*
  1650. * TODO: test suspend/resume
  1651. *
  1652. * AI chip doesn't restore bar0win2 on
  1653. * hibernation/resume, need sw fixup
  1654. */
  1655. bcma_core_enable(wlc_hw->d11core, flags);
  1656. brcms_c_mctrl_reset(wlc_hw);
  1657. }
  1658. v = ((bcma_read32(wlc_hw->d11core,
  1659. D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
  1660. /* put core back into reset */
  1661. if (!clk)
  1662. bcma_core_disable(wlc_hw->d11core, 0);
  1663. if (!xtal)
  1664. brcms_b_xtal(wlc_hw, OFF);
  1665. return v;
  1666. }
  1667. static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
  1668. {
  1669. struct dma_pub *di = wlc_hw->di[fifo];
  1670. return dma_rxreset(di);
  1671. }
  1672. /* d11 core reset
  1673. * ensure fask clock during reset
  1674. * reset dma
  1675. * reset d11(out of reset)
  1676. * reset phy(out of reset)
  1677. * clear software macintstatus for fresh new start
  1678. * one testing hack wlc_hw->noreset will bypass the d11/phy reset
  1679. */
  1680. void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
  1681. {
  1682. uint i;
  1683. bool fastclk;
  1684. if (flags == BRCMS_USE_COREFLAGS)
  1685. flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
  1686. brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
  1687. /* request FAST clock if not on */
  1688. fastclk = wlc_hw->forcefastclk;
  1689. if (!fastclk)
  1690. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  1691. /* reset the dma engines except first time thru */
  1692. if (bcma_core_is_enabled(wlc_hw->d11core)) {
  1693. for (i = 0; i < NFIFO; i++)
  1694. if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
  1695. brcms_err(wlc_hw->d11core, "wl%d: %s: "
  1696. "dma_txreset[%d]: cannot stop dma\n",
  1697. wlc_hw->unit, __func__, i);
  1698. if ((wlc_hw->di[RX_FIFO])
  1699. && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
  1700. brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
  1701. "[%d]: cannot stop dma\n",
  1702. wlc_hw->unit, __func__, RX_FIFO);
  1703. }
  1704. /* if noreset, just stop the psm and return */
  1705. if (wlc_hw->noreset) {
  1706. wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
  1707. brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
  1708. return;
  1709. }
  1710. /*
  1711. * mac no longer enables phyclk automatically when driver accesses
  1712. * phyreg throughput mac, AND phy_reset is skipped at early stage when
  1713. * band->pi is invalid. need to enable PHY CLK
  1714. */
  1715. if (D11REV_GE(wlc_hw->corerev, 18))
  1716. flags |= SICF_PCLKE;
  1717. /*
  1718. * reset the core
  1719. * In chips with PMU, the fastclk request goes through d11 core
  1720. * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
  1721. *
  1722. * This adds some delay and we can optimize it by also requesting
  1723. * fastclk through chipcommon during this period if necessary. But
  1724. * that has to work coordinate with other driver like mips/arm since
  1725. * they may touch chipcommon as well.
  1726. */
  1727. wlc_hw->clk = false;
  1728. bcma_core_enable(wlc_hw->d11core, flags);
  1729. wlc_hw->clk = true;
  1730. if (wlc_hw->band && wlc_hw->band->pi)
  1731. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
  1732. brcms_c_mctrl_reset(wlc_hw);
  1733. if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
  1734. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  1735. brcms_b_phy_reset(wlc_hw);
  1736. /* turn on PHY_PLL */
  1737. brcms_b_core_phypll_ctl(wlc_hw, true);
  1738. /* clear sw intstatus */
  1739. wlc_hw->wlc->macintstatus = 0;
  1740. /* restore the clk setting */
  1741. if (!fastclk)
  1742. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  1743. }
  1744. /* txfifo sizes needs to be modified(increased) since the newer cores
  1745. * have more memory.
  1746. */
  1747. static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
  1748. {
  1749. struct bcma_device *core = wlc_hw->d11core;
  1750. u16 fifo_nu;
  1751. u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
  1752. u16 txfifo_def, txfifo_def1;
  1753. u16 txfifo_cmd;
  1754. /* tx fifos start at TXFIFO_START_BLK from the Base address */
  1755. txfifo_startblk = TXFIFO_START_BLK;
  1756. /* sequence of operations: reset fifo, set fifo size, reset fifo */
  1757. for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
  1758. txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
  1759. txfifo_def = (txfifo_startblk & 0xff) |
  1760. (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
  1761. txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
  1762. ((((txfifo_endblk -
  1763. 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
  1764. txfifo_cmd =
  1765. TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
  1766. bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
  1767. bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
  1768. bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
  1769. bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
  1770. txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
  1771. }
  1772. /*
  1773. * need to propagate to shm location to be in sync since ucode/hw won't
  1774. * do this
  1775. */
  1776. brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
  1777. wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
  1778. brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
  1779. wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
  1780. brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
  1781. ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
  1782. xmtfifo_sz[TX_AC_BK_FIFO]));
  1783. brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
  1784. ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
  1785. xmtfifo_sz[TX_BCMC_FIFO]));
  1786. }
  1787. /* This function is used for changing the tsf frac register
  1788. * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
  1789. * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
  1790. * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
  1791. * HTPHY Formula is 2^26/freq(MHz) e.g.
  1792. * For spuron2 - 126MHz -> 2^26/126 = 532610.0
  1793. * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
  1794. * For spuron: 123MHz -> 2^26/123 = 545600.5
  1795. * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
  1796. * For spur off: 120MHz -> 2^26/120 = 559240.5
  1797. * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
  1798. */
  1799. void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
  1800. {
  1801. struct bcma_device *core = wlc_hw->d11core;
  1802. if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
  1803. (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
  1804. if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
  1805. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
  1806. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1807. } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
  1808. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
  1809. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1810. } else { /* 120Mhz */
  1811. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
  1812. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1813. }
  1814. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1815. if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
  1816. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
  1817. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
  1818. } else { /* 80Mhz */
  1819. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
  1820. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
  1821. }
  1822. }
  1823. }
  1824. /* Initialize GPIOs that are controlled by D11 core */
  1825. static void brcms_c_gpio_init(struct brcms_c_info *wlc)
  1826. {
  1827. struct brcms_hardware *wlc_hw = wlc->hw;
  1828. u32 gc, gm;
  1829. /* use GPIO select 0 to get all gpio signals from the gpio out reg */
  1830. brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
  1831. /*
  1832. * Common GPIO setup:
  1833. * G0 = LED 0 = WLAN Activity
  1834. * G1 = LED 1 = WLAN 2.4 GHz Radio State
  1835. * G2 = LED 2 = WLAN 5 GHz Radio State
  1836. * G4 = radio disable input (HI enabled, LO disabled)
  1837. */
  1838. gc = gm = 0;
  1839. /* Allocate GPIOs for mimo antenna diversity feature */
  1840. if (wlc_hw->antsel_type == ANTSEL_2x3) {
  1841. /* Enable antenna diversity, use 2x3 mode */
  1842. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1843. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1844. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
  1845. MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
  1846. /* init superswitch control */
  1847. wlc_phy_antsel_init(wlc_hw->band->pi, false);
  1848. } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
  1849. gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
  1850. /*
  1851. * The board itself is powered by these GPIOs
  1852. * (when not sending pattern) so set them high
  1853. */
  1854. bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
  1855. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1856. bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
  1857. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1858. /* Enable antenna diversity, use 2x4 mode */
  1859. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1860. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1861. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
  1862. BRCM_BAND_ALL);
  1863. /* Configure the desired clock to be 4Mhz */
  1864. brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
  1865. ANTSEL_CLKDIV_4MHZ);
  1866. }
  1867. /*
  1868. * gpio 9 controls the PA. ucode is responsible
  1869. * for wiggling out and oe
  1870. */
  1871. if (wlc_hw->boardflags & BFL_PACTRL)
  1872. gm |= gc |= BOARD_GPIO_PACTRL;
  1873. /* apply to gpiocontrol register */
  1874. bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
  1875. }
  1876. static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
  1877. const __le32 ucode[], const size_t nbytes)
  1878. {
  1879. struct bcma_device *core = wlc_hw->d11core;
  1880. uint i;
  1881. uint count;
  1882. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  1883. count = (nbytes / sizeof(u32));
  1884. bcma_write32(core, D11REGOFFS(objaddr),
  1885. OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
  1886. (void)bcma_read32(core, D11REGOFFS(objaddr));
  1887. for (i = 0; i < count; i++)
  1888. bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
  1889. }
  1890. static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
  1891. {
  1892. struct brcms_c_info *wlc;
  1893. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  1894. wlc = wlc_hw->wlc;
  1895. if (wlc_hw->ucode_loaded)
  1896. return;
  1897. if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
  1898. if (BRCMS_ISNPHY(wlc_hw->band)) {
  1899. brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
  1900. ucode->bcm43xx_16_mimosz);
  1901. wlc_hw->ucode_loaded = true;
  1902. } else
  1903. brcms_err(wlc_hw->d11core,
  1904. "%s: wl%d: unsupported phy in corerev %d\n",
  1905. __func__, wlc_hw->unit, wlc_hw->corerev);
  1906. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  1907. if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1908. brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
  1909. ucode->bcm43xx_24_lcnsz);
  1910. wlc_hw->ucode_loaded = true;
  1911. } else {
  1912. brcms_err(wlc_hw->d11core,
  1913. "%s: wl%d: unsupported phy in corerev %d\n",
  1914. __func__, wlc_hw->unit, wlc_hw->corerev);
  1915. }
  1916. }
  1917. }
  1918. void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
  1919. {
  1920. /* update sw state */
  1921. wlc_hw->bmac_phytxant = phytxant;
  1922. /* push to ucode if up */
  1923. if (!wlc_hw->up)
  1924. return;
  1925. brcms_c_ucode_txant_set(wlc_hw);
  1926. }
  1927. u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
  1928. {
  1929. return (u16) wlc_hw->wlc->stf->txant;
  1930. }
  1931. void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
  1932. {
  1933. wlc_hw->antsel_type = antsel_type;
  1934. /* Update the antsel type for phy module to use */
  1935. wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
  1936. }
  1937. static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
  1938. {
  1939. bool fatal = false;
  1940. uint unit;
  1941. uint intstatus, idx;
  1942. struct bcma_device *core = wlc_hw->d11core;
  1943. unit = wlc_hw->unit;
  1944. for (idx = 0; idx < NFIFO; idx++) {
  1945. /* read intstatus register and ignore any non-error bits */
  1946. intstatus =
  1947. bcma_read32(core,
  1948. D11REGOFFS(intctrlregs[idx].intstatus)) &
  1949. I_ERRORS;
  1950. if (!intstatus)
  1951. continue;
  1952. brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
  1953. unit, idx, intstatus);
  1954. if (intstatus & I_RO) {
  1955. brcms_err(core, "wl%d: fifo %d: receive fifo "
  1956. "overflow\n", unit, idx);
  1957. fatal = true;
  1958. }
  1959. if (intstatus & I_PC) {
  1960. brcms_err(core, "wl%d: fifo %d: descriptor error\n",
  1961. unit, idx);
  1962. fatal = true;
  1963. }
  1964. if (intstatus & I_PD) {
  1965. brcms_err(core, "wl%d: fifo %d: data error\n", unit,
  1966. idx);
  1967. fatal = true;
  1968. }
  1969. if (intstatus & I_DE) {
  1970. brcms_err(core, "wl%d: fifo %d: descriptor protocol "
  1971. "error\n", unit, idx);
  1972. fatal = true;
  1973. }
  1974. if (intstatus & I_RU)
  1975. brcms_err(core, "wl%d: fifo %d: receive descriptor "
  1976. "underflow\n", idx, unit);
  1977. if (intstatus & I_XU) {
  1978. brcms_err(core, "wl%d: fifo %d: transmit fifo "
  1979. "underflow\n", idx, unit);
  1980. fatal = true;
  1981. }
  1982. if (fatal) {
  1983. brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
  1984. break;
  1985. } else
  1986. bcma_write32(core,
  1987. D11REGOFFS(intctrlregs[idx].intstatus),
  1988. intstatus);
  1989. }
  1990. }
  1991. void brcms_c_intrson(struct brcms_c_info *wlc)
  1992. {
  1993. struct brcms_hardware *wlc_hw = wlc->hw;
  1994. wlc->macintmask = wlc->defmacintmask;
  1995. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
  1996. }
  1997. u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
  1998. {
  1999. struct brcms_hardware *wlc_hw = wlc->hw;
  2000. u32 macintmask;
  2001. if (!wlc_hw->clk)
  2002. return 0;
  2003. macintmask = wlc->macintmask; /* isr can still happen */
  2004. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
  2005. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
  2006. udelay(1); /* ensure int line is no longer driven */
  2007. wlc->macintmask = 0;
  2008. /* return previous macintmask; resolve race between us and our isr */
  2009. return wlc->macintstatus ? 0 : macintmask;
  2010. }
  2011. void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
  2012. {
  2013. struct brcms_hardware *wlc_hw = wlc->hw;
  2014. if (!wlc_hw->clk)
  2015. return;
  2016. wlc->macintmask = macintmask;
  2017. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
  2018. }
  2019. /* assumes that the d11 MAC is enabled */
  2020. static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
  2021. uint tx_fifo)
  2022. {
  2023. u8 fifo = 1 << tx_fifo;
  2024. /* Two clients of this code, 11h Quiet period and scanning. */
  2025. /* only suspend if not already suspended */
  2026. if ((wlc_hw->suspended_fifos & fifo) == fifo)
  2027. return;
  2028. /* force the core awake only if not already */
  2029. if (wlc_hw->suspended_fifos == 0)
  2030. brcms_c_ucode_wake_override_set(wlc_hw,
  2031. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2032. wlc_hw->suspended_fifos |= fifo;
  2033. if (wlc_hw->di[tx_fifo]) {
  2034. /*
  2035. * Suspending AMPDU transmissions in the middle can cause
  2036. * underflow which may result in mismatch between ucode and
  2037. * driver so suspend the mac before suspending the FIFO
  2038. */
  2039. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2040. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  2041. dma_txsuspend(wlc_hw->di[tx_fifo]);
  2042. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2043. brcms_c_enable_mac(wlc_hw->wlc);
  2044. }
  2045. }
  2046. static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
  2047. uint tx_fifo)
  2048. {
  2049. /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
  2050. * but need to be done here for PIO otherwise the watchdog will catch
  2051. * the inconsistency and fire
  2052. */
  2053. /* Two clients of this code, 11h Quiet period and scanning. */
  2054. if (wlc_hw->di[tx_fifo])
  2055. dma_txresume(wlc_hw->di[tx_fifo]);
  2056. /* allow core to sleep again */
  2057. if (wlc_hw->suspended_fifos == 0)
  2058. return;
  2059. else {
  2060. wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
  2061. if (wlc_hw->suspended_fifos == 0)
  2062. brcms_c_ucode_wake_override_clear(wlc_hw,
  2063. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2064. }
  2065. }
  2066. /* precondition: requires the mac core to be enabled */
  2067. static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
  2068. {
  2069. static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
  2070. u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
  2071. if (mute_tx) {
  2072. /* suspend tx fifos */
  2073. brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
  2074. brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
  2075. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
  2076. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
  2077. /* zero the address match register so we do not send ACKs */
  2078. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
  2079. } else {
  2080. /* resume tx fifos */
  2081. brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
  2082. brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
  2083. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
  2084. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
  2085. /* Restore address */
  2086. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
  2087. }
  2088. wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
  2089. if (mute_tx)
  2090. brcms_c_ucode_mute_override_set(wlc_hw);
  2091. else
  2092. brcms_c_ucode_mute_override_clear(wlc_hw);
  2093. }
  2094. void
  2095. brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
  2096. {
  2097. brcms_b_mute(wlc->hw, mute_tx);
  2098. }
  2099. /*
  2100. * Read and clear macintmask and macintstatus and intstatus registers.
  2101. * This routine should be called with interrupts off
  2102. * Return:
  2103. * -1 if brcms_deviceremoved(wlc) evaluates to true;
  2104. * 0 if the interrupt is not for us, or we are in some special cases;
  2105. * device interrupt status bits otherwise.
  2106. */
  2107. static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
  2108. {
  2109. struct brcms_hardware *wlc_hw = wlc->hw;
  2110. struct bcma_device *core = wlc_hw->d11core;
  2111. u32 macintstatus, mask;
  2112. /* macintstatus includes a DMA interrupt summary bit */
  2113. macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
  2114. mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
  2115. trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
  2116. /* detect cardbus removed, in power down(suspend) and in reset */
  2117. if (brcms_deviceremoved(wlc))
  2118. return -1;
  2119. /* brcms_deviceremoved() succeeds even when the core is still resetting,
  2120. * handle that case here.
  2121. */
  2122. if (macintstatus == 0xffffffff)
  2123. return 0;
  2124. /* defer unsolicited interrupts */
  2125. macintstatus &= mask;
  2126. /* if not for us */
  2127. if (macintstatus == 0)
  2128. return 0;
  2129. /* turn off the interrupts */
  2130. bcma_write32(core, D11REGOFFS(macintmask), 0);
  2131. (void)bcma_read32(core, D11REGOFFS(macintmask));
  2132. wlc->macintmask = 0;
  2133. /* clear device interrupts */
  2134. bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
  2135. /* MI_DMAINT is indication of non-zero intstatus */
  2136. if (macintstatus & MI_DMAINT)
  2137. /*
  2138. * only fifo interrupt enabled is I_RI in
  2139. * RX_FIFO. If MI_DMAINT is set, assume it
  2140. * is set and clear the interrupt.
  2141. */
  2142. bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
  2143. DEF_RXINTMASK);
  2144. return macintstatus;
  2145. }
  2146. /* Update wlc->macintstatus and wlc->intstatus[]. */
  2147. /* Return true if they are updated successfully. false otherwise */
  2148. bool brcms_c_intrsupd(struct brcms_c_info *wlc)
  2149. {
  2150. u32 macintstatus;
  2151. /* read and clear macintstatus and intstatus registers */
  2152. macintstatus = wlc_intstatus(wlc, false);
  2153. /* device is removed */
  2154. if (macintstatus == 0xffffffff)
  2155. return false;
  2156. /* update interrupt status in software */
  2157. wlc->macintstatus |= macintstatus;
  2158. return true;
  2159. }
  2160. /*
  2161. * First-level interrupt processing.
  2162. * Return true if this was our interrupt
  2163. * and if further brcms_c_dpc() processing is required,
  2164. * false otherwise.
  2165. */
  2166. bool brcms_c_isr(struct brcms_c_info *wlc)
  2167. {
  2168. struct brcms_hardware *wlc_hw = wlc->hw;
  2169. u32 macintstatus;
  2170. if (!wlc_hw->up || !wlc->macintmask)
  2171. return false;
  2172. /* read and clear macintstatus and intstatus registers */
  2173. macintstatus = wlc_intstatus(wlc, true);
  2174. if (macintstatus == 0xffffffff) {
  2175. brcms_err(wlc_hw->d11core,
  2176. "DEVICEREMOVED detected in the ISR code path\n");
  2177. return false;
  2178. }
  2179. /* it is not for us */
  2180. if (macintstatus == 0)
  2181. return false;
  2182. /* save interrupt status bits */
  2183. wlc->macintstatus = macintstatus;
  2184. return true;
  2185. }
  2186. void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
  2187. {
  2188. struct brcms_hardware *wlc_hw = wlc->hw;
  2189. struct bcma_device *core = wlc_hw->d11core;
  2190. u32 mc, mi;
  2191. brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
  2192. wlc_hw->band->bandunit);
  2193. /*
  2194. * Track overlapping suspend requests
  2195. */
  2196. wlc_hw->mac_suspend_depth++;
  2197. if (wlc_hw->mac_suspend_depth > 1)
  2198. return;
  2199. /* force the core awake */
  2200. brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2201. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2202. if (mc == 0xffffffff) {
  2203. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2204. __func__);
  2205. brcms_down(wlc->wl);
  2206. return;
  2207. }
  2208. WARN_ON(mc & MCTL_PSM_JMP_0);
  2209. WARN_ON(!(mc & MCTL_PSM_RUN));
  2210. WARN_ON(!(mc & MCTL_EN_MAC));
  2211. mi = bcma_read32(core, D11REGOFFS(macintstatus));
  2212. if (mi == 0xffffffff) {
  2213. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2214. __func__);
  2215. brcms_down(wlc->wl);
  2216. return;
  2217. }
  2218. WARN_ON(mi & MI_MACSSPNDD);
  2219. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
  2220. SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
  2221. BRCMS_MAX_MAC_SUSPEND);
  2222. if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
  2223. brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
  2224. " and MI_MACSSPNDD is still not on.\n",
  2225. wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
  2226. brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
  2227. "psm_brc 0x%04x\n", wlc_hw->unit,
  2228. bcma_read32(core, D11REGOFFS(psmdebug)),
  2229. bcma_read32(core, D11REGOFFS(phydebug)),
  2230. bcma_read16(core, D11REGOFFS(psm_brc)));
  2231. }
  2232. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2233. if (mc == 0xffffffff) {
  2234. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2235. __func__);
  2236. brcms_down(wlc->wl);
  2237. return;
  2238. }
  2239. WARN_ON(mc & MCTL_PSM_JMP_0);
  2240. WARN_ON(!(mc & MCTL_PSM_RUN));
  2241. WARN_ON(mc & MCTL_EN_MAC);
  2242. }
  2243. void brcms_c_enable_mac(struct brcms_c_info *wlc)
  2244. {
  2245. struct brcms_hardware *wlc_hw = wlc->hw;
  2246. struct bcma_device *core = wlc_hw->d11core;
  2247. u32 mc, mi;
  2248. brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
  2249. wlc->band->bandunit);
  2250. /*
  2251. * Track overlapping suspend requests
  2252. */
  2253. wlc_hw->mac_suspend_depth--;
  2254. if (wlc_hw->mac_suspend_depth > 0)
  2255. return;
  2256. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2257. WARN_ON(mc & MCTL_PSM_JMP_0);
  2258. WARN_ON(mc & MCTL_EN_MAC);
  2259. WARN_ON(!(mc & MCTL_PSM_RUN));
  2260. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
  2261. bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
  2262. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2263. WARN_ON(mc & MCTL_PSM_JMP_0);
  2264. WARN_ON(!(mc & MCTL_EN_MAC));
  2265. WARN_ON(!(mc & MCTL_PSM_RUN));
  2266. mi = bcma_read32(core, D11REGOFFS(macintstatus));
  2267. WARN_ON(mi & MI_MACSSPNDD);
  2268. brcms_c_ucode_wake_override_clear(wlc_hw,
  2269. BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2270. }
  2271. void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
  2272. {
  2273. wlc_hw->hw_stf_ss_opmode = stf_mode;
  2274. if (wlc_hw->clk)
  2275. brcms_upd_ofdm_pctl1_table(wlc_hw);
  2276. }
  2277. static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
  2278. {
  2279. struct bcma_device *core = wlc_hw->d11core;
  2280. u32 w, val;
  2281. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  2282. /* Validate dchip register access */
  2283. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2284. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2285. w = bcma_read32(core, D11REGOFFS(objdata));
  2286. /* Can we write and read back a 32bit register? */
  2287. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2288. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2289. bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
  2290. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2291. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2292. val = bcma_read32(core, D11REGOFFS(objdata));
  2293. if (val != (u32) 0xaa5555aa) {
  2294. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2295. "expected 0xaa5555aa\n", wlc_hw->unit, val);
  2296. return false;
  2297. }
  2298. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2299. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2300. bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
  2301. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2302. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2303. val = bcma_read32(core, D11REGOFFS(objdata));
  2304. if (val != (u32) 0x55aaaa55) {
  2305. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2306. "expected 0x55aaaa55\n", wlc_hw->unit, val);
  2307. return false;
  2308. }
  2309. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2310. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2311. bcma_write32(core, D11REGOFFS(objdata), w);
  2312. /* clear CFPStart */
  2313. bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
  2314. w = bcma_read32(core, D11REGOFFS(maccontrol));
  2315. if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
  2316. (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
  2317. wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
  2318. "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
  2319. (MCTL_IHR_EN | MCTL_WAKE),
  2320. (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
  2321. return false;
  2322. }
  2323. return true;
  2324. }
  2325. #define PHYPLL_WAIT_US 100000
  2326. void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
  2327. {
  2328. struct bcma_device *core = wlc_hw->d11core;
  2329. u32 tmp;
  2330. brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
  2331. tmp = 0;
  2332. if (on) {
  2333. if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
  2334. bcma_set32(core, D11REGOFFS(clk_ctl_st),
  2335. CCS_ERSRC_REQ_HT |
  2336. CCS_ERSRC_REQ_D11PLL |
  2337. CCS_ERSRC_REQ_PHYPLL);
  2338. SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
  2339. CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
  2340. PHYPLL_WAIT_US);
  2341. tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2342. if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
  2343. brcms_err(core, "%s: turn on PHY PLL failed\n",
  2344. __func__);
  2345. } else {
  2346. bcma_set32(core, D11REGOFFS(clk_ctl_st),
  2347. tmp | CCS_ERSRC_REQ_D11PLL |
  2348. CCS_ERSRC_REQ_PHYPLL);
  2349. SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
  2350. (CCS_ERSRC_AVAIL_D11PLL |
  2351. CCS_ERSRC_AVAIL_PHYPLL)) !=
  2352. (CCS_ERSRC_AVAIL_D11PLL |
  2353. CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
  2354. tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2355. if ((tmp &
  2356. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2357. !=
  2358. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2359. brcms_err(core, "%s: turn on PHY PLL failed\n",
  2360. __func__);
  2361. }
  2362. } else {
  2363. /*
  2364. * Since the PLL may be shared, other cores can still
  2365. * be requesting it; so we'll deassert the request but
  2366. * not wait for status to comply.
  2367. */
  2368. bcma_mask32(core, D11REGOFFS(clk_ctl_st),
  2369. ~CCS_ERSRC_REQ_PHYPLL);
  2370. (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2371. }
  2372. }
  2373. static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
  2374. {
  2375. bool dev_gone;
  2376. brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
  2377. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  2378. if (dev_gone)
  2379. return;
  2380. if (wlc_hw->noreset)
  2381. return;
  2382. /* radio off */
  2383. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  2384. /* turn off analog core */
  2385. wlc_phy_anacore(wlc_hw->band->pi, OFF);
  2386. /* turn off PHYPLL to save power */
  2387. brcms_b_core_phypll_ctl(wlc_hw, false);
  2388. wlc_hw->clk = false;
  2389. bcma_core_disable(wlc_hw->d11core, 0);
  2390. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  2391. }
  2392. static void brcms_c_flushqueues(struct brcms_c_info *wlc)
  2393. {
  2394. struct brcms_hardware *wlc_hw = wlc->hw;
  2395. uint i;
  2396. /* free any posted tx packets */
  2397. for (i = 0; i < NFIFO; i++) {
  2398. if (wlc_hw->di[i]) {
  2399. dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
  2400. if (i < TX_BCMC_FIFO)
  2401. ieee80211_wake_queue(wlc->pub->ieee_hw,
  2402. brcms_fifo_to_ac(i));
  2403. }
  2404. }
  2405. /* free any posted rx packets */
  2406. dma_rxreclaim(wlc_hw->di[RX_FIFO]);
  2407. }
  2408. static u16
  2409. brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
  2410. {
  2411. struct bcma_device *core = wlc_hw->d11core;
  2412. u16 objoff = D11REGOFFS(objdata);
  2413. bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
  2414. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2415. if (offset & 2)
  2416. objoff += 2;
  2417. return bcma_read16(core, objoff);
  2418. }
  2419. static void
  2420. brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
  2421. u32 sel)
  2422. {
  2423. struct bcma_device *core = wlc_hw->d11core;
  2424. u16 objoff = D11REGOFFS(objdata);
  2425. bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
  2426. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2427. if (offset & 2)
  2428. objoff += 2;
  2429. bcma_wflush16(core, objoff, v);
  2430. }
  2431. /*
  2432. * Read a single u16 from shared memory.
  2433. * SHM 'offset' needs to be an even address
  2434. */
  2435. u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
  2436. {
  2437. return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
  2438. }
  2439. /*
  2440. * Write a single u16 to shared memory.
  2441. * SHM 'offset' needs to be an even address
  2442. */
  2443. void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
  2444. {
  2445. brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
  2446. }
  2447. /*
  2448. * Copy a buffer to shared memory of specified type .
  2449. * SHM 'offset' needs to be an even address and
  2450. * Buffer length 'len' must be an even number of bytes
  2451. * 'sel' selects the type of memory
  2452. */
  2453. void
  2454. brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
  2455. const void *buf, int len, u32 sel)
  2456. {
  2457. u16 v;
  2458. const u8 *p = (const u8 *)buf;
  2459. int i;
  2460. if (len <= 0 || (offset & 1) || (len & 1))
  2461. return;
  2462. for (i = 0; i < len; i += 2) {
  2463. v = p[i] | (p[i + 1] << 8);
  2464. brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
  2465. }
  2466. }
  2467. /*
  2468. * Copy a piece of shared memory of specified type to a buffer .
  2469. * SHM 'offset' needs to be an even address and
  2470. * Buffer length 'len' must be an even number of bytes
  2471. * 'sel' selects the type of memory
  2472. */
  2473. void
  2474. brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
  2475. int len, u32 sel)
  2476. {
  2477. u16 v;
  2478. u8 *p = (u8 *) buf;
  2479. int i;
  2480. if (len <= 0 || (offset & 1) || (len & 1))
  2481. return;
  2482. for (i = 0; i < len; i += 2) {
  2483. v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
  2484. p[i] = v & 0xFF;
  2485. p[i + 1] = (v >> 8) & 0xFF;
  2486. }
  2487. }
  2488. /* Copy a buffer to shared memory.
  2489. * SHM 'offset' needs to be an even address and
  2490. * Buffer length 'len' must be an even number of bytes
  2491. */
  2492. static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
  2493. const void *buf, int len)
  2494. {
  2495. brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
  2496. }
  2497. static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
  2498. u16 SRL, u16 LRL)
  2499. {
  2500. wlc_hw->SRL = SRL;
  2501. wlc_hw->LRL = LRL;
  2502. /* write retry limit to SCR, shouldn't need to suspend */
  2503. if (wlc_hw->up) {
  2504. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  2505. OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2506. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  2507. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
  2508. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  2509. OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2510. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  2511. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
  2512. }
  2513. }
  2514. static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
  2515. {
  2516. if (set) {
  2517. if (mboolisset(wlc_hw->pllreq, req_bit))
  2518. return;
  2519. mboolset(wlc_hw->pllreq, req_bit);
  2520. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2521. if (!wlc_hw->sbclk)
  2522. brcms_b_xtal(wlc_hw, ON);
  2523. }
  2524. } else {
  2525. if (!mboolisset(wlc_hw->pllreq, req_bit))
  2526. return;
  2527. mboolclr(wlc_hw->pllreq, req_bit);
  2528. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2529. if (wlc_hw->sbclk)
  2530. brcms_b_xtal(wlc_hw, OFF);
  2531. }
  2532. }
  2533. }
  2534. static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
  2535. {
  2536. wlc_hw->antsel_avail = antsel_avail;
  2537. }
  2538. /*
  2539. * conditions under which the PM bit should be set in outgoing frames
  2540. * and STAY_AWAKE is meaningful
  2541. */
  2542. static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
  2543. {
  2544. struct brcms_bss_cfg *cfg = wlc->bsscfg;
  2545. /* disallow PS when one of the following global conditions meets */
  2546. if (!wlc->pub->associated)
  2547. return false;
  2548. /* disallow PS when one of these meets when not scanning */
  2549. if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
  2550. return false;
  2551. if (cfg->associated) {
  2552. /*
  2553. * disallow PS when one of the following
  2554. * bsscfg specific conditions meets
  2555. */
  2556. if (!cfg->BSS)
  2557. return false;
  2558. return false;
  2559. }
  2560. return true;
  2561. }
  2562. static void brcms_c_statsupd(struct brcms_c_info *wlc)
  2563. {
  2564. int i;
  2565. struct macstat macstats;
  2566. #ifdef DEBUG
  2567. u16 delta;
  2568. u16 rxf0ovfl;
  2569. u16 txfunfl[NFIFO];
  2570. #endif /* DEBUG */
  2571. /* if driver down, make no sense to update stats */
  2572. if (!wlc->pub->up)
  2573. return;
  2574. #ifdef DEBUG
  2575. /* save last rx fifo 0 overflow count */
  2576. rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
  2577. /* save last tx fifo underflow count */
  2578. for (i = 0; i < NFIFO; i++)
  2579. txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
  2580. #endif /* DEBUG */
  2581. /* Read mac stats from contiguous shared memory */
  2582. brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
  2583. sizeof(struct macstat), OBJADDR_SHM_SEL);
  2584. #ifdef DEBUG
  2585. /* check for rx fifo 0 overflow */
  2586. delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
  2587. if (delta)
  2588. brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
  2589. wlc->pub->unit, delta);
  2590. /* check for tx fifo underflows */
  2591. for (i = 0; i < NFIFO; i++) {
  2592. delta =
  2593. (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
  2594. txfunfl[i]);
  2595. if (delta)
  2596. brcms_err(wlc->hw->d11core,
  2597. "wl%d: %u tx fifo %d underflows!\n",
  2598. wlc->pub->unit, delta, i);
  2599. }
  2600. #endif /* DEBUG */
  2601. /* merge counters from dma module */
  2602. for (i = 0; i < NFIFO; i++) {
  2603. if (wlc->hw->di[i])
  2604. dma_counterreset(wlc->hw->di[i]);
  2605. }
  2606. }
  2607. static void brcms_b_reset(struct brcms_hardware *wlc_hw)
  2608. {
  2609. /* reset the core */
  2610. if (!brcms_deviceremoved(wlc_hw->wlc))
  2611. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  2612. /* purge the dma rings */
  2613. brcms_c_flushqueues(wlc_hw->wlc);
  2614. }
  2615. void brcms_c_reset(struct brcms_c_info *wlc)
  2616. {
  2617. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  2618. /* slurp up hw mac counters before core reset */
  2619. brcms_c_statsupd(wlc);
  2620. /* reset our snapshot of macstat counters */
  2621. memset((char *)wlc->core->macstat_snapshot, 0,
  2622. sizeof(struct macstat));
  2623. brcms_b_reset(wlc->hw);
  2624. }
  2625. void brcms_c_init_scb(struct scb *scb)
  2626. {
  2627. int i;
  2628. memset(scb, 0, sizeof(struct scb));
  2629. scb->flags = SCB_WMECAP | SCB_HTCAP;
  2630. for (i = 0; i < NUMPRIO; i++) {
  2631. scb->seqnum[i] = 0;
  2632. scb->seqctl[i] = 0xFFFF;
  2633. }
  2634. scb->seqctl_nonqos = 0xFFFF;
  2635. scb->magic = SCB_MAGIC;
  2636. }
  2637. /* d11 core init
  2638. * reset PSM
  2639. * download ucode/PCM
  2640. * let ucode run to suspended
  2641. * download ucode inits
  2642. * config other core registers
  2643. * init dma
  2644. */
  2645. static void brcms_b_coreinit(struct brcms_c_info *wlc)
  2646. {
  2647. struct brcms_hardware *wlc_hw = wlc->hw;
  2648. struct bcma_device *core = wlc_hw->d11core;
  2649. u32 sflags;
  2650. u32 bcnint_us;
  2651. uint i = 0;
  2652. bool fifosz_fixup = false;
  2653. int err = 0;
  2654. u16 buf[NFIFO];
  2655. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  2656. brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
  2657. /* reset PSM */
  2658. brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
  2659. brcms_ucode_download(wlc_hw);
  2660. /*
  2661. * FIFOSZ fixup. driver wants to controls the fifo allocation.
  2662. */
  2663. fifosz_fixup = true;
  2664. /* let the PSM run to the suspended state, set mode to BSS STA */
  2665. bcma_write32(core, D11REGOFFS(macintstatus), -1);
  2666. brcms_b_mctrl(wlc_hw, ~0,
  2667. (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
  2668. /* wait for ucode to self-suspend after auto-init */
  2669. SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
  2670. MI_MACSSPNDD) == 0), 1000 * 1000);
  2671. if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
  2672. brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
  2673. "suspend!\n", wlc_hw->unit);
  2674. brcms_c_gpio_init(wlc);
  2675. sflags = bcma_aread32(core, BCMA_IOST);
  2676. if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
  2677. if (BRCMS_ISNPHY(wlc_hw->band))
  2678. brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
  2679. else
  2680. brcms_err(core, "%s: wl%d: unsupported phy in corerev"
  2681. " %d\n", __func__, wlc_hw->unit,
  2682. wlc_hw->corerev);
  2683. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  2684. if (BRCMS_ISLCNPHY(wlc_hw->band))
  2685. brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
  2686. else
  2687. brcms_err(core, "%s: wl%d: unsupported phy in corerev"
  2688. " %d\n", __func__, wlc_hw->unit,
  2689. wlc_hw->corerev);
  2690. } else {
  2691. brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
  2692. __func__, wlc_hw->unit, wlc_hw->corerev);
  2693. }
  2694. /* For old ucode, txfifo sizes needs to be modified(increased) */
  2695. if (fifosz_fixup)
  2696. brcms_b_corerev_fifofixup(wlc_hw);
  2697. /* check txfifo allocations match between ucode and driver */
  2698. buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
  2699. if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
  2700. i = TX_AC_BE_FIFO;
  2701. err = -1;
  2702. }
  2703. buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
  2704. if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
  2705. i = TX_AC_VI_FIFO;
  2706. err = -1;
  2707. }
  2708. buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
  2709. buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
  2710. buf[TX_AC_BK_FIFO] &= 0xff;
  2711. if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
  2712. i = TX_AC_BK_FIFO;
  2713. err = -1;
  2714. }
  2715. if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
  2716. i = TX_AC_VO_FIFO;
  2717. err = -1;
  2718. }
  2719. buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
  2720. buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
  2721. buf[TX_BCMC_FIFO] &= 0xff;
  2722. if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
  2723. i = TX_BCMC_FIFO;
  2724. err = -1;
  2725. }
  2726. if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
  2727. i = TX_ATIM_FIFO;
  2728. err = -1;
  2729. }
  2730. if (err != 0)
  2731. brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
  2732. " driver size %d index %d\n", buf[i],
  2733. wlc_hw->xmtfifo_sz[i], i);
  2734. /* make sure we can still talk to the mac */
  2735. WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
  2736. /* band-specific inits done by wlc_bsinit() */
  2737. /* Set up frame burst size and antenna swap threshold init values */
  2738. brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
  2739. brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
  2740. /* enable one rx interrupt per received frame */
  2741. bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
  2742. /* set the station mode (BSS STA) */
  2743. brcms_b_mctrl(wlc_hw,
  2744. (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
  2745. (MCTL_INFRA | MCTL_DISCARD_PMQ));
  2746. /* set up Beacon interval */
  2747. bcnint_us = 0x8000 << 10;
  2748. bcma_write32(core, D11REGOFFS(tsf_cfprep),
  2749. (bcnint_us << CFPREP_CBI_SHIFT));
  2750. bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
  2751. bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
  2752. /* write interrupt mask */
  2753. bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
  2754. DEF_RXINTMASK);
  2755. /* allow the MAC to control the PHY clock (dynamic on/off) */
  2756. brcms_b_macphyclk_set(wlc_hw, ON);
  2757. /* program dynamic clock control fast powerup delay register */
  2758. wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
  2759. bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
  2760. /* tell the ucode the corerev */
  2761. brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
  2762. /* tell the ucode MAC capabilities */
  2763. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
  2764. (u16) (wlc_hw->machwcap & 0xffff));
  2765. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
  2766. (u16) ((wlc_hw->
  2767. machwcap >> 16) & 0xffff));
  2768. /* write retry limits to SCR, this done after PSM init */
  2769. bcma_write32(core, D11REGOFFS(objaddr),
  2770. OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2771. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2772. bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
  2773. bcma_write32(core, D11REGOFFS(objaddr),
  2774. OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2775. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2776. bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
  2777. /* write rate fallback retry limits */
  2778. brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
  2779. brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
  2780. bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
  2781. bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
  2782. /* init the tx dma engines */
  2783. for (i = 0; i < NFIFO; i++) {
  2784. if (wlc_hw->di[i])
  2785. dma_txinit(wlc_hw->di[i]);
  2786. }
  2787. /* init the rx dma engine(s) and post receive buffers */
  2788. dma_rxinit(wlc_hw->di[RX_FIFO]);
  2789. dma_rxfill(wlc_hw->di[RX_FIFO]);
  2790. }
  2791. void
  2792. static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
  2793. u32 macintmask;
  2794. bool fastclk;
  2795. struct brcms_c_info *wlc = wlc_hw->wlc;
  2796. /* request FAST clock if not on */
  2797. fastclk = wlc_hw->forcefastclk;
  2798. if (!fastclk)
  2799. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  2800. /* disable interrupts */
  2801. macintmask = brcms_intrsoff(wlc->wl);
  2802. /* set up the specified band and chanspec */
  2803. brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
  2804. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  2805. /* do one-time phy inits and calibration */
  2806. wlc_phy_cal_init(wlc_hw->band->pi);
  2807. /* core-specific initialization */
  2808. brcms_b_coreinit(wlc);
  2809. /* band-specific inits */
  2810. brcms_b_bsinit(wlc, chanspec);
  2811. /* restore macintmask */
  2812. brcms_intrsrestore(wlc->wl, macintmask);
  2813. /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
  2814. * is suspended and brcms_c_enable_mac() will clear this override bit.
  2815. */
  2816. mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2817. /*
  2818. * initialize mac_suspend_depth to 1 to match ucode
  2819. * initial suspended state
  2820. */
  2821. wlc_hw->mac_suspend_depth = 1;
  2822. /* restore the clk */
  2823. if (!fastclk)
  2824. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  2825. }
  2826. static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
  2827. u16 chanspec)
  2828. {
  2829. /* Save our copy of the chanspec */
  2830. wlc->chanspec = chanspec;
  2831. /* Set the chanspec and power limits for this locale */
  2832. brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
  2833. if (wlc->stf->ss_algosel_auto)
  2834. brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
  2835. chanspec);
  2836. brcms_c_stf_ss_update(wlc, wlc->band);
  2837. }
  2838. static void
  2839. brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
  2840. {
  2841. brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
  2842. wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
  2843. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  2844. brcms_chspec_bw(wlc->default_bss->chanspec),
  2845. wlc->stf->txstreams);
  2846. }
  2847. /* derive wlc->band->basic_rate[] table from 'rateset' */
  2848. static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
  2849. struct brcms_c_rateset *rateset)
  2850. {
  2851. u8 rate;
  2852. u8 mandatory;
  2853. u8 cck_basic = 0;
  2854. u8 ofdm_basic = 0;
  2855. u8 *br = wlc->band->basic_rate;
  2856. uint i;
  2857. /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
  2858. memset(br, 0, BRCM_MAXRATE + 1);
  2859. /* For each basic rate in the rates list, make an entry in the
  2860. * best basic lookup.
  2861. */
  2862. for (i = 0; i < rateset->count; i++) {
  2863. /* only make an entry for a basic rate */
  2864. if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
  2865. continue;
  2866. /* mask off basic bit */
  2867. rate = (rateset->rates[i] & BRCMS_RATE_MASK);
  2868. if (rate > BRCM_MAXRATE) {
  2869. brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
  2870. "invalid rate 0x%X in rate set\n",
  2871. rateset->rates[i]);
  2872. continue;
  2873. }
  2874. br[rate] = rate;
  2875. }
  2876. /* The rate lookup table now has non-zero entries for each
  2877. * basic rate, equal to the basic rate: br[basicN] = basicN
  2878. *
  2879. * To look up the best basic rate corresponding to any
  2880. * particular rate, code can use the basic_rate table
  2881. * like this
  2882. *
  2883. * basic_rate = wlc->band->basic_rate[tx_rate]
  2884. *
  2885. * Make sure there is a best basic rate entry for
  2886. * every rate by walking up the table from low rates
  2887. * to high, filling in holes in the lookup table
  2888. */
  2889. for (i = 0; i < wlc->band->hw_rateset.count; i++) {
  2890. rate = wlc->band->hw_rateset.rates[i];
  2891. if (br[rate] != 0) {
  2892. /* This rate is a basic rate.
  2893. * Keep track of the best basic rate so far by
  2894. * modulation type.
  2895. */
  2896. if (is_ofdm_rate(rate))
  2897. ofdm_basic = rate;
  2898. else
  2899. cck_basic = rate;
  2900. continue;
  2901. }
  2902. /* This rate is not a basic rate so figure out the
  2903. * best basic rate less than this rate and fill in
  2904. * the hole in the table
  2905. */
  2906. br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
  2907. if (br[rate] != 0)
  2908. continue;
  2909. if (is_ofdm_rate(rate)) {
  2910. /*
  2911. * In 11g and 11a, the OFDM mandatory rates
  2912. * are 6, 12, and 24 Mbps
  2913. */
  2914. if (rate >= BRCM_RATE_24M)
  2915. mandatory = BRCM_RATE_24M;
  2916. else if (rate >= BRCM_RATE_12M)
  2917. mandatory = BRCM_RATE_12M;
  2918. else
  2919. mandatory = BRCM_RATE_6M;
  2920. } else {
  2921. /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
  2922. mandatory = rate;
  2923. }
  2924. br[rate] = mandatory;
  2925. }
  2926. }
  2927. static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
  2928. u16 chanspec)
  2929. {
  2930. struct brcms_c_rateset default_rateset;
  2931. uint parkband;
  2932. uint i, band_order[2];
  2933. /*
  2934. * We might have been bandlocked during down and the chip
  2935. * power-cycled (hibernate). Figure out the right band to park on
  2936. */
  2937. if (wlc->bandlocked || wlc->pub->_nbands == 1) {
  2938. /* updated in brcms_c_bandlock() */
  2939. parkband = wlc->band->bandunit;
  2940. band_order[0] = band_order[1] = parkband;
  2941. } else {
  2942. /* park on the band of the specified chanspec */
  2943. parkband = chspec_bandunit(chanspec);
  2944. /* order so that parkband initialize last */
  2945. band_order[0] = parkband ^ 1;
  2946. band_order[1] = parkband;
  2947. }
  2948. /* make each band operational, software state init */
  2949. for (i = 0; i < wlc->pub->_nbands; i++) {
  2950. uint j = band_order[i];
  2951. wlc->band = wlc->bandstate[j];
  2952. brcms_default_rateset(wlc, &default_rateset);
  2953. /* fill in hw_rate */
  2954. brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
  2955. false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  2956. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  2957. /* init basic rate lookup */
  2958. brcms_c_rate_lookup_init(wlc, &default_rateset);
  2959. }
  2960. /* sync up phy/radio chanspec */
  2961. brcms_c_set_phy_chanspec(wlc, chanspec);
  2962. }
  2963. /*
  2964. * Set or clear filtering related maccontrol bits based on
  2965. * specified filter flags
  2966. */
  2967. void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
  2968. {
  2969. u32 promisc_bits = 0;
  2970. wlc->filter_flags = filter_flags;
  2971. if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
  2972. promisc_bits |= MCTL_PROMISC;
  2973. if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
  2974. promisc_bits |= MCTL_BCNS_PROMISC;
  2975. if (filter_flags & FIF_FCSFAIL)
  2976. promisc_bits |= MCTL_KEEPBADFCS;
  2977. if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
  2978. promisc_bits |= MCTL_KEEPCONTROL;
  2979. brcms_b_mctrl(wlc->hw,
  2980. MCTL_PROMISC | MCTL_BCNS_PROMISC |
  2981. MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
  2982. promisc_bits);
  2983. }
  2984. /*
  2985. * ucode, hwmac update
  2986. * Channel dependent updates for ucode and hw
  2987. */
  2988. static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
  2989. {
  2990. /* enable or disable any active IBSSs depending on whether or not
  2991. * we are on the home channel
  2992. */
  2993. if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
  2994. if (wlc->pub->associated) {
  2995. /*
  2996. * BMAC_NOTE: This is something that should be fixed
  2997. * in ucode inits. I think that the ucode inits set
  2998. * up the bcn templates and shm values with a bogus
  2999. * beacon. This should not be done in the inits. If
  3000. * ucode needs to set up a beacon for testing, the
  3001. * test routines should write it down, not expect the
  3002. * inits to populate a bogus beacon.
  3003. */
  3004. if (BRCMS_PHY_11N_CAP(wlc->band))
  3005. brcms_b_write_shm(wlc->hw,
  3006. M_BCN_TXTSF_OFFSET, 0);
  3007. }
  3008. } else {
  3009. /* disable an active IBSS if we are not on the home channel */
  3010. }
  3011. }
  3012. static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
  3013. u8 basic_rate)
  3014. {
  3015. u8 phy_rate, index;
  3016. u8 basic_phy_rate, basic_index;
  3017. u16 dir_table, basic_table;
  3018. u16 basic_ptr;
  3019. /* Shared memory address for the table we are reading */
  3020. dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
  3021. /* Shared memory address for the table we are writing */
  3022. basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
  3023. /*
  3024. * for a given rate, the LS-nibble of the PLCP SIGNAL field is
  3025. * the index into the rate table.
  3026. */
  3027. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  3028. basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
  3029. index = phy_rate & 0xf;
  3030. basic_index = basic_phy_rate & 0xf;
  3031. /* Find the SHM pointer to the ACK rate entry by looking in the
  3032. * Direct-map Table
  3033. */
  3034. basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
  3035. /* Update the SHM BSS-basic-rate-set mapping table with the pointer
  3036. * to the correct basic rate for the given incoming rate
  3037. */
  3038. brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
  3039. }
  3040. static const struct brcms_c_rateset *
  3041. brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
  3042. {
  3043. const struct brcms_c_rateset *rs_dflt;
  3044. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  3045. if (wlc->band->bandtype == BRCM_BAND_5G)
  3046. rs_dflt = &ofdm_mimo_rates;
  3047. else
  3048. rs_dflt = &cck_ofdm_mimo_rates;
  3049. } else if (wlc->band->gmode)
  3050. rs_dflt = &cck_ofdm_rates;
  3051. else
  3052. rs_dflt = &cck_rates;
  3053. return rs_dflt;
  3054. }
  3055. static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
  3056. {
  3057. const struct brcms_c_rateset *rs_dflt;
  3058. struct brcms_c_rateset rs;
  3059. u8 rate, basic_rate;
  3060. uint i;
  3061. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  3062. brcms_c_rateset_copy(rs_dflt, &rs);
  3063. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  3064. /* walk the phy rate table and update SHM basic rate lookup table */
  3065. for (i = 0; i < rs.count; i++) {
  3066. rate = rs.rates[i] & BRCMS_RATE_MASK;
  3067. /* for a given rate brcms_basic_rate returns the rate at
  3068. * which a response ACK/CTS should be sent.
  3069. */
  3070. basic_rate = brcms_basic_rate(wlc, rate);
  3071. if (basic_rate == 0)
  3072. /* This should only happen if we are using a
  3073. * restricted rateset.
  3074. */
  3075. basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
  3076. brcms_c_write_rate_shm(wlc, rate, basic_rate);
  3077. }
  3078. }
  3079. /* band-specific init */
  3080. static void brcms_c_bsinit(struct brcms_c_info *wlc)
  3081. {
  3082. brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
  3083. wlc->pub->unit, wlc->band->bandunit);
  3084. /* write ucode ACK/CTS rate table */
  3085. brcms_c_set_ratetable(wlc);
  3086. /* update some band specific mac configuration */
  3087. brcms_c_ucode_mac_upd(wlc);
  3088. /* init antenna selection */
  3089. brcms_c_antsel_init(wlc->asi);
  3090. }
  3091. /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
  3092. static int
  3093. brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
  3094. bool writeToShm)
  3095. {
  3096. int idle_busy_ratio_x_16 = 0;
  3097. uint offset =
  3098. isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
  3099. M_TX_IDLE_BUSY_RATIO_X_16_CCK;
  3100. if (duty_cycle > 100 || duty_cycle < 0) {
  3101. brcms_err(wlc->hw->d11core,
  3102. "wl%d: duty cycle value off limit\n",
  3103. wlc->pub->unit);
  3104. return -EINVAL;
  3105. }
  3106. if (duty_cycle)
  3107. idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
  3108. /* Only write to shared memory when wl is up */
  3109. if (writeToShm)
  3110. brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
  3111. if (isOFDM)
  3112. wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
  3113. else
  3114. wlc->tx_duty_cycle_cck = (u16) duty_cycle;
  3115. return 0;
  3116. }
  3117. /* push sw hps and wake state through hardware */
  3118. static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
  3119. {
  3120. u32 v1, v2;
  3121. bool hps;
  3122. bool awake_before;
  3123. hps = brcms_c_ps_allowed(wlc);
  3124. brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
  3125. hps);
  3126. v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
  3127. v2 = MCTL_WAKE;
  3128. if (hps)
  3129. v2 |= MCTL_HPS;
  3130. brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
  3131. awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
  3132. if (!awake_before)
  3133. brcms_b_wait_for_wake(wlc->hw);
  3134. }
  3135. /*
  3136. * Write this BSS config's MAC address to core.
  3137. * Updates RXE match engine.
  3138. */
  3139. static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
  3140. {
  3141. int err = 0;
  3142. struct brcms_c_info *wlc = bsscfg->wlc;
  3143. /* enter the MAC addr into the RXE match registers */
  3144. brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
  3145. brcms_c_ampdu_macaddr_upd(wlc);
  3146. return err;
  3147. }
  3148. /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
  3149. * Updates RXE match engine.
  3150. */
  3151. static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
  3152. {
  3153. /* we need to update BSSID in RXE match registers */
  3154. brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
  3155. }
  3156. static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
  3157. {
  3158. wlc_hw->shortslot = shortslot;
  3159. if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
  3160. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  3161. brcms_b_update_slot_timing(wlc_hw, shortslot);
  3162. brcms_c_enable_mac(wlc_hw->wlc);
  3163. }
  3164. }
  3165. /*
  3166. * Suspend the the MAC and update the slot timing
  3167. * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
  3168. */
  3169. static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
  3170. {
  3171. /* use the override if it is set */
  3172. if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
  3173. shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
  3174. if (wlc->shortslot == shortslot)
  3175. return;
  3176. wlc->shortslot = shortslot;
  3177. brcms_b_set_shortslot(wlc->hw, shortslot);
  3178. }
  3179. static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3180. {
  3181. if (wlc->home_chanspec != chanspec) {
  3182. wlc->home_chanspec = chanspec;
  3183. if (wlc->bsscfg->associated)
  3184. wlc->bsscfg->current_bss->chanspec = chanspec;
  3185. }
  3186. }
  3187. void
  3188. brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
  3189. bool mute_tx, struct txpwr_limits *txpwr)
  3190. {
  3191. uint bandunit;
  3192. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
  3193. chanspec);
  3194. wlc_hw->chanspec = chanspec;
  3195. /* Switch bands if necessary */
  3196. if (wlc_hw->_nbands > 1) {
  3197. bandunit = chspec_bandunit(chanspec);
  3198. if (wlc_hw->band->bandunit != bandunit) {
  3199. /* brcms_b_setband disables other bandunit,
  3200. * use light band switch if not up yet
  3201. */
  3202. if (wlc_hw->up) {
  3203. wlc_phy_chanspec_radio_set(wlc_hw->
  3204. bandstate[bandunit]->
  3205. pi, chanspec);
  3206. brcms_b_setband(wlc_hw, bandunit, chanspec);
  3207. } else {
  3208. brcms_c_setxband(wlc_hw, bandunit);
  3209. }
  3210. }
  3211. }
  3212. wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
  3213. if (!wlc_hw->up) {
  3214. if (wlc_hw->clk)
  3215. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
  3216. chanspec);
  3217. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  3218. } else {
  3219. wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
  3220. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
  3221. /* Update muting of the channel */
  3222. brcms_b_mute(wlc_hw, mute_tx);
  3223. }
  3224. }
  3225. /* switch to and initialize new band */
  3226. static void brcms_c_setband(struct brcms_c_info *wlc,
  3227. uint bandunit)
  3228. {
  3229. wlc->band = wlc->bandstate[bandunit];
  3230. if (!wlc->pub->up)
  3231. return;
  3232. /* wait for at least one beacon before entering sleeping state */
  3233. brcms_c_set_ps_ctrl(wlc);
  3234. /* band-specific initializations */
  3235. brcms_c_bsinit(wlc);
  3236. }
  3237. static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3238. {
  3239. uint bandunit;
  3240. bool switchband = false;
  3241. u16 old_chanspec = wlc->chanspec;
  3242. if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
  3243. brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
  3244. wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
  3245. return;
  3246. }
  3247. /* Switch bands if necessary */
  3248. if (wlc->pub->_nbands > 1) {
  3249. bandunit = chspec_bandunit(chanspec);
  3250. if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
  3251. switchband = true;
  3252. if (wlc->bandlocked) {
  3253. brcms_err(wlc->hw->d11core,
  3254. "wl%d: %s: chspec %d band is locked!\n",
  3255. wlc->pub->unit, __func__,
  3256. CHSPEC_CHANNEL(chanspec));
  3257. return;
  3258. }
  3259. /*
  3260. * should the setband call come after the
  3261. * brcms_b_chanspec() ? if the setband updates
  3262. * (brcms_c_bsinit) use low level calls to inspect and
  3263. * set state, the state inspected may be from the wrong
  3264. * band, or the following brcms_b_set_chanspec() may
  3265. * undo the work.
  3266. */
  3267. brcms_c_setband(wlc, bandunit);
  3268. }
  3269. }
  3270. /* sync up phy/radio chanspec */
  3271. brcms_c_set_phy_chanspec(wlc, chanspec);
  3272. /* init antenna selection */
  3273. if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
  3274. brcms_c_antsel_init(wlc->asi);
  3275. /* Fix the hardware rateset based on bw.
  3276. * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
  3277. */
  3278. brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
  3279. wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
  3280. }
  3281. /* update some mac configuration since chanspec changed */
  3282. brcms_c_ucode_mac_upd(wlc);
  3283. }
  3284. /*
  3285. * This function changes the phytxctl for beacon based on current
  3286. * beacon ratespec AND txant setting as per this table:
  3287. * ratespec CCK ant = wlc->stf->txant
  3288. * OFDM ant = 3
  3289. */
  3290. void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
  3291. u32 bcn_rspec)
  3292. {
  3293. u16 phyctl;
  3294. u16 phytxant = wlc->stf->phytxant;
  3295. u16 mask = PHY_TXC_ANT_MASK;
  3296. /* for non-siso rates or default setting, use the available chains */
  3297. if (BRCMS_PHY_11N_CAP(wlc->band))
  3298. phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
  3299. phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
  3300. phyctl = (phyctl & ~mask) | phytxant;
  3301. brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
  3302. }
  3303. /*
  3304. * centralized protection config change function to simplify debugging, no
  3305. * consistency checking this should be called only on changes to avoid overhead
  3306. * in periodic function
  3307. */
  3308. void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
  3309. {
  3310. /*
  3311. * Cannot use brcms_dbg_* here because this function is called
  3312. * before wlc is sufficiently initialized.
  3313. */
  3314. BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
  3315. switch (idx) {
  3316. case BRCMS_PROT_G_SPEC:
  3317. wlc->protection->_g = (bool) val;
  3318. break;
  3319. case BRCMS_PROT_G_OVR:
  3320. wlc->protection->g_override = (s8) val;
  3321. break;
  3322. case BRCMS_PROT_G_USER:
  3323. wlc->protection->gmode_user = (u8) val;
  3324. break;
  3325. case BRCMS_PROT_OVERLAP:
  3326. wlc->protection->overlap = (s8) val;
  3327. break;
  3328. case BRCMS_PROT_N_USER:
  3329. wlc->protection->nmode_user = (s8) val;
  3330. break;
  3331. case BRCMS_PROT_N_CFG:
  3332. wlc->protection->n_cfg = (s8) val;
  3333. break;
  3334. case BRCMS_PROT_N_CFG_OVR:
  3335. wlc->protection->n_cfg_override = (s8) val;
  3336. break;
  3337. case BRCMS_PROT_N_NONGF:
  3338. wlc->protection->nongf = (bool) val;
  3339. break;
  3340. case BRCMS_PROT_N_NONGF_OVR:
  3341. wlc->protection->nongf_override = (s8) val;
  3342. break;
  3343. case BRCMS_PROT_N_PAM_OVR:
  3344. wlc->protection->n_pam_override = (s8) val;
  3345. break;
  3346. case BRCMS_PROT_N_OBSS:
  3347. wlc->protection->n_obss = (bool) val;
  3348. break;
  3349. default:
  3350. break;
  3351. }
  3352. }
  3353. static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
  3354. {
  3355. if (wlc->pub->up) {
  3356. brcms_c_update_beacon(wlc);
  3357. brcms_c_update_probe_resp(wlc, true);
  3358. }
  3359. }
  3360. static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
  3361. {
  3362. wlc->stf->ldpc = val;
  3363. if (wlc->pub->up) {
  3364. brcms_c_update_beacon(wlc);
  3365. brcms_c_update_probe_resp(wlc, true);
  3366. wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
  3367. }
  3368. }
  3369. void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
  3370. const struct ieee80211_tx_queue_params *params,
  3371. bool suspend)
  3372. {
  3373. int i;
  3374. struct shm_acparams acp_shm;
  3375. u16 *shm_entry;
  3376. /* Only apply params if the core is out of reset and has clocks */
  3377. if (!wlc->clk) {
  3378. brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
  3379. wlc->pub->unit, __func__);
  3380. return;
  3381. }
  3382. memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
  3383. /* fill in shm ac params struct */
  3384. acp_shm.txop = params->txop;
  3385. /* convert from units of 32us to us for ucode */
  3386. wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
  3387. EDCF_TXOP2USEC(acp_shm.txop);
  3388. acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
  3389. if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
  3390. && acp_shm.aifs < EDCF_AIFSN_MAX)
  3391. acp_shm.aifs++;
  3392. if (acp_shm.aifs < EDCF_AIFSN_MIN
  3393. || acp_shm.aifs > EDCF_AIFSN_MAX) {
  3394. brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
  3395. "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
  3396. } else {
  3397. acp_shm.cwmin = params->cw_min;
  3398. acp_shm.cwmax = params->cw_max;
  3399. acp_shm.cwcur = acp_shm.cwmin;
  3400. acp_shm.bslots =
  3401. bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
  3402. acp_shm.cwcur;
  3403. acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
  3404. /* Indicate the new params to the ucode */
  3405. acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
  3406. wme_ac2fifo[aci] *
  3407. M_EDCF_QLEN +
  3408. M_EDCF_STATUS_OFF));
  3409. acp_shm.status |= WME_STATUS_NEWAC;
  3410. /* Fill in shm acparam table */
  3411. shm_entry = (u16 *) &acp_shm;
  3412. for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
  3413. brcms_b_write_shm(wlc->hw,
  3414. M_EDCF_QINFO +
  3415. wme_ac2fifo[aci] * M_EDCF_QLEN + i,
  3416. *shm_entry++);
  3417. }
  3418. if (suspend) {
  3419. brcms_c_suspend_mac_and_wait(wlc);
  3420. brcms_c_enable_mac(wlc);
  3421. }
  3422. }
  3423. static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
  3424. {
  3425. u16 aci;
  3426. int i_ac;
  3427. struct ieee80211_tx_queue_params txq_pars;
  3428. static const struct edcf_acparam default_edcf_acparams[] = {
  3429. {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
  3430. {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
  3431. {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
  3432. {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
  3433. }; /* ucode needs these parameters during its initialization */
  3434. const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
  3435. for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
  3436. /* find out which ac this set of params applies to */
  3437. aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
  3438. /* fill in shm ac params struct */
  3439. txq_pars.txop = edcf_acp->TXOP;
  3440. txq_pars.aifs = edcf_acp->ACI;
  3441. /* CWmin = 2^(ECWmin) - 1 */
  3442. txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
  3443. /* CWmax = 2^(ECWmax) - 1 */
  3444. txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
  3445. >> EDCF_ECWMAX_SHIFT);
  3446. brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
  3447. }
  3448. if (suspend) {
  3449. brcms_c_suspend_mac_and_wait(wlc);
  3450. brcms_c_enable_mac(wlc);
  3451. }
  3452. }
  3453. static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
  3454. {
  3455. /* Don't start the timer if HWRADIO feature is disabled */
  3456. if (wlc->radio_monitor)
  3457. return;
  3458. wlc->radio_monitor = true;
  3459. brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
  3460. brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
  3461. }
  3462. static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
  3463. {
  3464. if (!wlc->radio_monitor)
  3465. return true;
  3466. wlc->radio_monitor = false;
  3467. brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
  3468. return brcms_del_timer(wlc->radio_timer);
  3469. }
  3470. /* read hwdisable state and propagate to wlc flag */
  3471. static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
  3472. {
  3473. if (wlc->pub->hw_off)
  3474. return;
  3475. if (brcms_b_radio_read_hwdisabled(wlc->hw))
  3476. mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3477. else
  3478. mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3479. }
  3480. /* update hwradio status and return it */
  3481. bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
  3482. {
  3483. brcms_c_radio_hwdisable_upd(wlc);
  3484. return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
  3485. true : false;
  3486. }
  3487. /* periodical query hw radio button while driver is "down" */
  3488. static void brcms_c_radio_timer(void *arg)
  3489. {
  3490. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3491. if (brcms_deviceremoved(wlc)) {
  3492. brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
  3493. wlc->pub->unit, __func__);
  3494. brcms_down(wlc->wl);
  3495. return;
  3496. }
  3497. brcms_c_radio_hwdisable_upd(wlc);
  3498. }
  3499. /* common low-level watchdog code */
  3500. static void brcms_b_watchdog(struct brcms_c_info *wlc)
  3501. {
  3502. struct brcms_hardware *wlc_hw = wlc->hw;
  3503. if (!wlc_hw->up)
  3504. return;
  3505. /* increment second count */
  3506. wlc_hw->now++;
  3507. /* Check for FIFO error interrupts */
  3508. brcms_b_fifoerrors(wlc_hw);
  3509. /* make sure RX dma has buffers */
  3510. dma_rxfill(wlc->hw->di[RX_FIFO]);
  3511. wlc_phy_watchdog(wlc_hw->band->pi);
  3512. }
  3513. /* common watchdog code */
  3514. static void brcms_c_watchdog(struct brcms_c_info *wlc)
  3515. {
  3516. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  3517. if (!wlc->pub->up)
  3518. return;
  3519. if (brcms_deviceremoved(wlc)) {
  3520. brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
  3521. wlc->pub->unit, __func__);
  3522. brcms_down(wlc->wl);
  3523. return;
  3524. }
  3525. /* increment second count */
  3526. wlc->pub->now++;
  3527. brcms_c_radio_hwdisable_upd(wlc);
  3528. /* if radio is disable, driver may be down, quit here */
  3529. if (wlc->pub->radio_disabled)
  3530. return;
  3531. brcms_b_watchdog(wlc);
  3532. /*
  3533. * occasionally sample mac stat counters to
  3534. * detect 16-bit counter wrap
  3535. */
  3536. if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
  3537. brcms_c_statsupd(wlc);
  3538. if (BRCMS_ISNPHY(wlc->band) &&
  3539. ((wlc->pub->now - wlc->tempsense_lasttime) >=
  3540. BRCMS_TEMPSENSE_PERIOD)) {
  3541. wlc->tempsense_lasttime = wlc->pub->now;
  3542. brcms_c_tempsense_upd(wlc);
  3543. }
  3544. }
  3545. static void brcms_c_watchdog_by_timer(void *arg)
  3546. {
  3547. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3548. brcms_c_watchdog(wlc);
  3549. }
  3550. static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
  3551. {
  3552. wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
  3553. wlc, "watchdog");
  3554. if (!wlc->wdtimer) {
  3555. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
  3556. "failed\n", unit);
  3557. goto fail;
  3558. }
  3559. wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
  3560. wlc, "radio");
  3561. if (!wlc->radio_timer) {
  3562. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
  3563. "failed\n", unit);
  3564. goto fail;
  3565. }
  3566. return true;
  3567. fail:
  3568. return false;
  3569. }
  3570. /*
  3571. * Initialize brcms_c_info default values ...
  3572. * may get overrides later in this function
  3573. */
  3574. static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
  3575. {
  3576. int i;
  3577. /* Save our copy of the chanspec */
  3578. wlc->chanspec = ch20mhz_chspec(1);
  3579. /* various 802.11g modes */
  3580. wlc->shortslot = false;
  3581. wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
  3582. brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
  3583. brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
  3584. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
  3585. BRCMS_PROTECTION_AUTO);
  3586. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
  3587. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
  3588. BRCMS_PROTECTION_AUTO);
  3589. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
  3590. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
  3591. brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
  3592. BRCMS_PROTECTION_CTL_OVERLAP);
  3593. /* 802.11g draft 4.0 NonERP elt advertisement */
  3594. wlc->include_legacy_erp = true;
  3595. wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
  3596. wlc->stf->txant = ANT_TX_DEF;
  3597. wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
  3598. wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
  3599. for (i = 0; i < NFIFO; i++)
  3600. wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
  3601. wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
  3602. /* default rate fallback retry limits */
  3603. wlc->SFBL = RETRY_SHORT_FB;
  3604. wlc->LFBL = RETRY_LONG_FB;
  3605. /* default mac retry limits */
  3606. wlc->SRL = RETRY_SHORT_DEF;
  3607. wlc->LRL = RETRY_LONG_DEF;
  3608. /* WME QoS mode is Auto by default */
  3609. wlc->pub->_ampdu = AMPDU_AGG_HOST;
  3610. wlc->pub->bcmerror = 0;
  3611. }
  3612. static uint brcms_c_attach_module(struct brcms_c_info *wlc)
  3613. {
  3614. uint err = 0;
  3615. uint unit;
  3616. unit = wlc->pub->unit;
  3617. wlc->asi = brcms_c_antsel_attach(wlc);
  3618. if (wlc->asi == NULL) {
  3619. wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
  3620. "failed\n", unit);
  3621. err = 44;
  3622. goto fail;
  3623. }
  3624. wlc->ampdu = brcms_c_ampdu_attach(wlc);
  3625. if (wlc->ampdu == NULL) {
  3626. wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
  3627. "failed\n", unit);
  3628. err = 50;
  3629. goto fail;
  3630. }
  3631. if ((brcms_c_stf_attach(wlc) != 0)) {
  3632. wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
  3633. "failed\n", unit);
  3634. err = 68;
  3635. goto fail;
  3636. }
  3637. fail:
  3638. return err;
  3639. }
  3640. struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
  3641. {
  3642. return wlc->pub;
  3643. }
  3644. /* low level attach
  3645. * run backplane attach, init nvram
  3646. * run phy attach
  3647. * initialize software state for each core and band
  3648. * put the whole chip in reset(driver down state), no clock
  3649. */
  3650. static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
  3651. uint unit, bool piomode)
  3652. {
  3653. struct brcms_hardware *wlc_hw;
  3654. uint err = 0;
  3655. uint j;
  3656. bool wme = false;
  3657. struct shared_phy_params sha_params;
  3658. struct wiphy *wiphy = wlc->wiphy;
  3659. struct pci_dev *pcidev = core->bus->host_pci;
  3660. struct ssb_sprom *sprom = &core->bus->sprom;
  3661. if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
  3662. brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
  3663. pcidev->vendor,
  3664. pcidev->device);
  3665. else
  3666. brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
  3667. core->bus->boardinfo.vendor,
  3668. core->bus->boardinfo.type);
  3669. wme = true;
  3670. wlc_hw = wlc->hw;
  3671. wlc_hw->wlc = wlc;
  3672. wlc_hw->unit = unit;
  3673. wlc_hw->band = wlc_hw->bandstate[0];
  3674. wlc_hw->_piomode = piomode;
  3675. /* populate struct brcms_hardware with default values */
  3676. brcms_b_info_init(wlc_hw);
  3677. /*
  3678. * Do the hardware portion of the attach. Also initialize software
  3679. * state that depends on the particular hardware we are running.
  3680. */
  3681. wlc_hw->sih = ai_attach(core->bus);
  3682. if (wlc_hw->sih == NULL) {
  3683. wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
  3684. unit);
  3685. err = 11;
  3686. goto fail;
  3687. }
  3688. /* verify again the device is supported */
  3689. if (!brcms_c_chipmatch(core)) {
  3690. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
  3691. unit);
  3692. err = 12;
  3693. goto fail;
  3694. }
  3695. if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
  3696. wlc_hw->vendorid = pcidev->vendor;
  3697. wlc_hw->deviceid = pcidev->device;
  3698. } else {
  3699. wlc_hw->vendorid = core->bus->boardinfo.vendor;
  3700. wlc_hw->deviceid = core->bus->boardinfo.type;
  3701. }
  3702. wlc_hw->d11core = core;
  3703. wlc_hw->corerev = core->id.rev;
  3704. /* validate chip, chiprev and corerev */
  3705. if (!brcms_c_isgoodchip(wlc_hw)) {
  3706. err = 13;
  3707. goto fail;
  3708. }
  3709. /* initialize power control registers */
  3710. ai_clkctl_init(wlc_hw->sih);
  3711. /* request fastclock and force fastclock for the rest of attach
  3712. * bring the d11 core out of reset.
  3713. * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
  3714. * is still false; But it will be called again inside wlc_corereset,
  3715. * after d11 is out of reset.
  3716. */
  3717. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  3718. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  3719. if (!brcms_b_validate_chip_access(wlc_hw)) {
  3720. wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
  3721. "failed\n", unit);
  3722. err = 14;
  3723. goto fail;
  3724. }
  3725. /* get the board rev, used just below */
  3726. j = sprom->board_rev;
  3727. /* promote srom boardrev of 0xFF to 1 */
  3728. if (j == BOARDREV_PROMOTABLE)
  3729. j = BOARDREV_PROMOTED;
  3730. wlc_hw->boardrev = (u16) j;
  3731. if (!brcms_c_validboardtype(wlc_hw)) {
  3732. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
  3733. "board type (0x%x)" " or revision level (0x%x)\n",
  3734. unit, ai_get_boardtype(wlc_hw->sih),
  3735. wlc_hw->boardrev);
  3736. err = 15;
  3737. goto fail;
  3738. }
  3739. wlc_hw->sromrev = sprom->revision;
  3740. wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
  3741. wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
  3742. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  3743. brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
  3744. /* check device id(srom, nvram etc.) to set bands */
  3745. if (wlc_hw->deviceid == BCM43224_D11N_ID ||
  3746. wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
  3747. wlc_hw->deviceid == BCM43224_CHIP_ID)
  3748. /* Dualband boards */
  3749. wlc_hw->_nbands = 2;
  3750. else
  3751. wlc_hw->_nbands = 1;
  3752. if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
  3753. wlc_hw->_nbands = 1;
  3754. /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
  3755. * unconditionally does the init of these values
  3756. */
  3757. wlc->vendorid = wlc_hw->vendorid;
  3758. wlc->deviceid = wlc_hw->deviceid;
  3759. wlc->pub->sih = wlc_hw->sih;
  3760. wlc->pub->corerev = wlc_hw->corerev;
  3761. wlc->pub->sromrev = wlc_hw->sromrev;
  3762. wlc->pub->boardrev = wlc_hw->boardrev;
  3763. wlc->pub->boardflags = wlc_hw->boardflags;
  3764. wlc->pub->boardflags2 = wlc_hw->boardflags2;
  3765. wlc->pub->_nbands = wlc_hw->_nbands;
  3766. wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
  3767. if (wlc_hw->physhim == NULL) {
  3768. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
  3769. "failed\n", unit);
  3770. err = 25;
  3771. goto fail;
  3772. }
  3773. /* pass all the parameters to wlc_phy_shared_attach in one struct */
  3774. sha_params.sih = wlc_hw->sih;
  3775. sha_params.physhim = wlc_hw->physhim;
  3776. sha_params.unit = unit;
  3777. sha_params.corerev = wlc_hw->corerev;
  3778. sha_params.vid = wlc_hw->vendorid;
  3779. sha_params.did = wlc_hw->deviceid;
  3780. sha_params.chip = ai_get_chip_id(wlc_hw->sih);
  3781. sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
  3782. sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
  3783. sha_params.sromrev = wlc_hw->sromrev;
  3784. sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
  3785. sha_params.boardrev = wlc_hw->boardrev;
  3786. sha_params.boardflags = wlc_hw->boardflags;
  3787. sha_params.boardflags2 = wlc_hw->boardflags2;
  3788. /* alloc and save pointer to shared phy state area */
  3789. wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
  3790. if (!wlc_hw->phy_sh) {
  3791. err = 16;
  3792. goto fail;
  3793. }
  3794. /* initialize software state for each core and band */
  3795. for (j = 0; j < wlc_hw->_nbands; j++) {
  3796. /*
  3797. * band0 is always 2.4Ghz
  3798. * band1, if present, is 5Ghz
  3799. */
  3800. brcms_c_setxband(wlc_hw, j);
  3801. wlc_hw->band->bandunit = j;
  3802. wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3803. wlc->band->bandunit = j;
  3804. wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3805. wlc->core->coreidx = core->core_index;
  3806. wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
  3807. wlc_hw->machwcap_backup = wlc_hw->machwcap;
  3808. /* init tx fifo size */
  3809. WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
  3810. (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
  3811. ARRAY_SIZE(xmtfifo_sz));
  3812. wlc_hw->xmtfifo_sz =
  3813. xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
  3814. WARN_ON(!wlc_hw->xmtfifo_sz[0]);
  3815. /* Get a phy for this band */
  3816. wlc_hw->band->pi =
  3817. wlc_phy_attach(wlc_hw->phy_sh, core,
  3818. wlc_hw->band->bandtype,
  3819. wlc->wiphy);
  3820. if (wlc_hw->band->pi == NULL) {
  3821. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
  3822. "attach failed\n", unit);
  3823. err = 17;
  3824. goto fail;
  3825. }
  3826. wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
  3827. wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
  3828. &wlc_hw->band->phyrev,
  3829. &wlc_hw->band->radioid,
  3830. &wlc_hw->band->radiorev);
  3831. wlc_hw->band->abgphy_encore =
  3832. wlc_phy_get_encore(wlc_hw->band->pi);
  3833. wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
  3834. wlc_hw->band->core_flags =
  3835. wlc_phy_get_coreflags(wlc_hw->band->pi);
  3836. /* verify good phy_type & supported phy revision */
  3837. if (BRCMS_ISNPHY(wlc_hw->band)) {
  3838. if (NCONF_HAS(wlc_hw->band->phyrev))
  3839. goto good_phy;
  3840. else
  3841. goto bad_phy;
  3842. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  3843. if (LCNCONF_HAS(wlc_hw->band->phyrev))
  3844. goto good_phy;
  3845. else
  3846. goto bad_phy;
  3847. } else {
  3848. bad_phy:
  3849. wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
  3850. "phy type/rev (%d/%d)\n", unit,
  3851. wlc_hw->band->phytype, wlc_hw->band->phyrev);
  3852. err = 18;
  3853. goto fail;
  3854. }
  3855. good_phy:
  3856. /*
  3857. * BMAC_NOTE: wlc->band->pi should not be set below and should
  3858. * be done in the high level attach. However we can not make
  3859. * that change until all low level access is changed to
  3860. * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
  3861. * keeping wlc_hw->band->pi as well for incremental update of
  3862. * low level fns, and cut over low only init when all fns
  3863. * updated.
  3864. */
  3865. wlc->band->pi = wlc_hw->band->pi;
  3866. wlc->band->phytype = wlc_hw->band->phytype;
  3867. wlc->band->phyrev = wlc_hw->band->phyrev;
  3868. wlc->band->radioid = wlc_hw->band->radioid;
  3869. wlc->band->radiorev = wlc_hw->band->radiorev;
  3870. /* default contention windows size limits */
  3871. wlc_hw->band->CWmin = APHY_CWMIN;
  3872. wlc_hw->band->CWmax = PHY_CWMAX;
  3873. if (!brcms_b_attach_dmapio(wlc, j, wme)) {
  3874. err = 19;
  3875. goto fail;
  3876. }
  3877. }
  3878. /* disable core to match driver "down" state */
  3879. brcms_c_coredisable(wlc_hw);
  3880. /* Match driver "down" state */
  3881. ai_pci_down(wlc_hw->sih);
  3882. /* turn off pll and xtal to match driver "down" state */
  3883. brcms_b_xtal(wlc_hw, OFF);
  3884. /* *******************************************************************
  3885. * The hardware is in the DOWN state at this point. D11 core
  3886. * or cores are in reset with clocks off, and the board PLLs
  3887. * are off if possible.
  3888. *
  3889. * Beyond this point, wlc->sbclk == false and chip registers
  3890. * should not be touched.
  3891. *********************************************************************
  3892. */
  3893. /* init etheraddr state variables */
  3894. brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
  3895. if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
  3896. is_zero_ether_addr(wlc_hw->etheraddr)) {
  3897. wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
  3898. unit);
  3899. err = 22;
  3900. goto fail;
  3901. }
  3902. brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
  3903. wlc_hw->deviceid, wlc_hw->_nbands,
  3904. ai_get_boardtype(wlc_hw->sih));
  3905. return err;
  3906. fail:
  3907. wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
  3908. err);
  3909. return err;
  3910. }
  3911. static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
  3912. {
  3913. uint unit;
  3914. unit = wlc->pub->unit;
  3915. if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
  3916. /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
  3917. wlc->band->antgain = 8;
  3918. } else if (wlc->band->antgain == -1) {
  3919. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  3920. " srom, using 2dB\n", unit, __func__);
  3921. wlc->band->antgain = 8;
  3922. } else {
  3923. s8 gain, fract;
  3924. /* Older sroms specified gain in whole dbm only. In order
  3925. * be able to specify qdbm granularity and remain backward
  3926. * compatible the whole dbms are now encoded in only
  3927. * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
  3928. * 6 bit signed number ranges from -32 - 31.
  3929. *
  3930. * Examples:
  3931. * 0x1 = 1 db,
  3932. * 0xc1 = 1.75 db (1 + 3 quarters),
  3933. * 0x3f = -1 (-1 + 0 quarters),
  3934. * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
  3935. * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
  3936. */
  3937. gain = wlc->band->antgain & 0x3f;
  3938. gain <<= 2; /* Sign extend */
  3939. gain >>= 2;
  3940. fract = (wlc->band->antgain & 0xc0) >> 6;
  3941. wlc->band->antgain = 4 * gain + fract;
  3942. }
  3943. }
  3944. static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
  3945. {
  3946. int aa;
  3947. uint unit;
  3948. int bandtype;
  3949. struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
  3950. unit = wlc->pub->unit;
  3951. bandtype = wlc->band->bandtype;
  3952. /* get antennas available */
  3953. if (bandtype == BRCM_BAND_5G)
  3954. aa = sprom->ant_available_a;
  3955. else
  3956. aa = sprom->ant_available_bg;
  3957. if ((aa < 1) || (aa > 15)) {
  3958. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  3959. " srom (0x%x), using 3\n", unit, __func__, aa);
  3960. aa = 3;
  3961. }
  3962. /* reset the defaults if we have a single antenna */
  3963. if (aa == 1) {
  3964. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
  3965. wlc->stf->txant = ANT_TX_FORCE_0;
  3966. } else if (aa == 2) {
  3967. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
  3968. wlc->stf->txant = ANT_TX_FORCE_1;
  3969. } else {
  3970. }
  3971. /* Compute Antenna Gain */
  3972. if (bandtype == BRCM_BAND_5G)
  3973. wlc->band->antgain = sprom->antenna_gain.a1;
  3974. else
  3975. wlc->band->antgain = sprom->antenna_gain.a0;
  3976. brcms_c_attach_antgain_init(wlc);
  3977. return true;
  3978. }
  3979. static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
  3980. {
  3981. u16 chanspec;
  3982. struct brcms_band *band;
  3983. struct brcms_bss_info *bi = wlc->default_bss;
  3984. /* init default and target BSS with some sane initial values */
  3985. memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
  3986. bi->beacon_period = BEACON_INTERVAL_DEFAULT;
  3987. /* fill the default channel as the first valid channel
  3988. * starting from the 2G channels
  3989. */
  3990. chanspec = ch20mhz_chspec(1);
  3991. wlc->home_chanspec = bi->chanspec = chanspec;
  3992. /* find the band of our default channel */
  3993. band = wlc->band;
  3994. if (wlc->pub->_nbands > 1 &&
  3995. band->bandunit != chspec_bandunit(chanspec))
  3996. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  3997. /* init bss rates to the band specific default rate set */
  3998. brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
  3999. band->bandtype, false, BRCMS_RATE_MASK_FULL,
  4000. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  4001. brcms_chspec_bw(chanspec), wlc->stf->txstreams);
  4002. if (wlc->pub->_n_enab & SUPPORT_11N)
  4003. bi->flags |= BRCMS_BSS_HT;
  4004. }
  4005. static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
  4006. {
  4007. uint i;
  4008. struct brcms_band *band;
  4009. for (i = 0; i < wlc->pub->_nbands; i++) {
  4010. band = wlc->bandstate[i];
  4011. if (band->bandtype == BRCM_BAND_5G) {
  4012. if ((bwcap == BRCMS_N_BW_40ALL)
  4013. || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
  4014. band->mimo_cap_40 = true;
  4015. else
  4016. band->mimo_cap_40 = false;
  4017. } else {
  4018. if (bwcap == BRCMS_N_BW_40ALL)
  4019. band->mimo_cap_40 = true;
  4020. else
  4021. band->mimo_cap_40 = false;
  4022. }
  4023. }
  4024. }
  4025. static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
  4026. {
  4027. /* free timer state */
  4028. if (wlc->wdtimer) {
  4029. brcms_free_timer(wlc->wdtimer);
  4030. wlc->wdtimer = NULL;
  4031. }
  4032. if (wlc->radio_timer) {
  4033. brcms_free_timer(wlc->radio_timer);
  4034. wlc->radio_timer = NULL;
  4035. }
  4036. }
  4037. static void brcms_c_detach_module(struct brcms_c_info *wlc)
  4038. {
  4039. if (wlc->asi) {
  4040. brcms_c_antsel_detach(wlc->asi);
  4041. wlc->asi = NULL;
  4042. }
  4043. if (wlc->ampdu) {
  4044. brcms_c_ampdu_detach(wlc->ampdu);
  4045. wlc->ampdu = NULL;
  4046. }
  4047. brcms_c_stf_detach(wlc);
  4048. }
  4049. /*
  4050. * low level detach
  4051. */
  4052. static int brcms_b_detach(struct brcms_c_info *wlc)
  4053. {
  4054. uint i;
  4055. struct brcms_hw_band *band;
  4056. struct brcms_hardware *wlc_hw = wlc->hw;
  4057. int callbacks;
  4058. callbacks = 0;
  4059. brcms_b_detach_dmapio(wlc_hw);
  4060. band = wlc_hw->band;
  4061. for (i = 0; i < wlc_hw->_nbands; i++) {
  4062. if (band->pi) {
  4063. /* Detach this band's phy */
  4064. wlc_phy_detach(band->pi);
  4065. band->pi = NULL;
  4066. }
  4067. band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
  4068. }
  4069. /* Free shared phy state */
  4070. kfree(wlc_hw->phy_sh);
  4071. wlc_phy_shim_detach(wlc_hw->physhim);
  4072. if (wlc_hw->sih) {
  4073. ai_detach(wlc_hw->sih);
  4074. wlc_hw->sih = NULL;
  4075. }
  4076. return callbacks;
  4077. }
  4078. /*
  4079. * Return a count of the number of driver callbacks still pending.
  4080. *
  4081. * General policy is that brcms_c_detach can only dealloc/free software states.
  4082. * It can NOT touch hardware registers since the d11core may be in reset and
  4083. * clock may not be available.
  4084. * One exception is sb register access, which is possible if crystal is turned
  4085. * on after "down" state, driver should avoid software timer with the exception
  4086. * of radio_monitor.
  4087. */
  4088. uint brcms_c_detach(struct brcms_c_info *wlc)
  4089. {
  4090. uint callbacks = 0;
  4091. if (wlc == NULL)
  4092. return 0;
  4093. callbacks += brcms_b_detach(wlc);
  4094. /* delete software timers */
  4095. if (!brcms_c_radio_monitor_stop(wlc))
  4096. callbacks++;
  4097. brcms_c_channel_mgr_detach(wlc->cmi);
  4098. brcms_c_timers_deinit(wlc);
  4099. brcms_c_detach_module(wlc);
  4100. brcms_c_detach_mfree(wlc);
  4101. return callbacks;
  4102. }
  4103. /* update state that depends on the current value of "ap" */
  4104. static void brcms_c_ap_upd(struct brcms_c_info *wlc)
  4105. {
  4106. /* STA-BSS; short capable */
  4107. wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
  4108. }
  4109. /* Initialize just the hardware when coming out of POR or S3/S5 system states */
  4110. static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
  4111. {
  4112. if (wlc_hw->wlc->pub->hw_up)
  4113. return;
  4114. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  4115. /*
  4116. * Enable pll and xtal, initialize the power control registers,
  4117. * and force fastclock for the remainder of brcms_c_up().
  4118. */
  4119. brcms_b_xtal(wlc_hw, ON);
  4120. ai_clkctl_init(wlc_hw->sih);
  4121. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  4122. /*
  4123. * TODO: test suspend/resume
  4124. *
  4125. * AI chip doesn't restore bar0win2 on
  4126. * hibernation/resume, need sw fixup
  4127. */
  4128. /*
  4129. * Inform phy that a POR reset has occurred so
  4130. * it does a complete phy init
  4131. */
  4132. wlc_phy_por_inform(wlc_hw->band->pi);
  4133. wlc_hw->ucode_loaded = false;
  4134. wlc_hw->wlc->pub->hw_up = true;
  4135. if ((wlc_hw->boardflags & BFL_FEM)
  4136. && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
  4137. if (!
  4138. (wlc_hw->boardrev >= 0x1250
  4139. && (wlc_hw->boardflags & BFL_FEM_BT)))
  4140. ai_epa_4313war(wlc_hw->sih);
  4141. }
  4142. }
  4143. static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
  4144. {
  4145. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  4146. /*
  4147. * Enable pll and xtal, initialize the power control registers,
  4148. * and force fastclock for the remainder of brcms_c_up().
  4149. */
  4150. brcms_b_xtal(wlc_hw, ON);
  4151. ai_clkctl_init(wlc_hw->sih);
  4152. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  4153. /*
  4154. * Configure pci/pcmcia here instead of in brcms_c_attach()
  4155. * to allow mfg hotswap: down, hotswap (chip power cycle), up.
  4156. */
  4157. bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
  4158. true);
  4159. /*
  4160. * Need to read the hwradio status here to cover the case where the
  4161. * system is loaded with the hw radio disabled. We do not want to
  4162. * bring the driver up in this case.
  4163. */
  4164. if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
  4165. /* put SB PCI in down state again */
  4166. ai_pci_down(wlc_hw->sih);
  4167. brcms_b_xtal(wlc_hw, OFF);
  4168. return -ENOMEDIUM;
  4169. }
  4170. ai_pci_up(wlc_hw->sih);
  4171. /* reset the d11 core */
  4172. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  4173. return 0;
  4174. }
  4175. static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
  4176. {
  4177. wlc_hw->up = true;
  4178. wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
  4179. /* FULLY enable dynamic power control and d11 core interrupt */
  4180. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  4181. brcms_intrson(wlc_hw->wlc->wl);
  4182. return 0;
  4183. }
  4184. /*
  4185. * Write WME tunable parameters for retransmit/max rate
  4186. * from wlc struct to ucode
  4187. */
  4188. static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
  4189. {
  4190. int ac;
  4191. /* Need clock to do this */
  4192. if (!wlc->clk)
  4193. return;
  4194. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  4195. brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
  4196. wlc->wme_retries[ac]);
  4197. }
  4198. /* make interface operational */
  4199. int brcms_c_up(struct brcms_c_info *wlc)
  4200. {
  4201. struct ieee80211_channel *ch;
  4202. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  4203. /* HW is turned off so don't try to access it */
  4204. if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
  4205. return -ENOMEDIUM;
  4206. if (!wlc->pub->hw_up) {
  4207. brcms_b_hw_up(wlc->hw);
  4208. wlc->pub->hw_up = true;
  4209. }
  4210. if ((wlc->pub->boardflags & BFL_FEM)
  4211. && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
  4212. if (wlc->pub->boardrev >= 0x1250
  4213. && (wlc->pub->boardflags & BFL_FEM_BT))
  4214. brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
  4215. MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
  4216. else
  4217. brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
  4218. MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
  4219. }
  4220. /*
  4221. * Need to read the hwradio status here to cover the case where the
  4222. * system is loaded with the hw radio disabled. We do not want to bring
  4223. * the driver up in this case. If radio is disabled, abort up, lower
  4224. * power, start radio timer and return 0(for NDIS) don't call
  4225. * radio_update to avoid looping brcms_c_up.
  4226. *
  4227. * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
  4228. */
  4229. if (!wlc->pub->radio_disabled) {
  4230. int status = brcms_b_up_prep(wlc->hw);
  4231. if (status == -ENOMEDIUM) {
  4232. if (!mboolisset
  4233. (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
  4234. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  4235. mboolset(wlc->pub->radio_disabled,
  4236. WL_RADIO_HW_DISABLE);
  4237. if (bsscfg->enable && bsscfg->BSS)
  4238. brcms_err(wlc->hw->d11core,
  4239. "wl%d: up: rfdisable -> "
  4240. "bsscfg_disable()\n",
  4241. wlc->pub->unit);
  4242. }
  4243. }
  4244. }
  4245. if (wlc->pub->radio_disabled) {
  4246. brcms_c_radio_monitor_start(wlc);
  4247. return 0;
  4248. }
  4249. /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
  4250. wlc->clk = true;
  4251. brcms_c_radio_monitor_stop(wlc);
  4252. /* Set EDCF hostflags */
  4253. brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
  4254. brcms_init(wlc->wl);
  4255. wlc->pub->up = true;
  4256. if (wlc->bandinit_pending) {
  4257. ch = wlc->pub->ieee_hw->conf.channel;
  4258. brcms_c_suspend_mac_and_wait(wlc);
  4259. brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
  4260. wlc->bandinit_pending = false;
  4261. brcms_c_enable_mac(wlc);
  4262. }
  4263. brcms_b_up_finish(wlc->hw);
  4264. /* Program the TX wme params with the current settings */
  4265. brcms_c_wme_retries_write(wlc);
  4266. /* start one second watchdog timer */
  4267. brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
  4268. wlc->WDarmed = true;
  4269. /* ensure antenna config is up to date */
  4270. brcms_c_stf_phy_txant_upd(wlc);
  4271. /* ensure LDPC config is in sync */
  4272. brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
  4273. return 0;
  4274. }
  4275. static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
  4276. {
  4277. uint callbacks = 0;
  4278. return callbacks;
  4279. }
  4280. static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
  4281. {
  4282. bool dev_gone;
  4283. uint callbacks = 0;
  4284. if (!wlc_hw->up)
  4285. return callbacks;
  4286. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4287. /* disable interrupts */
  4288. if (dev_gone)
  4289. wlc_hw->wlc->macintmask = 0;
  4290. else {
  4291. /* now disable interrupts */
  4292. brcms_intrsoff(wlc_hw->wlc->wl);
  4293. /* ensure we're running on the pll clock again */
  4294. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  4295. }
  4296. /* down phy at the last of this stage */
  4297. callbacks += wlc_phy_down(wlc_hw->band->pi);
  4298. return callbacks;
  4299. }
  4300. static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
  4301. {
  4302. uint callbacks = 0;
  4303. bool dev_gone;
  4304. if (!wlc_hw->up)
  4305. return callbacks;
  4306. wlc_hw->up = false;
  4307. wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
  4308. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4309. if (dev_gone) {
  4310. wlc_hw->sbclk = false;
  4311. wlc_hw->clk = false;
  4312. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  4313. /* reclaim any posted packets */
  4314. brcms_c_flushqueues(wlc_hw->wlc);
  4315. } else {
  4316. /* Reset and disable the core */
  4317. if (bcma_core_is_enabled(wlc_hw->d11core)) {
  4318. if (bcma_read32(wlc_hw->d11core,
  4319. D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
  4320. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  4321. callbacks += brcms_reset(wlc_hw->wlc->wl);
  4322. brcms_c_coredisable(wlc_hw);
  4323. }
  4324. /* turn off primary xtal and pll */
  4325. if (!wlc_hw->noreset) {
  4326. ai_pci_down(wlc_hw->sih);
  4327. brcms_b_xtal(wlc_hw, OFF);
  4328. }
  4329. }
  4330. return callbacks;
  4331. }
  4332. /*
  4333. * Mark the interface nonoperational, stop the software mechanisms,
  4334. * disable the hardware, free any transient buffer state.
  4335. * Return a count of the number of driver callbacks still pending.
  4336. */
  4337. uint brcms_c_down(struct brcms_c_info *wlc)
  4338. {
  4339. uint callbacks = 0;
  4340. int i;
  4341. bool dev_gone = false;
  4342. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  4343. /* check if we are already in the going down path */
  4344. if (wlc->going_down) {
  4345. brcms_err(wlc->hw->d11core,
  4346. "wl%d: %s: Driver going down so return\n",
  4347. wlc->pub->unit, __func__);
  4348. return 0;
  4349. }
  4350. if (!wlc->pub->up)
  4351. return callbacks;
  4352. wlc->going_down = true;
  4353. callbacks += brcms_b_bmac_down_prep(wlc->hw);
  4354. dev_gone = brcms_deviceremoved(wlc);
  4355. /* Call any registered down handlers */
  4356. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4357. if (wlc->modulecb[i].down_fn)
  4358. callbacks +=
  4359. wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
  4360. }
  4361. /* cancel the watchdog timer */
  4362. if (wlc->WDarmed) {
  4363. if (!brcms_del_timer(wlc->wdtimer))
  4364. callbacks++;
  4365. wlc->WDarmed = false;
  4366. }
  4367. /* cancel all other timers */
  4368. callbacks += brcms_c_down_del_timer(wlc);
  4369. wlc->pub->up = false;
  4370. wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
  4371. callbacks += brcms_b_down_finish(wlc->hw);
  4372. /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
  4373. wlc->clk = false;
  4374. wlc->going_down = false;
  4375. return callbacks;
  4376. }
  4377. /* Set the current gmode configuration */
  4378. int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
  4379. {
  4380. int ret = 0;
  4381. uint i;
  4382. struct brcms_c_rateset rs;
  4383. /* Default to 54g Auto */
  4384. /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
  4385. s8 shortslot = BRCMS_SHORTSLOT_AUTO;
  4386. bool shortslot_restrict = false; /* Restrict association to stations
  4387. * that support shortslot
  4388. */
  4389. bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
  4390. /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
  4391. int preamble = BRCMS_PLCP_LONG;
  4392. bool preamble_restrict = false; /* Restrict association to stations
  4393. * that support short preambles
  4394. */
  4395. struct brcms_band *band;
  4396. /* if N-support is enabled, allow Gmode set as long as requested
  4397. * Gmode is not GMODE_LEGACY_B
  4398. */
  4399. if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
  4400. return -ENOTSUPP;
  4401. /* verify that we are dealing with 2G band and grab the band pointer */
  4402. if (wlc->band->bandtype == BRCM_BAND_2G)
  4403. band = wlc->band;
  4404. else if ((wlc->pub->_nbands > 1) &&
  4405. (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
  4406. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  4407. else
  4408. return -EINVAL;
  4409. /* update configuration value */
  4410. if (config)
  4411. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
  4412. /* Clear rateset override */
  4413. memset(&rs, 0, sizeof(struct brcms_c_rateset));
  4414. switch (gmode) {
  4415. case GMODE_LEGACY_B:
  4416. shortslot = BRCMS_SHORTSLOT_OFF;
  4417. brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
  4418. break;
  4419. case GMODE_LRS:
  4420. break;
  4421. case GMODE_AUTO:
  4422. /* Accept defaults */
  4423. break;
  4424. case GMODE_ONLY:
  4425. ofdm_basic = true;
  4426. preamble = BRCMS_PLCP_SHORT;
  4427. preamble_restrict = true;
  4428. break;
  4429. case GMODE_PERFORMANCE:
  4430. shortslot = BRCMS_SHORTSLOT_ON;
  4431. shortslot_restrict = true;
  4432. ofdm_basic = true;
  4433. preamble = BRCMS_PLCP_SHORT;
  4434. preamble_restrict = true;
  4435. break;
  4436. default:
  4437. /* Error */
  4438. brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
  4439. wlc->pub->unit, __func__, gmode);
  4440. return -ENOTSUPP;
  4441. }
  4442. band->gmode = gmode;
  4443. wlc->shortslot_override = shortslot;
  4444. /* Use the default 11g rateset */
  4445. if (!rs.count)
  4446. brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
  4447. if (ofdm_basic) {
  4448. for (i = 0; i < rs.count; i++) {
  4449. if (rs.rates[i] == BRCM_RATE_6M
  4450. || rs.rates[i] == BRCM_RATE_12M
  4451. || rs.rates[i] == BRCM_RATE_24M)
  4452. rs.rates[i] |= BRCMS_RATE_FLAG;
  4453. }
  4454. }
  4455. /* Set default bss rateset */
  4456. wlc->default_bss->rateset.count = rs.count;
  4457. memcpy(wlc->default_bss->rateset.rates, rs.rates,
  4458. sizeof(wlc->default_bss->rateset.rates));
  4459. return ret;
  4460. }
  4461. int brcms_c_set_nmode(struct brcms_c_info *wlc)
  4462. {
  4463. uint i;
  4464. s32 nmode = AUTO;
  4465. if (wlc->stf->txstreams == WL_11N_3x3)
  4466. nmode = WL_11N_3x3;
  4467. else
  4468. nmode = WL_11N_2x2;
  4469. /* force GMODE_AUTO if NMODE is ON */
  4470. brcms_c_set_gmode(wlc, GMODE_AUTO, true);
  4471. if (nmode == WL_11N_3x3)
  4472. wlc->pub->_n_enab = SUPPORT_HT;
  4473. else
  4474. wlc->pub->_n_enab = SUPPORT_11N;
  4475. wlc->default_bss->flags |= BRCMS_BSS_HT;
  4476. /* add the mcs rates to the default and hw ratesets */
  4477. brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
  4478. wlc->stf->txstreams);
  4479. for (i = 0; i < wlc->pub->_nbands; i++)
  4480. memcpy(wlc->bandstate[i]->hw_rateset.mcs,
  4481. wlc->default_bss->rateset.mcs, MCSSET_LEN);
  4482. return 0;
  4483. }
  4484. static int
  4485. brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
  4486. struct brcms_c_rateset *rs_arg)
  4487. {
  4488. struct brcms_c_rateset rs, new;
  4489. uint bandunit;
  4490. memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
  4491. /* check for bad count value */
  4492. if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
  4493. return -EINVAL;
  4494. /* try the current band */
  4495. bandunit = wlc->band->bandunit;
  4496. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4497. if (brcms_c_rate_hwrs_filter_sort_validate
  4498. (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
  4499. wlc->stf->txstreams))
  4500. goto good;
  4501. /* try the other band */
  4502. if (brcms_is_mband_unlocked(wlc)) {
  4503. bandunit = OTHERBANDUNIT(wlc);
  4504. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4505. if (brcms_c_rate_hwrs_filter_sort_validate(&new,
  4506. &wlc->
  4507. bandstate[bandunit]->
  4508. hw_rateset, true,
  4509. wlc->stf->txstreams))
  4510. goto good;
  4511. }
  4512. return -EBADE;
  4513. good:
  4514. /* apply new rateset */
  4515. memcpy(&wlc->default_bss->rateset, &new,
  4516. sizeof(struct brcms_c_rateset));
  4517. memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
  4518. sizeof(struct brcms_c_rateset));
  4519. return 0;
  4520. }
  4521. static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
  4522. {
  4523. u8 r;
  4524. bool war = false;
  4525. if (wlc->bsscfg->associated)
  4526. r = wlc->bsscfg->current_bss->rateset.rates[0];
  4527. else
  4528. r = wlc->default_bss->rateset.rates[0];
  4529. wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
  4530. }
  4531. int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
  4532. {
  4533. u16 chspec = ch20mhz_chspec(channel);
  4534. if (channel < 0 || channel > MAXCHANNEL)
  4535. return -EINVAL;
  4536. if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
  4537. return -EINVAL;
  4538. if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
  4539. if (wlc->band->bandunit != chspec_bandunit(chspec))
  4540. wlc->bandinit_pending = true;
  4541. else
  4542. wlc->bandinit_pending = false;
  4543. }
  4544. wlc->default_bss->chanspec = chspec;
  4545. /* brcms_c_BSSinit() will sanitize the rateset before
  4546. * using it.. */
  4547. if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
  4548. brcms_c_set_home_chanspec(wlc, chspec);
  4549. brcms_c_suspend_mac_and_wait(wlc);
  4550. brcms_c_set_chanspec(wlc, chspec);
  4551. brcms_c_enable_mac(wlc);
  4552. }
  4553. return 0;
  4554. }
  4555. int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
  4556. {
  4557. int ac;
  4558. if (srl < 1 || srl > RETRY_SHORT_MAX ||
  4559. lrl < 1 || lrl > RETRY_SHORT_MAX)
  4560. return -EINVAL;
  4561. wlc->SRL = srl;
  4562. wlc->LRL = lrl;
  4563. brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
  4564. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
  4565. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4566. EDCF_SHORT, wlc->SRL);
  4567. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4568. EDCF_LONG, wlc->LRL);
  4569. }
  4570. brcms_c_wme_retries_write(wlc);
  4571. return 0;
  4572. }
  4573. void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
  4574. struct brcm_rateset *currs)
  4575. {
  4576. struct brcms_c_rateset *rs;
  4577. if (wlc->pub->associated)
  4578. rs = &wlc->bsscfg->current_bss->rateset;
  4579. else
  4580. rs = &wlc->default_bss->rateset;
  4581. /* Copy only legacy rateset section */
  4582. currs->count = rs->count;
  4583. memcpy(&currs->rates, &rs->rates, rs->count);
  4584. }
  4585. int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
  4586. {
  4587. struct brcms_c_rateset internal_rs;
  4588. int bcmerror;
  4589. if (rs->count > BRCMS_NUMRATES)
  4590. return -ENOBUFS;
  4591. memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
  4592. /* Copy only legacy rateset section */
  4593. internal_rs.count = rs->count;
  4594. memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
  4595. /* merge rateset coming in with the current mcsset */
  4596. if (wlc->pub->_n_enab & SUPPORT_11N) {
  4597. struct brcms_bss_info *mcsset_bss;
  4598. if (wlc->bsscfg->associated)
  4599. mcsset_bss = wlc->bsscfg->current_bss;
  4600. else
  4601. mcsset_bss = wlc->default_bss;
  4602. memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
  4603. MCSSET_LEN);
  4604. }
  4605. bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
  4606. if (!bcmerror)
  4607. brcms_c_ofdm_rateset_war(wlc);
  4608. return bcmerror;
  4609. }
  4610. int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
  4611. {
  4612. if (period < DOT11_MIN_BEACON_PERIOD ||
  4613. period > DOT11_MAX_BEACON_PERIOD)
  4614. return -EINVAL;
  4615. wlc->default_bss->beacon_period = period;
  4616. return 0;
  4617. }
  4618. u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
  4619. {
  4620. return wlc->band->phytype;
  4621. }
  4622. void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
  4623. {
  4624. wlc->shortslot_override = sslot_override;
  4625. /*
  4626. * shortslot is an 11g feature, so no more work if we are
  4627. * currently on the 5G band
  4628. */
  4629. if (wlc->band->bandtype == BRCM_BAND_5G)
  4630. return;
  4631. if (wlc->pub->up && wlc->pub->associated) {
  4632. /* let watchdog or beacon processing update shortslot */
  4633. } else if (wlc->pub->up) {
  4634. /* unassociated shortslot is off */
  4635. brcms_c_switch_shortslot(wlc, false);
  4636. } else {
  4637. /* driver is down, so just update the brcms_c_info
  4638. * value */
  4639. if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
  4640. wlc->shortslot = false;
  4641. else
  4642. wlc->shortslot =
  4643. (wlc->shortslot_override ==
  4644. BRCMS_SHORTSLOT_ON);
  4645. }
  4646. }
  4647. /*
  4648. * register watchdog and down handlers.
  4649. */
  4650. int brcms_c_module_register(struct brcms_pub *pub,
  4651. const char *name, struct brcms_info *hdl,
  4652. int (*d_fn)(void *handle))
  4653. {
  4654. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4655. int i;
  4656. /* find an empty entry and just add, no duplication check! */
  4657. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4658. if (wlc->modulecb[i].name[0] == '\0') {
  4659. strncpy(wlc->modulecb[i].name, name,
  4660. sizeof(wlc->modulecb[i].name) - 1);
  4661. wlc->modulecb[i].hdl = hdl;
  4662. wlc->modulecb[i].down_fn = d_fn;
  4663. return 0;
  4664. }
  4665. }
  4666. return -ENOSR;
  4667. }
  4668. /* unregister module callbacks */
  4669. int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
  4670. struct brcms_info *hdl)
  4671. {
  4672. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4673. int i;
  4674. if (wlc == NULL)
  4675. return -ENODATA;
  4676. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4677. if (!strcmp(wlc->modulecb[i].name, name) &&
  4678. (wlc->modulecb[i].hdl == hdl)) {
  4679. memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
  4680. return 0;
  4681. }
  4682. }
  4683. /* table not found! */
  4684. return -ENODATA;
  4685. }
  4686. static bool brcms_c_chipmatch_pci(struct bcma_device *core)
  4687. {
  4688. struct pci_dev *pcidev = core->bus->host_pci;
  4689. u16 vendor = pcidev->vendor;
  4690. u16 device = pcidev->device;
  4691. if (vendor != PCI_VENDOR_ID_BROADCOM) {
  4692. pr_err("unknown vendor id %04x\n", vendor);
  4693. return false;
  4694. }
  4695. if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
  4696. return true;
  4697. if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
  4698. return true;
  4699. if (device == BCM4313_D11N2G_ID)
  4700. return true;
  4701. if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
  4702. return true;
  4703. pr_err("unknown device id %04x\n", device);
  4704. return false;
  4705. }
  4706. static bool brcms_c_chipmatch_soc(struct bcma_device *core)
  4707. {
  4708. struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
  4709. if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
  4710. return true;
  4711. pr_err("unknown chip id %04x\n", chipinfo->id);
  4712. return false;
  4713. }
  4714. bool brcms_c_chipmatch(struct bcma_device *core)
  4715. {
  4716. switch (core->bus->hosttype) {
  4717. case BCMA_HOSTTYPE_PCI:
  4718. return brcms_c_chipmatch_pci(core);
  4719. case BCMA_HOSTTYPE_SOC:
  4720. return brcms_c_chipmatch_soc(core);
  4721. default:
  4722. pr_err("unknown host type: %i\n", core->bus->hosttype);
  4723. return false;
  4724. }
  4725. }
  4726. u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
  4727. {
  4728. u16 table_ptr;
  4729. u8 phy_rate, index;
  4730. /* get the phy specific rate encoding for the PLCP SIGNAL field */
  4731. if (is_ofdm_rate(rate))
  4732. table_ptr = M_RT_DIRMAP_A;
  4733. else
  4734. table_ptr = M_RT_DIRMAP_B;
  4735. /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
  4736. * the index into the rate table.
  4737. */
  4738. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  4739. index = phy_rate & 0xf;
  4740. /* Find the SHM pointer to the rate table entry by looking in the
  4741. * Direct-map Table
  4742. */
  4743. return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
  4744. }
  4745. /*
  4746. * bcmc_fid_generate:
  4747. * Generate frame ID for a BCMC packet. The frag field is not used
  4748. * for MC frames so is used as part of the sequence number.
  4749. */
  4750. static inline u16
  4751. bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
  4752. struct d11txh *txh)
  4753. {
  4754. u16 frameid;
  4755. frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
  4756. TXFID_QUEUE_MASK);
  4757. frameid |=
  4758. (((wlc->
  4759. mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  4760. TX_BCMC_FIFO;
  4761. return frameid;
  4762. }
  4763. static uint
  4764. brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
  4765. u8 preamble_type)
  4766. {
  4767. uint dur = 0;
  4768. /*
  4769. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  4770. * is less than or equal to the rate of the immediately previous
  4771. * frame in the FES
  4772. */
  4773. rspec = brcms_basic_rate(wlc, rspec);
  4774. /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
  4775. dur =
  4776. brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  4777. (DOT11_ACK_LEN + FCS_LEN));
  4778. return dur;
  4779. }
  4780. static uint
  4781. brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
  4782. u8 preamble_type)
  4783. {
  4784. return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
  4785. }
  4786. static uint
  4787. brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
  4788. u8 preamble_type)
  4789. {
  4790. /*
  4791. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  4792. * is less than or equal to the rate of the immediately previous
  4793. * frame in the FES
  4794. */
  4795. rspec = brcms_basic_rate(wlc, rspec);
  4796. /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
  4797. return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  4798. (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
  4799. FCS_LEN));
  4800. }
  4801. /* brcms_c_compute_frame_dur()
  4802. *
  4803. * Calculate the 802.11 MAC header DUR field for MPDU
  4804. * DUR for a single frame = 1 SIFS + 1 ACK
  4805. * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
  4806. *
  4807. * rate MPDU rate in unit of 500kbps
  4808. * next_frag_len next MPDU length in bytes
  4809. * preamble_type use short/GF or long/MM PLCP header
  4810. */
  4811. static u16
  4812. brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
  4813. u8 preamble_type, uint next_frag_len)
  4814. {
  4815. u16 dur, sifs;
  4816. sifs = get_sifs(wlc->band);
  4817. dur = sifs;
  4818. dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
  4819. if (next_frag_len) {
  4820. /* Double the current DUR to get 2 SIFS + 2 ACKs */
  4821. dur *= 2;
  4822. /* add another SIFS and the frag time */
  4823. dur += sifs;
  4824. dur +=
  4825. (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
  4826. next_frag_len);
  4827. }
  4828. return dur;
  4829. }
  4830. /* The opposite of brcms_c_calc_frame_time */
  4831. static uint
  4832. brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
  4833. u8 preamble_type, uint dur)
  4834. {
  4835. uint nsyms, mac_len, Ndps, kNdps;
  4836. uint rate = rspec2rate(ratespec);
  4837. if (is_mcs_rate(ratespec)) {
  4838. uint mcs = ratespec & RSPEC_RATE_MASK;
  4839. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  4840. dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  4841. /* payload calculation matches that of regular ofdm */
  4842. if (wlc->band->bandtype == BRCM_BAND_2G)
  4843. dur -= DOT11_OFDM_SIGNAL_EXTENSION;
  4844. /* kNdbps = kbps * 4 */
  4845. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  4846. rspec_issgi(ratespec)) * 4;
  4847. nsyms = dur / APHY_SYMBOL_TIME;
  4848. mac_len =
  4849. ((nsyms * kNdps) -
  4850. ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
  4851. } else if (is_ofdm_rate(ratespec)) {
  4852. dur -= APHY_PREAMBLE_TIME;
  4853. dur -= APHY_SIGNAL_TIME;
  4854. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  4855. Ndps = rate * 2;
  4856. nsyms = dur / APHY_SYMBOL_TIME;
  4857. mac_len =
  4858. ((nsyms * Ndps) -
  4859. (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
  4860. } else {
  4861. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  4862. dur -= BPHY_PLCP_SHORT_TIME;
  4863. else
  4864. dur -= BPHY_PLCP_TIME;
  4865. mac_len = dur * rate;
  4866. /* divide out factor of 2 in rate (1/2 mbps) */
  4867. mac_len = mac_len / 8 / 2;
  4868. }
  4869. return mac_len;
  4870. }
  4871. /*
  4872. * Return true if the specified rate is supported by the specified band.
  4873. * BRCM_BAND_AUTO indicates the current band.
  4874. */
  4875. static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
  4876. bool verbose)
  4877. {
  4878. struct brcms_c_rateset *hw_rateset;
  4879. uint i;
  4880. if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
  4881. hw_rateset = &wlc->band->hw_rateset;
  4882. else if (wlc->pub->_nbands > 1)
  4883. hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
  4884. else
  4885. /* other band specified and we are a single band device */
  4886. return false;
  4887. /* check if this is a mimo rate */
  4888. if (is_mcs_rate(rspec)) {
  4889. if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
  4890. goto error;
  4891. return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
  4892. }
  4893. for (i = 0; i < hw_rateset->count; i++)
  4894. if (hw_rateset->rates[i] == rspec2rate(rspec))
  4895. return true;
  4896. error:
  4897. if (verbose)
  4898. brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
  4899. "not in hw_rateset\n", wlc->pub->unit, rspec);
  4900. return false;
  4901. }
  4902. static u32
  4903. mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
  4904. u32 int_val)
  4905. {
  4906. struct bcma_device *core = wlc->hw->d11core;
  4907. u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
  4908. u8 rate = int_val & NRATE_RATE_MASK;
  4909. u32 rspec;
  4910. bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
  4911. bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
  4912. bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
  4913. == NRATE_OVERRIDE_MCS_ONLY);
  4914. int bcmerror = 0;
  4915. if (!ismcs)
  4916. return (u32) rate;
  4917. /* validate the combination of rate/mcs/stf is allowed */
  4918. if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
  4919. /* mcs only allowed when nmode */
  4920. if (stf > PHY_TXC1_MODE_SDM) {
  4921. brcms_err(core, "wl%d: %s: Invalid stf\n",
  4922. wlc->pub->unit, __func__);
  4923. bcmerror = -EINVAL;
  4924. goto done;
  4925. }
  4926. /* mcs 32 is a special case, DUP mode 40 only */
  4927. if (rate == 32) {
  4928. if (!CHSPEC_IS40(wlc->home_chanspec) ||
  4929. ((stf != PHY_TXC1_MODE_SISO)
  4930. && (stf != PHY_TXC1_MODE_CDD))) {
  4931. brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
  4932. wlc->pub->unit, __func__);
  4933. bcmerror = -EINVAL;
  4934. goto done;
  4935. }
  4936. /* mcs > 7 must use stf SDM */
  4937. } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
  4938. /* mcs > 7 must use stf SDM */
  4939. if (stf != PHY_TXC1_MODE_SDM) {
  4940. brcms_dbg_mac80211(core, "wl%d: enabling "
  4941. "SDM mode for mcs %d\n",
  4942. wlc->pub->unit, rate);
  4943. stf = PHY_TXC1_MODE_SDM;
  4944. }
  4945. } else {
  4946. /*
  4947. * MCS 0-7 may use SISO, CDD, and for
  4948. * phy_rev >= 3 STBC
  4949. */
  4950. if ((stf > PHY_TXC1_MODE_STBC) ||
  4951. (!BRCMS_STBC_CAP_PHY(wlc)
  4952. && (stf == PHY_TXC1_MODE_STBC))) {
  4953. brcms_err(core, "wl%d: %s: Invalid STBC\n",
  4954. wlc->pub->unit, __func__);
  4955. bcmerror = -EINVAL;
  4956. goto done;
  4957. }
  4958. }
  4959. } else if (is_ofdm_rate(rate)) {
  4960. if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
  4961. brcms_err(core, "wl%d: %s: Invalid OFDM\n",
  4962. wlc->pub->unit, __func__);
  4963. bcmerror = -EINVAL;
  4964. goto done;
  4965. }
  4966. } else if (is_cck_rate(rate)) {
  4967. if ((cur_band->bandtype != BRCM_BAND_2G)
  4968. || (stf != PHY_TXC1_MODE_SISO)) {
  4969. brcms_err(core, "wl%d: %s: Invalid CCK\n",
  4970. wlc->pub->unit, __func__);
  4971. bcmerror = -EINVAL;
  4972. goto done;
  4973. }
  4974. } else {
  4975. brcms_err(core, "wl%d: %s: Unknown rate type\n",
  4976. wlc->pub->unit, __func__);
  4977. bcmerror = -EINVAL;
  4978. goto done;
  4979. }
  4980. /* make sure multiple antennae are available for non-siso rates */
  4981. if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
  4982. brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
  4983. "request\n", wlc->pub->unit, __func__);
  4984. bcmerror = -EINVAL;
  4985. goto done;
  4986. }
  4987. rspec = rate;
  4988. if (ismcs) {
  4989. rspec |= RSPEC_MIMORATE;
  4990. /* For STBC populate the STC field of the ratespec */
  4991. if (stf == PHY_TXC1_MODE_STBC) {
  4992. u8 stc;
  4993. stc = 1; /* Nss for single stream is always 1 */
  4994. rspec |= (stc << RSPEC_STC_SHIFT);
  4995. }
  4996. }
  4997. rspec |= (stf << RSPEC_STF_SHIFT);
  4998. if (override_mcs_only)
  4999. rspec |= RSPEC_OVERRIDE_MCS_ONLY;
  5000. if (issgi)
  5001. rspec |= RSPEC_SHORT_GI;
  5002. if ((rate != 0)
  5003. && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
  5004. return rate;
  5005. return rspec;
  5006. done:
  5007. return rate;
  5008. }
  5009. /*
  5010. * Compute PLCP, but only requires actual rate and length of pkt.
  5011. * Rate is given in the driver standard multiple of 500 kbps.
  5012. * le is set for 11 Mbps rate if necessary.
  5013. * Broken out for PRQ.
  5014. */
  5015. static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
  5016. uint length, u8 *plcp)
  5017. {
  5018. u16 usec = 0;
  5019. u8 le = 0;
  5020. switch (rate_500) {
  5021. case BRCM_RATE_1M:
  5022. usec = length << 3;
  5023. break;
  5024. case BRCM_RATE_2M:
  5025. usec = length << 2;
  5026. break;
  5027. case BRCM_RATE_5M5:
  5028. usec = (length << 4) / 11;
  5029. if ((length << 4) - (usec * 11) > 0)
  5030. usec++;
  5031. break;
  5032. case BRCM_RATE_11M:
  5033. usec = (length << 3) / 11;
  5034. if ((length << 3) - (usec * 11) > 0) {
  5035. usec++;
  5036. if ((usec * 11) - (length << 3) >= 8)
  5037. le = D11B_PLCP_SIGNAL_LE;
  5038. }
  5039. break;
  5040. default:
  5041. brcms_err(wlc->hw->d11core,
  5042. "brcms_c_cck_plcp_set: unsupported rate %d\n",
  5043. rate_500);
  5044. rate_500 = BRCM_RATE_1M;
  5045. usec = length << 3;
  5046. break;
  5047. }
  5048. /* PLCP signal byte */
  5049. plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
  5050. /* PLCP service byte */
  5051. plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
  5052. /* PLCP length u16, little endian */
  5053. plcp[2] = usec & 0xff;
  5054. plcp[3] = (usec >> 8) & 0xff;
  5055. /* PLCP CRC16 */
  5056. plcp[4] = 0;
  5057. plcp[5] = 0;
  5058. }
  5059. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5060. static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
  5061. {
  5062. u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
  5063. plcp[0] = mcs;
  5064. if (rspec_is40mhz(rspec) || (mcs == 32))
  5065. plcp[0] |= MIMO_PLCP_40MHZ;
  5066. BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
  5067. plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
  5068. plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
  5069. plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
  5070. plcp[5] = 0;
  5071. }
  5072. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5073. static void
  5074. brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
  5075. {
  5076. u8 rate_signal;
  5077. u32 tmp = 0;
  5078. int rate = rspec2rate(rspec);
  5079. /*
  5080. * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
  5081. * transmitted first
  5082. */
  5083. rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
  5084. memset(plcp, 0, D11_PHY_HDR_LEN);
  5085. D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
  5086. tmp = (length & 0xfff) << 5;
  5087. plcp[2] |= (tmp >> 16) & 0xff;
  5088. plcp[1] |= (tmp >> 8) & 0xff;
  5089. plcp[0] |= tmp & 0xff;
  5090. }
  5091. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5092. static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
  5093. uint length, u8 *plcp)
  5094. {
  5095. int rate = rspec2rate(rspec);
  5096. brcms_c_cck_plcp_set(wlc, rate, length, plcp);
  5097. }
  5098. static void
  5099. brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
  5100. uint length, u8 *plcp)
  5101. {
  5102. if (is_mcs_rate(rspec))
  5103. brcms_c_compute_mimo_plcp(rspec, length, plcp);
  5104. else if (is_ofdm_rate(rspec))
  5105. brcms_c_compute_ofdm_plcp(rspec, length, plcp);
  5106. else
  5107. brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
  5108. }
  5109. /* brcms_c_compute_rtscts_dur()
  5110. *
  5111. * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
  5112. * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
  5113. * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
  5114. *
  5115. * cts cts-to-self or rts/cts
  5116. * rts_rate rts or cts rate in unit of 500kbps
  5117. * rate next MPDU rate in unit of 500kbps
  5118. * frame_len next MPDU frame length in bytes
  5119. */
  5120. u16
  5121. brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
  5122. u32 rts_rate,
  5123. u32 frame_rate, u8 rts_preamble_type,
  5124. u8 frame_preamble_type, uint frame_len, bool ba)
  5125. {
  5126. u16 dur, sifs;
  5127. sifs = get_sifs(wlc->band);
  5128. if (!cts_only) {
  5129. /* RTS/CTS */
  5130. dur = 3 * sifs;
  5131. dur +=
  5132. (u16) brcms_c_calc_cts_time(wlc, rts_rate,
  5133. rts_preamble_type);
  5134. } else {
  5135. /* CTS-TO-SELF */
  5136. dur = 2 * sifs;
  5137. }
  5138. dur +=
  5139. (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
  5140. frame_len);
  5141. if (ba)
  5142. dur +=
  5143. (u16) brcms_c_calc_ba_time(wlc, frame_rate,
  5144. BRCMS_SHORT_PREAMBLE);
  5145. else
  5146. dur +=
  5147. (u16) brcms_c_calc_ack_time(wlc, frame_rate,
  5148. frame_preamble_type);
  5149. return dur;
  5150. }
  5151. static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
  5152. {
  5153. u16 phyctl1 = 0;
  5154. u16 bw;
  5155. if (BRCMS_ISLCNPHY(wlc->band)) {
  5156. bw = PHY_TXC1_BW_20MHZ;
  5157. } else {
  5158. bw = rspec_get_bw(rspec);
  5159. /* 10Mhz is not supported yet */
  5160. if (bw < PHY_TXC1_BW_20MHZ) {
  5161. brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
  5162. "not supported yet, set to 20L\n", bw);
  5163. bw = PHY_TXC1_BW_20MHZ;
  5164. }
  5165. }
  5166. if (is_mcs_rate(rspec)) {
  5167. uint mcs = rspec & RSPEC_RATE_MASK;
  5168. /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
  5169. phyctl1 = rspec_phytxbyte2(rspec);
  5170. /* set the upper byte of phyctl1 */
  5171. phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
  5172. } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
  5173. && !BRCMS_ISSSLPNPHY(wlc->band)) {
  5174. /*
  5175. * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
  5176. * Data Rate. Eventually MIMOPHY would also be converted to
  5177. * this format
  5178. */
  5179. /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
  5180. phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5181. } else { /* legacy OFDM/CCK */
  5182. s16 phycfg;
  5183. /* get the phyctl byte from rate phycfg table */
  5184. phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
  5185. if (phycfg == -1) {
  5186. brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
  5187. "legacy OFDM/CCK rate\n");
  5188. phycfg = 0;
  5189. }
  5190. /* set the upper byte of phyctl1 */
  5191. phyctl1 =
  5192. (bw | (phycfg << 8) |
  5193. (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5194. }
  5195. return phyctl1;
  5196. }
  5197. /*
  5198. * Add struct d11txh, struct cck_phy_hdr.
  5199. *
  5200. * 'p' data must start with 802.11 MAC header
  5201. * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
  5202. *
  5203. * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
  5204. *
  5205. */
  5206. static u16
  5207. brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
  5208. struct sk_buff *p, struct scb *scb, uint frag,
  5209. uint nfrags, uint queue, uint next_frag_len)
  5210. {
  5211. struct ieee80211_hdr *h;
  5212. struct d11txh *txh;
  5213. u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
  5214. int len, phylen, rts_phylen;
  5215. u16 mch, phyctl, xfts, mainrates;
  5216. u16 seq = 0, mcl = 0, status = 0, frameid = 0;
  5217. u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5218. u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5219. bool use_rts = false;
  5220. bool use_cts = false;
  5221. bool use_rifs = false;
  5222. bool short_preamble[2] = { false, false };
  5223. u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5224. u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5225. u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
  5226. struct ieee80211_rts *rts = NULL;
  5227. bool qos;
  5228. uint ac;
  5229. bool hwtkmic = false;
  5230. u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
  5231. #define ANTCFG_NONE 0xFF
  5232. u8 antcfg = ANTCFG_NONE;
  5233. u8 fbantcfg = ANTCFG_NONE;
  5234. uint phyctl1_stf = 0;
  5235. u16 durid = 0;
  5236. struct ieee80211_tx_rate *txrate[2];
  5237. int k;
  5238. struct ieee80211_tx_info *tx_info;
  5239. bool is_mcs;
  5240. u16 mimo_txbw;
  5241. u8 mimo_preamble_type;
  5242. /* locate 802.11 MAC header */
  5243. h = (struct ieee80211_hdr *)(p->data);
  5244. qos = ieee80211_is_data_qos(h->frame_control);
  5245. /* compute length of frame in bytes for use in PLCP computations */
  5246. len = p->len;
  5247. phylen = len + FCS_LEN;
  5248. /* Get tx_info */
  5249. tx_info = IEEE80211_SKB_CB(p);
  5250. /* add PLCP */
  5251. plcp = skb_push(p, D11_PHY_HDR_LEN);
  5252. /* add Broadcom tx descriptor header */
  5253. txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
  5254. memset(txh, 0, D11_TXH_LEN);
  5255. /* setup frameid */
  5256. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  5257. /* non-AP STA should never use BCMC queue */
  5258. if (queue == TX_BCMC_FIFO) {
  5259. brcms_err(wlc->hw->d11core,
  5260. "wl%d: %s: ASSERT queue == TX_BCMC!\n",
  5261. wlc->pub->unit, __func__);
  5262. frameid = bcmc_fid_generate(wlc, NULL, txh);
  5263. } else {
  5264. /* Increment the counter for first fragment */
  5265. if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  5266. scb->seqnum[p->priority]++;
  5267. /* extract fragment number from frame first */
  5268. seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
  5269. seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
  5270. h->seq_ctrl = cpu_to_le16(seq);
  5271. frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  5272. (queue & TXFID_QUEUE_MASK);
  5273. }
  5274. }
  5275. frameid |= queue & TXFID_QUEUE_MASK;
  5276. /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
  5277. if (ieee80211_is_beacon(h->frame_control))
  5278. mcl |= TXC_IGNOREPMQ;
  5279. txrate[0] = tx_info->control.rates;
  5280. txrate[1] = txrate[0] + 1;
  5281. /*
  5282. * if rate control algorithm didn't give us a fallback
  5283. * rate, use the primary rate
  5284. */
  5285. if (txrate[1]->idx < 0)
  5286. txrate[1] = txrate[0];
  5287. for (k = 0; k < hw->max_rates; k++) {
  5288. is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
  5289. if (!is_mcs) {
  5290. if ((txrate[k]->idx >= 0)
  5291. && (txrate[k]->idx <
  5292. hw->wiphy->bands[tx_info->band]->n_bitrates)) {
  5293. rspec[k] =
  5294. hw->wiphy->bands[tx_info->band]->
  5295. bitrates[txrate[k]->idx].hw_value;
  5296. short_preamble[k] =
  5297. txrate[k]->
  5298. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
  5299. true : false;
  5300. } else {
  5301. rspec[k] = BRCM_RATE_1M;
  5302. }
  5303. } else {
  5304. rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
  5305. NRATE_MCS_INUSE | txrate[k]->idx);
  5306. }
  5307. /*
  5308. * Currently only support same setting for primay and
  5309. * fallback rates. Unify flags for each rate into a
  5310. * single value for the frame
  5311. */
  5312. use_rts |=
  5313. txrate[k]->
  5314. flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
  5315. use_cts |=
  5316. txrate[k]->
  5317. flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
  5318. /*
  5319. * (1) RATE:
  5320. * determine and validate primary rate
  5321. * and fallback rates
  5322. */
  5323. if (!rspec_active(rspec[k])) {
  5324. rspec[k] = BRCM_RATE_1M;
  5325. } else {
  5326. if (!is_multicast_ether_addr(h->addr1)) {
  5327. /* set tx antenna config */
  5328. brcms_c_antsel_antcfg_get(wlc->asi, false,
  5329. false, 0, 0, &antcfg, &fbantcfg);
  5330. }
  5331. }
  5332. }
  5333. phyctl1_stf = wlc->stf->ss_opmode;
  5334. if (wlc->pub->_n_enab & SUPPORT_11N) {
  5335. for (k = 0; k < hw->max_rates; k++) {
  5336. /*
  5337. * apply siso/cdd to single stream mcs's or ofdm
  5338. * if rspec is auto selected
  5339. */
  5340. if (((is_mcs_rate(rspec[k]) &&
  5341. is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
  5342. is_ofdm_rate(rspec[k]))
  5343. && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
  5344. || !(rspec[k] & RSPEC_OVERRIDE))) {
  5345. rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
  5346. /* For SISO MCS use STBC if possible */
  5347. if (is_mcs_rate(rspec[k])
  5348. && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
  5349. u8 stc;
  5350. /* Nss for single stream is always 1 */
  5351. stc = 1;
  5352. rspec[k] |= (PHY_TXC1_MODE_STBC <<
  5353. RSPEC_STF_SHIFT) |
  5354. (stc << RSPEC_STC_SHIFT);
  5355. } else
  5356. rspec[k] |=
  5357. (phyctl1_stf << RSPEC_STF_SHIFT);
  5358. }
  5359. /*
  5360. * Is the phy configured to use 40MHZ frames? If
  5361. * so then pick the desired txbw
  5362. */
  5363. if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
  5364. /* default txbw is 20in40 SB */
  5365. mimo_ctlchbw = mimo_txbw =
  5366. CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
  5367. wlc->band->pi))
  5368. ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
  5369. if (is_mcs_rate(rspec[k])) {
  5370. /* mcs 32 must be 40b/w DUP */
  5371. if ((rspec[k] & RSPEC_RATE_MASK)
  5372. == 32) {
  5373. mimo_txbw =
  5374. PHY_TXC1_BW_40MHZ_DUP;
  5375. /* use override */
  5376. } else if (wlc->mimo_40txbw != AUTO)
  5377. mimo_txbw = wlc->mimo_40txbw;
  5378. /* else check if dst is using 40 Mhz */
  5379. else if (scb->flags & SCB_IS40)
  5380. mimo_txbw = PHY_TXC1_BW_40MHZ;
  5381. } else if (is_ofdm_rate(rspec[k])) {
  5382. if (wlc->ofdm_40txbw != AUTO)
  5383. mimo_txbw = wlc->ofdm_40txbw;
  5384. } else if (wlc->cck_40txbw != AUTO) {
  5385. mimo_txbw = wlc->cck_40txbw;
  5386. }
  5387. } else {
  5388. /*
  5389. * mcs32 is 40 b/w only.
  5390. * This is possible for probe packets on
  5391. * a STA during SCAN
  5392. */
  5393. if ((rspec[k] & RSPEC_RATE_MASK) == 32)
  5394. /* mcs 0 */
  5395. rspec[k] = RSPEC_MIMORATE;
  5396. mimo_txbw = PHY_TXC1_BW_20MHZ;
  5397. }
  5398. /* Set channel width */
  5399. rspec[k] &= ~RSPEC_BW_MASK;
  5400. if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
  5401. rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
  5402. else
  5403. rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  5404. /* Disable short GI, not supported yet */
  5405. rspec[k] &= ~RSPEC_SHORT_GI;
  5406. mimo_preamble_type = BRCMS_MM_PREAMBLE;
  5407. if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
  5408. mimo_preamble_type = BRCMS_GF_PREAMBLE;
  5409. if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
  5410. && (!is_mcs_rate(rspec[k]))) {
  5411. brcms_err(wlc->hw->d11core,
  5412. "wl%d: %s: IEEE80211_TX_"
  5413. "RC_MCS != is_mcs_rate(rspec)\n",
  5414. wlc->pub->unit, __func__);
  5415. }
  5416. if (is_mcs_rate(rspec[k])) {
  5417. preamble_type[k] = mimo_preamble_type;
  5418. /*
  5419. * if SGI is selected, then forced mm
  5420. * for single stream
  5421. */
  5422. if ((rspec[k] & RSPEC_SHORT_GI)
  5423. && is_single_stream(rspec[k] &
  5424. RSPEC_RATE_MASK))
  5425. preamble_type[k] = BRCMS_MM_PREAMBLE;
  5426. }
  5427. /* should be better conditionalized */
  5428. if (!is_mcs_rate(rspec[0])
  5429. && (tx_info->control.rates[0].
  5430. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
  5431. preamble_type[k] = BRCMS_SHORT_PREAMBLE;
  5432. }
  5433. } else {
  5434. for (k = 0; k < hw->max_rates; k++) {
  5435. /* Set ctrlchbw as 20Mhz */
  5436. rspec[k] &= ~RSPEC_BW_MASK;
  5437. rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
  5438. /* for nphy, stf of ofdm frames must follow policies */
  5439. if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
  5440. rspec[k] &= ~RSPEC_STF_MASK;
  5441. rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
  5442. }
  5443. }
  5444. }
  5445. /* Reset these for use with AMPDU's */
  5446. txrate[0]->count = 0;
  5447. txrate[1]->count = 0;
  5448. /* (2) PROTECTION, may change rspec */
  5449. if ((ieee80211_is_data(h->frame_control) ||
  5450. ieee80211_is_mgmt(h->frame_control)) &&
  5451. (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
  5452. use_rts = true;
  5453. /* (3) PLCP: determine PLCP header and MAC duration,
  5454. * fill struct d11txh */
  5455. brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
  5456. brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
  5457. memcpy(&txh->FragPLCPFallback,
  5458. plcp_fallback, sizeof(txh->FragPLCPFallback));
  5459. /* Length field now put in CCK FBR CRC field */
  5460. if (is_cck_rate(rspec[1])) {
  5461. txh->FragPLCPFallback[4] = phylen & 0xff;
  5462. txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
  5463. }
  5464. /* MIMO-RATE: need validation ?? */
  5465. mainrates = is_ofdm_rate(rspec[0]) ?
  5466. D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
  5467. plcp[0];
  5468. /* DUR field for main rate */
  5469. if (!ieee80211_is_pspoll(h->frame_control) &&
  5470. !is_multicast_ether_addr(h->addr1) && !use_rifs) {
  5471. durid =
  5472. brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
  5473. next_frag_len);
  5474. h->duration_id = cpu_to_le16(durid);
  5475. } else if (use_rifs) {
  5476. /* NAV protect to end of next max packet size */
  5477. durid =
  5478. (u16) brcms_c_calc_frame_time(wlc, rspec[0],
  5479. preamble_type[0],
  5480. DOT11_MAX_FRAG_LEN);
  5481. durid += RIFS_11N_TIME;
  5482. h->duration_id = cpu_to_le16(durid);
  5483. }
  5484. /* DUR field for fallback rate */
  5485. if (ieee80211_is_pspoll(h->frame_control))
  5486. txh->FragDurFallback = h->duration_id;
  5487. else if (is_multicast_ether_addr(h->addr1) || use_rifs)
  5488. txh->FragDurFallback = 0;
  5489. else {
  5490. durid = brcms_c_compute_frame_dur(wlc, rspec[1],
  5491. preamble_type[1], next_frag_len);
  5492. txh->FragDurFallback = cpu_to_le16(durid);
  5493. }
  5494. /* (4) MAC-HDR: MacTxControlLow */
  5495. if (frag == 0)
  5496. mcl |= TXC_STARTMSDU;
  5497. if (!is_multicast_ether_addr(h->addr1))
  5498. mcl |= TXC_IMMEDACK;
  5499. if (wlc->band->bandtype == BRCM_BAND_5G)
  5500. mcl |= TXC_FREQBAND_5G;
  5501. if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
  5502. mcl |= TXC_BW_40;
  5503. /* set AMIC bit if using hardware TKIP MIC */
  5504. if (hwtkmic)
  5505. mcl |= TXC_AMIC;
  5506. txh->MacTxControlLow = cpu_to_le16(mcl);
  5507. /* MacTxControlHigh */
  5508. mch = 0;
  5509. /* Set fallback rate preamble type */
  5510. if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
  5511. (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
  5512. if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
  5513. mch |= TXC_PREAMBLE_DATA_FB_SHORT;
  5514. }
  5515. /* MacFrameControl */
  5516. memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
  5517. txh->TxFesTimeNormal = cpu_to_le16(0);
  5518. txh->TxFesTimeFallback = cpu_to_le16(0);
  5519. /* TxFrameRA */
  5520. memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
  5521. /* TxFrameID */
  5522. txh->TxFrameID = cpu_to_le16(frameid);
  5523. /*
  5524. * TxStatus, Note the case of recreating the first frag of a suppressed
  5525. * frame then we may need to reset the retry cnt's via the status reg
  5526. */
  5527. txh->TxStatus = cpu_to_le16(status);
  5528. /*
  5529. * extra fields for ucode AMPDU aggregation, the new fields are added to
  5530. * the END of previous structure so that it's compatible in driver.
  5531. */
  5532. txh->MaxNMpdus = cpu_to_le16(0);
  5533. txh->MaxABytes_MRT = cpu_to_le16(0);
  5534. txh->MaxABytes_FBR = cpu_to_le16(0);
  5535. txh->MinMBytes = cpu_to_le16(0);
  5536. /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
  5537. * furnish struct d11txh */
  5538. /* RTS PLCP header and RTS frame */
  5539. if (use_rts || use_cts) {
  5540. if (use_rts && use_cts)
  5541. use_cts = false;
  5542. for (k = 0; k < 2; k++) {
  5543. rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
  5544. false,
  5545. mimo_ctlchbw);
  5546. }
  5547. if (!is_ofdm_rate(rts_rspec[0]) &&
  5548. !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
  5549. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5550. rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
  5551. mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
  5552. }
  5553. if (!is_ofdm_rate(rts_rspec[1]) &&
  5554. !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
  5555. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5556. rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
  5557. mch |= TXC_PREAMBLE_RTS_FB_SHORT;
  5558. }
  5559. /* RTS/CTS additions to MacTxControlLow */
  5560. if (use_cts) {
  5561. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
  5562. } else {
  5563. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
  5564. txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
  5565. }
  5566. /* RTS PLCP header */
  5567. rts_plcp = txh->RTSPhyHeader;
  5568. if (use_cts)
  5569. rts_phylen = DOT11_CTS_LEN + FCS_LEN;
  5570. else
  5571. rts_phylen = DOT11_RTS_LEN + FCS_LEN;
  5572. brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
  5573. /* fallback rate version of RTS PLCP header */
  5574. brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
  5575. rts_plcp_fallback);
  5576. memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
  5577. sizeof(txh->RTSPLCPFallback));
  5578. /* RTS frame fields... */
  5579. rts = (struct ieee80211_rts *)&txh->rts_frame;
  5580. durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
  5581. rspec[0], rts_preamble_type[0],
  5582. preamble_type[0], phylen, false);
  5583. rts->duration = cpu_to_le16(durid);
  5584. /* fallback rate version of RTS DUR field */
  5585. durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
  5586. rts_rspec[1], rspec[1],
  5587. rts_preamble_type[1],
  5588. preamble_type[1], phylen, false);
  5589. txh->RTSDurFallback = cpu_to_le16(durid);
  5590. if (use_cts) {
  5591. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5592. IEEE80211_STYPE_CTS);
  5593. memcpy(&rts->ra, &h->addr2, ETH_ALEN);
  5594. } else {
  5595. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5596. IEEE80211_STYPE_RTS);
  5597. memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
  5598. }
  5599. /* mainrate
  5600. * low 8 bits: main frag rate/mcs,
  5601. * high 8 bits: rts/cts rate/mcs
  5602. */
  5603. mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
  5604. D11A_PHY_HDR_GRATE(
  5605. (struct ofdm_phy_hdr *) rts_plcp) :
  5606. rts_plcp[0]) << 8;
  5607. } else {
  5608. memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
  5609. memset((char *)&txh->rts_frame, 0,
  5610. sizeof(struct ieee80211_rts));
  5611. memset((char *)txh->RTSPLCPFallback, 0,
  5612. sizeof(txh->RTSPLCPFallback));
  5613. txh->RTSDurFallback = 0;
  5614. }
  5615. #ifdef SUPPORT_40MHZ
  5616. /* add null delimiter count */
  5617. if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
  5618. txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
  5619. brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
  5620. #endif
  5621. /*
  5622. * Now that RTS/RTS FB preamble types are updated, write
  5623. * the final value
  5624. */
  5625. txh->MacTxControlHigh = cpu_to_le16(mch);
  5626. /*
  5627. * MainRates (both the rts and frag plcp rates have
  5628. * been calculated now)
  5629. */
  5630. txh->MainRates = cpu_to_le16(mainrates);
  5631. /* XtraFrameTypes */
  5632. xfts = frametype(rspec[1], wlc->mimoft);
  5633. xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
  5634. xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
  5635. xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
  5636. XFTS_CHANNEL_SHIFT;
  5637. txh->XtraFrameTypes = cpu_to_le16(xfts);
  5638. /* PhyTxControlWord */
  5639. phyctl = frametype(rspec[0], wlc->mimoft);
  5640. if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
  5641. (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
  5642. if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
  5643. phyctl |= PHY_TXC_SHORT_HDR;
  5644. }
  5645. /* phytxant is properly bit shifted */
  5646. phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
  5647. txh->PhyTxControlWord = cpu_to_le16(phyctl);
  5648. /* PhyTxControlWord_1 */
  5649. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  5650. u16 phyctl1 = 0;
  5651. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
  5652. txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
  5653. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
  5654. txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
  5655. if (use_rts || use_cts) {
  5656. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
  5657. txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
  5658. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
  5659. txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
  5660. }
  5661. /*
  5662. * For mcs frames, if mixedmode(overloaded with long preamble)
  5663. * is going to be set, fill in non-zero MModeLen and/or
  5664. * MModeFbrLen it will be unnecessary if they are separated
  5665. */
  5666. if (is_mcs_rate(rspec[0]) &&
  5667. (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
  5668. u16 mmodelen =
  5669. brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
  5670. txh->MModeLen = cpu_to_le16(mmodelen);
  5671. }
  5672. if (is_mcs_rate(rspec[1]) &&
  5673. (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
  5674. u16 mmodefbrlen =
  5675. brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
  5676. txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
  5677. }
  5678. }
  5679. ac = skb_get_queue_mapping(p);
  5680. if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
  5681. uint frag_dur, dur, dur_fallback;
  5682. /* WME: Update TXOP threshold */
  5683. if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
  5684. frag_dur =
  5685. brcms_c_calc_frame_time(wlc, rspec[0],
  5686. preamble_type[0], phylen);
  5687. if (rts) {
  5688. /* 1 RTS or CTS-to-self frame */
  5689. dur =
  5690. brcms_c_calc_cts_time(wlc, rts_rspec[0],
  5691. rts_preamble_type[0]);
  5692. dur_fallback =
  5693. brcms_c_calc_cts_time(wlc, rts_rspec[1],
  5694. rts_preamble_type[1]);
  5695. /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
  5696. dur += le16_to_cpu(rts->duration);
  5697. dur_fallback +=
  5698. le16_to_cpu(txh->RTSDurFallback);
  5699. } else if (use_rifs) {
  5700. dur = frag_dur;
  5701. dur_fallback = 0;
  5702. } else {
  5703. /* frame + SIFS + ACK */
  5704. dur = frag_dur;
  5705. dur +=
  5706. brcms_c_compute_frame_dur(wlc, rspec[0],
  5707. preamble_type[0], 0);
  5708. dur_fallback =
  5709. brcms_c_calc_frame_time(wlc, rspec[1],
  5710. preamble_type[1],
  5711. phylen);
  5712. dur_fallback +=
  5713. brcms_c_compute_frame_dur(wlc, rspec[1],
  5714. preamble_type[1], 0);
  5715. }
  5716. /* NEED to set TxFesTimeNormal (hard) */
  5717. txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
  5718. /*
  5719. * NEED to set fallback rate version of
  5720. * TxFesTimeNormal (hard)
  5721. */
  5722. txh->TxFesTimeFallback =
  5723. cpu_to_le16((u16) dur_fallback);
  5724. /*
  5725. * update txop byte threshold (txop minus intraframe
  5726. * overhead)
  5727. */
  5728. if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
  5729. uint newfragthresh;
  5730. newfragthresh =
  5731. brcms_c_calc_frame_len(wlc,
  5732. rspec[0], preamble_type[0],
  5733. (wlc->edcf_txop[ac] -
  5734. (dur - frag_dur)));
  5735. /* range bound the fragthreshold */
  5736. if (newfragthresh < DOT11_MIN_FRAG_LEN)
  5737. newfragthresh =
  5738. DOT11_MIN_FRAG_LEN;
  5739. else if (newfragthresh >
  5740. wlc->usr_fragthresh)
  5741. newfragthresh =
  5742. wlc->usr_fragthresh;
  5743. /* update the fragthresh and do txc update */
  5744. if (wlc->fragthresh[queue] !=
  5745. (u16) newfragthresh)
  5746. wlc->fragthresh[queue] =
  5747. (u16) newfragthresh;
  5748. } else {
  5749. brcms_err(wlc->hw->d11core,
  5750. "wl%d: %s txop invalid "
  5751. "for rate %d\n",
  5752. wlc->pub->unit, fifo_names[queue],
  5753. rspec2rate(rspec[0]));
  5754. }
  5755. if (dur > wlc->edcf_txop[ac])
  5756. brcms_err(wlc->hw->d11core,
  5757. "wl%d: %s: %s txop "
  5758. "exceeded phylen %d/%d dur %d/%d\n",
  5759. wlc->pub->unit, __func__,
  5760. fifo_names[queue],
  5761. phylen, wlc->fragthresh[queue],
  5762. dur, wlc->edcf_txop[ac]);
  5763. }
  5764. }
  5765. return 0;
  5766. }
  5767. static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
  5768. {
  5769. struct dma_pub *dma;
  5770. int fifo, ret = -ENOSPC;
  5771. struct d11txh *txh;
  5772. u16 frameid = INVALIDFID;
  5773. fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
  5774. dma = wlc->hw->di[fifo];
  5775. txh = (struct d11txh *)(skb->data);
  5776. if (dma->txavail == 0) {
  5777. /*
  5778. * We sometimes get a frame from mac80211 after stopping
  5779. * the queues. This only ever seems to be a single frame
  5780. * and is seems likely to be a race. TX_HEADROOM should
  5781. * ensure that we have enough space to handle these stray
  5782. * packets, so warn if there isn't. If we're out of space
  5783. * in the tx ring and the tx queue isn't stopped then
  5784. * we've really got a bug; warn loudly if that happens.
  5785. */
  5786. brcms_warn(wlc->hw->d11core,
  5787. "Received frame for tx with no space in DMA ring\n");
  5788. WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
  5789. skb_get_queue_mapping(skb)));
  5790. return -ENOSPC;
  5791. }
  5792. /* When a BC/MC frame is being committed to the BCMC fifo
  5793. * via DMA (NOT PIO), update ucode or BSS info as appropriate.
  5794. */
  5795. if (fifo == TX_BCMC_FIFO)
  5796. frameid = le16_to_cpu(txh->TxFrameID);
  5797. /* Commit BCMC sequence number in the SHM frame ID location */
  5798. if (frameid != INVALIDFID) {
  5799. /*
  5800. * To inform the ucode of the last mcast frame posted
  5801. * so that it can clear moredata bit
  5802. */
  5803. brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
  5804. }
  5805. ret = brcms_c_txfifo(wlc, fifo, skb);
  5806. /*
  5807. * The only reason for brcms_c_txfifo to fail is because
  5808. * there weren't any DMA descriptors, but we've already
  5809. * checked for that. So if it does fail yell loudly.
  5810. */
  5811. WARN_ON_ONCE(ret);
  5812. return ret;
  5813. }
  5814. bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
  5815. struct ieee80211_hw *hw)
  5816. {
  5817. uint fifo;
  5818. struct scb *scb = &wlc->pri_scb;
  5819. fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
  5820. brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
  5821. if (!brcms_c_tx(wlc, sdu))
  5822. return true;
  5823. /* packet discarded */
  5824. dev_kfree_skb_any(sdu);
  5825. return false;
  5826. }
  5827. int
  5828. brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
  5829. {
  5830. struct dma_pub *dma = wlc->hw->di[fifo];
  5831. int ret;
  5832. u16 queue;
  5833. ret = dma_txfast(wlc, dma, p);
  5834. if (ret < 0)
  5835. wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
  5836. /*
  5837. * Stop queue if DMA ring is full. Reserve some free descriptors,
  5838. * as we sometimes receive a frame from mac80211 after the queues
  5839. * are stopped.
  5840. */
  5841. queue = skb_get_queue_mapping(p);
  5842. if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
  5843. !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
  5844. ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
  5845. return ret;
  5846. }
  5847. u32
  5848. brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
  5849. bool use_rspec, u16 mimo_ctlchbw)
  5850. {
  5851. u32 rts_rspec = 0;
  5852. if (use_rspec)
  5853. /* use frame rate as rts rate */
  5854. rts_rspec = rspec;
  5855. else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
  5856. /* Use 11Mbps as the g protection RTS target rate and fallback.
  5857. * Use the brcms_basic_rate() lookup to find the best basic rate
  5858. * under the target in case 11 Mbps is not Basic.
  5859. * 6 and 9 Mbps are not usually selected by rate selection, but
  5860. * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
  5861. * is more robust.
  5862. */
  5863. rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
  5864. else
  5865. /* calculate RTS rate and fallback rate based on the frame rate
  5866. * RTS must be sent at a basic rate since it is a
  5867. * control frame, sec 9.6 of 802.11 spec
  5868. */
  5869. rts_rspec = brcms_basic_rate(wlc, rspec);
  5870. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  5871. /* set rts txbw to correct side band */
  5872. rts_rspec &= ~RSPEC_BW_MASK;
  5873. /*
  5874. * if rspec/rspec_fallback is 40MHz, then send RTS on both
  5875. * 20MHz channel (DUP), otherwise send RTS on control channel
  5876. */
  5877. if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
  5878. rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
  5879. else
  5880. rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  5881. /* pick siso/cdd as default for ofdm */
  5882. if (is_ofdm_rate(rts_rspec)) {
  5883. rts_rspec &= ~RSPEC_STF_MASK;
  5884. rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
  5885. }
  5886. }
  5887. return rts_rspec;
  5888. }
  5889. /* Update beacon listen interval in shared memory */
  5890. static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
  5891. {
  5892. /* wake up every DTIM is the default */
  5893. if (wlc->bcn_li_dtim == 1)
  5894. brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
  5895. else
  5896. brcms_b_write_shm(wlc->hw, M_BCN_LI,
  5897. (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
  5898. }
  5899. static void
  5900. brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
  5901. u32 *tsf_h_ptr)
  5902. {
  5903. struct bcma_device *core = wlc_hw->d11core;
  5904. /* read the tsf timer low, then high to get an atomic read */
  5905. *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
  5906. *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
  5907. }
  5908. /*
  5909. * recover 64bit TSF value from the 16bit TSF value in the rx header
  5910. * given the assumption that the TSF passed in header is within 65ms
  5911. * of the current tsf.
  5912. *
  5913. * 6 5 4 4 3 2 1
  5914. * 3.......6.......8.......0.......2.......4.......6.......8......0
  5915. * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
  5916. *
  5917. * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
  5918. * tsf_l is filled in by brcms_b_recv, which is done earlier in the
  5919. * receive call sequence after rx interrupt. Only the higher 16 bits
  5920. * are used. Finally, the tsf_h is read from the tsf register.
  5921. */
  5922. static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
  5923. struct d11rxhdr *rxh)
  5924. {
  5925. u32 tsf_h, tsf_l;
  5926. u16 rx_tsf_0_15, rx_tsf_16_31;
  5927. brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
  5928. rx_tsf_16_31 = (u16)(tsf_l >> 16);
  5929. rx_tsf_0_15 = rxh->RxTSFTime;
  5930. /*
  5931. * a greater tsf time indicates the low 16 bits of
  5932. * tsf_l wrapped, so decrement the high 16 bits.
  5933. */
  5934. if ((u16)tsf_l < rx_tsf_0_15) {
  5935. rx_tsf_16_31 -= 1;
  5936. if (rx_tsf_16_31 == 0xffff)
  5937. tsf_h -= 1;
  5938. }
  5939. return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
  5940. }
  5941. static void
  5942. prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  5943. struct sk_buff *p,
  5944. struct ieee80211_rx_status *rx_status)
  5945. {
  5946. int preamble;
  5947. int channel;
  5948. u32 rspec;
  5949. unsigned char *plcp;
  5950. /* fill in TSF and flag its presence */
  5951. rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
  5952. rx_status->flag |= RX_FLAG_MACTIME_START;
  5953. channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
  5954. rx_status->band =
  5955. channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
  5956. rx_status->freq =
  5957. ieee80211_channel_to_frequency(channel, rx_status->band);
  5958. rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
  5959. /* noise */
  5960. /* qual */
  5961. rx_status->antenna =
  5962. (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
  5963. plcp = p->data;
  5964. rspec = brcms_c_compute_rspec(rxh, plcp);
  5965. if (is_mcs_rate(rspec)) {
  5966. rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
  5967. rx_status->flag |= RX_FLAG_HT;
  5968. if (rspec_is40mhz(rspec))
  5969. rx_status->flag |= RX_FLAG_40MHZ;
  5970. } else {
  5971. switch (rspec2rate(rspec)) {
  5972. case BRCM_RATE_1M:
  5973. rx_status->rate_idx = 0;
  5974. break;
  5975. case BRCM_RATE_2M:
  5976. rx_status->rate_idx = 1;
  5977. break;
  5978. case BRCM_RATE_5M5:
  5979. rx_status->rate_idx = 2;
  5980. break;
  5981. case BRCM_RATE_11M:
  5982. rx_status->rate_idx = 3;
  5983. break;
  5984. case BRCM_RATE_6M:
  5985. rx_status->rate_idx = 4;
  5986. break;
  5987. case BRCM_RATE_9M:
  5988. rx_status->rate_idx = 5;
  5989. break;
  5990. case BRCM_RATE_12M:
  5991. rx_status->rate_idx = 6;
  5992. break;
  5993. case BRCM_RATE_18M:
  5994. rx_status->rate_idx = 7;
  5995. break;
  5996. case BRCM_RATE_24M:
  5997. rx_status->rate_idx = 8;
  5998. break;
  5999. case BRCM_RATE_36M:
  6000. rx_status->rate_idx = 9;
  6001. break;
  6002. case BRCM_RATE_48M:
  6003. rx_status->rate_idx = 10;
  6004. break;
  6005. case BRCM_RATE_54M:
  6006. rx_status->rate_idx = 11;
  6007. break;
  6008. default:
  6009. brcms_err(wlc->hw->d11core,
  6010. "%s: Unknown rate\n", __func__);
  6011. }
  6012. /*
  6013. * For 5GHz, we should decrease the index as it is
  6014. * a subset of the 2.4G rates. See bitrates field
  6015. * of brcms_band_5GHz_nphy (in mac80211_if.c).
  6016. */
  6017. if (rx_status->band == IEEE80211_BAND_5GHZ)
  6018. rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
  6019. /* Determine short preamble and rate_idx */
  6020. preamble = 0;
  6021. if (is_cck_rate(rspec)) {
  6022. if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
  6023. rx_status->flag |= RX_FLAG_SHORTPRE;
  6024. } else if (is_ofdm_rate(rspec)) {
  6025. rx_status->flag |= RX_FLAG_SHORTPRE;
  6026. } else {
  6027. brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
  6028. __func__);
  6029. }
  6030. }
  6031. if (plcp3_issgi(plcp[3]))
  6032. rx_status->flag |= RX_FLAG_SHORT_GI;
  6033. if (rxh->RxStatus1 & RXS_DECERR) {
  6034. rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
  6035. brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
  6036. __func__);
  6037. }
  6038. if (rxh->RxStatus1 & RXS_FCSERR) {
  6039. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  6040. brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n",
  6041. __func__);
  6042. }
  6043. }
  6044. static void
  6045. brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  6046. struct sk_buff *p)
  6047. {
  6048. int len_mpdu;
  6049. struct ieee80211_rx_status rx_status;
  6050. struct ieee80211_hdr *hdr;
  6051. memset(&rx_status, 0, sizeof(rx_status));
  6052. prep_mac80211_status(wlc, rxh, p, &rx_status);
  6053. /* mac header+body length, exclude CRC and plcp header */
  6054. len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
  6055. skb_pull(p, D11_PHY_HDR_LEN);
  6056. __skb_trim(p, len_mpdu);
  6057. /* unmute transmit */
  6058. if (wlc->hw->suspended_fifos) {
  6059. hdr = (struct ieee80211_hdr *)p->data;
  6060. if (ieee80211_is_beacon(hdr->frame_control))
  6061. brcms_b_mute(wlc->hw, false);
  6062. }
  6063. memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
  6064. ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
  6065. }
  6066. /* calculate frame duration for Mixed-mode L-SIG spoofing, return
  6067. * number of bytes goes in the length field
  6068. *
  6069. * Formula given by HT PHY Spec v 1.13
  6070. * len = 3(nsyms + nstream + 3) - 3
  6071. */
  6072. u16
  6073. brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
  6074. uint mac_len)
  6075. {
  6076. uint nsyms, len = 0, kNdps;
  6077. if (is_mcs_rate(ratespec)) {
  6078. uint mcs = ratespec & RSPEC_RATE_MASK;
  6079. int tot_streams = (mcs_2_txstreams(mcs) + 1) +
  6080. rspec_stc(ratespec);
  6081. /*
  6082. * the payload duration calculation matches that
  6083. * of regular ofdm
  6084. */
  6085. /* 1000Ndbps = kbps * 4 */
  6086. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  6087. rspec_issgi(ratespec)) * 4;
  6088. if (rspec_stc(ratespec) == 0)
  6089. nsyms =
  6090. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6091. APHY_TAIL_NBITS) * 1000, kNdps);
  6092. else
  6093. /* STBC needs to have even number of symbols */
  6094. nsyms =
  6095. 2 *
  6096. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6097. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  6098. /* (+3) account for HT-SIG(2) and HT-STF(1) */
  6099. nsyms += (tot_streams + 3);
  6100. /*
  6101. * 3 bytes/symbol @ legacy 6Mbps rate
  6102. * (-3) excluding service bits and tail bits
  6103. */
  6104. len = (3 * nsyms) - 3;
  6105. }
  6106. return (u16) len;
  6107. }
  6108. static void
  6109. brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
  6110. {
  6111. const struct brcms_c_rateset *rs_dflt;
  6112. struct brcms_c_rateset rs;
  6113. u8 rate;
  6114. u16 entry_ptr;
  6115. u8 plcp[D11_PHY_HDR_LEN];
  6116. u16 dur, sifs;
  6117. uint i;
  6118. sifs = get_sifs(wlc->band);
  6119. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  6120. brcms_c_rateset_copy(rs_dflt, &rs);
  6121. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  6122. /*
  6123. * walk the phy rate table and update MAC core SHM
  6124. * basic rate table entries
  6125. */
  6126. for (i = 0; i < rs.count; i++) {
  6127. rate = rs.rates[i] & BRCMS_RATE_MASK;
  6128. entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
  6129. /* Calculate the Probe Response PLCP for the given rate */
  6130. brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
  6131. /*
  6132. * Calculate the duration of the Probe Response
  6133. * frame plus SIFS for the MAC
  6134. */
  6135. dur = (u16) brcms_c_calc_frame_time(wlc, rate,
  6136. BRCMS_LONG_PREAMBLE, frame_len);
  6137. dur += sifs;
  6138. /* Update the SHM Rate Table entry Probe Response values */
  6139. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
  6140. (u16) (plcp[0] + (plcp[1] << 8)));
  6141. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
  6142. (u16) (plcp[2] + (plcp[3] << 8)));
  6143. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
  6144. }
  6145. }
  6146. /* Max buffering needed for beacon template/prb resp template is 142 bytes.
  6147. *
  6148. * PLCP header is 6 bytes.
  6149. * 802.11 A3 header is 24 bytes.
  6150. * Max beacon frame body template length is 112 bytes.
  6151. * Max probe resp frame body template length is 110 bytes.
  6152. *
  6153. * *len on input contains the max length of the packet available.
  6154. *
  6155. * The *len value is set to the number of bytes in buf used, and starts
  6156. * with the PLCP and included up to, but not including, the 4 byte FCS.
  6157. */
  6158. static void
  6159. brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
  6160. u32 bcn_rspec,
  6161. struct brcms_bss_cfg *cfg, u16 *buf, int *len)
  6162. {
  6163. static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
  6164. struct cck_phy_hdr *plcp;
  6165. struct ieee80211_mgmt *h;
  6166. int hdr_len, body_len;
  6167. hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
  6168. /* calc buffer size provided for frame body */
  6169. body_len = *len - hdr_len;
  6170. /* return actual size */
  6171. *len = hdr_len + body_len;
  6172. /* format PHY and MAC headers */
  6173. memset((char *)buf, 0, hdr_len);
  6174. plcp = (struct cck_phy_hdr *) buf;
  6175. /*
  6176. * PLCP for Probe Response frames are filled in from
  6177. * core's rate table
  6178. */
  6179. if (type == IEEE80211_STYPE_BEACON)
  6180. /* fill in PLCP */
  6181. brcms_c_compute_plcp(wlc, bcn_rspec,
  6182. (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
  6183. (u8 *) plcp);
  6184. /* "Regular" and 16 MBSS but not for 4 MBSS */
  6185. /* Update the phytxctl for the beacon based on the rspec */
  6186. brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
  6187. h = (struct ieee80211_mgmt *)&plcp[1];
  6188. /* fill in 802.11 header */
  6189. h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
  6190. /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
  6191. /* A1 filled in by MAC for prb resp, broadcast for bcn */
  6192. if (type == IEEE80211_STYPE_BEACON)
  6193. memcpy(&h->da, &ether_bcast, ETH_ALEN);
  6194. memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
  6195. memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
  6196. /* SEQ filled in by MAC */
  6197. }
  6198. int brcms_c_get_header_len(void)
  6199. {
  6200. return TXOFF;
  6201. }
  6202. /*
  6203. * Update all beacons for the system.
  6204. */
  6205. void brcms_c_update_beacon(struct brcms_c_info *wlc)
  6206. {
  6207. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6208. if (bsscfg->up && !bsscfg->BSS)
  6209. /* Clear the soft intmask */
  6210. wlc->defmacintmask &= ~MI_BCNTPL;
  6211. }
  6212. /* Write ssid into shared memory */
  6213. static void
  6214. brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
  6215. {
  6216. u8 *ssidptr = cfg->SSID;
  6217. u16 base = M_SSID;
  6218. u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
  6219. /* padding the ssid with zero and copy it into shm */
  6220. memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
  6221. memcpy(ssidbuf, ssidptr, cfg->SSID_len);
  6222. brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
  6223. brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
  6224. }
  6225. static void
  6226. brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
  6227. struct brcms_bss_cfg *cfg,
  6228. bool suspend)
  6229. {
  6230. u16 prb_resp[BCN_TMPL_LEN / 2];
  6231. int len = BCN_TMPL_LEN;
  6232. /*
  6233. * write the probe response to hardware, or save in
  6234. * the config structure
  6235. */
  6236. /* create the probe response template */
  6237. brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
  6238. cfg, prb_resp, &len);
  6239. if (suspend)
  6240. brcms_c_suspend_mac_and_wait(wlc);
  6241. /* write the probe response into the template region */
  6242. brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
  6243. (len + 3) & ~3, prb_resp);
  6244. /* write the length of the probe response frame (+PLCP/-FCS) */
  6245. brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
  6246. /* write the SSID and SSID length */
  6247. brcms_c_shm_ssid_upd(wlc, cfg);
  6248. /*
  6249. * Write PLCP headers and durations for probe response frames
  6250. * at all rates. Use the actual frame length covered by the
  6251. * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
  6252. * by subtracting the PLCP len and adding the FCS.
  6253. */
  6254. len += (-D11_PHY_HDR_LEN + FCS_LEN);
  6255. brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
  6256. if (suspend)
  6257. brcms_c_enable_mac(wlc);
  6258. }
  6259. void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
  6260. {
  6261. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6262. /* update AP or IBSS probe responses */
  6263. if (bsscfg->up && !bsscfg->BSS)
  6264. brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
  6265. }
  6266. int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
  6267. uint *blocks)
  6268. {
  6269. if (fifo >= NFIFO)
  6270. return -EINVAL;
  6271. *blocks = wlc_hw->xmtfifo_sz[fifo];
  6272. return 0;
  6273. }
  6274. void
  6275. brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
  6276. const u8 *addr)
  6277. {
  6278. brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
  6279. if (match_reg_offset == RCM_BSSID_OFFSET)
  6280. memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
  6281. }
  6282. /*
  6283. * Flag 'scan in progress' to withhold dynamic phy calibration
  6284. */
  6285. void brcms_c_scan_start(struct brcms_c_info *wlc)
  6286. {
  6287. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
  6288. }
  6289. void brcms_c_scan_stop(struct brcms_c_info *wlc)
  6290. {
  6291. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
  6292. }
  6293. void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
  6294. {
  6295. wlc->pub->associated = state;
  6296. wlc->bsscfg->associated = state;
  6297. }
  6298. /*
  6299. * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
  6300. * AMPDU traffic, packets pending in hardware have to be invalidated so that
  6301. * when later on hardware releases them, they can be handled appropriately.
  6302. */
  6303. void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
  6304. struct ieee80211_sta *sta,
  6305. void (*dma_callback_fn))
  6306. {
  6307. struct dma_pub *dmah;
  6308. int i;
  6309. for (i = 0; i < NFIFO; i++) {
  6310. dmah = hw->di[i];
  6311. if (dmah != NULL)
  6312. dma_walk_packets(dmah, dma_callback_fn, sta);
  6313. }
  6314. }
  6315. int brcms_c_get_curband(struct brcms_c_info *wlc)
  6316. {
  6317. return wlc->band->bandunit;
  6318. }
  6319. void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
  6320. {
  6321. int timeout = 20;
  6322. int i;
  6323. /* Kick DMA to send any pending AMPDU */
  6324. for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
  6325. if (wlc->hw->di[i])
  6326. dma_txflush(wlc->hw->di[i]);
  6327. /* wait for queue and DMA fifos to run dry */
  6328. while (brcms_txpktpendtot(wlc) > 0) {
  6329. brcms_msleep(wlc->wl, 1);
  6330. if (--timeout == 0)
  6331. break;
  6332. }
  6333. WARN_ON_ONCE(timeout == 0);
  6334. }
  6335. void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
  6336. {
  6337. wlc->bcn_li_bcn = interval;
  6338. if (wlc->pub->up)
  6339. brcms_c_bcn_li_upd(wlc);
  6340. }
  6341. int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
  6342. {
  6343. uint qdbm;
  6344. /* Remove override bit and clip to max qdbm value */
  6345. qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
  6346. return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
  6347. }
  6348. int brcms_c_get_tx_power(struct brcms_c_info *wlc)
  6349. {
  6350. uint qdbm;
  6351. bool override;
  6352. wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
  6353. /* Return qdbm units */
  6354. return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
  6355. }
  6356. /* Process received frames */
  6357. /*
  6358. * Return true if more frames need to be processed. false otherwise.
  6359. * Param 'bound' indicates max. # frames to process before break out.
  6360. */
  6361. static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
  6362. {
  6363. struct d11rxhdr *rxh;
  6364. struct ieee80211_hdr *h;
  6365. uint len;
  6366. bool is_amsdu;
  6367. /* frame starts with rxhdr */
  6368. rxh = (struct d11rxhdr *) (p->data);
  6369. /* strip off rxhdr */
  6370. skb_pull(p, BRCMS_HWRXOFF);
  6371. /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
  6372. if (rxh->RxStatus1 & RXS_PBPRES) {
  6373. if (p->len < 2) {
  6374. brcms_err(wlc->hw->d11core,
  6375. "wl%d: recv: rcvd runt of len %d\n",
  6376. wlc->pub->unit, p->len);
  6377. goto toss;
  6378. }
  6379. skb_pull(p, 2);
  6380. }
  6381. h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
  6382. len = p->len;
  6383. if (rxh->RxStatus1 & RXS_FCSERR) {
  6384. if (!(wlc->filter_flags & FIF_FCSFAIL))
  6385. goto toss;
  6386. }
  6387. /* check received pkt has at least frame control field */
  6388. if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
  6389. goto toss;
  6390. /* not supporting A-MSDU */
  6391. is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
  6392. if (is_amsdu)
  6393. goto toss;
  6394. brcms_c_recvctl(wlc, rxh, p);
  6395. return;
  6396. toss:
  6397. brcmu_pkt_buf_free_skb(p);
  6398. }
  6399. /* Process received frames */
  6400. /*
  6401. * Return true if more frames need to be processed. false otherwise.
  6402. * Param 'bound' indicates max. # frames to process before break out.
  6403. */
  6404. static bool
  6405. brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
  6406. {
  6407. struct sk_buff *p;
  6408. struct sk_buff *next = NULL;
  6409. struct sk_buff_head recv_frames;
  6410. uint n = 0;
  6411. uint bound_limit = bound ? RXBND : -1;
  6412. bool morepending = false;
  6413. skb_queue_head_init(&recv_frames);
  6414. /* gather received frames */
  6415. do {
  6416. /* !give others some time to run! */
  6417. if (n >= bound_limit)
  6418. break;
  6419. morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
  6420. n++;
  6421. } while (morepending);
  6422. /* post more rbufs */
  6423. dma_rxfill(wlc_hw->di[fifo]);
  6424. /* process each frame */
  6425. skb_queue_walk_safe(&recv_frames, p, next) {
  6426. struct d11rxhdr_le *rxh_le;
  6427. struct d11rxhdr *rxh;
  6428. skb_unlink(p, &recv_frames);
  6429. rxh_le = (struct d11rxhdr_le *)p->data;
  6430. rxh = (struct d11rxhdr *)p->data;
  6431. /* fixup rx header endianness */
  6432. rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
  6433. rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
  6434. rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
  6435. rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
  6436. rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
  6437. rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
  6438. rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
  6439. rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
  6440. rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
  6441. rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
  6442. rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
  6443. brcms_c_recv(wlc_hw->wlc, p);
  6444. }
  6445. return morepending;
  6446. }
  6447. /* second-level interrupt processing
  6448. * Return true if another dpc needs to be re-scheduled. false otherwise.
  6449. * Param 'bounded' indicates if applicable loops should be bounded.
  6450. */
  6451. bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
  6452. {
  6453. u32 macintstatus;
  6454. struct brcms_hardware *wlc_hw = wlc->hw;
  6455. struct bcma_device *core = wlc_hw->d11core;
  6456. if (brcms_deviceremoved(wlc)) {
  6457. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  6458. __func__);
  6459. brcms_down(wlc->wl);
  6460. return false;
  6461. }
  6462. /* grab and clear the saved software intstatus bits */
  6463. macintstatus = wlc->macintstatus;
  6464. wlc->macintstatus = 0;
  6465. brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
  6466. wlc_hw->unit, macintstatus);
  6467. WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
  6468. /* tx status */
  6469. if (macintstatus & MI_TFS) {
  6470. bool fatal;
  6471. if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
  6472. wlc->macintstatus |= MI_TFS;
  6473. if (fatal) {
  6474. brcms_err(core, "MI_TFS: fatal\n");
  6475. goto fatal;
  6476. }
  6477. }
  6478. if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
  6479. brcms_c_tbtt(wlc);
  6480. /* ATIM window end */
  6481. if (macintstatus & MI_ATIMWINEND) {
  6482. brcms_dbg_info(core, "end of ATIM window\n");
  6483. bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
  6484. wlc->qvalid = 0;
  6485. }
  6486. /*
  6487. * received data or control frame, MI_DMAINT is
  6488. * indication of RX_FIFO interrupt
  6489. */
  6490. if (macintstatus & MI_DMAINT)
  6491. if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
  6492. wlc->macintstatus |= MI_DMAINT;
  6493. /* noise sample collected */
  6494. if (macintstatus & MI_BG_NOISE)
  6495. wlc_phy_noise_sample_intr(wlc_hw->band->pi);
  6496. if (macintstatus & MI_GP0) {
  6497. brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
  6498. "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
  6499. printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
  6500. __func__, ai_get_chip_id(wlc_hw->sih),
  6501. ai_get_chiprev(wlc_hw->sih));
  6502. brcms_fatal_error(wlc_hw->wlc->wl);
  6503. }
  6504. /* gptimer timeout */
  6505. if (macintstatus & MI_TO)
  6506. bcma_write32(core, D11REGOFFS(gptimer), 0);
  6507. if (macintstatus & MI_RFDISABLE) {
  6508. brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
  6509. " RF Disable Input\n", wlc_hw->unit);
  6510. brcms_rfkill_set_hw_state(wlc->wl);
  6511. }
  6512. /* it isn't done and needs to be resched if macintstatus is non-zero */
  6513. return wlc->macintstatus != 0;
  6514. fatal:
  6515. brcms_fatal_error(wlc_hw->wlc->wl);
  6516. return wlc->macintstatus != 0;
  6517. }
  6518. void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
  6519. {
  6520. struct bcma_device *core = wlc->hw->d11core;
  6521. struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
  6522. u16 chanspec;
  6523. brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
  6524. chanspec = ch20mhz_chspec(ch->hw_value);
  6525. brcms_b_init(wlc->hw, chanspec);
  6526. /* update beacon listen interval */
  6527. brcms_c_bcn_li_upd(wlc);
  6528. /* write ethernet address to core */
  6529. brcms_c_set_mac(wlc->bsscfg);
  6530. brcms_c_set_bssid(wlc->bsscfg);
  6531. /* Update tsf_cfprep if associated and up */
  6532. if (wlc->pub->associated && wlc->bsscfg->up) {
  6533. u32 bi;
  6534. /* get beacon period and convert to uS */
  6535. bi = wlc->bsscfg->current_bss->beacon_period << 10;
  6536. /*
  6537. * update since init path would reset
  6538. * to default value
  6539. */
  6540. bcma_write32(core, D11REGOFFS(tsf_cfprep),
  6541. bi << CFPREP_CBI_SHIFT);
  6542. /* Update maccontrol PM related bits */
  6543. brcms_c_set_ps_ctrl(wlc);
  6544. }
  6545. brcms_c_bandinit_ordered(wlc, chanspec);
  6546. /* init probe response timeout */
  6547. brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
  6548. /* init max burst txop (framebursting) */
  6549. brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
  6550. (wlc->
  6551. _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
  6552. /* initialize maximum allowed duty cycle */
  6553. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
  6554. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
  6555. /*
  6556. * Update some shared memory locations related to
  6557. * max AMPDU size allowed to received
  6558. */
  6559. brcms_c_ampdu_shm_upd(wlc->ampdu);
  6560. /* band-specific inits */
  6561. brcms_c_bsinit(wlc);
  6562. /* Enable EDCF mode (while the MAC is suspended) */
  6563. bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
  6564. brcms_c_edcf_setparams(wlc, false);
  6565. /* read the ucode version if we have not yet done so */
  6566. if (wlc->ucode_rev == 0) {
  6567. wlc->ucode_rev =
  6568. brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
  6569. wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
  6570. }
  6571. /* ..now really unleash hell (allow the MAC out of suspend) */
  6572. brcms_c_enable_mac(wlc);
  6573. /* suspend the tx fifos and mute the phy for preism cac time */
  6574. if (mute_tx)
  6575. brcms_b_mute(wlc->hw, true);
  6576. /* enable the RF Disable Delay timer */
  6577. bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
  6578. /*
  6579. * Initialize WME parameters; if they haven't been set by some other
  6580. * mechanism (IOVar, etc) then read them from the hardware.
  6581. */
  6582. if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
  6583. /* Uninitialized; read from HW */
  6584. int ac;
  6585. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  6586. wlc->wme_retries[ac] =
  6587. brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
  6588. }
  6589. }
  6590. /*
  6591. * The common driver entry routine. Error codes should be unique
  6592. */
  6593. struct brcms_c_info *
  6594. brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
  6595. bool piomode, uint *perr)
  6596. {
  6597. struct brcms_c_info *wlc;
  6598. uint err = 0;
  6599. uint i, j;
  6600. struct brcms_pub *pub;
  6601. /* allocate struct brcms_c_info state and its substructures */
  6602. wlc = brcms_c_attach_malloc(unit, &err, 0);
  6603. if (wlc == NULL)
  6604. goto fail;
  6605. wlc->wiphy = wl->wiphy;
  6606. pub = wlc->pub;
  6607. #if defined(DEBUG)
  6608. wlc_info_dbg = wlc;
  6609. #endif
  6610. wlc->band = wlc->bandstate[0];
  6611. wlc->core = wlc->corestate;
  6612. wlc->wl = wl;
  6613. pub->unit = unit;
  6614. pub->_piomode = piomode;
  6615. wlc->bandinit_pending = false;
  6616. /* populate struct brcms_c_info with default values */
  6617. brcms_c_info_init(wlc, unit);
  6618. /* update sta/ap related parameters */
  6619. brcms_c_ap_upd(wlc);
  6620. /*
  6621. * low level attach steps(all hw accesses go
  6622. * inside, no more in rest of the attach)
  6623. */
  6624. err = brcms_b_attach(wlc, core, unit, piomode);
  6625. if (err)
  6626. goto fail;
  6627. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
  6628. pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
  6629. /* disable allowed duty cycle */
  6630. wlc->tx_duty_cycle_ofdm = 0;
  6631. wlc->tx_duty_cycle_cck = 0;
  6632. brcms_c_stf_phy_chain_calc(wlc);
  6633. /* txchain 1: txant 0, txchain 2: txant 1 */
  6634. if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
  6635. wlc->stf->txant = wlc->stf->hw_txchain - 1;
  6636. /* push to BMAC driver */
  6637. wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
  6638. wlc->stf->hw_rxchain);
  6639. /* pull up some info resulting from the low attach */
  6640. for (i = 0; i < NFIFO; i++)
  6641. wlc->core->txavail[i] = wlc->hw->txavail[i];
  6642. memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  6643. memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  6644. for (j = 0; j < wlc->pub->_nbands; j++) {
  6645. wlc->band = wlc->bandstate[j];
  6646. if (!brcms_c_attach_stf_ant_init(wlc)) {
  6647. err = 24;
  6648. goto fail;
  6649. }
  6650. /* default contention windows size limits */
  6651. wlc->band->CWmin = APHY_CWMIN;
  6652. wlc->band->CWmax = PHY_CWMAX;
  6653. /* init gmode value */
  6654. if (wlc->band->bandtype == BRCM_BAND_2G) {
  6655. wlc->band->gmode = GMODE_AUTO;
  6656. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
  6657. wlc->band->gmode);
  6658. }
  6659. /* init _n_enab supported mode */
  6660. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  6661. pub->_n_enab = SUPPORT_11N;
  6662. brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
  6663. ((pub->_n_enab ==
  6664. SUPPORT_11N) ? WL_11N_2x2 :
  6665. WL_11N_3x3));
  6666. }
  6667. /* init per-band default rateset, depend on band->gmode */
  6668. brcms_default_rateset(wlc, &wlc->band->defrateset);
  6669. /* fill in hw_rateset */
  6670. brcms_c_rateset_filter(&wlc->band->defrateset,
  6671. &wlc->band->hw_rateset, false,
  6672. BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  6673. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  6674. }
  6675. /*
  6676. * update antenna config due to
  6677. * wlc->stf->txant/txchain/ant_rx_ovr change
  6678. */
  6679. brcms_c_stf_phy_txant_upd(wlc);
  6680. /* attach each modules */
  6681. err = brcms_c_attach_module(wlc);
  6682. if (err != 0)
  6683. goto fail;
  6684. if (!brcms_c_timers_init(wlc, unit)) {
  6685. wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
  6686. __func__);
  6687. err = 32;
  6688. goto fail;
  6689. }
  6690. /* depend on rateset, gmode */
  6691. wlc->cmi = brcms_c_channel_mgr_attach(wlc);
  6692. if (!wlc->cmi) {
  6693. wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
  6694. "\n", unit, __func__);
  6695. err = 33;
  6696. goto fail;
  6697. }
  6698. /* init default when all parameters are ready, i.e. ->rateset */
  6699. brcms_c_bss_default_init(wlc);
  6700. /*
  6701. * Complete the wlc default state initializations..
  6702. */
  6703. wlc->bsscfg->wlc = wlc;
  6704. wlc->mimoft = FT_HT;
  6705. wlc->mimo_40txbw = AUTO;
  6706. wlc->ofdm_40txbw = AUTO;
  6707. wlc->cck_40txbw = AUTO;
  6708. brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
  6709. /* Set default values of SGI */
  6710. if (BRCMS_SGI_CAP_PHY(wlc)) {
  6711. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  6712. BRCMS_N_SGI_40));
  6713. } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
  6714. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  6715. BRCMS_N_SGI_40));
  6716. } else {
  6717. brcms_c_ht_update_sgi_rx(wlc, 0);
  6718. }
  6719. brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
  6720. if (perr)
  6721. *perr = 0;
  6722. return wlc;
  6723. fail:
  6724. wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
  6725. unit, __func__, err);
  6726. if (wlc)
  6727. brcms_c_detach(wlc);
  6728. if (perr)
  6729. *perr = err;
  6730. return NULL;
  6731. }