qeth_core_main.c 123 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm/ebcdic.h>
  21. #include <asm/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_TRACE] = {"qeth_trace",
  33. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_MSG] = {"qeth_msg",
  35. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  36. [QETH_DBF_SENSE] = {"qeth_sense",
  37. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_MISC] = {"qeth_misc",
  39. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_CTRL] = {"qeth_control",
  41. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  42. };
  43. EXPORT_SYMBOL_GPL(qeth_dbf);
  44. struct qeth_card_list_struct qeth_core_card_list;
  45. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  46. struct kmem_cache *qeth_core_header_cache;
  47. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  48. static struct device *qeth_core_root_dev;
  49. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  50. static struct lock_class_key qdio_out_skb_queue_key;
  51. static void qeth_send_control_data_cb(struct qeth_channel *,
  52. struct qeth_cmd_buffer *);
  53. static int qeth_issue_next_read(struct qeth_card *);
  54. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  55. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  56. static void qeth_free_buffer_pool(struct qeth_card *);
  57. static int qeth_qdio_establish(struct qeth_card *);
  58. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  59. struct qdio_buffer *buffer, int is_tso,
  60. int *next_element_to_fill)
  61. {
  62. struct skb_frag_struct *frag;
  63. int fragno;
  64. unsigned long addr;
  65. int element, cnt, dlen;
  66. fragno = skb_shinfo(skb)->nr_frags;
  67. element = *next_element_to_fill;
  68. dlen = 0;
  69. if (is_tso)
  70. buffer->element[element].flags =
  71. SBAL_FLAGS_MIDDLE_FRAG;
  72. else
  73. buffer->element[element].flags =
  74. SBAL_FLAGS_FIRST_FRAG;
  75. dlen = skb->len - skb->data_len;
  76. if (dlen) {
  77. buffer->element[element].addr = skb->data;
  78. buffer->element[element].length = dlen;
  79. element++;
  80. }
  81. for (cnt = 0; cnt < fragno; cnt++) {
  82. frag = &skb_shinfo(skb)->frags[cnt];
  83. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  84. frag->page_offset;
  85. buffer->element[element].addr = (char *)addr;
  86. buffer->element[element].length = frag->size;
  87. if (cnt < (fragno - 1))
  88. buffer->element[element].flags =
  89. SBAL_FLAGS_MIDDLE_FRAG;
  90. else
  91. buffer->element[element].flags =
  92. SBAL_FLAGS_LAST_FRAG;
  93. element++;
  94. }
  95. *next_element_to_fill = element;
  96. }
  97. static inline const char *qeth_get_cardname(struct qeth_card *card)
  98. {
  99. if (card->info.guestlan) {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSAE:
  102. return " Guest LAN QDIO";
  103. case QETH_CARD_TYPE_IQD:
  104. return " Guest LAN Hiper";
  105. default:
  106. return " unknown";
  107. }
  108. } else {
  109. switch (card->info.type) {
  110. case QETH_CARD_TYPE_OSAE:
  111. return " OSD Express";
  112. case QETH_CARD_TYPE_IQD:
  113. return " HiperSockets";
  114. case QETH_CARD_TYPE_OSN:
  115. return " OSN QDIO";
  116. default:
  117. return " unknown";
  118. }
  119. }
  120. return " n/a";
  121. }
  122. /* max length to be returned: 14 */
  123. const char *qeth_get_cardname_short(struct qeth_card *card)
  124. {
  125. if (card->info.guestlan) {
  126. switch (card->info.type) {
  127. case QETH_CARD_TYPE_OSAE:
  128. return "GuestLAN QDIO";
  129. case QETH_CARD_TYPE_IQD:
  130. return "GuestLAN Hiper";
  131. default:
  132. return "unknown";
  133. }
  134. } else {
  135. switch (card->info.type) {
  136. case QETH_CARD_TYPE_OSAE:
  137. switch (card->info.link_type) {
  138. case QETH_LINK_TYPE_FAST_ETH:
  139. return "OSD_100";
  140. case QETH_LINK_TYPE_HSTR:
  141. return "HSTR";
  142. case QETH_LINK_TYPE_GBIT_ETH:
  143. return "OSD_1000";
  144. case QETH_LINK_TYPE_10GBIT_ETH:
  145. return "OSD_10GIG";
  146. case QETH_LINK_TYPE_LANE_ETH100:
  147. return "OSD_FE_LANE";
  148. case QETH_LINK_TYPE_LANE_TR:
  149. return "OSD_TR_LANE";
  150. case QETH_LINK_TYPE_LANE_ETH1000:
  151. return "OSD_GbE_LANE";
  152. case QETH_LINK_TYPE_LANE:
  153. return "OSD_ATM_LANE";
  154. default:
  155. return "OSD_Express";
  156. }
  157. case QETH_CARD_TYPE_IQD:
  158. return "HiperSockets";
  159. case QETH_CARD_TYPE_OSN:
  160. return "OSN";
  161. default:
  162. return "unknown";
  163. }
  164. }
  165. return "n/a";
  166. }
  167. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  168. int clear_start_mask)
  169. {
  170. unsigned long flags;
  171. spin_lock_irqsave(&card->thread_mask_lock, flags);
  172. card->thread_allowed_mask = threads;
  173. if (clear_start_mask)
  174. card->thread_start_mask &= threads;
  175. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  176. wake_up(&card->wait_q);
  177. }
  178. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  179. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  180. {
  181. unsigned long flags;
  182. int rc = 0;
  183. spin_lock_irqsave(&card->thread_mask_lock, flags);
  184. rc = (card->thread_running_mask & threads);
  185. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  186. return rc;
  187. }
  188. EXPORT_SYMBOL_GPL(qeth_threads_running);
  189. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  190. {
  191. return wait_event_interruptible(card->wait_q,
  192. qeth_threads_running(card, threads) == 0);
  193. }
  194. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  195. void qeth_clear_working_pool_list(struct qeth_card *card)
  196. {
  197. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  198. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  199. list_for_each_entry_safe(pool_entry, tmp,
  200. &card->qdio.in_buf_pool.entry_list, list){
  201. list_del(&pool_entry->list);
  202. }
  203. }
  204. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  205. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  206. {
  207. struct qeth_buffer_pool_entry *pool_entry;
  208. void *ptr;
  209. int i, j;
  210. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  211. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  212. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  213. if (!pool_entry) {
  214. qeth_free_buffer_pool(card);
  215. return -ENOMEM;
  216. }
  217. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  218. ptr = (void *) __get_free_page(GFP_KERNEL);
  219. if (!ptr) {
  220. while (j > 0)
  221. free_page((unsigned long)
  222. pool_entry->elements[--j]);
  223. kfree(pool_entry);
  224. qeth_free_buffer_pool(card);
  225. return -ENOMEM;
  226. }
  227. pool_entry->elements[j] = ptr;
  228. }
  229. list_add(&pool_entry->init_list,
  230. &card->qdio.init_pool.entry_list);
  231. }
  232. return 0;
  233. }
  234. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  235. {
  236. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  237. if ((card->state != CARD_STATE_DOWN) &&
  238. (card->state != CARD_STATE_RECOVER))
  239. return -EPERM;
  240. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  241. qeth_clear_working_pool_list(card);
  242. qeth_free_buffer_pool(card);
  243. card->qdio.in_buf_pool.buf_count = bufcnt;
  244. card->qdio.init_pool.buf_count = bufcnt;
  245. return qeth_alloc_buffer_pool(card);
  246. }
  247. int qeth_set_large_send(struct qeth_card *card,
  248. enum qeth_large_send_types type)
  249. {
  250. int rc = 0;
  251. if (card->dev == NULL) {
  252. card->options.large_send = type;
  253. return 0;
  254. }
  255. if (card->state == CARD_STATE_UP)
  256. netif_tx_disable(card->dev);
  257. card->options.large_send = type;
  258. switch (card->options.large_send) {
  259. case QETH_LARGE_SEND_EDDP:
  260. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  261. NETIF_F_HW_CSUM;
  262. break;
  263. case QETH_LARGE_SEND_TSO:
  264. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  265. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  266. NETIF_F_HW_CSUM;
  267. } else {
  268. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  269. NETIF_F_HW_CSUM);
  270. card->options.large_send = QETH_LARGE_SEND_NO;
  271. rc = -EOPNOTSUPP;
  272. }
  273. break;
  274. default: /* includes QETH_LARGE_SEND_NO */
  275. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  276. NETIF_F_HW_CSUM);
  277. break;
  278. }
  279. if (card->state == CARD_STATE_UP)
  280. netif_wake_queue(card->dev);
  281. return rc;
  282. }
  283. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  284. static int qeth_issue_next_read(struct qeth_card *card)
  285. {
  286. int rc;
  287. struct qeth_cmd_buffer *iob;
  288. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  289. if (card->read.state != CH_STATE_UP)
  290. return -EIO;
  291. iob = qeth_get_buffer(&card->read);
  292. if (!iob) {
  293. PRINT_WARN("issue_next_read failed: no iob available!\n");
  294. return -ENOMEM;
  295. }
  296. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  297. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  298. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  299. (addr_t) iob, 0, 0);
  300. if (rc) {
  301. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  302. atomic_set(&card->read.irq_pending, 0);
  303. qeth_schedule_recovery(card);
  304. wake_up(&card->wait_q);
  305. }
  306. return rc;
  307. }
  308. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  309. {
  310. struct qeth_reply *reply;
  311. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  312. if (reply) {
  313. atomic_set(&reply->refcnt, 1);
  314. atomic_set(&reply->received, 0);
  315. reply->card = card;
  316. };
  317. return reply;
  318. }
  319. static void qeth_get_reply(struct qeth_reply *reply)
  320. {
  321. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  322. atomic_inc(&reply->refcnt);
  323. }
  324. static void qeth_put_reply(struct qeth_reply *reply)
  325. {
  326. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  327. if (atomic_dec_and_test(&reply->refcnt))
  328. kfree(reply);
  329. }
  330. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  331. struct qeth_card *card)
  332. {
  333. char *ipa_name;
  334. int com = cmd->hdr.command;
  335. ipa_name = qeth_get_ipa_cmd_name(com);
  336. if (rc)
  337. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  338. ipa_name, com, QETH_CARD_IFNAME(card),
  339. rc, qeth_get_ipa_msg(rc));
  340. else
  341. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  342. ipa_name, com, QETH_CARD_IFNAME(card));
  343. }
  344. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  345. struct qeth_cmd_buffer *iob)
  346. {
  347. struct qeth_ipa_cmd *cmd = NULL;
  348. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  349. if (IS_IPA(iob->data)) {
  350. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  351. if (IS_IPA_REPLY(cmd)) {
  352. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  353. cmd->hdr.command > IPA_CMD_MODCCID)
  354. qeth_issue_ipa_msg(cmd,
  355. cmd->hdr.return_code, card);
  356. return cmd;
  357. } else {
  358. switch (cmd->hdr.command) {
  359. case IPA_CMD_STOPLAN:
  360. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  361. "there is a network problem or "
  362. "someone pulled the cable or "
  363. "disabled the port.\n",
  364. QETH_CARD_IFNAME(card),
  365. card->info.chpid);
  366. card->lan_online = 0;
  367. if (card->dev && netif_carrier_ok(card->dev))
  368. netif_carrier_off(card->dev);
  369. return NULL;
  370. case IPA_CMD_STARTLAN:
  371. PRINT_INFO("Link reestablished on %s "
  372. "(CHPID 0x%X). Scheduling "
  373. "IP address reset.\n",
  374. QETH_CARD_IFNAME(card),
  375. card->info.chpid);
  376. netif_carrier_on(card->dev);
  377. card->lan_online = 1;
  378. qeth_schedule_recovery(card);
  379. return NULL;
  380. case IPA_CMD_MODCCID:
  381. return cmd;
  382. case IPA_CMD_REGISTER_LOCAL_ADDR:
  383. QETH_DBF_TEXT(TRACE, 3, "irla");
  384. break;
  385. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  386. QETH_DBF_TEXT(TRACE, 3, "urla");
  387. break;
  388. default:
  389. QETH_DBF_MESSAGE(2, "Received data is IPA "
  390. "but not a reply!\n");
  391. break;
  392. }
  393. }
  394. }
  395. return cmd;
  396. }
  397. void qeth_clear_ipacmd_list(struct qeth_card *card)
  398. {
  399. struct qeth_reply *reply, *r;
  400. unsigned long flags;
  401. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  402. spin_lock_irqsave(&card->lock, flags);
  403. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  404. qeth_get_reply(reply);
  405. reply->rc = -EIO;
  406. atomic_inc(&reply->received);
  407. list_del_init(&reply->list);
  408. wake_up(&reply->wait_q);
  409. qeth_put_reply(reply);
  410. }
  411. spin_unlock_irqrestore(&card->lock, flags);
  412. }
  413. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  414. static int qeth_check_idx_response(unsigned char *buffer)
  415. {
  416. if (!buffer)
  417. return 0;
  418. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  419. if ((buffer[2] & 0xc0) == 0xc0) {
  420. PRINT_WARN("received an IDX TERMINATE "
  421. "with cause code 0x%02x%s\n",
  422. buffer[4],
  423. ((buffer[4] == 0x22) ?
  424. " -- try another portname" : ""));
  425. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  426. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  427. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  428. return -EIO;
  429. }
  430. return 0;
  431. }
  432. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  433. __u32 len)
  434. {
  435. struct qeth_card *card;
  436. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  437. card = CARD_FROM_CDEV(channel->ccwdev);
  438. if (channel == &card->read)
  439. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  440. else
  441. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  442. channel->ccw.count = len;
  443. channel->ccw.cda = (__u32) __pa(iob);
  444. }
  445. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  446. {
  447. __u8 index;
  448. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  449. index = channel->io_buf_no;
  450. do {
  451. if (channel->iob[index].state == BUF_STATE_FREE) {
  452. channel->iob[index].state = BUF_STATE_LOCKED;
  453. channel->io_buf_no = (channel->io_buf_no + 1) %
  454. QETH_CMD_BUFFER_NO;
  455. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  456. return channel->iob + index;
  457. }
  458. index = (index + 1) % QETH_CMD_BUFFER_NO;
  459. } while (index != channel->io_buf_no);
  460. return NULL;
  461. }
  462. void qeth_release_buffer(struct qeth_channel *channel,
  463. struct qeth_cmd_buffer *iob)
  464. {
  465. unsigned long flags;
  466. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  467. spin_lock_irqsave(&channel->iob_lock, flags);
  468. memset(iob->data, 0, QETH_BUFSIZE);
  469. iob->state = BUF_STATE_FREE;
  470. iob->callback = qeth_send_control_data_cb;
  471. iob->rc = 0;
  472. spin_unlock_irqrestore(&channel->iob_lock, flags);
  473. }
  474. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  475. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  476. {
  477. struct qeth_cmd_buffer *buffer = NULL;
  478. unsigned long flags;
  479. spin_lock_irqsave(&channel->iob_lock, flags);
  480. buffer = __qeth_get_buffer(channel);
  481. spin_unlock_irqrestore(&channel->iob_lock, flags);
  482. return buffer;
  483. }
  484. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  485. {
  486. struct qeth_cmd_buffer *buffer;
  487. wait_event(channel->wait_q,
  488. ((buffer = qeth_get_buffer(channel)) != NULL));
  489. return buffer;
  490. }
  491. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  492. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  493. {
  494. int cnt;
  495. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  496. qeth_release_buffer(channel, &channel->iob[cnt]);
  497. channel->buf_no = 0;
  498. channel->io_buf_no = 0;
  499. }
  500. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  501. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  502. struct qeth_cmd_buffer *iob)
  503. {
  504. struct qeth_card *card;
  505. struct qeth_reply *reply, *r;
  506. struct qeth_ipa_cmd *cmd;
  507. unsigned long flags;
  508. int keep_reply;
  509. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  510. card = CARD_FROM_CDEV(channel->ccwdev);
  511. if (qeth_check_idx_response(iob->data)) {
  512. qeth_clear_ipacmd_list(card);
  513. qeth_schedule_recovery(card);
  514. goto out;
  515. }
  516. cmd = qeth_check_ipa_data(card, iob);
  517. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  518. goto out;
  519. /*in case of OSN : check if cmd is set */
  520. if (card->info.type == QETH_CARD_TYPE_OSN &&
  521. cmd &&
  522. cmd->hdr.command != IPA_CMD_STARTLAN &&
  523. card->osn_info.assist_cb != NULL) {
  524. card->osn_info.assist_cb(card->dev, cmd);
  525. goto out;
  526. }
  527. spin_lock_irqsave(&card->lock, flags);
  528. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  529. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  530. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  531. qeth_get_reply(reply);
  532. list_del_init(&reply->list);
  533. spin_unlock_irqrestore(&card->lock, flags);
  534. keep_reply = 0;
  535. if (reply->callback != NULL) {
  536. if (cmd) {
  537. reply->offset = (__u16)((char *)cmd -
  538. (char *)iob->data);
  539. keep_reply = reply->callback(card,
  540. reply,
  541. (unsigned long)cmd);
  542. } else
  543. keep_reply = reply->callback(card,
  544. reply,
  545. (unsigned long)iob);
  546. }
  547. if (cmd)
  548. reply->rc = (u16) cmd->hdr.return_code;
  549. else if (iob->rc)
  550. reply->rc = iob->rc;
  551. if (keep_reply) {
  552. spin_lock_irqsave(&card->lock, flags);
  553. list_add_tail(&reply->list,
  554. &card->cmd_waiter_list);
  555. spin_unlock_irqrestore(&card->lock, flags);
  556. } else {
  557. atomic_inc(&reply->received);
  558. wake_up(&reply->wait_q);
  559. }
  560. qeth_put_reply(reply);
  561. goto out;
  562. }
  563. }
  564. spin_unlock_irqrestore(&card->lock, flags);
  565. out:
  566. memcpy(&card->seqno.pdu_hdr_ack,
  567. QETH_PDU_HEADER_SEQ_NO(iob->data),
  568. QETH_SEQ_NO_LENGTH);
  569. qeth_release_buffer(channel, iob);
  570. }
  571. static int qeth_setup_channel(struct qeth_channel *channel)
  572. {
  573. int cnt;
  574. QETH_DBF_TEXT(SETUP, 2, "setupch");
  575. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  576. channel->iob[cnt].data = (char *)
  577. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  578. if (channel->iob[cnt].data == NULL)
  579. break;
  580. channel->iob[cnt].state = BUF_STATE_FREE;
  581. channel->iob[cnt].channel = channel;
  582. channel->iob[cnt].callback = qeth_send_control_data_cb;
  583. channel->iob[cnt].rc = 0;
  584. }
  585. if (cnt < QETH_CMD_BUFFER_NO) {
  586. while (cnt-- > 0)
  587. kfree(channel->iob[cnt].data);
  588. return -ENOMEM;
  589. }
  590. channel->buf_no = 0;
  591. channel->io_buf_no = 0;
  592. atomic_set(&channel->irq_pending, 0);
  593. spin_lock_init(&channel->iob_lock);
  594. init_waitqueue_head(&channel->wait_q);
  595. return 0;
  596. }
  597. static int qeth_set_thread_start_bit(struct qeth_card *card,
  598. unsigned long thread)
  599. {
  600. unsigned long flags;
  601. spin_lock_irqsave(&card->thread_mask_lock, flags);
  602. if (!(card->thread_allowed_mask & thread) ||
  603. (card->thread_start_mask & thread)) {
  604. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  605. return -EPERM;
  606. }
  607. card->thread_start_mask |= thread;
  608. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  609. return 0;
  610. }
  611. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  612. {
  613. unsigned long flags;
  614. spin_lock_irqsave(&card->thread_mask_lock, flags);
  615. card->thread_start_mask &= ~thread;
  616. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  617. wake_up(&card->wait_q);
  618. }
  619. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  620. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  621. {
  622. unsigned long flags;
  623. spin_lock_irqsave(&card->thread_mask_lock, flags);
  624. card->thread_running_mask &= ~thread;
  625. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  626. wake_up(&card->wait_q);
  627. }
  628. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  629. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  630. {
  631. unsigned long flags;
  632. int rc = 0;
  633. spin_lock_irqsave(&card->thread_mask_lock, flags);
  634. if (card->thread_start_mask & thread) {
  635. if ((card->thread_allowed_mask & thread) &&
  636. !(card->thread_running_mask & thread)) {
  637. rc = 1;
  638. card->thread_start_mask &= ~thread;
  639. card->thread_running_mask |= thread;
  640. } else
  641. rc = -EPERM;
  642. }
  643. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  644. return rc;
  645. }
  646. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  647. {
  648. int rc = 0;
  649. wait_event(card->wait_q,
  650. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  651. return rc;
  652. }
  653. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  654. void qeth_schedule_recovery(struct qeth_card *card)
  655. {
  656. QETH_DBF_TEXT(TRACE, 2, "startrec");
  657. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  658. schedule_work(&card->kernel_thread_starter);
  659. }
  660. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  661. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  662. {
  663. int dstat, cstat;
  664. char *sense;
  665. sense = (char *) irb->ecw;
  666. cstat = irb->scsw.cmd.cstat;
  667. dstat = irb->scsw.cmd.dstat;
  668. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  669. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  670. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  671. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  672. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  673. cdev->dev.bus_id, dstat, cstat);
  674. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  675. 16, 1, irb, 64, 1);
  676. return 1;
  677. }
  678. if (dstat & DEV_STAT_UNIT_CHECK) {
  679. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  680. SENSE_RESETTING_EVENT_FLAG) {
  681. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  682. return 1;
  683. }
  684. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  685. SENSE_COMMAND_REJECT_FLAG) {
  686. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  687. return 0;
  688. }
  689. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  690. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  691. return 1;
  692. }
  693. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  694. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  695. return 0;
  696. }
  697. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  698. return 1;
  699. }
  700. return 0;
  701. }
  702. static long __qeth_check_irb_error(struct ccw_device *cdev,
  703. unsigned long intparm, struct irb *irb)
  704. {
  705. if (!IS_ERR(irb))
  706. return 0;
  707. switch (PTR_ERR(irb)) {
  708. case -EIO:
  709. PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
  710. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  711. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  712. break;
  713. case -ETIMEDOUT:
  714. PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
  715. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  716. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  717. if (intparm == QETH_RCD_PARM) {
  718. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  719. if (card && (card->data.ccwdev == cdev)) {
  720. card->data.state = CH_STATE_DOWN;
  721. wake_up(&card->wait_q);
  722. }
  723. }
  724. break;
  725. default:
  726. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  727. cdev->dev.bus_id);
  728. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  729. QETH_DBF_TEXT(TRACE, 2, " rc???");
  730. }
  731. return PTR_ERR(irb);
  732. }
  733. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  734. struct irb *irb)
  735. {
  736. int rc;
  737. int cstat, dstat;
  738. struct qeth_cmd_buffer *buffer;
  739. struct qeth_channel *channel;
  740. struct qeth_card *card;
  741. struct qeth_cmd_buffer *iob;
  742. __u8 index;
  743. QETH_DBF_TEXT(TRACE, 5, "irq");
  744. if (__qeth_check_irb_error(cdev, intparm, irb))
  745. return;
  746. cstat = irb->scsw.cmd.cstat;
  747. dstat = irb->scsw.cmd.dstat;
  748. card = CARD_FROM_CDEV(cdev);
  749. if (!card)
  750. return;
  751. if (card->read.ccwdev == cdev) {
  752. channel = &card->read;
  753. QETH_DBF_TEXT(TRACE, 5, "read");
  754. } else if (card->write.ccwdev == cdev) {
  755. channel = &card->write;
  756. QETH_DBF_TEXT(TRACE, 5, "write");
  757. } else {
  758. channel = &card->data;
  759. QETH_DBF_TEXT(TRACE, 5, "data");
  760. }
  761. atomic_set(&channel->irq_pending, 0);
  762. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  763. channel->state = CH_STATE_STOPPED;
  764. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  765. channel->state = CH_STATE_HALTED;
  766. /*let's wake up immediately on data channel*/
  767. if ((channel == &card->data) && (intparm != 0) &&
  768. (intparm != QETH_RCD_PARM))
  769. goto out;
  770. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  771. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  772. /* we don't have to handle this further */
  773. intparm = 0;
  774. }
  775. if (intparm == QETH_HALT_CHANNEL_PARM) {
  776. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  777. /* we don't have to handle this further */
  778. intparm = 0;
  779. }
  780. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  781. (dstat & DEV_STAT_UNIT_CHECK) ||
  782. (cstat)) {
  783. if (irb->esw.esw0.erw.cons) {
  784. /* TODO: we should make this s390dbf */
  785. PRINT_WARN("sense data available on channel %s.\n",
  786. CHANNEL_ID(channel));
  787. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  788. print_hex_dump(KERN_WARNING, "qeth: irb ",
  789. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  790. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  791. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  792. }
  793. if (intparm == QETH_RCD_PARM) {
  794. channel->state = CH_STATE_DOWN;
  795. goto out;
  796. }
  797. rc = qeth_get_problem(cdev, irb);
  798. if (rc) {
  799. qeth_schedule_recovery(card);
  800. goto out;
  801. }
  802. }
  803. if (intparm == QETH_RCD_PARM) {
  804. channel->state = CH_STATE_RCD_DONE;
  805. goto out;
  806. }
  807. if (intparm) {
  808. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  809. buffer->state = BUF_STATE_PROCESSED;
  810. }
  811. if (channel == &card->data)
  812. return;
  813. if (channel == &card->read &&
  814. channel->state == CH_STATE_UP)
  815. qeth_issue_next_read(card);
  816. iob = channel->iob;
  817. index = channel->buf_no;
  818. while (iob[index].state == BUF_STATE_PROCESSED) {
  819. if (iob[index].callback != NULL)
  820. iob[index].callback(channel, iob + index);
  821. index = (index + 1) % QETH_CMD_BUFFER_NO;
  822. }
  823. channel->buf_no = index;
  824. out:
  825. wake_up(&card->wait_q);
  826. return;
  827. }
  828. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  829. struct qeth_qdio_out_buffer *buf)
  830. {
  831. int i;
  832. struct sk_buff *skb;
  833. /* is PCI flag set on buffer? */
  834. if (buf->buffer->element[0].flags & 0x40)
  835. atomic_dec(&queue->set_pci_flags_count);
  836. skb = skb_dequeue(&buf->skb_list);
  837. while (skb) {
  838. atomic_dec(&skb->users);
  839. dev_kfree_skb_any(skb);
  840. skb = skb_dequeue(&buf->skb_list);
  841. }
  842. qeth_eddp_buf_release_contexts(buf);
  843. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  844. if (buf->buffer->element[i].addr && buf->is_header[i])
  845. kmem_cache_free(qeth_core_header_cache,
  846. buf->buffer->element[i].addr);
  847. buf->is_header[i] = 0;
  848. buf->buffer->element[i].length = 0;
  849. buf->buffer->element[i].addr = NULL;
  850. buf->buffer->element[i].flags = 0;
  851. }
  852. buf->next_element_to_fill = 0;
  853. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  854. }
  855. void qeth_clear_qdio_buffers(struct qeth_card *card)
  856. {
  857. int i, j;
  858. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  859. /* clear outbound buffers to free skbs */
  860. for (i = 0; i < card->qdio.no_out_queues; ++i)
  861. if (card->qdio.out_qs[i]) {
  862. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  863. qeth_clear_output_buffer(card->qdio.out_qs[i],
  864. &card->qdio.out_qs[i]->bufs[j]);
  865. }
  866. }
  867. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  868. static void qeth_free_buffer_pool(struct qeth_card *card)
  869. {
  870. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  871. int i = 0;
  872. QETH_DBF_TEXT(TRACE, 5, "freepool");
  873. list_for_each_entry_safe(pool_entry, tmp,
  874. &card->qdio.init_pool.entry_list, init_list){
  875. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  876. free_page((unsigned long)pool_entry->elements[i]);
  877. list_del(&pool_entry->init_list);
  878. kfree(pool_entry);
  879. }
  880. }
  881. static void qeth_free_qdio_buffers(struct qeth_card *card)
  882. {
  883. int i, j;
  884. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  885. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  886. QETH_QDIO_UNINITIALIZED)
  887. return;
  888. kfree(card->qdio.in_q);
  889. card->qdio.in_q = NULL;
  890. /* inbound buffer pool */
  891. qeth_free_buffer_pool(card);
  892. /* free outbound qdio_qs */
  893. if (card->qdio.out_qs) {
  894. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  895. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  896. qeth_clear_output_buffer(card->qdio.out_qs[i],
  897. &card->qdio.out_qs[i]->bufs[j]);
  898. kfree(card->qdio.out_qs[i]);
  899. }
  900. kfree(card->qdio.out_qs);
  901. card->qdio.out_qs = NULL;
  902. }
  903. }
  904. static void qeth_clean_channel(struct qeth_channel *channel)
  905. {
  906. int cnt;
  907. QETH_DBF_TEXT(SETUP, 2, "freech");
  908. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  909. kfree(channel->iob[cnt].data);
  910. }
  911. static int qeth_is_1920_device(struct qeth_card *card)
  912. {
  913. int single_queue = 0;
  914. struct ccw_device *ccwdev;
  915. struct channelPath_dsc {
  916. u8 flags;
  917. u8 lsn;
  918. u8 desc;
  919. u8 chpid;
  920. u8 swla;
  921. u8 zeroes;
  922. u8 chla;
  923. u8 chpp;
  924. } *chp_dsc;
  925. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  926. ccwdev = card->data.ccwdev;
  927. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  928. if (chp_dsc != NULL) {
  929. /* CHPP field bit 6 == 1 -> single queue */
  930. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  931. kfree(chp_dsc);
  932. }
  933. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  934. return single_queue;
  935. }
  936. static void qeth_init_qdio_info(struct qeth_card *card)
  937. {
  938. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  939. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  940. /* inbound */
  941. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  942. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  943. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  944. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  945. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  946. }
  947. static void qeth_set_intial_options(struct qeth_card *card)
  948. {
  949. card->options.route4.type = NO_ROUTER;
  950. card->options.route6.type = NO_ROUTER;
  951. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  952. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  953. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  954. card->options.fake_broadcast = 0;
  955. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  956. card->options.fake_ll = 0;
  957. card->options.performance_stats = 0;
  958. card->options.rx_sg_cb = QETH_RX_SG_CB;
  959. }
  960. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  961. {
  962. unsigned long flags;
  963. int rc = 0;
  964. spin_lock_irqsave(&card->thread_mask_lock, flags);
  965. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  966. (u8) card->thread_start_mask,
  967. (u8) card->thread_allowed_mask,
  968. (u8) card->thread_running_mask);
  969. rc = (card->thread_start_mask & thread);
  970. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  971. return rc;
  972. }
  973. static void qeth_start_kernel_thread(struct work_struct *work)
  974. {
  975. struct qeth_card *card = container_of(work, struct qeth_card,
  976. kernel_thread_starter);
  977. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  978. if (card->read.state != CH_STATE_UP &&
  979. card->write.state != CH_STATE_UP)
  980. return;
  981. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  982. kthread_run(card->discipline.recover, (void *) card,
  983. "qeth_recover");
  984. }
  985. static int qeth_setup_card(struct qeth_card *card)
  986. {
  987. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  988. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  989. card->read.state = CH_STATE_DOWN;
  990. card->write.state = CH_STATE_DOWN;
  991. card->data.state = CH_STATE_DOWN;
  992. card->state = CARD_STATE_DOWN;
  993. card->lan_online = 0;
  994. card->use_hard_stop = 0;
  995. card->dev = NULL;
  996. spin_lock_init(&card->vlanlock);
  997. spin_lock_init(&card->mclock);
  998. card->vlangrp = NULL;
  999. spin_lock_init(&card->lock);
  1000. spin_lock_init(&card->ip_lock);
  1001. spin_lock_init(&card->thread_mask_lock);
  1002. card->thread_start_mask = 0;
  1003. card->thread_allowed_mask = 0;
  1004. card->thread_running_mask = 0;
  1005. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1006. INIT_LIST_HEAD(&card->ip_list);
  1007. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1008. if (!card->ip_tbd_list) {
  1009. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1010. return -ENOMEM;
  1011. }
  1012. INIT_LIST_HEAD(card->ip_tbd_list);
  1013. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1014. init_waitqueue_head(&card->wait_q);
  1015. /* intial options */
  1016. qeth_set_intial_options(card);
  1017. /* IP address takeover */
  1018. INIT_LIST_HEAD(&card->ipato.entries);
  1019. card->ipato.enabled = 0;
  1020. card->ipato.invert4 = 0;
  1021. card->ipato.invert6 = 0;
  1022. /* init QDIO stuff */
  1023. qeth_init_qdio_info(card);
  1024. return 0;
  1025. }
  1026. static struct qeth_card *qeth_alloc_card(void)
  1027. {
  1028. struct qeth_card *card;
  1029. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1030. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1031. if (!card)
  1032. return NULL;
  1033. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1034. if (qeth_setup_channel(&card->read)) {
  1035. kfree(card);
  1036. return NULL;
  1037. }
  1038. if (qeth_setup_channel(&card->write)) {
  1039. qeth_clean_channel(&card->read);
  1040. kfree(card);
  1041. return NULL;
  1042. }
  1043. card->options.layer2 = -1;
  1044. return card;
  1045. }
  1046. static int qeth_determine_card_type(struct qeth_card *card)
  1047. {
  1048. int i = 0;
  1049. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1050. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1051. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1052. while (known_devices[i][4]) {
  1053. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1054. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1055. card->info.type = known_devices[i][4];
  1056. card->qdio.no_out_queues = known_devices[i][8];
  1057. card->info.is_multicast_different = known_devices[i][9];
  1058. if (qeth_is_1920_device(card)) {
  1059. PRINT_INFO("Priority Queueing not able "
  1060. "due to hardware limitations!\n");
  1061. card->qdio.no_out_queues = 1;
  1062. card->qdio.default_out_queue = 0;
  1063. }
  1064. return 0;
  1065. }
  1066. i++;
  1067. }
  1068. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1069. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1070. return -ENOENT;
  1071. }
  1072. static int qeth_clear_channel(struct qeth_channel *channel)
  1073. {
  1074. unsigned long flags;
  1075. struct qeth_card *card;
  1076. int rc;
  1077. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1078. card = CARD_FROM_CDEV(channel->ccwdev);
  1079. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1080. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1081. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1082. if (rc)
  1083. return rc;
  1084. rc = wait_event_interruptible_timeout(card->wait_q,
  1085. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1086. if (rc == -ERESTARTSYS)
  1087. return rc;
  1088. if (channel->state != CH_STATE_STOPPED)
  1089. return -ETIME;
  1090. channel->state = CH_STATE_DOWN;
  1091. return 0;
  1092. }
  1093. static int qeth_halt_channel(struct qeth_channel *channel)
  1094. {
  1095. unsigned long flags;
  1096. struct qeth_card *card;
  1097. int rc;
  1098. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1099. card = CARD_FROM_CDEV(channel->ccwdev);
  1100. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1101. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1102. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1103. if (rc)
  1104. return rc;
  1105. rc = wait_event_interruptible_timeout(card->wait_q,
  1106. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1107. if (rc == -ERESTARTSYS)
  1108. return rc;
  1109. if (channel->state != CH_STATE_HALTED)
  1110. return -ETIME;
  1111. return 0;
  1112. }
  1113. static int qeth_halt_channels(struct qeth_card *card)
  1114. {
  1115. int rc1 = 0, rc2 = 0, rc3 = 0;
  1116. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1117. rc1 = qeth_halt_channel(&card->read);
  1118. rc2 = qeth_halt_channel(&card->write);
  1119. rc3 = qeth_halt_channel(&card->data);
  1120. if (rc1)
  1121. return rc1;
  1122. if (rc2)
  1123. return rc2;
  1124. return rc3;
  1125. }
  1126. static int qeth_clear_channels(struct qeth_card *card)
  1127. {
  1128. int rc1 = 0, rc2 = 0, rc3 = 0;
  1129. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1130. rc1 = qeth_clear_channel(&card->read);
  1131. rc2 = qeth_clear_channel(&card->write);
  1132. rc3 = qeth_clear_channel(&card->data);
  1133. if (rc1)
  1134. return rc1;
  1135. if (rc2)
  1136. return rc2;
  1137. return rc3;
  1138. }
  1139. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1140. {
  1141. int rc = 0;
  1142. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1143. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1144. if (halt)
  1145. rc = qeth_halt_channels(card);
  1146. if (rc)
  1147. return rc;
  1148. return qeth_clear_channels(card);
  1149. }
  1150. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1151. {
  1152. int rc = 0;
  1153. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1154. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1155. QETH_QDIO_CLEANING)) {
  1156. case QETH_QDIO_ESTABLISHED:
  1157. if (card->info.type == QETH_CARD_TYPE_IQD)
  1158. rc = qdio_cleanup(CARD_DDEV(card),
  1159. QDIO_FLAG_CLEANUP_USING_HALT);
  1160. else
  1161. rc = qdio_cleanup(CARD_DDEV(card),
  1162. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1163. if (rc)
  1164. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1165. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1166. break;
  1167. case QETH_QDIO_CLEANING:
  1168. return rc;
  1169. default:
  1170. break;
  1171. }
  1172. rc = qeth_clear_halt_card(card, use_halt);
  1173. if (rc)
  1174. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1175. card->state = CARD_STATE_DOWN;
  1176. return rc;
  1177. }
  1178. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1179. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1180. int *length)
  1181. {
  1182. struct ciw *ciw;
  1183. char *rcd_buf;
  1184. int ret;
  1185. struct qeth_channel *channel = &card->data;
  1186. unsigned long flags;
  1187. /*
  1188. * scan for RCD command in extended SenseID data
  1189. */
  1190. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1191. if (!ciw || ciw->cmd == 0)
  1192. return -EOPNOTSUPP;
  1193. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1194. if (!rcd_buf)
  1195. return -ENOMEM;
  1196. channel->ccw.cmd_code = ciw->cmd;
  1197. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1198. channel->ccw.count = ciw->count;
  1199. channel->ccw.flags = CCW_FLAG_SLI;
  1200. channel->state = CH_STATE_RCD;
  1201. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1202. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1203. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1204. QETH_RCD_TIMEOUT);
  1205. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1206. if (!ret)
  1207. wait_event(card->wait_q,
  1208. (channel->state == CH_STATE_RCD_DONE ||
  1209. channel->state == CH_STATE_DOWN));
  1210. if (channel->state == CH_STATE_DOWN)
  1211. ret = -EIO;
  1212. else
  1213. channel->state = CH_STATE_DOWN;
  1214. if (ret) {
  1215. kfree(rcd_buf);
  1216. *buffer = NULL;
  1217. *length = 0;
  1218. } else {
  1219. *length = ciw->count;
  1220. *buffer = rcd_buf;
  1221. }
  1222. return ret;
  1223. }
  1224. static int qeth_get_unitaddr(struct qeth_card *card)
  1225. {
  1226. int length;
  1227. char *prcd;
  1228. int rc;
  1229. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1230. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1231. if (rc) {
  1232. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1233. CARD_DDEV_ID(card), rc);
  1234. return rc;
  1235. }
  1236. card->info.chpid = prcd[30];
  1237. card->info.unit_addr2 = prcd[31];
  1238. card->info.cula = prcd[63];
  1239. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1240. (prcd[0x11] == _ascebc['M']));
  1241. kfree(prcd);
  1242. return 0;
  1243. }
  1244. static void qeth_init_tokens(struct qeth_card *card)
  1245. {
  1246. card->token.issuer_rm_w = 0x00010103UL;
  1247. card->token.cm_filter_w = 0x00010108UL;
  1248. card->token.cm_connection_w = 0x0001010aUL;
  1249. card->token.ulp_filter_w = 0x0001010bUL;
  1250. card->token.ulp_connection_w = 0x0001010dUL;
  1251. }
  1252. static void qeth_init_func_level(struct qeth_card *card)
  1253. {
  1254. if (card->ipato.enabled) {
  1255. if (card->info.type == QETH_CARD_TYPE_IQD)
  1256. card->info.func_level =
  1257. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1258. else
  1259. card->info.func_level =
  1260. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1261. } else {
  1262. if (card->info.type == QETH_CARD_TYPE_IQD)
  1263. /*FIXME:why do we have same values for dis and ena for
  1264. osae??? */
  1265. card->info.func_level =
  1266. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1267. else
  1268. card->info.func_level =
  1269. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1270. }
  1271. }
  1272. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1273. void (*idx_reply_cb)(struct qeth_channel *,
  1274. struct qeth_cmd_buffer *))
  1275. {
  1276. struct qeth_cmd_buffer *iob;
  1277. unsigned long flags;
  1278. int rc;
  1279. struct qeth_card *card;
  1280. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1281. card = CARD_FROM_CDEV(channel->ccwdev);
  1282. iob = qeth_get_buffer(channel);
  1283. iob->callback = idx_reply_cb;
  1284. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1285. channel->ccw.count = QETH_BUFSIZE;
  1286. channel->ccw.cda = (__u32) __pa(iob->data);
  1287. wait_event(card->wait_q,
  1288. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1289. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1290. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1291. rc = ccw_device_start(channel->ccwdev,
  1292. &channel->ccw, (addr_t) iob, 0, 0);
  1293. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1294. if (rc) {
  1295. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1296. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1297. atomic_set(&channel->irq_pending, 0);
  1298. wake_up(&card->wait_q);
  1299. return rc;
  1300. }
  1301. rc = wait_event_interruptible_timeout(card->wait_q,
  1302. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1303. if (rc == -ERESTARTSYS)
  1304. return rc;
  1305. if (channel->state != CH_STATE_UP) {
  1306. rc = -ETIME;
  1307. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1308. qeth_clear_cmd_buffers(channel);
  1309. } else
  1310. rc = 0;
  1311. return rc;
  1312. }
  1313. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1314. void (*idx_reply_cb)(struct qeth_channel *,
  1315. struct qeth_cmd_buffer *))
  1316. {
  1317. struct qeth_card *card;
  1318. struct qeth_cmd_buffer *iob;
  1319. unsigned long flags;
  1320. __u16 temp;
  1321. __u8 tmp;
  1322. int rc;
  1323. struct ccw_dev_id temp_devid;
  1324. card = CARD_FROM_CDEV(channel->ccwdev);
  1325. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1326. iob = qeth_get_buffer(channel);
  1327. iob->callback = idx_reply_cb;
  1328. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1329. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1330. channel->ccw.cda = (__u32) __pa(iob->data);
  1331. if (channel == &card->write) {
  1332. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1333. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1334. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1335. card->seqno.trans_hdr++;
  1336. } else {
  1337. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1338. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1339. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1340. }
  1341. tmp = ((__u8)card->info.portno) | 0x80;
  1342. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1343. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1344. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1345. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1346. &card->info.func_level, sizeof(__u16));
  1347. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1348. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1349. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1350. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1351. wait_event(card->wait_q,
  1352. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1353. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1354. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1355. rc = ccw_device_start(channel->ccwdev,
  1356. &channel->ccw, (addr_t) iob, 0, 0);
  1357. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1358. if (rc) {
  1359. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1360. rc);
  1361. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1362. atomic_set(&channel->irq_pending, 0);
  1363. wake_up(&card->wait_q);
  1364. return rc;
  1365. }
  1366. rc = wait_event_interruptible_timeout(card->wait_q,
  1367. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1368. if (rc == -ERESTARTSYS)
  1369. return rc;
  1370. if (channel->state != CH_STATE_ACTIVATING) {
  1371. PRINT_WARN("IDX activate timed out!\n");
  1372. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1373. qeth_clear_cmd_buffers(channel);
  1374. return -ETIME;
  1375. }
  1376. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1377. }
  1378. static int qeth_peer_func_level(int level)
  1379. {
  1380. if ((level & 0xff) == 8)
  1381. return (level & 0xff) + 0x400;
  1382. if (((level >> 8) & 3) == 1)
  1383. return (level & 0xff) + 0x200;
  1384. return level;
  1385. }
  1386. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1387. struct qeth_cmd_buffer *iob)
  1388. {
  1389. struct qeth_card *card;
  1390. __u16 temp;
  1391. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1392. if (channel->state == CH_STATE_DOWN) {
  1393. channel->state = CH_STATE_ACTIVATING;
  1394. goto out;
  1395. }
  1396. card = CARD_FROM_CDEV(channel->ccwdev);
  1397. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1398. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1399. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1400. "adapter exclusively used by another host\n",
  1401. CARD_WDEV_ID(card));
  1402. else
  1403. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1404. "negative reply\n", CARD_WDEV_ID(card));
  1405. goto out;
  1406. }
  1407. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1408. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1409. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1410. "function level mismatch "
  1411. "(sent: 0x%x, received: 0x%x)\n",
  1412. CARD_WDEV_ID(card), card->info.func_level, temp);
  1413. goto out;
  1414. }
  1415. channel->state = CH_STATE_UP;
  1416. out:
  1417. qeth_release_buffer(channel, iob);
  1418. }
  1419. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1420. struct qeth_cmd_buffer *iob)
  1421. {
  1422. struct qeth_card *card;
  1423. __u16 temp;
  1424. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1425. if (channel->state == CH_STATE_DOWN) {
  1426. channel->state = CH_STATE_ACTIVATING;
  1427. goto out;
  1428. }
  1429. card = CARD_FROM_CDEV(channel->ccwdev);
  1430. if (qeth_check_idx_response(iob->data))
  1431. goto out;
  1432. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1433. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1434. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1435. "adapter exclusively used by another host\n",
  1436. CARD_RDEV_ID(card));
  1437. else
  1438. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1439. "negative reply\n", CARD_RDEV_ID(card));
  1440. goto out;
  1441. }
  1442. /**
  1443. * temporary fix for microcode bug
  1444. * to revert it,replace OR by AND
  1445. */
  1446. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1447. (card->info.type == QETH_CARD_TYPE_OSAE))
  1448. card->info.portname_required = 1;
  1449. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1450. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1451. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1452. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1453. CARD_RDEV_ID(card), card->info.func_level, temp);
  1454. goto out;
  1455. }
  1456. memcpy(&card->token.issuer_rm_r,
  1457. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1458. QETH_MPC_TOKEN_LENGTH);
  1459. memcpy(&card->info.mcl_level[0],
  1460. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1461. channel->state = CH_STATE_UP;
  1462. out:
  1463. qeth_release_buffer(channel, iob);
  1464. }
  1465. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1466. struct qeth_cmd_buffer *iob)
  1467. {
  1468. qeth_setup_ccw(&card->write, iob->data, len);
  1469. iob->callback = qeth_release_buffer;
  1470. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1471. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1472. card->seqno.trans_hdr++;
  1473. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1474. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1475. card->seqno.pdu_hdr++;
  1476. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1477. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1478. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1479. }
  1480. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1481. int qeth_send_control_data(struct qeth_card *card, int len,
  1482. struct qeth_cmd_buffer *iob,
  1483. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1484. unsigned long),
  1485. void *reply_param)
  1486. {
  1487. int rc;
  1488. unsigned long flags;
  1489. struct qeth_reply *reply = NULL;
  1490. unsigned long timeout;
  1491. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1492. reply = qeth_alloc_reply(card);
  1493. if (!reply) {
  1494. return -ENOMEM;
  1495. }
  1496. reply->callback = reply_cb;
  1497. reply->param = reply_param;
  1498. if (card->state == CARD_STATE_DOWN)
  1499. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1500. else
  1501. reply->seqno = card->seqno.ipa++;
  1502. init_waitqueue_head(&reply->wait_q);
  1503. spin_lock_irqsave(&card->lock, flags);
  1504. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1505. spin_unlock_irqrestore(&card->lock, flags);
  1506. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1507. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1508. qeth_prepare_control_data(card, len, iob);
  1509. if (IS_IPA(iob->data))
  1510. timeout = jiffies + QETH_IPA_TIMEOUT;
  1511. else
  1512. timeout = jiffies + QETH_TIMEOUT;
  1513. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1514. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1515. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1516. (addr_t) iob, 0, 0);
  1517. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1518. if (rc) {
  1519. PRINT_WARN("qeth_send_control_data: "
  1520. "ccw_device_start rc = %i\n", rc);
  1521. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1522. spin_lock_irqsave(&card->lock, flags);
  1523. list_del_init(&reply->list);
  1524. qeth_put_reply(reply);
  1525. spin_unlock_irqrestore(&card->lock, flags);
  1526. qeth_release_buffer(iob->channel, iob);
  1527. atomic_set(&card->write.irq_pending, 0);
  1528. wake_up(&card->wait_q);
  1529. return rc;
  1530. }
  1531. while (!atomic_read(&reply->received)) {
  1532. if (time_after(jiffies, timeout)) {
  1533. spin_lock_irqsave(&reply->card->lock, flags);
  1534. list_del_init(&reply->list);
  1535. spin_unlock_irqrestore(&reply->card->lock, flags);
  1536. reply->rc = -ETIME;
  1537. atomic_inc(&reply->received);
  1538. wake_up(&reply->wait_q);
  1539. }
  1540. cpu_relax();
  1541. };
  1542. rc = reply->rc;
  1543. qeth_put_reply(reply);
  1544. return rc;
  1545. }
  1546. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1547. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1548. unsigned long data)
  1549. {
  1550. struct qeth_cmd_buffer *iob;
  1551. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1552. iob = (struct qeth_cmd_buffer *) data;
  1553. memcpy(&card->token.cm_filter_r,
  1554. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1555. QETH_MPC_TOKEN_LENGTH);
  1556. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1557. return 0;
  1558. }
  1559. static int qeth_cm_enable(struct qeth_card *card)
  1560. {
  1561. int rc;
  1562. struct qeth_cmd_buffer *iob;
  1563. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1564. iob = qeth_wait_for_buffer(&card->write);
  1565. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1566. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1567. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1568. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1569. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1570. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1571. qeth_cm_enable_cb, NULL);
  1572. return rc;
  1573. }
  1574. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1575. unsigned long data)
  1576. {
  1577. struct qeth_cmd_buffer *iob;
  1578. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1579. iob = (struct qeth_cmd_buffer *) data;
  1580. memcpy(&card->token.cm_connection_r,
  1581. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1582. QETH_MPC_TOKEN_LENGTH);
  1583. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1584. return 0;
  1585. }
  1586. static int qeth_cm_setup(struct qeth_card *card)
  1587. {
  1588. int rc;
  1589. struct qeth_cmd_buffer *iob;
  1590. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1591. iob = qeth_wait_for_buffer(&card->write);
  1592. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1593. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1594. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1595. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1596. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1597. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1598. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1599. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1600. qeth_cm_setup_cb, NULL);
  1601. return rc;
  1602. }
  1603. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1604. {
  1605. switch (card->info.type) {
  1606. case QETH_CARD_TYPE_UNKNOWN:
  1607. return 1500;
  1608. case QETH_CARD_TYPE_IQD:
  1609. return card->info.max_mtu;
  1610. case QETH_CARD_TYPE_OSAE:
  1611. switch (card->info.link_type) {
  1612. case QETH_LINK_TYPE_HSTR:
  1613. case QETH_LINK_TYPE_LANE_TR:
  1614. return 2000;
  1615. default:
  1616. return 1492;
  1617. }
  1618. default:
  1619. return 1500;
  1620. }
  1621. }
  1622. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1623. {
  1624. switch (cardtype) {
  1625. case QETH_CARD_TYPE_UNKNOWN:
  1626. case QETH_CARD_TYPE_OSAE:
  1627. case QETH_CARD_TYPE_OSN:
  1628. return 61440;
  1629. case QETH_CARD_TYPE_IQD:
  1630. return 57344;
  1631. default:
  1632. return 1500;
  1633. }
  1634. }
  1635. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1636. {
  1637. switch (cardtype) {
  1638. case QETH_CARD_TYPE_IQD:
  1639. return 1;
  1640. default:
  1641. return 0;
  1642. }
  1643. }
  1644. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1645. {
  1646. switch (framesize) {
  1647. case 0x4000:
  1648. return 8192;
  1649. case 0x6000:
  1650. return 16384;
  1651. case 0xa000:
  1652. return 32768;
  1653. case 0xffff:
  1654. return 57344;
  1655. default:
  1656. return 0;
  1657. }
  1658. }
  1659. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1660. {
  1661. switch (card->info.type) {
  1662. case QETH_CARD_TYPE_OSAE:
  1663. return ((mtu >= 576) && (mtu <= 61440));
  1664. case QETH_CARD_TYPE_IQD:
  1665. return ((mtu >= 576) &&
  1666. (mtu <= card->info.max_mtu + 4096 - 32));
  1667. case QETH_CARD_TYPE_OSN:
  1668. case QETH_CARD_TYPE_UNKNOWN:
  1669. default:
  1670. return 1;
  1671. }
  1672. }
  1673. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1674. unsigned long data)
  1675. {
  1676. __u16 mtu, framesize;
  1677. __u16 len;
  1678. __u8 link_type;
  1679. struct qeth_cmd_buffer *iob;
  1680. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1681. iob = (struct qeth_cmd_buffer *) data;
  1682. memcpy(&card->token.ulp_filter_r,
  1683. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1684. QETH_MPC_TOKEN_LENGTH);
  1685. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1686. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1687. mtu = qeth_get_mtu_outof_framesize(framesize);
  1688. if (!mtu) {
  1689. iob->rc = -EINVAL;
  1690. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1691. return 0;
  1692. }
  1693. card->info.max_mtu = mtu;
  1694. card->info.initial_mtu = mtu;
  1695. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1696. } else {
  1697. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1698. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1699. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1700. }
  1701. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1702. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1703. memcpy(&link_type,
  1704. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1705. card->info.link_type = link_type;
  1706. } else
  1707. card->info.link_type = 0;
  1708. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1709. return 0;
  1710. }
  1711. static int qeth_ulp_enable(struct qeth_card *card)
  1712. {
  1713. int rc;
  1714. char prot_type;
  1715. struct qeth_cmd_buffer *iob;
  1716. /*FIXME: trace view callbacks*/
  1717. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1718. iob = qeth_wait_for_buffer(&card->write);
  1719. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1720. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1721. (__u8) card->info.portno;
  1722. if (card->options.layer2)
  1723. if (card->info.type == QETH_CARD_TYPE_OSN)
  1724. prot_type = QETH_PROT_OSN2;
  1725. else
  1726. prot_type = QETH_PROT_LAYER2;
  1727. else
  1728. prot_type = QETH_PROT_TCPIP;
  1729. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1730. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1731. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1732. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1733. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1734. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1735. card->info.portname, 9);
  1736. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1737. qeth_ulp_enable_cb, NULL);
  1738. return rc;
  1739. }
  1740. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1741. unsigned long data)
  1742. {
  1743. struct qeth_cmd_buffer *iob;
  1744. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1745. iob = (struct qeth_cmd_buffer *) data;
  1746. memcpy(&card->token.ulp_connection_r,
  1747. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1748. QETH_MPC_TOKEN_LENGTH);
  1749. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1750. return 0;
  1751. }
  1752. static int qeth_ulp_setup(struct qeth_card *card)
  1753. {
  1754. int rc;
  1755. __u16 temp;
  1756. struct qeth_cmd_buffer *iob;
  1757. struct ccw_dev_id dev_id;
  1758. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1759. iob = qeth_wait_for_buffer(&card->write);
  1760. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1761. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1762. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1763. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1764. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1765. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1766. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1767. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1768. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1769. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1770. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1771. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1772. qeth_ulp_setup_cb, NULL);
  1773. return rc;
  1774. }
  1775. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1776. {
  1777. int i, j;
  1778. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1779. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1780. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1781. return 0;
  1782. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1783. GFP_KERNEL);
  1784. if (!card->qdio.in_q)
  1785. goto out_nomem;
  1786. QETH_DBF_TEXT(SETUP, 2, "inq");
  1787. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1788. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1789. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1790. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1791. card->qdio.in_q->bufs[i].buffer =
  1792. &card->qdio.in_q->qdio_bufs[i];
  1793. /* inbound buffer pool */
  1794. if (qeth_alloc_buffer_pool(card))
  1795. goto out_freeinq;
  1796. /* outbound */
  1797. card->qdio.out_qs =
  1798. kmalloc(card->qdio.no_out_queues *
  1799. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1800. if (!card->qdio.out_qs)
  1801. goto out_freepool;
  1802. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1803. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1804. GFP_KERNEL);
  1805. if (!card->qdio.out_qs[i])
  1806. goto out_freeoutq;
  1807. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1808. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1809. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1810. card->qdio.out_qs[i]->queue_no = i;
  1811. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1812. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1813. card->qdio.out_qs[i]->bufs[j].buffer =
  1814. &card->qdio.out_qs[i]->qdio_bufs[j];
  1815. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1816. skb_list);
  1817. lockdep_set_class(
  1818. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1819. &qdio_out_skb_queue_key);
  1820. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1821. }
  1822. }
  1823. return 0;
  1824. out_freeoutq:
  1825. while (i > 0)
  1826. kfree(card->qdio.out_qs[--i]);
  1827. kfree(card->qdio.out_qs);
  1828. card->qdio.out_qs = NULL;
  1829. out_freepool:
  1830. qeth_free_buffer_pool(card);
  1831. out_freeinq:
  1832. kfree(card->qdio.in_q);
  1833. card->qdio.in_q = NULL;
  1834. out_nomem:
  1835. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1836. return -ENOMEM;
  1837. }
  1838. static void qeth_create_qib_param_field(struct qeth_card *card,
  1839. char *param_field)
  1840. {
  1841. param_field[0] = _ascebc['P'];
  1842. param_field[1] = _ascebc['C'];
  1843. param_field[2] = _ascebc['I'];
  1844. param_field[3] = _ascebc['T'];
  1845. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1846. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1847. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1848. }
  1849. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1850. char *param_field)
  1851. {
  1852. param_field[16] = _ascebc['B'];
  1853. param_field[17] = _ascebc['L'];
  1854. param_field[18] = _ascebc['K'];
  1855. param_field[19] = _ascebc['T'];
  1856. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1857. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1858. *((unsigned int *) (&param_field[28])) =
  1859. card->info.blkt.inter_packet_jumbo;
  1860. }
  1861. static int qeth_qdio_activate(struct qeth_card *card)
  1862. {
  1863. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1864. return qdio_activate(CARD_DDEV(card));
  1865. }
  1866. static int qeth_dm_act(struct qeth_card *card)
  1867. {
  1868. int rc;
  1869. struct qeth_cmd_buffer *iob;
  1870. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1871. iob = qeth_wait_for_buffer(&card->write);
  1872. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1873. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1874. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1875. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1876. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1877. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1878. return rc;
  1879. }
  1880. static int qeth_mpc_initialize(struct qeth_card *card)
  1881. {
  1882. int rc;
  1883. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1884. rc = qeth_issue_next_read(card);
  1885. if (rc) {
  1886. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1887. return rc;
  1888. }
  1889. rc = qeth_cm_enable(card);
  1890. if (rc) {
  1891. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1892. goto out_qdio;
  1893. }
  1894. rc = qeth_cm_setup(card);
  1895. if (rc) {
  1896. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1897. goto out_qdio;
  1898. }
  1899. rc = qeth_ulp_enable(card);
  1900. if (rc) {
  1901. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1902. goto out_qdio;
  1903. }
  1904. rc = qeth_ulp_setup(card);
  1905. if (rc) {
  1906. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1907. goto out_qdio;
  1908. }
  1909. rc = qeth_alloc_qdio_buffers(card);
  1910. if (rc) {
  1911. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1912. goto out_qdio;
  1913. }
  1914. rc = qeth_qdio_establish(card);
  1915. if (rc) {
  1916. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1917. qeth_free_qdio_buffers(card);
  1918. goto out_qdio;
  1919. }
  1920. rc = qeth_qdio_activate(card);
  1921. if (rc) {
  1922. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1923. goto out_qdio;
  1924. }
  1925. rc = qeth_dm_act(card);
  1926. if (rc) {
  1927. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1928. goto out_qdio;
  1929. }
  1930. return 0;
  1931. out_qdio:
  1932. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1933. return rc;
  1934. }
  1935. static void qeth_print_status_with_portname(struct qeth_card *card)
  1936. {
  1937. char dbf_text[15];
  1938. int i;
  1939. sprintf(dbf_text, "%s", card->info.portname + 1);
  1940. for (i = 0; i < 8; i++)
  1941. dbf_text[i] =
  1942. (char) _ebcasc[(__u8) dbf_text[i]];
  1943. dbf_text[8] = 0;
  1944. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1945. "with link type %s (portname: %s)\n",
  1946. CARD_RDEV_ID(card),
  1947. CARD_WDEV_ID(card),
  1948. CARD_DDEV_ID(card),
  1949. qeth_get_cardname(card),
  1950. (card->info.mcl_level[0]) ? " (level: " : "",
  1951. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1952. (card->info.mcl_level[0]) ? ")" : "",
  1953. qeth_get_cardname_short(card),
  1954. dbf_text);
  1955. }
  1956. static void qeth_print_status_no_portname(struct qeth_card *card)
  1957. {
  1958. if (card->info.portname[0])
  1959. PRINT_INFO("Device %s/%s/%s is a%s "
  1960. "card%s%s%s\nwith link type %s "
  1961. "(no portname needed by interface).\n",
  1962. CARD_RDEV_ID(card),
  1963. CARD_WDEV_ID(card),
  1964. CARD_DDEV_ID(card),
  1965. qeth_get_cardname(card),
  1966. (card->info.mcl_level[0]) ? " (level: " : "",
  1967. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1968. (card->info.mcl_level[0]) ? ")" : "",
  1969. qeth_get_cardname_short(card));
  1970. else
  1971. PRINT_INFO("Device %s/%s/%s is a%s "
  1972. "card%s%s%s\nwith link type %s.\n",
  1973. CARD_RDEV_ID(card),
  1974. CARD_WDEV_ID(card),
  1975. CARD_DDEV_ID(card),
  1976. qeth_get_cardname(card),
  1977. (card->info.mcl_level[0]) ? " (level: " : "",
  1978. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1979. (card->info.mcl_level[0]) ? ")" : "",
  1980. qeth_get_cardname_short(card));
  1981. }
  1982. void qeth_print_status_message(struct qeth_card *card)
  1983. {
  1984. switch (card->info.type) {
  1985. case QETH_CARD_TYPE_OSAE:
  1986. /* VM will use a non-zero first character
  1987. * to indicate a HiperSockets like reporting
  1988. * of the level OSA sets the first character to zero
  1989. * */
  1990. if (!card->info.mcl_level[0]) {
  1991. sprintf(card->info.mcl_level, "%02x%02x",
  1992. card->info.mcl_level[2],
  1993. card->info.mcl_level[3]);
  1994. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  1995. break;
  1996. }
  1997. /* fallthrough */
  1998. case QETH_CARD_TYPE_IQD:
  1999. if (card->info.guestlan) {
  2000. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2001. card->info.mcl_level[0]];
  2002. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2003. card->info.mcl_level[1]];
  2004. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2005. card->info.mcl_level[2]];
  2006. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2007. card->info.mcl_level[3]];
  2008. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2009. }
  2010. break;
  2011. default:
  2012. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2013. }
  2014. if (card->info.portname_required)
  2015. qeth_print_status_with_portname(card);
  2016. else
  2017. qeth_print_status_no_portname(card);
  2018. }
  2019. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2020. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2021. {
  2022. struct qeth_buffer_pool_entry *entry;
  2023. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2024. list_for_each_entry(entry,
  2025. &card->qdio.init_pool.entry_list, init_list) {
  2026. qeth_put_buffer_pool_entry(card, entry);
  2027. }
  2028. }
  2029. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2030. struct qeth_card *card)
  2031. {
  2032. struct list_head *plh;
  2033. struct qeth_buffer_pool_entry *entry;
  2034. int i, free;
  2035. struct page *page;
  2036. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2037. return NULL;
  2038. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2039. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2040. free = 1;
  2041. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2042. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2043. free = 0;
  2044. break;
  2045. }
  2046. }
  2047. if (free) {
  2048. list_del_init(&entry->list);
  2049. return entry;
  2050. }
  2051. }
  2052. /* no free buffer in pool so take first one and swap pages */
  2053. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2054. struct qeth_buffer_pool_entry, list);
  2055. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2056. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2057. page = alloc_page(GFP_ATOMIC);
  2058. if (!page) {
  2059. return NULL;
  2060. } else {
  2061. free_page((unsigned long)entry->elements[i]);
  2062. entry->elements[i] = page_address(page);
  2063. if (card->options.performance_stats)
  2064. card->perf_stats.sg_alloc_page_rx++;
  2065. }
  2066. }
  2067. }
  2068. list_del_init(&entry->list);
  2069. return entry;
  2070. }
  2071. static int qeth_init_input_buffer(struct qeth_card *card,
  2072. struct qeth_qdio_buffer *buf)
  2073. {
  2074. struct qeth_buffer_pool_entry *pool_entry;
  2075. int i;
  2076. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2077. if (!pool_entry)
  2078. return 1;
  2079. /*
  2080. * since the buffer is accessed only from the input_tasklet
  2081. * there shouldn't be a need to synchronize; also, since we use
  2082. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2083. * buffers
  2084. */
  2085. BUG_ON(!pool_entry);
  2086. buf->pool_entry = pool_entry;
  2087. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2088. buf->buffer->element[i].length = PAGE_SIZE;
  2089. buf->buffer->element[i].addr = pool_entry->elements[i];
  2090. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2091. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2092. else
  2093. buf->buffer->element[i].flags = 0;
  2094. }
  2095. return 0;
  2096. }
  2097. int qeth_init_qdio_queues(struct qeth_card *card)
  2098. {
  2099. int i, j;
  2100. int rc;
  2101. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2102. /* inbound queue */
  2103. memset(card->qdio.in_q->qdio_bufs, 0,
  2104. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2105. qeth_initialize_working_pool_list(card);
  2106. /*give only as many buffers to hardware as we have buffer pool entries*/
  2107. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2108. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2109. card->qdio.in_q->next_buf_to_init =
  2110. card->qdio.in_buf_pool.buf_count - 1;
  2111. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2112. card->qdio.in_buf_pool.buf_count - 1);
  2113. if (rc) {
  2114. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2115. return rc;
  2116. }
  2117. /* outbound queue */
  2118. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2119. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2120. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2121. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2122. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2123. &card->qdio.out_qs[i]->bufs[j]);
  2124. }
  2125. card->qdio.out_qs[i]->card = card;
  2126. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2127. card->qdio.out_qs[i]->do_pack = 0;
  2128. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2129. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2130. atomic_set(&card->qdio.out_qs[i]->state,
  2131. QETH_OUT_Q_UNLOCKED);
  2132. }
  2133. return 0;
  2134. }
  2135. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2136. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2137. {
  2138. switch (link_type) {
  2139. case QETH_LINK_TYPE_HSTR:
  2140. return 2;
  2141. default:
  2142. return 1;
  2143. }
  2144. }
  2145. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2146. struct qeth_ipa_cmd *cmd, __u8 command,
  2147. enum qeth_prot_versions prot)
  2148. {
  2149. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2150. cmd->hdr.command = command;
  2151. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2152. cmd->hdr.seqno = card->seqno.ipa;
  2153. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2154. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2155. if (card->options.layer2)
  2156. cmd->hdr.prim_version_no = 2;
  2157. else
  2158. cmd->hdr.prim_version_no = 1;
  2159. cmd->hdr.param_count = 1;
  2160. cmd->hdr.prot_version = prot;
  2161. cmd->hdr.ipa_supported = 0;
  2162. cmd->hdr.ipa_enabled = 0;
  2163. }
  2164. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2165. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2166. {
  2167. struct qeth_cmd_buffer *iob;
  2168. struct qeth_ipa_cmd *cmd;
  2169. iob = qeth_wait_for_buffer(&card->write);
  2170. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2171. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2172. return iob;
  2173. }
  2174. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2175. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2176. char prot_type)
  2177. {
  2178. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2179. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2180. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2181. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2182. }
  2183. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2184. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2185. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2186. unsigned long),
  2187. void *reply_param)
  2188. {
  2189. int rc;
  2190. char prot_type;
  2191. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2192. if (card->options.layer2)
  2193. if (card->info.type == QETH_CARD_TYPE_OSN)
  2194. prot_type = QETH_PROT_OSN2;
  2195. else
  2196. prot_type = QETH_PROT_LAYER2;
  2197. else
  2198. prot_type = QETH_PROT_TCPIP;
  2199. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2200. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2201. iob, reply_cb, reply_param);
  2202. return rc;
  2203. }
  2204. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2205. static int qeth_send_startstoplan(struct qeth_card *card,
  2206. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2207. {
  2208. int rc;
  2209. struct qeth_cmd_buffer *iob;
  2210. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2211. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2212. return rc;
  2213. }
  2214. int qeth_send_startlan(struct qeth_card *card)
  2215. {
  2216. int rc;
  2217. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2218. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2219. return rc;
  2220. }
  2221. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2222. int qeth_send_stoplan(struct qeth_card *card)
  2223. {
  2224. int rc = 0;
  2225. /*
  2226. * TODO: according to the IPA format document page 14,
  2227. * TCP/IP (we!) never issue a STOPLAN
  2228. * is this right ?!?
  2229. */
  2230. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2231. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2232. return rc;
  2233. }
  2234. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2235. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2236. struct qeth_reply *reply, unsigned long data)
  2237. {
  2238. struct qeth_ipa_cmd *cmd;
  2239. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2240. cmd = (struct qeth_ipa_cmd *) data;
  2241. if (cmd->hdr.return_code == 0)
  2242. cmd->hdr.return_code =
  2243. cmd->data.setadapterparms.hdr.return_code;
  2244. return 0;
  2245. }
  2246. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2247. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2248. struct qeth_reply *reply, unsigned long data)
  2249. {
  2250. struct qeth_ipa_cmd *cmd;
  2251. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2252. cmd = (struct qeth_ipa_cmd *) data;
  2253. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2254. card->info.link_type =
  2255. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2256. card->options.adp.supported_funcs =
  2257. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2258. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2259. }
  2260. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2261. __u32 command, __u32 cmdlen)
  2262. {
  2263. struct qeth_cmd_buffer *iob;
  2264. struct qeth_ipa_cmd *cmd;
  2265. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2266. QETH_PROT_IPV4);
  2267. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2268. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2269. cmd->data.setadapterparms.hdr.command_code = command;
  2270. cmd->data.setadapterparms.hdr.used_total = 1;
  2271. cmd->data.setadapterparms.hdr.seq_no = 1;
  2272. return iob;
  2273. }
  2274. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2275. int qeth_query_setadapterparms(struct qeth_card *card)
  2276. {
  2277. int rc;
  2278. struct qeth_cmd_buffer *iob;
  2279. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2280. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2281. sizeof(struct qeth_ipacmd_setadpparms));
  2282. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2283. return rc;
  2284. }
  2285. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2286. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2287. const char *dbftext)
  2288. {
  2289. if (qdio_error) {
  2290. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2291. QETH_DBF_TEXT(QERR, 2, dbftext);
  2292. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2293. buf->element[15].flags & 0xff);
  2294. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2295. buf->element[14].flags & 0xff);
  2296. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2297. return 1;
  2298. }
  2299. return 0;
  2300. }
  2301. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2302. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2303. {
  2304. struct qeth_qdio_q *queue = card->qdio.in_q;
  2305. int count;
  2306. int i;
  2307. int rc;
  2308. int newcount = 0;
  2309. count = (index < queue->next_buf_to_init)?
  2310. card->qdio.in_buf_pool.buf_count -
  2311. (queue->next_buf_to_init - index) :
  2312. card->qdio.in_buf_pool.buf_count -
  2313. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2314. /* only requeue at a certain threshold to avoid SIGAs */
  2315. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2316. for (i = queue->next_buf_to_init;
  2317. i < queue->next_buf_to_init + count; ++i) {
  2318. if (qeth_init_input_buffer(card,
  2319. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2320. break;
  2321. } else {
  2322. newcount++;
  2323. }
  2324. }
  2325. if (newcount < count) {
  2326. /* we are in memory shortage so we switch back to
  2327. traditional skb allocation and drop packages */
  2328. atomic_set(&card->force_alloc_skb, 3);
  2329. count = newcount;
  2330. } else {
  2331. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2332. }
  2333. /*
  2334. * according to old code it should be avoided to requeue all
  2335. * 128 buffers in order to benefit from PCI avoidance.
  2336. * this function keeps at least one buffer (the buffer at
  2337. * 'index') un-requeued -> this buffer is the first buffer that
  2338. * will be requeued the next time
  2339. */
  2340. if (card->options.performance_stats) {
  2341. card->perf_stats.inbound_do_qdio_cnt++;
  2342. card->perf_stats.inbound_do_qdio_start_time =
  2343. qeth_get_micros();
  2344. }
  2345. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2346. queue->next_buf_to_init, count);
  2347. if (card->options.performance_stats)
  2348. card->perf_stats.inbound_do_qdio_time +=
  2349. qeth_get_micros() -
  2350. card->perf_stats.inbound_do_qdio_start_time;
  2351. if (rc) {
  2352. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2353. "return %i (device %s).\n",
  2354. rc, CARD_DDEV_ID(card));
  2355. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2356. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2357. }
  2358. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2359. QDIO_MAX_BUFFERS_PER_Q;
  2360. }
  2361. }
  2362. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2363. static int qeth_handle_send_error(struct qeth_card *card,
  2364. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2365. {
  2366. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2367. int cc = qdio_err & 3;
  2368. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2369. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2370. switch (cc) {
  2371. case 0:
  2372. if (qdio_err) {
  2373. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2374. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2375. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2376. (u16)qdio_err, (u8)sbalf15);
  2377. return QETH_SEND_ERROR_LINK_FAILURE;
  2378. }
  2379. return QETH_SEND_ERROR_NONE;
  2380. case 2:
  2381. if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
  2382. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2383. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2384. return QETH_SEND_ERROR_KICK_IT;
  2385. }
  2386. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2387. return QETH_SEND_ERROR_RETRY;
  2388. return QETH_SEND_ERROR_LINK_FAILURE;
  2389. /* look at qdio_error and sbalf 15 */
  2390. case 1:
  2391. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2392. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2393. return QETH_SEND_ERROR_LINK_FAILURE;
  2394. case 3:
  2395. default:
  2396. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2397. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2398. return QETH_SEND_ERROR_KICK_IT;
  2399. }
  2400. }
  2401. /*
  2402. * Switched to packing state if the number of used buffers on a queue
  2403. * reaches a certain limit.
  2404. */
  2405. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2406. {
  2407. if (!queue->do_pack) {
  2408. if (atomic_read(&queue->used_buffers)
  2409. >= QETH_HIGH_WATERMARK_PACK){
  2410. /* switch non-PACKING -> PACKING */
  2411. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2412. if (queue->card->options.performance_stats)
  2413. queue->card->perf_stats.sc_dp_p++;
  2414. queue->do_pack = 1;
  2415. }
  2416. }
  2417. }
  2418. /*
  2419. * Switches from packing to non-packing mode. If there is a packing
  2420. * buffer on the queue this buffer will be prepared to be flushed.
  2421. * In that case 1 is returned to inform the caller. If no buffer
  2422. * has to be flushed, zero is returned.
  2423. */
  2424. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2425. {
  2426. struct qeth_qdio_out_buffer *buffer;
  2427. int flush_count = 0;
  2428. if (queue->do_pack) {
  2429. if (atomic_read(&queue->used_buffers)
  2430. <= QETH_LOW_WATERMARK_PACK) {
  2431. /* switch PACKING -> non-PACKING */
  2432. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2433. if (queue->card->options.performance_stats)
  2434. queue->card->perf_stats.sc_p_dp++;
  2435. queue->do_pack = 0;
  2436. /* flush packing buffers */
  2437. buffer = &queue->bufs[queue->next_buf_to_fill];
  2438. if ((atomic_read(&buffer->state) ==
  2439. QETH_QDIO_BUF_EMPTY) &&
  2440. (buffer->next_element_to_fill > 0)) {
  2441. atomic_set(&buffer->state,
  2442. QETH_QDIO_BUF_PRIMED);
  2443. flush_count++;
  2444. queue->next_buf_to_fill =
  2445. (queue->next_buf_to_fill + 1) %
  2446. QDIO_MAX_BUFFERS_PER_Q;
  2447. }
  2448. }
  2449. }
  2450. return flush_count;
  2451. }
  2452. /*
  2453. * Called to flush a packing buffer if no more pci flags are on the queue.
  2454. * Checks if there is a packing buffer and prepares it to be flushed.
  2455. * In that case returns 1, otherwise zero.
  2456. */
  2457. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2458. {
  2459. struct qeth_qdio_out_buffer *buffer;
  2460. buffer = &queue->bufs[queue->next_buf_to_fill];
  2461. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2462. (buffer->next_element_to_fill > 0)) {
  2463. /* it's a packing buffer */
  2464. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2465. queue->next_buf_to_fill =
  2466. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2467. return 1;
  2468. }
  2469. return 0;
  2470. }
  2471. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2472. int count)
  2473. {
  2474. struct qeth_qdio_out_buffer *buf;
  2475. int rc;
  2476. int i;
  2477. unsigned int qdio_flags;
  2478. for (i = index; i < index + count; ++i) {
  2479. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2480. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2481. SBAL_FLAGS_LAST_ENTRY;
  2482. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2483. continue;
  2484. if (!queue->do_pack) {
  2485. if ((atomic_read(&queue->used_buffers) >=
  2486. (QETH_HIGH_WATERMARK_PACK -
  2487. QETH_WATERMARK_PACK_FUZZ)) &&
  2488. !atomic_read(&queue->set_pci_flags_count)) {
  2489. /* it's likely that we'll go to packing
  2490. * mode soon */
  2491. atomic_inc(&queue->set_pci_flags_count);
  2492. buf->buffer->element[0].flags |= 0x40;
  2493. }
  2494. } else {
  2495. if (!atomic_read(&queue->set_pci_flags_count)) {
  2496. /*
  2497. * there's no outstanding PCI any more, so we
  2498. * have to request a PCI to be sure the the PCI
  2499. * will wake at some time in the future then we
  2500. * can flush packed buffers that might still be
  2501. * hanging around, which can happen if no
  2502. * further send was requested by the stack
  2503. */
  2504. atomic_inc(&queue->set_pci_flags_count);
  2505. buf->buffer->element[0].flags |= 0x40;
  2506. }
  2507. }
  2508. }
  2509. queue->card->dev->trans_start = jiffies;
  2510. if (queue->card->options.performance_stats) {
  2511. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2512. queue->card->perf_stats.outbound_do_qdio_start_time =
  2513. qeth_get_micros();
  2514. }
  2515. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2516. if (atomic_read(&queue->set_pci_flags_count))
  2517. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2518. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2519. queue->queue_no, index, count);
  2520. if (queue->card->options.performance_stats)
  2521. queue->card->perf_stats.outbound_do_qdio_time +=
  2522. qeth_get_micros() -
  2523. queue->card->perf_stats.outbound_do_qdio_start_time;
  2524. if (rc) {
  2525. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2526. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2527. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2528. queue->card->stats.tx_errors += count;
  2529. /* this must not happen under normal circumstances. if it
  2530. * happens something is really wrong -> recover */
  2531. qeth_schedule_recovery(queue->card);
  2532. return;
  2533. }
  2534. atomic_add(count, &queue->used_buffers);
  2535. if (queue->card->options.performance_stats)
  2536. queue->card->perf_stats.bufs_sent += count;
  2537. }
  2538. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2539. {
  2540. int index;
  2541. int flush_cnt = 0;
  2542. int q_was_packing = 0;
  2543. /*
  2544. * check if weed have to switch to non-packing mode or if
  2545. * we have to get a pci flag out on the queue
  2546. */
  2547. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2548. !atomic_read(&queue->set_pci_flags_count)) {
  2549. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2550. QETH_OUT_Q_UNLOCKED) {
  2551. /*
  2552. * If we get in here, there was no action in
  2553. * do_send_packet. So, we check if there is a
  2554. * packing buffer to be flushed here.
  2555. */
  2556. netif_stop_queue(queue->card->dev);
  2557. index = queue->next_buf_to_fill;
  2558. q_was_packing = queue->do_pack;
  2559. /* queue->do_pack may change */
  2560. barrier();
  2561. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2562. if (!flush_cnt &&
  2563. !atomic_read(&queue->set_pci_flags_count))
  2564. flush_cnt +=
  2565. qeth_flush_buffers_on_no_pci(queue);
  2566. if (queue->card->options.performance_stats &&
  2567. q_was_packing)
  2568. queue->card->perf_stats.bufs_sent_pack +=
  2569. flush_cnt;
  2570. if (flush_cnt)
  2571. qeth_flush_buffers(queue, index, flush_cnt);
  2572. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2573. }
  2574. }
  2575. }
  2576. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2577. unsigned int qdio_error, int __queue, int first_element,
  2578. int count, unsigned long card_ptr)
  2579. {
  2580. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2581. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2582. struct qeth_qdio_out_buffer *buffer;
  2583. int i;
  2584. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2585. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2586. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2587. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2588. netif_stop_queue(card->dev);
  2589. qeth_schedule_recovery(card);
  2590. return;
  2591. }
  2592. if (card->options.performance_stats) {
  2593. card->perf_stats.outbound_handler_cnt++;
  2594. card->perf_stats.outbound_handler_start_time =
  2595. qeth_get_micros();
  2596. }
  2597. for (i = first_element; i < (first_element + count); ++i) {
  2598. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2599. /*we only handle the KICK_IT error by doing a recovery */
  2600. if (qeth_handle_send_error(card, buffer, qdio_error)
  2601. == QETH_SEND_ERROR_KICK_IT){
  2602. netif_stop_queue(card->dev);
  2603. qeth_schedule_recovery(card);
  2604. return;
  2605. }
  2606. qeth_clear_output_buffer(queue, buffer);
  2607. }
  2608. atomic_sub(count, &queue->used_buffers);
  2609. /* check if we need to do something on this outbound queue */
  2610. if (card->info.type != QETH_CARD_TYPE_IQD)
  2611. qeth_check_outbound_queue(queue);
  2612. netif_wake_queue(queue->card->dev);
  2613. if (card->options.performance_stats)
  2614. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2615. card->perf_stats.outbound_handler_start_time;
  2616. }
  2617. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2618. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2619. {
  2620. int cast_type = RTN_UNSPEC;
  2621. if (card->info.type == QETH_CARD_TYPE_OSN)
  2622. return cast_type;
  2623. if (skb->dst && skb->dst->neighbour) {
  2624. cast_type = skb->dst->neighbour->type;
  2625. if ((cast_type == RTN_BROADCAST) ||
  2626. (cast_type == RTN_MULTICAST) ||
  2627. (cast_type == RTN_ANYCAST))
  2628. return cast_type;
  2629. else
  2630. return RTN_UNSPEC;
  2631. }
  2632. /* try something else */
  2633. if (skb->protocol == ETH_P_IPV6)
  2634. return (skb_network_header(skb)[24] == 0xff) ?
  2635. RTN_MULTICAST : 0;
  2636. else if (skb->protocol == ETH_P_IP)
  2637. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2638. RTN_MULTICAST : 0;
  2639. /* ... */
  2640. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2641. return RTN_BROADCAST;
  2642. else {
  2643. u16 hdr_mac;
  2644. hdr_mac = *((u16 *)skb->data);
  2645. /* tr multicast? */
  2646. switch (card->info.link_type) {
  2647. case QETH_LINK_TYPE_HSTR:
  2648. case QETH_LINK_TYPE_LANE_TR:
  2649. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2650. (hdr_mac == QETH_TR_MAC_C))
  2651. return RTN_MULTICAST;
  2652. break;
  2653. /* eth or so multicast? */
  2654. default:
  2655. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2656. (hdr_mac == QETH_ETH_MAC_V6))
  2657. return RTN_MULTICAST;
  2658. }
  2659. }
  2660. return cast_type;
  2661. }
  2662. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2663. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2664. int ipv, int cast_type)
  2665. {
  2666. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2667. return card->qdio.default_out_queue;
  2668. switch (card->qdio.no_out_queues) {
  2669. case 4:
  2670. if (cast_type && card->info.is_multicast_different)
  2671. return card->info.is_multicast_different &
  2672. (card->qdio.no_out_queues - 1);
  2673. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2674. const u8 tos = ip_hdr(skb)->tos;
  2675. if (card->qdio.do_prio_queueing ==
  2676. QETH_PRIO_Q_ING_TOS) {
  2677. if (tos & IP_TOS_NOTIMPORTANT)
  2678. return 3;
  2679. if (tos & IP_TOS_HIGHRELIABILITY)
  2680. return 2;
  2681. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2682. return 1;
  2683. if (tos & IP_TOS_LOWDELAY)
  2684. return 0;
  2685. }
  2686. if (card->qdio.do_prio_queueing ==
  2687. QETH_PRIO_Q_ING_PREC)
  2688. return 3 - (tos >> 6);
  2689. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2690. /* TODO: IPv6!!! */
  2691. }
  2692. return card->qdio.default_out_queue;
  2693. case 1: /* fallthrough for single-out-queue 1920-device */
  2694. default:
  2695. return card->qdio.default_out_queue;
  2696. }
  2697. }
  2698. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2699. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2700. struct sk_buff *skb, int elems)
  2701. {
  2702. int elements_needed = 0;
  2703. if (skb_shinfo(skb)->nr_frags > 0)
  2704. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2705. if (elements_needed == 0)
  2706. elements_needed = 1 + (((((unsigned long) skb->data) %
  2707. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2708. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2709. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2710. "(Number=%d / Length=%d). Discarded.\n",
  2711. (elements_needed+elems), skb->len);
  2712. return 0;
  2713. }
  2714. return elements_needed;
  2715. }
  2716. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2717. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2718. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2719. int offset)
  2720. {
  2721. int length = skb->len - offset;
  2722. int length_here;
  2723. int element;
  2724. char *data;
  2725. int first_lap ;
  2726. element = *next_element_to_fill;
  2727. data = skb->data;
  2728. first_lap = (is_tso == 0 ? 1 : 0);
  2729. if (offset >= 0) {
  2730. data = skb->data + offset;
  2731. first_lap = 0;
  2732. }
  2733. while (length > 0) {
  2734. /* length_here is the remaining amount of data in this page */
  2735. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2736. if (length < length_here)
  2737. length_here = length;
  2738. buffer->element[element].addr = data;
  2739. buffer->element[element].length = length_here;
  2740. length -= length_here;
  2741. if (!length) {
  2742. if (first_lap)
  2743. buffer->element[element].flags = 0;
  2744. else
  2745. buffer->element[element].flags =
  2746. SBAL_FLAGS_LAST_FRAG;
  2747. } else {
  2748. if (first_lap)
  2749. buffer->element[element].flags =
  2750. SBAL_FLAGS_FIRST_FRAG;
  2751. else
  2752. buffer->element[element].flags =
  2753. SBAL_FLAGS_MIDDLE_FRAG;
  2754. }
  2755. data += length_here;
  2756. element++;
  2757. first_lap = 0;
  2758. }
  2759. *next_element_to_fill = element;
  2760. }
  2761. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2762. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2763. struct qeth_hdr *hdr, int offset, int hd_len)
  2764. {
  2765. struct qdio_buffer *buffer;
  2766. int flush_cnt = 0, hdr_len, large_send = 0;
  2767. buffer = buf->buffer;
  2768. atomic_inc(&skb->users);
  2769. skb_queue_tail(&buf->skb_list, skb);
  2770. /*check first on TSO ....*/
  2771. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2772. int element = buf->next_element_to_fill;
  2773. hdr_len = sizeof(struct qeth_hdr_tso) +
  2774. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2775. /*fill first buffer entry only with header information */
  2776. buffer->element[element].addr = skb->data;
  2777. buffer->element[element].length = hdr_len;
  2778. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2779. buf->next_element_to_fill++;
  2780. skb->data += hdr_len;
  2781. skb->len -= hdr_len;
  2782. large_send = 1;
  2783. }
  2784. if (offset >= 0) {
  2785. int element = buf->next_element_to_fill;
  2786. buffer->element[element].addr = hdr;
  2787. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2788. hd_len;
  2789. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2790. buf->is_header[element] = 1;
  2791. buf->next_element_to_fill++;
  2792. }
  2793. if (skb_shinfo(skb)->nr_frags == 0)
  2794. __qeth_fill_buffer(skb, buffer, large_send,
  2795. (int *)&buf->next_element_to_fill, offset);
  2796. else
  2797. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2798. (int *)&buf->next_element_to_fill);
  2799. if (!queue->do_pack) {
  2800. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2801. /* set state to PRIMED -> will be flushed */
  2802. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2803. flush_cnt = 1;
  2804. } else {
  2805. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2806. if (queue->card->options.performance_stats)
  2807. queue->card->perf_stats.skbs_sent_pack++;
  2808. if (buf->next_element_to_fill >=
  2809. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2810. /*
  2811. * packed buffer if full -> set state PRIMED
  2812. * -> will be flushed
  2813. */
  2814. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2815. flush_cnt = 1;
  2816. }
  2817. }
  2818. return flush_cnt;
  2819. }
  2820. int qeth_do_send_packet_fast(struct qeth_card *card,
  2821. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2822. struct qeth_hdr *hdr, int elements_needed,
  2823. struct qeth_eddp_context *ctx, int offset, int hd_len)
  2824. {
  2825. struct qeth_qdio_out_buffer *buffer;
  2826. int buffers_needed = 0;
  2827. int flush_cnt = 0;
  2828. int index;
  2829. /* spin until we get the queue ... */
  2830. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2831. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2832. /* ... now we've got the queue */
  2833. index = queue->next_buf_to_fill;
  2834. buffer = &queue->bufs[queue->next_buf_to_fill];
  2835. /*
  2836. * check if buffer is empty to make sure that we do not 'overtake'
  2837. * ourselves and try to fill a buffer that is already primed
  2838. */
  2839. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2840. goto out;
  2841. if (ctx == NULL)
  2842. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2843. QDIO_MAX_BUFFERS_PER_Q;
  2844. else {
  2845. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2846. ctx);
  2847. if (buffers_needed < 0)
  2848. goto out;
  2849. queue->next_buf_to_fill =
  2850. (queue->next_buf_to_fill + buffers_needed) %
  2851. QDIO_MAX_BUFFERS_PER_Q;
  2852. }
  2853. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2854. if (ctx == NULL) {
  2855. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2856. qeth_flush_buffers(queue, index, 1);
  2857. } else {
  2858. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2859. WARN_ON(buffers_needed != flush_cnt);
  2860. qeth_flush_buffers(queue, index, flush_cnt);
  2861. }
  2862. return 0;
  2863. out:
  2864. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2865. return -EBUSY;
  2866. }
  2867. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2868. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2869. struct sk_buff *skb, struct qeth_hdr *hdr,
  2870. int elements_needed, struct qeth_eddp_context *ctx)
  2871. {
  2872. struct qeth_qdio_out_buffer *buffer;
  2873. int start_index;
  2874. int flush_count = 0;
  2875. int do_pack = 0;
  2876. int tmp;
  2877. int rc = 0;
  2878. /* spin until we get the queue ... */
  2879. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2880. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2881. start_index = queue->next_buf_to_fill;
  2882. buffer = &queue->bufs[queue->next_buf_to_fill];
  2883. /*
  2884. * check if buffer is empty to make sure that we do not 'overtake'
  2885. * ourselves and try to fill a buffer that is already primed
  2886. */
  2887. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2888. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2889. return -EBUSY;
  2890. }
  2891. /* check if we need to switch packing state of this queue */
  2892. qeth_switch_to_packing_if_needed(queue);
  2893. if (queue->do_pack) {
  2894. do_pack = 1;
  2895. if (ctx == NULL) {
  2896. /* does packet fit in current buffer? */
  2897. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2898. buffer->next_element_to_fill) < elements_needed) {
  2899. /* ... no -> set state PRIMED */
  2900. atomic_set(&buffer->state,
  2901. QETH_QDIO_BUF_PRIMED);
  2902. flush_count++;
  2903. queue->next_buf_to_fill =
  2904. (queue->next_buf_to_fill + 1) %
  2905. QDIO_MAX_BUFFERS_PER_Q;
  2906. buffer = &queue->bufs[queue->next_buf_to_fill];
  2907. /* we did a step forward, so check buffer state
  2908. * again */
  2909. if (atomic_read(&buffer->state) !=
  2910. QETH_QDIO_BUF_EMPTY){
  2911. qeth_flush_buffers(queue, start_index,
  2912. flush_count);
  2913. atomic_set(&queue->state,
  2914. QETH_OUT_Q_UNLOCKED);
  2915. return -EBUSY;
  2916. }
  2917. }
  2918. } else {
  2919. /* check if we have enough elements (including following
  2920. * free buffers) to handle eddp context */
  2921. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2922. < 0) {
  2923. rc = -EBUSY;
  2924. goto out;
  2925. }
  2926. }
  2927. }
  2928. if (ctx == NULL)
  2929. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2930. else {
  2931. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2932. queue->next_buf_to_fill);
  2933. if (tmp < 0) {
  2934. rc = -EBUSY;
  2935. goto out;
  2936. }
  2937. }
  2938. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2939. QDIO_MAX_BUFFERS_PER_Q;
  2940. flush_count += tmp;
  2941. out:
  2942. if (flush_count)
  2943. qeth_flush_buffers(queue, start_index, flush_count);
  2944. else if (!atomic_read(&queue->set_pci_flags_count))
  2945. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2946. /*
  2947. * queue->state will go from LOCKED -> UNLOCKED or from
  2948. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2949. * (switch packing state or flush buffer to get another pci flag out).
  2950. * In that case we will enter this loop
  2951. */
  2952. while (atomic_dec_return(&queue->state)) {
  2953. flush_count = 0;
  2954. start_index = queue->next_buf_to_fill;
  2955. /* check if we can go back to non-packing state */
  2956. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2957. /*
  2958. * check if we need to flush a packing buffer to get a pci
  2959. * flag out on the queue
  2960. */
  2961. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2962. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2963. if (flush_count)
  2964. qeth_flush_buffers(queue, start_index, flush_count);
  2965. }
  2966. /* at this point the queue is UNLOCKED again */
  2967. if (queue->card->options.performance_stats && do_pack)
  2968. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2969. return rc;
  2970. }
  2971. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2972. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2973. struct qeth_reply *reply, unsigned long data)
  2974. {
  2975. struct qeth_ipa_cmd *cmd;
  2976. struct qeth_ipacmd_setadpparms *setparms;
  2977. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2978. cmd = (struct qeth_ipa_cmd *) data;
  2979. setparms = &(cmd->data.setadapterparms);
  2980. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2981. if (cmd->hdr.return_code) {
  2982. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2983. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2984. }
  2985. card->info.promisc_mode = setparms->data.mode;
  2986. return 0;
  2987. }
  2988. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2989. {
  2990. enum qeth_ipa_promisc_modes mode;
  2991. struct net_device *dev = card->dev;
  2992. struct qeth_cmd_buffer *iob;
  2993. struct qeth_ipa_cmd *cmd;
  2994. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2995. if (((dev->flags & IFF_PROMISC) &&
  2996. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2997. (!(dev->flags & IFF_PROMISC) &&
  2998. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2999. return;
  3000. mode = SET_PROMISC_MODE_OFF;
  3001. if (dev->flags & IFF_PROMISC)
  3002. mode = SET_PROMISC_MODE_ON;
  3003. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3004. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3005. sizeof(struct qeth_ipacmd_setadpparms));
  3006. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3007. cmd->data.setadapterparms.data.mode = mode;
  3008. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3009. }
  3010. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3011. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3012. {
  3013. struct qeth_card *card;
  3014. char dbf_text[15];
  3015. card = dev->ml_priv;
  3016. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3017. sprintf(dbf_text, "%8x", new_mtu);
  3018. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3019. if (new_mtu < 64)
  3020. return -EINVAL;
  3021. if (new_mtu > 65535)
  3022. return -EINVAL;
  3023. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3024. (!qeth_mtu_is_valid(card, new_mtu)))
  3025. return -EINVAL;
  3026. dev->mtu = new_mtu;
  3027. return 0;
  3028. }
  3029. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3030. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3031. {
  3032. struct qeth_card *card;
  3033. card = dev->ml_priv;
  3034. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3035. return &card->stats;
  3036. }
  3037. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3038. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3039. struct qeth_reply *reply, unsigned long data)
  3040. {
  3041. struct qeth_ipa_cmd *cmd;
  3042. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3043. cmd = (struct qeth_ipa_cmd *) data;
  3044. if (!card->options.layer2 ||
  3045. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3046. memcpy(card->dev->dev_addr,
  3047. &cmd->data.setadapterparms.data.change_addr.addr,
  3048. OSA_ADDR_LEN);
  3049. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3050. }
  3051. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3052. return 0;
  3053. }
  3054. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3055. {
  3056. int rc;
  3057. struct qeth_cmd_buffer *iob;
  3058. struct qeth_ipa_cmd *cmd;
  3059. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3060. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3061. sizeof(struct qeth_ipacmd_setadpparms));
  3062. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3063. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3064. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3065. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3066. card->dev->dev_addr, OSA_ADDR_LEN);
  3067. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3068. NULL);
  3069. return rc;
  3070. }
  3071. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3072. void qeth_tx_timeout(struct net_device *dev)
  3073. {
  3074. struct qeth_card *card;
  3075. card = dev->ml_priv;
  3076. card->stats.tx_errors++;
  3077. qeth_schedule_recovery(card);
  3078. }
  3079. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3080. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3081. {
  3082. struct qeth_card *card = dev->ml_priv;
  3083. int rc = 0;
  3084. switch (regnum) {
  3085. case MII_BMCR: /* Basic mode control register */
  3086. rc = BMCR_FULLDPLX;
  3087. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3088. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3089. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3090. rc |= BMCR_SPEED100;
  3091. break;
  3092. case MII_BMSR: /* Basic mode status register */
  3093. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3094. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3095. BMSR_100BASE4;
  3096. break;
  3097. case MII_PHYSID1: /* PHYS ID 1 */
  3098. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3099. dev->dev_addr[2];
  3100. rc = (rc >> 5) & 0xFFFF;
  3101. break;
  3102. case MII_PHYSID2: /* PHYS ID 2 */
  3103. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3104. break;
  3105. case MII_ADVERTISE: /* Advertisement control reg */
  3106. rc = ADVERTISE_ALL;
  3107. break;
  3108. case MII_LPA: /* Link partner ability reg */
  3109. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3110. LPA_100BASE4 | LPA_LPACK;
  3111. break;
  3112. case MII_EXPANSION: /* Expansion register */
  3113. break;
  3114. case MII_DCOUNTER: /* disconnect counter */
  3115. break;
  3116. case MII_FCSCOUNTER: /* false carrier counter */
  3117. break;
  3118. case MII_NWAYTEST: /* N-way auto-neg test register */
  3119. break;
  3120. case MII_RERRCOUNTER: /* rx error counter */
  3121. rc = card->stats.rx_errors;
  3122. break;
  3123. case MII_SREVISION: /* silicon revision */
  3124. break;
  3125. case MII_RESV1: /* reserved 1 */
  3126. break;
  3127. case MII_LBRERROR: /* loopback, rx, bypass error */
  3128. break;
  3129. case MII_PHYADDR: /* physical address */
  3130. break;
  3131. case MII_RESV2: /* reserved 2 */
  3132. break;
  3133. case MII_TPISTATUS: /* TPI status for 10mbps */
  3134. break;
  3135. case MII_NCONFIG: /* network interface config */
  3136. break;
  3137. default:
  3138. break;
  3139. }
  3140. return rc;
  3141. }
  3142. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3143. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3144. struct qeth_cmd_buffer *iob, int len,
  3145. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3146. unsigned long),
  3147. void *reply_param)
  3148. {
  3149. u16 s1, s2;
  3150. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3151. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3152. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3153. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3154. /* adjust PDU length fields in IPA_PDU_HEADER */
  3155. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3156. s2 = (u32) len;
  3157. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3158. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3159. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3160. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3161. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3162. reply_cb, reply_param);
  3163. }
  3164. static int qeth_snmp_command_cb(struct qeth_card *card,
  3165. struct qeth_reply *reply, unsigned long sdata)
  3166. {
  3167. struct qeth_ipa_cmd *cmd;
  3168. struct qeth_arp_query_info *qinfo;
  3169. struct qeth_snmp_cmd *snmp;
  3170. unsigned char *data;
  3171. __u16 data_len;
  3172. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3173. cmd = (struct qeth_ipa_cmd *) sdata;
  3174. data = (unsigned char *)((char *)cmd - reply->offset);
  3175. qinfo = (struct qeth_arp_query_info *) reply->param;
  3176. snmp = &cmd->data.setadapterparms.data.snmp;
  3177. if (cmd->hdr.return_code) {
  3178. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3179. return 0;
  3180. }
  3181. if (cmd->data.setadapterparms.hdr.return_code) {
  3182. cmd->hdr.return_code =
  3183. cmd->data.setadapterparms.hdr.return_code;
  3184. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3185. return 0;
  3186. }
  3187. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3188. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3189. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3190. else
  3191. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3192. /* check if there is enough room in userspace */
  3193. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3194. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3195. cmd->hdr.return_code = -ENOMEM;
  3196. return 0;
  3197. }
  3198. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3199. cmd->data.setadapterparms.hdr.used_total);
  3200. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3201. cmd->data.setadapterparms.hdr.seq_no);
  3202. /*copy entries to user buffer*/
  3203. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3204. memcpy(qinfo->udata + qinfo->udata_offset,
  3205. (char *)snmp,
  3206. data_len + offsetof(struct qeth_snmp_cmd, data));
  3207. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3208. } else {
  3209. memcpy(qinfo->udata + qinfo->udata_offset,
  3210. (char *)&snmp->request, data_len);
  3211. }
  3212. qinfo->udata_offset += data_len;
  3213. /* check if all replies received ... */
  3214. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3215. cmd->data.setadapterparms.hdr.used_total);
  3216. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3217. cmd->data.setadapterparms.hdr.seq_no);
  3218. if (cmd->data.setadapterparms.hdr.seq_no <
  3219. cmd->data.setadapterparms.hdr.used_total)
  3220. return 1;
  3221. return 0;
  3222. }
  3223. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3224. {
  3225. struct qeth_cmd_buffer *iob;
  3226. struct qeth_ipa_cmd *cmd;
  3227. struct qeth_snmp_ureq *ureq;
  3228. int req_len;
  3229. struct qeth_arp_query_info qinfo = {0, };
  3230. int rc = 0;
  3231. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3232. if (card->info.guestlan)
  3233. return -EOPNOTSUPP;
  3234. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3235. (!card->options.layer2)) {
  3236. return -EOPNOTSUPP;
  3237. }
  3238. /* skip 4 bytes (data_len struct member) to get req_len */
  3239. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3240. return -EFAULT;
  3241. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3242. if (!ureq) {
  3243. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3244. return -ENOMEM;
  3245. }
  3246. if (copy_from_user(ureq, udata,
  3247. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3248. kfree(ureq);
  3249. return -EFAULT;
  3250. }
  3251. qinfo.udata_len = ureq->hdr.data_len;
  3252. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3253. if (!qinfo.udata) {
  3254. kfree(ureq);
  3255. return -ENOMEM;
  3256. }
  3257. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3258. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3259. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3260. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3261. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3262. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3263. qeth_snmp_command_cb, (void *)&qinfo);
  3264. if (rc)
  3265. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3266. QETH_CARD_IFNAME(card), rc);
  3267. else {
  3268. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3269. rc = -EFAULT;
  3270. }
  3271. kfree(ureq);
  3272. kfree(qinfo.udata);
  3273. return rc;
  3274. }
  3275. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3276. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3277. {
  3278. switch (card->info.type) {
  3279. case QETH_CARD_TYPE_IQD:
  3280. return 2;
  3281. default:
  3282. return 0;
  3283. }
  3284. }
  3285. static int qeth_qdio_establish(struct qeth_card *card)
  3286. {
  3287. struct qdio_initialize init_data;
  3288. char *qib_param_field;
  3289. struct qdio_buffer **in_sbal_ptrs;
  3290. struct qdio_buffer **out_sbal_ptrs;
  3291. int i, j, k;
  3292. int rc = 0;
  3293. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3294. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3295. GFP_KERNEL);
  3296. if (!qib_param_field)
  3297. return -ENOMEM;
  3298. qeth_create_qib_param_field(card, qib_param_field);
  3299. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3300. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3301. GFP_KERNEL);
  3302. if (!in_sbal_ptrs) {
  3303. kfree(qib_param_field);
  3304. return -ENOMEM;
  3305. }
  3306. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3307. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3308. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3309. out_sbal_ptrs =
  3310. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3311. sizeof(void *), GFP_KERNEL);
  3312. if (!out_sbal_ptrs) {
  3313. kfree(in_sbal_ptrs);
  3314. kfree(qib_param_field);
  3315. return -ENOMEM;
  3316. }
  3317. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3318. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3319. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3320. card->qdio.out_qs[i]->bufs[j].buffer);
  3321. }
  3322. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3323. init_data.cdev = CARD_DDEV(card);
  3324. init_data.q_format = qeth_get_qdio_q_format(card);
  3325. init_data.qib_param_field_format = 0;
  3326. init_data.qib_param_field = qib_param_field;
  3327. init_data.no_input_qs = 1;
  3328. init_data.no_output_qs = card->qdio.no_out_queues;
  3329. init_data.input_handler = card->discipline.input_handler;
  3330. init_data.output_handler = card->discipline.output_handler;
  3331. init_data.int_parm = (unsigned long) card;
  3332. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3333. QDIO_OUTBOUND_0COPY_SBALS |
  3334. QDIO_USE_OUTBOUND_PCIS;
  3335. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3336. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3337. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3338. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3339. rc = qdio_initialize(&init_data);
  3340. if (rc)
  3341. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3342. }
  3343. kfree(out_sbal_ptrs);
  3344. kfree(in_sbal_ptrs);
  3345. kfree(qib_param_field);
  3346. return rc;
  3347. }
  3348. static void qeth_core_free_card(struct qeth_card *card)
  3349. {
  3350. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3351. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3352. qeth_clean_channel(&card->read);
  3353. qeth_clean_channel(&card->write);
  3354. if (card->dev)
  3355. free_netdev(card->dev);
  3356. kfree(card->ip_tbd_list);
  3357. qeth_free_qdio_buffers(card);
  3358. kfree(card);
  3359. }
  3360. static struct ccw_device_id qeth_ids[] = {
  3361. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3362. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3363. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3364. {},
  3365. };
  3366. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3367. static struct ccw_driver qeth_ccw_driver = {
  3368. .name = "qeth",
  3369. .ids = qeth_ids,
  3370. .probe = ccwgroup_probe_ccwdev,
  3371. .remove = ccwgroup_remove_ccwdev,
  3372. };
  3373. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3374. unsigned long driver_id)
  3375. {
  3376. return ccwgroup_create_from_string(root_dev, driver_id,
  3377. &qeth_ccw_driver, 3, buf);
  3378. }
  3379. int qeth_core_hardsetup_card(struct qeth_card *card)
  3380. {
  3381. struct qdio_ssqd_desc *qdio_ssqd;
  3382. int retries = 3;
  3383. int mpno = 0;
  3384. int rc;
  3385. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3386. atomic_set(&card->force_alloc_skb, 0);
  3387. retry:
  3388. if (retries < 3) {
  3389. PRINT_WARN("Retrying to do IDX activates.\n");
  3390. ccw_device_set_offline(CARD_DDEV(card));
  3391. ccw_device_set_offline(CARD_WDEV(card));
  3392. ccw_device_set_offline(CARD_RDEV(card));
  3393. ccw_device_set_online(CARD_RDEV(card));
  3394. ccw_device_set_online(CARD_WDEV(card));
  3395. ccw_device_set_online(CARD_DDEV(card));
  3396. }
  3397. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3398. if (rc == -ERESTARTSYS) {
  3399. QETH_DBF_TEXT(SETUP, 2, "break1");
  3400. return rc;
  3401. } else if (rc) {
  3402. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3403. if (--retries < 0)
  3404. goto out;
  3405. else
  3406. goto retry;
  3407. }
  3408. rc = qeth_get_unitaddr(card);
  3409. if (rc) {
  3410. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3411. return rc;
  3412. }
  3413. qdio_ssqd = qdio_get_ssqd_desc(CARD_DDEV(card));
  3414. if (qdio_ssqd)
  3415. mpno = qdio_ssqd->pcnt;
  3416. if (mpno)
  3417. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3418. if (card->info.portno > mpno) {
  3419. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3420. "\n.", CARD_BUS_ID(card), card->info.portno);
  3421. rc = -ENODEV;
  3422. goto out;
  3423. }
  3424. qeth_init_tokens(card);
  3425. qeth_init_func_level(card);
  3426. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3427. if (rc == -ERESTARTSYS) {
  3428. QETH_DBF_TEXT(SETUP, 2, "break2");
  3429. return rc;
  3430. } else if (rc) {
  3431. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3432. if (--retries < 0)
  3433. goto out;
  3434. else
  3435. goto retry;
  3436. }
  3437. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3438. if (rc == -ERESTARTSYS) {
  3439. QETH_DBF_TEXT(SETUP, 2, "break3");
  3440. return rc;
  3441. } else if (rc) {
  3442. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3443. if (--retries < 0)
  3444. goto out;
  3445. else
  3446. goto retry;
  3447. }
  3448. rc = qeth_mpc_initialize(card);
  3449. if (rc) {
  3450. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3451. goto out;
  3452. }
  3453. return 0;
  3454. out:
  3455. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3456. return rc;
  3457. }
  3458. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3459. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3460. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3461. {
  3462. struct page *page = virt_to_page(element->addr);
  3463. if (*pskb == NULL) {
  3464. /* the upper protocol layers assume that there is data in the
  3465. * skb itself. Copy a small amount (64 bytes) to make them
  3466. * happy. */
  3467. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3468. if (!(*pskb))
  3469. return -ENOMEM;
  3470. skb_reserve(*pskb, ETH_HLEN);
  3471. if (data_len <= 64) {
  3472. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3473. data_len);
  3474. } else {
  3475. get_page(page);
  3476. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3477. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3478. data_len - 64);
  3479. (*pskb)->data_len += data_len - 64;
  3480. (*pskb)->len += data_len - 64;
  3481. (*pskb)->truesize += data_len - 64;
  3482. (*pfrag)++;
  3483. }
  3484. } else {
  3485. get_page(page);
  3486. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3487. (*pskb)->data_len += data_len;
  3488. (*pskb)->len += data_len;
  3489. (*pskb)->truesize += data_len;
  3490. (*pfrag)++;
  3491. }
  3492. return 0;
  3493. }
  3494. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3495. struct qdio_buffer *buffer,
  3496. struct qdio_buffer_element **__element, int *__offset,
  3497. struct qeth_hdr **hdr)
  3498. {
  3499. struct qdio_buffer_element *element = *__element;
  3500. int offset = *__offset;
  3501. struct sk_buff *skb = NULL;
  3502. int skb_len;
  3503. void *data_ptr;
  3504. int data_len;
  3505. int headroom = 0;
  3506. int use_rx_sg = 0;
  3507. int frag = 0;
  3508. /* qeth_hdr must not cross element boundaries */
  3509. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3510. if (qeth_is_last_sbale(element))
  3511. return NULL;
  3512. element++;
  3513. offset = 0;
  3514. if (element->length < sizeof(struct qeth_hdr))
  3515. return NULL;
  3516. }
  3517. *hdr = element->addr + offset;
  3518. offset += sizeof(struct qeth_hdr);
  3519. if (card->options.layer2) {
  3520. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3521. skb_len = (*hdr)->hdr.osn.pdu_length;
  3522. headroom = sizeof(struct qeth_hdr);
  3523. } else {
  3524. skb_len = (*hdr)->hdr.l2.pkt_length;
  3525. }
  3526. } else {
  3527. skb_len = (*hdr)->hdr.l3.length;
  3528. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3529. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3530. headroom = TR_HLEN;
  3531. else
  3532. headroom = ETH_HLEN;
  3533. }
  3534. if (!skb_len)
  3535. return NULL;
  3536. if ((skb_len >= card->options.rx_sg_cb) &&
  3537. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3538. (!atomic_read(&card->force_alloc_skb))) {
  3539. use_rx_sg = 1;
  3540. } else {
  3541. skb = dev_alloc_skb(skb_len + headroom);
  3542. if (!skb)
  3543. goto no_mem;
  3544. if (headroom)
  3545. skb_reserve(skb, headroom);
  3546. }
  3547. data_ptr = element->addr + offset;
  3548. while (skb_len) {
  3549. data_len = min(skb_len, (int)(element->length - offset));
  3550. if (data_len) {
  3551. if (use_rx_sg) {
  3552. if (qeth_create_skb_frag(element, &skb, offset,
  3553. &frag, data_len))
  3554. goto no_mem;
  3555. } else {
  3556. memcpy(skb_put(skb, data_len), data_ptr,
  3557. data_len);
  3558. }
  3559. }
  3560. skb_len -= data_len;
  3561. if (skb_len) {
  3562. if (qeth_is_last_sbale(element)) {
  3563. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3564. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3565. CARD_BUS_ID(card));
  3566. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3567. QETH_DBF_TEXT_(QERR, 2, "%s",
  3568. CARD_BUS_ID(card));
  3569. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3570. dev_kfree_skb_any(skb);
  3571. card->stats.rx_errors++;
  3572. return NULL;
  3573. }
  3574. element++;
  3575. offset = 0;
  3576. data_ptr = element->addr;
  3577. } else {
  3578. offset += data_len;
  3579. }
  3580. }
  3581. *__element = element;
  3582. *__offset = offset;
  3583. if (use_rx_sg && card->options.performance_stats) {
  3584. card->perf_stats.sg_skbs_rx++;
  3585. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3586. }
  3587. return skb;
  3588. no_mem:
  3589. if (net_ratelimit()) {
  3590. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3591. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3592. }
  3593. card->stats.rx_dropped++;
  3594. return NULL;
  3595. }
  3596. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3597. static void qeth_unregister_dbf_views(void)
  3598. {
  3599. int x;
  3600. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3601. debug_unregister(qeth_dbf[x].id);
  3602. qeth_dbf[x].id = NULL;
  3603. }
  3604. }
  3605. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3606. {
  3607. char dbf_txt_buf[32];
  3608. va_list args;
  3609. if (level > (qeth_dbf[dbf_nix].id)->level)
  3610. return;
  3611. va_start(args, fmt);
  3612. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3613. va_end(args);
  3614. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3615. }
  3616. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3617. static int qeth_register_dbf_views(void)
  3618. {
  3619. int ret;
  3620. int x;
  3621. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3622. /* register the areas */
  3623. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3624. qeth_dbf[x].pages,
  3625. qeth_dbf[x].areas,
  3626. qeth_dbf[x].len);
  3627. if (qeth_dbf[x].id == NULL) {
  3628. qeth_unregister_dbf_views();
  3629. return -ENOMEM;
  3630. }
  3631. /* register a view */
  3632. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3633. if (ret) {
  3634. qeth_unregister_dbf_views();
  3635. return ret;
  3636. }
  3637. /* set a passing level */
  3638. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3639. }
  3640. return 0;
  3641. }
  3642. int qeth_core_load_discipline(struct qeth_card *card,
  3643. enum qeth_discipline_id discipline)
  3644. {
  3645. int rc = 0;
  3646. switch (discipline) {
  3647. case QETH_DISCIPLINE_LAYER3:
  3648. card->discipline.ccwgdriver = try_then_request_module(
  3649. symbol_get(qeth_l3_ccwgroup_driver),
  3650. "qeth_l3");
  3651. break;
  3652. case QETH_DISCIPLINE_LAYER2:
  3653. card->discipline.ccwgdriver = try_then_request_module(
  3654. symbol_get(qeth_l2_ccwgroup_driver),
  3655. "qeth_l2");
  3656. break;
  3657. }
  3658. if (!card->discipline.ccwgdriver) {
  3659. PRINT_ERR("Support for discipline %d not present\n",
  3660. discipline);
  3661. rc = -EINVAL;
  3662. }
  3663. return rc;
  3664. }
  3665. void qeth_core_free_discipline(struct qeth_card *card)
  3666. {
  3667. if (card->options.layer2)
  3668. symbol_put(qeth_l2_ccwgroup_driver);
  3669. else
  3670. symbol_put(qeth_l3_ccwgroup_driver);
  3671. card->discipline.ccwgdriver = NULL;
  3672. }
  3673. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3674. {
  3675. struct qeth_card *card;
  3676. struct device *dev;
  3677. int rc;
  3678. unsigned long flags;
  3679. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3680. dev = &gdev->dev;
  3681. if (!get_device(dev))
  3682. return -ENODEV;
  3683. QETH_DBF_TEXT_(SETUP, 2, "%s", gdev->dev.bus_id);
  3684. card = qeth_alloc_card();
  3685. if (!card) {
  3686. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3687. rc = -ENOMEM;
  3688. goto err_dev;
  3689. }
  3690. card->read.ccwdev = gdev->cdev[0];
  3691. card->write.ccwdev = gdev->cdev[1];
  3692. card->data.ccwdev = gdev->cdev[2];
  3693. dev_set_drvdata(&gdev->dev, card);
  3694. card->gdev = gdev;
  3695. gdev->cdev[0]->handler = qeth_irq;
  3696. gdev->cdev[1]->handler = qeth_irq;
  3697. gdev->cdev[2]->handler = qeth_irq;
  3698. rc = qeth_determine_card_type(card);
  3699. if (rc) {
  3700. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3701. goto err_card;
  3702. }
  3703. rc = qeth_setup_card(card);
  3704. if (rc) {
  3705. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3706. goto err_card;
  3707. }
  3708. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3709. rc = qeth_core_create_osn_attributes(dev);
  3710. if (rc)
  3711. goto err_card;
  3712. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3713. if (rc) {
  3714. qeth_core_remove_osn_attributes(dev);
  3715. goto err_card;
  3716. }
  3717. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3718. if (rc) {
  3719. qeth_core_free_discipline(card);
  3720. qeth_core_remove_osn_attributes(dev);
  3721. goto err_card;
  3722. }
  3723. } else {
  3724. rc = qeth_core_create_device_attributes(dev);
  3725. if (rc)
  3726. goto err_card;
  3727. }
  3728. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3729. list_add_tail(&card->list, &qeth_core_card_list.list);
  3730. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3731. return 0;
  3732. err_card:
  3733. qeth_core_free_card(card);
  3734. err_dev:
  3735. put_device(dev);
  3736. return rc;
  3737. }
  3738. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3739. {
  3740. unsigned long flags;
  3741. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3742. if (card->discipline.ccwgdriver) {
  3743. card->discipline.ccwgdriver->remove(gdev);
  3744. qeth_core_free_discipline(card);
  3745. }
  3746. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3747. qeth_core_remove_osn_attributes(&gdev->dev);
  3748. } else {
  3749. qeth_core_remove_device_attributes(&gdev->dev);
  3750. }
  3751. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3752. list_del(&card->list);
  3753. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3754. qeth_core_free_card(card);
  3755. dev_set_drvdata(&gdev->dev, NULL);
  3756. put_device(&gdev->dev);
  3757. return;
  3758. }
  3759. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3760. {
  3761. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3762. int rc = 0;
  3763. int def_discipline;
  3764. if (!card->discipline.ccwgdriver) {
  3765. if (card->info.type == QETH_CARD_TYPE_IQD)
  3766. def_discipline = QETH_DISCIPLINE_LAYER3;
  3767. else
  3768. def_discipline = QETH_DISCIPLINE_LAYER2;
  3769. rc = qeth_core_load_discipline(card, def_discipline);
  3770. if (rc)
  3771. goto err;
  3772. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3773. if (rc)
  3774. goto err;
  3775. }
  3776. rc = card->discipline.ccwgdriver->set_online(gdev);
  3777. err:
  3778. return rc;
  3779. }
  3780. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3781. {
  3782. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3783. return card->discipline.ccwgdriver->set_offline(gdev);
  3784. }
  3785. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3786. {
  3787. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3788. if (card->discipline.ccwgdriver &&
  3789. card->discipline.ccwgdriver->shutdown)
  3790. card->discipline.ccwgdriver->shutdown(gdev);
  3791. }
  3792. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3793. .owner = THIS_MODULE,
  3794. .name = "qeth",
  3795. .driver_id = 0xD8C5E3C8,
  3796. .probe = qeth_core_probe_device,
  3797. .remove = qeth_core_remove_device,
  3798. .set_online = qeth_core_set_online,
  3799. .set_offline = qeth_core_set_offline,
  3800. .shutdown = qeth_core_shutdown,
  3801. };
  3802. static ssize_t
  3803. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3804. size_t count)
  3805. {
  3806. int err;
  3807. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3808. qeth_core_ccwgroup_driver.driver_id);
  3809. if (err)
  3810. return err;
  3811. else
  3812. return count;
  3813. }
  3814. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3815. static struct {
  3816. const char str[ETH_GSTRING_LEN];
  3817. } qeth_ethtool_stats_keys[] = {
  3818. /* 0 */{"rx skbs"},
  3819. {"rx buffers"},
  3820. {"tx skbs"},
  3821. {"tx buffers"},
  3822. {"tx skbs no packing"},
  3823. {"tx buffers no packing"},
  3824. {"tx skbs packing"},
  3825. {"tx buffers packing"},
  3826. {"tx sg skbs"},
  3827. {"tx sg frags"},
  3828. /* 10 */{"rx sg skbs"},
  3829. {"rx sg frags"},
  3830. {"rx sg page allocs"},
  3831. {"tx large kbytes"},
  3832. {"tx large count"},
  3833. {"tx pk state ch n->p"},
  3834. {"tx pk state ch p->n"},
  3835. {"tx pk watermark low"},
  3836. {"tx pk watermark high"},
  3837. {"queue 0 buffer usage"},
  3838. /* 20 */{"queue 1 buffer usage"},
  3839. {"queue 2 buffer usage"},
  3840. {"queue 3 buffer usage"},
  3841. {"rx handler time"},
  3842. {"rx handler count"},
  3843. {"rx do_QDIO time"},
  3844. {"rx do_QDIO count"},
  3845. {"tx handler time"},
  3846. {"tx handler count"},
  3847. {"tx time"},
  3848. /* 30 */{"tx count"},
  3849. {"tx do_QDIO time"},
  3850. {"tx do_QDIO count"},
  3851. };
  3852. int qeth_core_get_stats_count(struct net_device *dev)
  3853. {
  3854. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3855. }
  3856. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3857. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3858. struct ethtool_stats *stats, u64 *data)
  3859. {
  3860. struct qeth_card *card = dev->ml_priv;
  3861. data[0] = card->stats.rx_packets -
  3862. card->perf_stats.initial_rx_packets;
  3863. data[1] = card->perf_stats.bufs_rec;
  3864. data[2] = card->stats.tx_packets -
  3865. card->perf_stats.initial_tx_packets;
  3866. data[3] = card->perf_stats.bufs_sent;
  3867. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3868. - card->perf_stats.skbs_sent_pack;
  3869. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3870. data[6] = card->perf_stats.skbs_sent_pack;
  3871. data[7] = card->perf_stats.bufs_sent_pack;
  3872. data[8] = card->perf_stats.sg_skbs_sent;
  3873. data[9] = card->perf_stats.sg_frags_sent;
  3874. data[10] = card->perf_stats.sg_skbs_rx;
  3875. data[11] = card->perf_stats.sg_frags_rx;
  3876. data[12] = card->perf_stats.sg_alloc_page_rx;
  3877. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3878. data[14] = card->perf_stats.large_send_cnt;
  3879. data[15] = card->perf_stats.sc_dp_p;
  3880. data[16] = card->perf_stats.sc_p_dp;
  3881. data[17] = QETH_LOW_WATERMARK_PACK;
  3882. data[18] = QETH_HIGH_WATERMARK_PACK;
  3883. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3884. data[20] = (card->qdio.no_out_queues > 1) ?
  3885. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3886. data[21] = (card->qdio.no_out_queues > 2) ?
  3887. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3888. data[22] = (card->qdio.no_out_queues > 3) ?
  3889. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3890. data[23] = card->perf_stats.inbound_time;
  3891. data[24] = card->perf_stats.inbound_cnt;
  3892. data[25] = card->perf_stats.inbound_do_qdio_time;
  3893. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3894. data[27] = card->perf_stats.outbound_handler_time;
  3895. data[28] = card->perf_stats.outbound_handler_cnt;
  3896. data[29] = card->perf_stats.outbound_time;
  3897. data[30] = card->perf_stats.outbound_cnt;
  3898. data[31] = card->perf_stats.outbound_do_qdio_time;
  3899. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3900. }
  3901. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3902. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3903. {
  3904. switch (stringset) {
  3905. case ETH_SS_STATS:
  3906. memcpy(data, &qeth_ethtool_stats_keys,
  3907. sizeof(qeth_ethtool_stats_keys));
  3908. break;
  3909. default:
  3910. WARN_ON(1);
  3911. break;
  3912. }
  3913. }
  3914. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3915. void qeth_core_get_drvinfo(struct net_device *dev,
  3916. struct ethtool_drvinfo *info)
  3917. {
  3918. struct qeth_card *card = dev->ml_priv;
  3919. if (card->options.layer2)
  3920. strcpy(info->driver, "qeth_l2");
  3921. else
  3922. strcpy(info->driver, "qeth_l3");
  3923. strcpy(info->version, "1.0");
  3924. strcpy(info->fw_version, card->info.mcl_level);
  3925. sprintf(info->bus_info, "%s/%s/%s",
  3926. CARD_RDEV_ID(card),
  3927. CARD_WDEV_ID(card),
  3928. CARD_DDEV_ID(card));
  3929. }
  3930. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3931. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3932. struct ethtool_cmd *ecmd)
  3933. {
  3934. struct qeth_card *card = netdev->ml_priv;
  3935. enum qeth_link_types link_type;
  3936. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3937. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3938. else
  3939. link_type = card->info.link_type;
  3940. ecmd->transceiver = XCVR_INTERNAL;
  3941. ecmd->supported = SUPPORTED_Autoneg;
  3942. ecmd->advertising = ADVERTISED_Autoneg;
  3943. ecmd->duplex = DUPLEX_FULL;
  3944. ecmd->autoneg = AUTONEG_ENABLE;
  3945. switch (link_type) {
  3946. case QETH_LINK_TYPE_FAST_ETH:
  3947. case QETH_LINK_TYPE_LANE_ETH100:
  3948. ecmd->supported |= SUPPORTED_10baseT_Half |
  3949. SUPPORTED_10baseT_Full |
  3950. SUPPORTED_100baseT_Half |
  3951. SUPPORTED_100baseT_Full |
  3952. SUPPORTED_TP;
  3953. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3954. ADVERTISED_10baseT_Full |
  3955. ADVERTISED_100baseT_Half |
  3956. ADVERTISED_100baseT_Full |
  3957. ADVERTISED_TP;
  3958. ecmd->speed = SPEED_100;
  3959. ecmd->port = PORT_TP;
  3960. break;
  3961. case QETH_LINK_TYPE_GBIT_ETH:
  3962. case QETH_LINK_TYPE_LANE_ETH1000:
  3963. ecmd->supported |= SUPPORTED_10baseT_Half |
  3964. SUPPORTED_10baseT_Full |
  3965. SUPPORTED_100baseT_Half |
  3966. SUPPORTED_100baseT_Full |
  3967. SUPPORTED_1000baseT_Half |
  3968. SUPPORTED_1000baseT_Full |
  3969. SUPPORTED_FIBRE;
  3970. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3971. ADVERTISED_10baseT_Full |
  3972. ADVERTISED_100baseT_Half |
  3973. ADVERTISED_100baseT_Full |
  3974. ADVERTISED_1000baseT_Half |
  3975. ADVERTISED_1000baseT_Full |
  3976. ADVERTISED_FIBRE;
  3977. ecmd->speed = SPEED_1000;
  3978. ecmd->port = PORT_FIBRE;
  3979. break;
  3980. case QETH_LINK_TYPE_10GBIT_ETH:
  3981. ecmd->supported |= SUPPORTED_10baseT_Half |
  3982. SUPPORTED_10baseT_Full |
  3983. SUPPORTED_100baseT_Half |
  3984. SUPPORTED_100baseT_Full |
  3985. SUPPORTED_1000baseT_Half |
  3986. SUPPORTED_1000baseT_Full |
  3987. SUPPORTED_10000baseT_Full |
  3988. SUPPORTED_FIBRE;
  3989. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3990. ADVERTISED_10baseT_Full |
  3991. ADVERTISED_100baseT_Half |
  3992. ADVERTISED_100baseT_Full |
  3993. ADVERTISED_1000baseT_Half |
  3994. ADVERTISED_1000baseT_Full |
  3995. ADVERTISED_10000baseT_Full |
  3996. ADVERTISED_FIBRE;
  3997. ecmd->speed = SPEED_10000;
  3998. ecmd->port = PORT_FIBRE;
  3999. break;
  4000. default:
  4001. ecmd->supported |= SUPPORTED_10baseT_Half |
  4002. SUPPORTED_10baseT_Full |
  4003. SUPPORTED_TP;
  4004. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4005. ADVERTISED_10baseT_Full |
  4006. ADVERTISED_TP;
  4007. ecmd->speed = SPEED_10;
  4008. ecmd->port = PORT_TP;
  4009. }
  4010. return 0;
  4011. }
  4012. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4013. static int __init qeth_core_init(void)
  4014. {
  4015. int rc;
  4016. PRINT_INFO("loading core functions\n");
  4017. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4018. rwlock_init(&qeth_core_card_list.rwlock);
  4019. rc = qeth_register_dbf_views();
  4020. if (rc)
  4021. goto out_err;
  4022. rc = ccw_driver_register(&qeth_ccw_driver);
  4023. if (rc)
  4024. goto ccw_err;
  4025. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4026. if (rc)
  4027. goto ccwgroup_err;
  4028. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4029. &driver_attr_group);
  4030. if (rc)
  4031. goto driver_err;
  4032. qeth_core_root_dev = s390_root_dev_register("qeth");
  4033. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4034. if (rc)
  4035. goto register_err;
  4036. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4037. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4038. if (!qeth_core_header_cache) {
  4039. rc = -ENOMEM;
  4040. goto slab_err;
  4041. }
  4042. return 0;
  4043. slab_err:
  4044. s390_root_dev_unregister(qeth_core_root_dev);
  4045. register_err:
  4046. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4047. &driver_attr_group);
  4048. driver_err:
  4049. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4050. ccwgroup_err:
  4051. ccw_driver_unregister(&qeth_ccw_driver);
  4052. ccw_err:
  4053. qeth_unregister_dbf_views();
  4054. out_err:
  4055. PRINT_ERR("Initialization failed with code %d\n", rc);
  4056. return rc;
  4057. }
  4058. static void __exit qeth_core_exit(void)
  4059. {
  4060. s390_root_dev_unregister(qeth_core_root_dev);
  4061. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4062. &driver_attr_group);
  4063. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4064. ccw_driver_unregister(&qeth_ccw_driver);
  4065. kmem_cache_destroy(qeth_core_header_cache);
  4066. qeth_unregister_dbf_views();
  4067. PRINT_INFO("core functions removed\n");
  4068. }
  4069. module_init(qeth_core_init);
  4070. module_exit(qeth_core_exit);
  4071. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4072. MODULE_DESCRIPTION("qeth core functions");
  4073. MODULE_LICENSE("GPL");