intel_ringbuffer.h 4.5 KB

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  1. #ifndef _INTEL_RINGBUFFER_H_
  2. #define _INTEL_RINGBUFFER_H_
  3. enum {
  4. RCS = 0x0,
  5. VCS,
  6. BCS,
  7. I915_NUM_RINGS,
  8. };
  9. struct intel_hw_status_page {
  10. u32 __iomem *page_addr;
  11. unsigned int gfx_addr;
  12. struct drm_i915_gem_object *obj;
  13. };
  14. #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
  15. #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL(ring->mmio_base))
  16. #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
  17. #define I915_READ_START(ring) I915_RING_READ(RING_START(ring->mmio_base))
  18. #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
  19. #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD(ring->mmio_base))
  20. #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
  21. #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL(ring->mmio_base))
  22. #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
  23. #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID(ring->mmio_base))
  24. #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0(ring->mmio_base))
  25. #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1(ring->mmio_base))
  26. struct intel_ring_buffer {
  27. const char *name;
  28. enum intel_ring_id {
  29. RING_RENDER = 0x1,
  30. RING_BSD = 0x2,
  31. RING_BLT = 0x4,
  32. } id;
  33. u32 mmio_base;
  34. void *virtual_start;
  35. struct drm_device *dev;
  36. struct drm_i915_gem_object *obj;
  37. u32 actual_head;
  38. u32 head;
  39. u32 tail;
  40. int space;
  41. int size;
  42. struct intel_hw_status_page status_page;
  43. u32 irq_seqno; /* last seq seem at irq time */
  44. u32 waiting_seqno;
  45. u32 sync_seqno[I915_NUM_RINGS-1];
  46. atomic_t irq_refcount;
  47. bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  48. void (*irq_put)(struct intel_ring_buffer *ring);
  49. int (*init)(struct intel_ring_buffer *ring);
  50. void (*write_tail)(struct intel_ring_buffer *ring,
  51. u32 value);
  52. void (*flush)(struct intel_ring_buffer *ring,
  53. u32 invalidate_domains,
  54. u32 flush_domains);
  55. int (*add_request)(struct intel_ring_buffer *ring,
  56. u32 *seqno);
  57. u32 (*get_seqno)(struct intel_ring_buffer *ring);
  58. int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  59. u32 offset, u32 length);
  60. void (*cleanup)(struct intel_ring_buffer *ring);
  61. /**
  62. * List of objects currently involved in rendering from the
  63. * ringbuffer.
  64. *
  65. * Includes buffers having the contents of their GPU caches
  66. * flushed, not necessarily primitives. last_rendering_seqno
  67. * represents when the rendering involved will be completed.
  68. *
  69. * A reference is held on the buffer while on this list.
  70. */
  71. struct list_head active_list;
  72. /**
  73. * List of breadcrumbs associated with GPU requests currently
  74. * outstanding.
  75. */
  76. struct list_head request_list;
  77. /**
  78. * List of objects currently pending a GPU write flush.
  79. *
  80. * All elements on this list will belong to either the
  81. * active_list or flushing_list, last_rendering_seqno can
  82. * be used to differentiate between the two elements.
  83. */
  84. struct list_head gpu_write_list;
  85. /**
  86. * Do we have some not yet emitted requests outstanding?
  87. */
  88. u32 outstanding_lazy_request;
  89. wait_queue_head_t irq_queue;
  90. drm_local_map_t map;
  91. void *private;
  92. };
  93. static inline u32
  94. intel_ring_sync_index(struct intel_ring_buffer *ring,
  95. struct intel_ring_buffer *other)
  96. {
  97. int idx;
  98. /*
  99. * cs -> 0 = vcs, 1 = bcs
  100. * vcs -> 0 = bcs, 1 = cs,
  101. * bcs -> 0 = cs, 1 = vcs.
  102. */
  103. idx = (other - ring) - 1;
  104. if (idx < 0)
  105. idx += I915_NUM_RINGS;
  106. return idx;
  107. }
  108. static inline u32
  109. intel_read_status_page(struct intel_ring_buffer *ring,
  110. int reg)
  111. {
  112. return ioread32(ring->status_page.page_addr + reg);
  113. }
  114. void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
  115. int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
  116. int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
  117. static inline void intel_ring_emit(struct intel_ring_buffer *ring,
  118. u32 data)
  119. {
  120. iowrite32(data, ring->virtual_start + ring->tail);
  121. ring->tail += 4;
  122. }
  123. void intel_ring_advance(struct intel_ring_buffer *ring);
  124. u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
  125. int intel_ring_sync(struct intel_ring_buffer *ring,
  126. struct intel_ring_buffer *to,
  127. u32 seqno);
  128. int intel_init_render_ring_buffer(struct drm_device *dev);
  129. int intel_init_bsd_ring_buffer(struct drm_device *dev);
  130. int intel_init_blt_ring_buffer(struct drm_device *dev);
  131. u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
  132. void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
  133. #endif /* _INTEL_RINGBUFFER_H_ */