i915_irq.c 47 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include <linux/sysrq.h>
  29. #include <linux/slab.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. #define MAX_NOPID ((u32)~0)
  37. /**
  38. * Interrupts that are always left unmasked.
  39. *
  40. * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  41. * we leave them always unmasked in IMR and then control enabling them through
  42. * PIPESTAT alone.
  43. */
  44. #define I915_INTERRUPT_ENABLE_FIX \
  45. (I915_ASLE_INTERRUPT | \
  46. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  47. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
  48. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
  49. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
  50. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  51. /** Interrupts that we mask and unmask at runtime. */
  52. #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  53. #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  54. PIPE_VBLANK_INTERRUPT_STATUS)
  55. #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  56. PIPE_VBLANK_INTERRUPT_ENABLE)
  57. #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
  58. DRM_I915_VBLANK_PIPE_B)
  59. void
  60. ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  61. {
  62. if ((dev_priv->gt_irq_mask & mask) != 0) {
  63. dev_priv->gt_irq_mask &= ~mask;
  64. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  65. POSTING_READ(GTIMR);
  66. }
  67. }
  68. void
  69. ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  70. {
  71. if ((dev_priv->gt_irq_mask & mask) != mask) {
  72. dev_priv->gt_irq_mask |= mask;
  73. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  74. POSTING_READ(GTIMR);
  75. }
  76. }
  77. /* For display hotplug interrupt */
  78. static void
  79. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80. {
  81. if ((dev_priv->irq_mask & mask) != 0) {
  82. dev_priv->irq_mask &= ~mask;
  83. I915_WRITE(DEIMR, dev_priv->irq_mask);
  84. POSTING_READ(DEIMR);
  85. }
  86. }
  87. static inline void
  88. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  89. {
  90. if ((dev_priv->irq_mask & mask) != mask) {
  91. dev_priv->irq_mask |= mask;
  92. I915_WRITE(DEIMR, dev_priv->irq_mask);
  93. POSTING_READ(DEIMR);
  94. }
  95. }
  96. void
  97. i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  98. {
  99. if ((dev_priv->irq_mask & mask) != 0) {
  100. dev_priv->irq_mask &= ~mask;
  101. I915_WRITE(IMR, dev_priv->irq_mask);
  102. POSTING_READ(IMR);
  103. }
  104. }
  105. void
  106. i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  107. {
  108. if ((dev_priv->irq_mask & mask) != mask) {
  109. dev_priv->irq_mask |= mask;
  110. I915_WRITE(IMR, dev_priv->irq_mask);
  111. POSTING_READ(IMR);
  112. }
  113. }
  114. static inline u32
  115. i915_pipestat(int pipe)
  116. {
  117. if (pipe == 0)
  118. return PIPEASTAT;
  119. if (pipe == 1)
  120. return PIPEBSTAT;
  121. BUG();
  122. }
  123. void
  124. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  125. {
  126. if ((dev_priv->pipestat[pipe] & mask) != mask) {
  127. u32 reg = i915_pipestat(pipe);
  128. dev_priv->pipestat[pipe] |= mask;
  129. /* Enable the interrupt, clear any pending status */
  130. I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  131. POSTING_READ(reg);
  132. }
  133. }
  134. void
  135. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  136. {
  137. if ((dev_priv->pipestat[pipe] & mask) != 0) {
  138. u32 reg = i915_pipestat(pipe);
  139. dev_priv->pipestat[pipe] &= ~mask;
  140. I915_WRITE(reg, dev_priv->pipestat[pipe]);
  141. POSTING_READ(reg);
  142. }
  143. }
  144. /**
  145. * intel_enable_asle - enable ASLE interrupt for OpRegion
  146. */
  147. void intel_enable_asle(struct drm_device *dev)
  148. {
  149. drm_i915_private_t *dev_priv = dev->dev_private;
  150. unsigned long irqflags;
  151. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  152. if (HAS_PCH_SPLIT(dev))
  153. ironlake_enable_display_irq(dev_priv, DE_GSE);
  154. else {
  155. i915_enable_pipestat(dev_priv, 1,
  156. PIPE_LEGACY_BLC_EVENT_ENABLE);
  157. if (INTEL_INFO(dev)->gen >= 4)
  158. i915_enable_pipestat(dev_priv, 0,
  159. PIPE_LEGACY_BLC_EVENT_ENABLE);
  160. }
  161. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  162. }
  163. /**
  164. * i915_pipe_enabled - check if a pipe is enabled
  165. * @dev: DRM device
  166. * @pipe: pipe to check
  167. *
  168. * Reading certain registers when the pipe is disabled can hang the chip.
  169. * Use this routine to make sure the PLL is running and the pipe is active
  170. * before reading such registers if unsure.
  171. */
  172. static int
  173. i915_pipe_enabled(struct drm_device *dev, int pipe)
  174. {
  175. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  176. return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
  177. }
  178. /* Called from drm generic code, passed a 'crtc', which
  179. * we use as a pipe index
  180. */
  181. u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  182. {
  183. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  184. unsigned long high_frame;
  185. unsigned long low_frame;
  186. u32 high1, high2, low;
  187. if (!i915_pipe_enabled(dev, pipe)) {
  188. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  189. "pipe %d\n", pipe);
  190. return 0;
  191. }
  192. high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
  193. low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
  194. /*
  195. * High & low register fields aren't synchronized, so make sure
  196. * we get a low value that's stable across two reads of the high
  197. * register.
  198. */
  199. do {
  200. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  201. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  202. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  203. } while (high1 != high2);
  204. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  205. low >>= PIPE_FRAME_LOW_SHIFT;
  206. return (high1 << 8) | low;
  207. }
  208. u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  209. {
  210. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  211. int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
  212. if (!i915_pipe_enabled(dev, pipe)) {
  213. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  214. "pipe %d\n", pipe);
  215. return 0;
  216. }
  217. return I915_READ(reg);
  218. }
  219. /*
  220. * Handle hotplug events outside the interrupt handler proper.
  221. */
  222. static void i915_hotplug_work_func(struct work_struct *work)
  223. {
  224. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  225. hotplug_work);
  226. struct drm_device *dev = dev_priv->dev;
  227. struct drm_mode_config *mode_config = &dev->mode_config;
  228. struct intel_encoder *encoder;
  229. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  230. if (encoder->hot_plug)
  231. encoder->hot_plug(encoder);
  232. /* Just fire off a uevent and let userspace tell us what to do */
  233. drm_helper_hpd_irq_event(dev);
  234. }
  235. static void i915_handle_rps_change(struct drm_device *dev)
  236. {
  237. drm_i915_private_t *dev_priv = dev->dev_private;
  238. u32 busy_up, busy_down, max_avg, min_avg;
  239. u8 new_delay = dev_priv->cur_delay;
  240. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  241. busy_up = I915_READ(RCPREVBSYTUPAVG);
  242. busy_down = I915_READ(RCPREVBSYTDNAVG);
  243. max_avg = I915_READ(RCBMAXAVG);
  244. min_avg = I915_READ(RCBMINAVG);
  245. /* Handle RCS change request from hw */
  246. if (busy_up > max_avg) {
  247. if (dev_priv->cur_delay != dev_priv->max_delay)
  248. new_delay = dev_priv->cur_delay - 1;
  249. if (new_delay < dev_priv->max_delay)
  250. new_delay = dev_priv->max_delay;
  251. } else if (busy_down < min_avg) {
  252. if (dev_priv->cur_delay != dev_priv->min_delay)
  253. new_delay = dev_priv->cur_delay + 1;
  254. if (new_delay > dev_priv->min_delay)
  255. new_delay = dev_priv->min_delay;
  256. }
  257. if (ironlake_set_drps(dev, new_delay))
  258. dev_priv->cur_delay = new_delay;
  259. return;
  260. }
  261. static void notify_ring(struct drm_device *dev,
  262. struct intel_ring_buffer *ring)
  263. {
  264. struct drm_i915_private *dev_priv = dev->dev_private;
  265. u32 seqno = ring->get_seqno(ring);
  266. ring->irq_seqno = seqno;
  267. trace_i915_gem_request_complete(dev, seqno);
  268. wake_up_all(&ring->irq_queue);
  269. dev_priv->hangcheck_count = 0;
  270. mod_timer(&dev_priv->hangcheck_timer,
  271. jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
  272. }
  273. static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
  274. {
  275. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  276. int ret = IRQ_NONE;
  277. u32 de_iir, gt_iir, de_ier, pch_iir;
  278. u32 hotplug_mask;
  279. struct drm_i915_master_private *master_priv;
  280. u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
  281. if (IS_GEN6(dev))
  282. bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
  283. /* disable master interrupt before clearing iir */
  284. de_ier = I915_READ(DEIER);
  285. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  286. POSTING_READ(DEIER);
  287. de_iir = I915_READ(DEIIR);
  288. gt_iir = I915_READ(GTIIR);
  289. pch_iir = I915_READ(SDEIIR);
  290. if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
  291. goto done;
  292. if (HAS_PCH_CPT(dev))
  293. hotplug_mask = SDE_HOTPLUG_MASK_CPT;
  294. else
  295. hotplug_mask = SDE_HOTPLUG_MASK;
  296. ret = IRQ_HANDLED;
  297. if (dev->primary->master) {
  298. master_priv = dev->primary->master->driver_priv;
  299. if (master_priv->sarea_priv)
  300. master_priv->sarea_priv->last_dispatch =
  301. READ_BREADCRUMB(dev_priv);
  302. }
  303. if (gt_iir & GT_USER_INTERRUPT)
  304. notify_ring(dev, &dev_priv->ring[RCS]);
  305. if (gt_iir & bsd_usr_interrupt)
  306. notify_ring(dev, &dev_priv->ring[VCS]);
  307. if (gt_iir & GT_BLT_USER_INTERRUPT)
  308. notify_ring(dev, &dev_priv->ring[BCS]);
  309. if (de_iir & DE_GSE)
  310. intel_opregion_gse_intr(dev);
  311. if (de_iir & DE_PLANEA_FLIP_DONE) {
  312. intel_prepare_page_flip(dev, 0);
  313. intel_finish_page_flip_plane(dev, 0);
  314. }
  315. if (de_iir & DE_PLANEB_FLIP_DONE) {
  316. intel_prepare_page_flip(dev, 1);
  317. intel_finish_page_flip_plane(dev, 1);
  318. }
  319. if (de_iir & DE_PIPEA_VBLANK)
  320. drm_handle_vblank(dev, 0);
  321. if (de_iir & DE_PIPEB_VBLANK)
  322. drm_handle_vblank(dev, 1);
  323. /* check event from PCH */
  324. if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
  325. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  326. if (de_iir & DE_PCU_EVENT) {
  327. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  328. i915_handle_rps_change(dev);
  329. }
  330. /* should clear PCH hotplug event before clear CPU irq */
  331. I915_WRITE(SDEIIR, pch_iir);
  332. I915_WRITE(GTIIR, gt_iir);
  333. I915_WRITE(DEIIR, de_iir);
  334. done:
  335. I915_WRITE(DEIER, de_ier);
  336. POSTING_READ(DEIER);
  337. return ret;
  338. }
  339. /**
  340. * i915_error_work_func - do process context error handling work
  341. * @work: work struct
  342. *
  343. * Fire an error uevent so userspace can see that a hang or error
  344. * was detected.
  345. */
  346. static void i915_error_work_func(struct work_struct *work)
  347. {
  348. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  349. error_work);
  350. struct drm_device *dev = dev_priv->dev;
  351. char *error_event[] = { "ERROR=1", NULL };
  352. char *reset_event[] = { "RESET=1", NULL };
  353. char *reset_done_event[] = { "ERROR=0", NULL };
  354. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  355. if (atomic_read(&dev_priv->mm.wedged)) {
  356. DRM_DEBUG_DRIVER("resetting chip\n");
  357. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
  358. if (!i915_reset(dev, GRDOM_RENDER)) {
  359. atomic_set(&dev_priv->mm.wedged, 0);
  360. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
  361. }
  362. complete_all(&dev_priv->error_completion);
  363. }
  364. }
  365. #ifdef CONFIG_DEBUG_FS
  366. static struct drm_i915_error_object *
  367. i915_error_object_create(struct drm_device *dev,
  368. struct drm_i915_gem_object *src)
  369. {
  370. drm_i915_private_t *dev_priv = dev->dev_private;
  371. struct drm_i915_error_object *dst;
  372. int page, page_count;
  373. u32 reloc_offset;
  374. if (src == NULL || src->pages == NULL)
  375. return NULL;
  376. page_count = src->base.size / PAGE_SIZE;
  377. dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
  378. if (dst == NULL)
  379. return NULL;
  380. reloc_offset = src->gtt_offset;
  381. for (page = 0; page < page_count; page++) {
  382. unsigned long flags;
  383. void __iomem *s;
  384. void *d;
  385. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  386. if (d == NULL)
  387. goto unwind;
  388. local_irq_save(flags);
  389. s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
  390. reloc_offset);
  391. memcpy_fromio(d, s, PAGE_SIZE);
  392. io_mapping_unmap_atomic(s);
  393. local_irq_restore(flags);
  394. dst->pages[page] = d;
  395. reloc_offset += PAGE_SIZE;
  396. }
  397. dst->page_count = page_count;
  398. dst->gtt_offset = src->gtt_offset;
  399. return dst;
  400. unwind:
  401. while (page--)
  402. kfree(dst->pages[page]);
  403. kfree(dst);
  404. return NULL;
  405. }
  406. static void
  407. i915_error_object_free(struct drm_i915_error_object *obj)
  408. {
  409. int page;
  410. if (obj == NULL)
  411. return;
  412. for (page = 0; page < obj->page_count; page++)
  413. kfree(obj->pages[page]);
  414. kfree(obj);
  415. }
  416. static void
  417. i915_error_state_free(struct drm_device *dev,
  418. struct drm_i915_error_state *error)
  419. {
  420. i915_error_object_free(error->batchbuffer[0]);
  421. i915_error_object_free(error->batchbuffer[1]);
  422. i915_error_object_free(error->ringbuffer);
  423. kfree(error->active_bo);
  424. kfree(error->overlay);
  425. kfree(error);
  426. }
  427. static u32
  428. i915_get_bbaddr(struct drm_device *dev, u32 *ring)
  429. {
  430. u32 cmd;
  431. if (IS_I830(dev) || IS_845G(dev))
  432. cmd = MI_BATCH_BUFFER;
  433. else if (INTEL_INFO(dev)->gen >= 4)
  434. cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
  435. MI_BATCH_NON_SECURE_I965);
  436. else
  437. cmd = (MI_BATCH_BUFFER_START | (2 << 6));
  438. return ring[0] == cmd ? ring[1] : 0;
  439. }
  440. static u32
  441. i915_ringbuffer_last_batch(struct drm_device *dev,
  442. struct intel_ring_buffer *ring)
  443. {
  444. struct drm_i915_private *dev_priv = dev->dev_private;
  445. u32 head, bbaddr;
  446. u32 *val;
  447. /* Locate the current position in the ringbuffer and walk back
  448. * to find the most recently dispatched batch buffer.
  449. */
  450. head = I915_READ_HEAD(ring) & HEAD_ADDR;
  451. val = (u32 *)(ring->virtual_start + head);
  452. while (--val >= (u32 *)ring->virtual_start) {
  453. bbaddr = i915_get_bbaddr(dev, val);
  454. if (bbaddr)
  455. return bbaddr;
  456. }
  457. val = (u32 *)(ring->virtual_start + ring->size);
  458. while (--val >= (u32 *)ring->virtual_start) {
  459. bbaddr = i915_get_bbaddr(dev, val);
  460. if (bbaddr)
  461. return bbaddr;
  462. }
  463. return 0;
  464. }
  465. static u32 capture_bo_list(struct drm_i915_error_buffer *err,
  466. int count,
  467. struct list_head *head)
  468. {
  469. struct drm_i915_gem_object *obj;
  470. int i = 0;
  471. list_for_each_entry(obj, head, mm_list) {
  472. err->size = obj->base.size;
  473. err->name = obj->base.name;
  474. err->seqno = obj->last_rendering_seqno;
  475. err->gtt_offset = obj->gtt_offset;
  476. err->read_domains = obj->base.read_domains;
  477. err->write_domain = obj->base.write_domain;
  478. err->fence_reg = obj->fence_reg;
  479. err->pinned = 0;
  480. if (obj->pin_count > 0)
  481. err->pinned = 1;
  482. if (obj->user_pin_count > 0)
  483. err->pinned = -1;
  484. err->tiling = obj->tiling_mode;
  485. err->dirty = obj->dirty;
  486. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  487. err->ring = obj->ring ? obj->ring->id : 0;
  488. if (++i == count)
  489. break;
  490. err++;
  491. }
  492. return i;
  493. }
  494. static void i915_gem_record_fences(struct drm_device *dev,
  495. struct drm_i915_error_state *error)
  496. {
  497. struct drm_i915_private *dev_priv = dev->dev_private;
  498. int i;
  499. /* Fences */
  500. switch (INTEL_INFO(dev)->gen) {
  501. case 6:
  502. for (i = 0; i < 16; i++)
  503. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  504. break;
  505. case 5:
  506. case 4:
  507. for (i = 0; i < 16; i++)
  508. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  509. break;
  510. case 3:
  511. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  512. for (i = 0; i < 8; i++)
  513. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  514. case 2:
  515. for (i = 0; i < 8; i++)
  516. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  517. break;
  518. }
  519. }
  520. /**
  521. * i915_capture_error_state - capture an error record for later analysis
  522. * @dev: drm device
  523. *
  524. * Should be called when an error is detected (either a hang or an error
  525. * interrupt) to capture error state from the time of the error. Fills
  526. * out a structure which becomes available in debugfs for user level tools
  527. * to pick up.
  528. */
  529. static void i915_capture_error_state(struct drm_device *dev)
  530. {
  531. struct drm_i915_private *dev_priv = dev->dev_private;
  532. struct drm_i915_gem_object *obj;
  533. struct drm_i915_error_state *error;
  534. struct drm_i915_gem_object *batchbuffer[2];
  535. unsigned long flags;
  536. u32 bbaddr;
  537. int count;
  538. spin_lock_irqsave(&dev_priv->error_lock, flags);
  539. error = dev_priv->first_error;
  540. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  541. if (error)
  542. return;
  543. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  544. if (!error) {
  545. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  546. return;
  547. }
  548. DRM_DEBUG_DRIVER("generating error event\n");
  549. error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
  550. error->eir = I915_READ(EIR);
  551. error->pgtbl_er = I915_READ(PGTBL_ER);
  552. error->pipeastat = I915_READ(PIPEASTAT);
  553. error->pipebstat = I915_READ(PIPEBSTAT);
  554. error->instpm = I915_READ(INSTPM);
  555. error->error = 0;
  556. if (INTEL_INFO(dev)->gen >= 6) {
  557. error->error = I915_READ(ERROR_GEN6);
  558. error->bcs_acthd = I915_READ(BCS_ACTHD);
  559. error->bcs_ipehr = I915_READ(BCS_IPEHR);
  560. error->bcs_ipeir = I915_READ(BCS_IPEIR);
  561. error->bcs_instdone = I915_READ(BCS_INSTDONE);
  562. error->bcs_seqno = 0;
  563. if (dev_priv->ring[BCS].get_seqno)
  564. error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
  565. error->vcs_acthd = I915_READ(VCS_ACTHD);
  566. error->vcs_ipehr = I915_READ(VCS_IPEHR);
  567. error->vcs_ipeir = I915_READ(VCS_IPEIR);
  568. error->vcs_instdone = I915_READ(VCS_INSTDONE);
  569. error->vcs_seqno = 0;
  570. if (dev_priv->ring[VCS].get_seqno)
  571. error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
  572. }
  573. if (INTEL_INFO(dev)->gen >= 4) {
  574. error->ipeir = I915_READ(IPEIR_I965);
  575. error->ipehr = I915_READ(IPEHR_I965);
  576. error->instdone = I915_READ(INSTDONE_I965);
  577. error->instps = I915_READ(INSTPS);
  578. error->instdone1 = I915_READ(INSTDONE1);
  579. error->acthd = I915_READ(ACTHD_I965);
  580. error->bbaddr = I915_READ64(BB_ADDR);
  581. } else {
  582. error->ipeir = I915_READ(IPEIR);
  583. error->ipehr = I915_READ(IPEHR);
  584. error->instdone = I915_READ(INSTDONE);
  585. error->acthd = I915_READ(ACTHD);
  586. error->bbaddr = 0;
  587. }
  588. i915_gem_record_fences(dev, error);
  589. bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->ring[RCS]);
  590. /* Grab the current batchbuffer, most likely to have crashed. */
  591. batchbuffer[0] = NULL;
  592. batchbuffer[1] = NULL;
  593. count = 0;
  594. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  595. if (batchbuffer[0] == NULL &&
  596. bbaddr >= obj->gtt_offset &&
  597. bbaddr < obj->gtt_offset + obj->base.size)
  598. batchbuffer[0] = obj;
  599. if (batchbuffer[1] == NULL &&
  600. error->acthd >= obj->gtt_offset &&
  601. error->acthd < obj->gtt_offset + obj->base.size)
  602. batchbuffer[1] = obj;
  603. count++;
  604. }
  605. /* Scan the other lists for completeness for those bizarre errors. */
  606. if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
  607. list_for_each_entry(obj, &dev_priv->mm.flushing_list, mm_list) {
  608. if (batchbuffer[0] == NULL &&
  609. bbaddr >= obj->gtt_offset &&
  610. bbaddr < obj->gtt_offset + obj->base.size)
  611. batchbuffer[0] = obj;
  612. if (batchbuffer[1] == NULL &&
  613. error->acthd >= obj->gtt_offset &&
  614. error->acthd < obj->gtt_offset + obj->base.size)
  615. batchbuffer[1] = obj;
  616. if (batchbuffer[0] && batchbuffer[1])
  617. break;
  618. }
  619. }
  620. if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
  621. list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
  622. if (batchbuffer[0] == NULL &&
  623. bbaddr >= obj->gtt_offset &&
  624. bbaddr < obj->gtt_offset + obj->base.size)
  625. batchbuffer[0] = obj;
  626. if (batchbuffer[1] == NULL &&
  627. error->acthd >= obj->gtt_offset &&
  628. error->acthd < obj->gtt_offset + obj->base.size)
  629. batchbuffer[1] = obj;
  630. if (batchbuffer[0] && batchbuffer[1])
  631. break;
  632. }
  633. }
  634. /* We need to copy these to an anonymous buffer as the simplest
  635. * method to avoid being overwritten by userspace.
  636. */
  637. error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
  638. if (batchbuffer[1] != batchbuffer[0])
  639. error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
  640. else
  641. error->batchbuffer[1] = NULL;
  642. /* Record the ringbuffer */
  643. error->ringbuffer = i915_error_object_create(dev,
  644. dev_priv->ring[RCS].obj);
  645. /* Record buffers on the active and pinned lists. */
  646. error->active_bo = NULL;
  647. error->pinned_bo = NULL;
  648. error->active_bo_count = count;
  649. list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
  650. count++;
  651. error->pinned_bo_count = count - error->active_bo_count;
  652. if (count) {
  653. error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
  654. GFP_ATOMIC);
  655. if (error->active_bo)
  656. error->pinned_bo =
  657. error->active_bo + error->active_bo_count;
  658. }
  659. if (error->active_bo)
  660. error->active_bo_count =
  661. capture_bo_list(error->active_bo,
  662. error->active_bo_count,
  663. &dev_priv->mm.active_list);
  664. if (error->pinned_bo)
  665. error->pinned_bo_count =
  666. capture_bo_list(error->pinned_bo,
  667. error->pinned_bo_count,
  668. &dev_priv->mm.pinned_list);
  669. do_gettimeofday(&error->time);
  670. error->overlay = intel_overlay_capture_error_state(dev);
  671. error->display = intel_display_capture_error_state(dev);
  672. spin_lock_irqsave(&dev_priv->error_lock, flags);
  673. if (dev_priv->first_error == NULL) {
  674. dev_priv->first_error = error;
  675. error = NULL;
  676. }
  677. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  678. if (error)
  679. i915_error_state_free(dev, error);
  680. }
  681. void i915_destroy_error_state(struct drm_device *dev)
  682. {
  683. struct drm_i915_private *dev_priv = dev->dev_private;
  684. struct drm_i915_error_state *error;
  685. spin_lock(&dev_priv->error_lock);
  686. error = dev_priv->first_error;
  687. dev_priv->first_error = NULL;
  688. spin_unlock(&dev_priv->error_lock);
  689. if (error)
  690. i915_error_state_free(dev, error);
  691. }
  692. #else
  693. #define i915_capture_error_state(x)
  694. #endif
  695. static void i915_report_and_clear_eir(struct drm_device *dev)
  696. {
  697. struct drm_i915_private *dev_priv = dev->dev_private;
  698. u32 eir = I915_READ(EIR);
  699. if (!eir)
  700. return;
  701. printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
  702. eir);
  703. if (IS_G4X(dev)) {
  704. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  705. u32 ipeir = I915_READ(IPEIR_I965);
  706. printk(KERN_ERR " IPEIR: 0x%08x\n",
  707. I915_READ(IPEIR_I965));
  708. printk(KERN_ERR " IPEHR: 0x%08x\n",
  709. I915_READ(IPEHR_I965));
  710. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  711. I915_READ(INSTDONE_I965));
  712. printk(KERN_ERR " INSTPS: 0x%08x\n",
  713. I915_READ(INSTPS));
  714. printk(KERN_ERR " INSTDONE1: 0x%08x\n",
  715. I915_READ(INSTDONE1));
  716. printk(KERN_ERR " ACTHD: 0x%08x\n",
  717. I915_READ(ACTHD_I965));
  718. I915_WRITE(IPEIR_I965, ipeir);
  719. POSTING_READ(IPEIR_I965);
  720. }
  721. if (eir & GM45_ERROR_PAGE_TABLE) {
  722. u32 pgtbl_err = I915_READ(PGTBL_ER);
  723. printk(KERN_ERR "page table error\n");
  724. printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
  725. pgtbl_err);
  726. I915_WRITE(PGTBL_ER, pgtbl_err);
  727. POSTING_READ(PGTBL_ER);
  728. }
  729. }
  730. if (!IS_GEN2(dev)) {
  731. if (eir & I915_ERROR_PAGE_TABLE) {
  732. u32 pgtbl_err = I915_READ(PGTBL_ER);
  733. printk(KERN_ERR "page table error\n");
  734. printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
  735. pgtbl_err);
  736. I915_WRITE(PGTBL_ER, pgtbl_err);
  737. POSTING_READ(PGTBL_ER);
  738. }
  739. }
  740. if (eir & I915_ERROR_MEMORY_REFRESH) {
  741. u32 pipea_stats = I915_READ(PIPEASTAT);
  742. u32 pipeb_stats = I915_READ(PIPEBSTAT);
  743. printk(KERN_ERR "memory refresh error\n");
  744. printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
  745. pipea_stats);
  746. printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
  747. pipeb_stats);
  748. /* pipestat has already been acked */
  749. }
  750. if (eir & I915_ERROR_INSTRUCTION) {
  751. printk(KERN_ERR "instruction error\n");
  752. printk(KERN_ERR " INSTPM: 0x%08x\n",
  753. I915_READ(INSTPM));
  754. if (INTEL_INFO(dev)->gen < 4) {
  755. u32 ipeir = I915_READ(IPEIR);
  756. printk(KERN_ERR " IPEIR: 0x%08x\n",
  757. I915_READ(IPEIR));
  758. printk(KERN_ERR " IPEHR: 0x%08x\n",
  759. I915_READ(IPEHR));
  760. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  761. I915_READ(INSTDONE));
  762. printk(KERN_ERR " ACTHD: 0x%08x\n",
  763. I915_READ(ACTHD));
  764. I915_WRITE(IPEIR, ipeir);
  765. POSTING_READ(IPEIR);
  766. } else {
  767. u32 ipeir = I915_READ(IPEIR_I965);
  768. printk(KERN_ERR " IPEIR: 0x%08x\n",
  769. I915_READ(IPEIR_I965));
  770. printk(KERN_ERR " IPEHR: 0x%08x\n",
  771. I915_READ(IPEHR_I965));
  772. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  773. I915_READ(INSTDONE_I965));
  774. printk(KERN_ERR " INSTPS: 0x%08x\n",
  775. I915_READ(INSTPS));
  776. printk(KERN_ERR " INSTDONE1: 0x%08x\n",
  777. I915_READ(INSTDONE1));
  778. printk(KERN_ERR " ACTHD: 0x%08x\n",
  779. I915_READ(ACTHD_I965));
  780. I915_WRITE(IPEIR_I965, ipeir);
  781. POSTING_READ(IPEIR_I965);
  782. }
  783. }
  784. I915_WRITE(EIR, eir);
  785. POSTING_READ(EIR);
  786. eir = I915_READ(EIR);
  787. if (eir) {
  788. /*
  789. * some errors might have become stuck,
  790. * mask them.
  791. */
  792. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  793. I915_WRITE(EMR, I915_READ(EMR) | eir);
  794. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  795. }
  796. }
  797. /**
  798. * i915_handle_error - handle an error interrupt
  799. * @dev: drm device
  800. *
  801. * Do some basic checking of regsiter state at error interrupt time and
  802. * dump it to the syslog. Also call i915_capture_error_state() to make
  803. * sure we get a record and make it available in debugfs. Fire a uevent
  804. * so userspace knows something bad happened (should trigger collection
  805. * of a ring dump etc.).
  806. */
  807. void i915_handle_error(struct drm_device *dev, bool wedged)
  808. {
  809. struct drm_i915_private *dev_priv = dev->dev_private;
  810. i915_capture_error_state(dev);
  811. i915_report_and_clear_eir(dev);
  812. if (wedged) {
  813. INIT_COMPLETION(dev_priv->error_completion);
  814. atomic_set(&dev_priv->mm.wedged, 1);
  815. /*
  816. * Wakeup waiting processes so they don't hang
  817. */
  818. wake_up_all(&dev_priv->ring[RCS].irq_queue);
  819. if (HAS_BSD(dev))
  820. wake_up_all(&dev_priv->ring[VCS].irq_queue);
  821. if (HAS_BLT(dev))
  822. wake_up_all(&dev_priv->ring[BCS].irq_queue);
  823. }
  824. queue_work(dev_priv->wq, &dev_priv->error_work);
  825. }
  826. static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  827. {
  828. drm_i915_private_t *dev_priv = dev->dev_private;
  829. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  830. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  831. struct drm_i915_gem_object *obj;
  832. struct intel_unpin_work *work;
  833. unsigned long flags;
  834. bool stall_detected;
  835. /* Ignore early vblank irqs */
  836. if (intel_crtc == NULL)
  837. return;
  838. spin_lock_irqsave(&dev->event_lock, flags);
  839. work = intel_crtc->unpin_work;
  840. if (work == NULL || work->pending || !work->enable_stall_check) {
  841. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  842. spin_unlock_irqrestore(&dev->event_lock, flags);
  843. return;
  844. }
  845. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  846. obj = work->pending_flip_obj;
  847. if (INTEL_INFO(dev)->gen >= 4) {
  848. int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
  849. stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
  850. } else {
  851. int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
  852. stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
  853. crtc->y * crtc->fb->pitch +
  854. crtc->x * crtc->fb->bits_per_pixel/8);
  855. }
  856. spin_unlock_irqrestore(&dev->event_lock, flags);
  857. if (stall_detected) {
  858. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  859. intel_prepare_page_flip(dev, intel_crtc->plane);
  860. }
  861. }
  862. irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
  863. {
  864. struct drm_device *dev = (struct drm_device *) arg;
  865. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  866. struct drm_i915_master_private *master_priv;
  867. u32 iir, new_iir;
  868. u32 pipea_stats, pipeb_stats;
  869. u32 vblank_status;
  870. int vblank = 0;
  871. unsigned long irqflags;
  872. int irq_received;
  873. int ret = IRQ_NONE;
  874. atomic_inc(&dev_priv->irq_received);
  875. if (HAS_PCH_SPLIT(dev))
  876. return ironlake_irq_handler(dev);
  877. iir = I915_READ(IIR);
  878. if (INTEL_INFO(dev)->gen >= 4)
  879. vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
  880. else
  881. vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
  882. for (;;) {
  883. irq_received = iir != 0;
  884. /* Can't rely on pipestat interrupt bit in iir as it might
  885. * have been cleared after the pipestat interrupt was received.
  886. * It doesn't set the bit in iir again, but it still produces
  887. * interrupts (for non-MSI).
  888. */
  889. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  890. pipea_stats = I915_READ(PIPEASTAT);
  891. pipeb_stats = I915_READ(PIPEBSTAT);
  892. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  893. i915_handle_error(dev, false);
  894. /*
  895. * Clear the PIPE(A|B)STAT regs before the IIR
  896. */
  897. if (pipea_stats & 0x8000ffff) {
  898. if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
  899. DRM_DEBUG_DRIVER("pipe a underrun\n");
  900. I915_WRITE(PIPEASTAT, pipea_stats);
  901. irq_received = 1;
  902. }
  903. if (pipeb_stats & 0x8000ffff) {
  904. if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
  905. DRM_DEBUG_DRIVER("pipe b underrun\n");
  906. I915_WRITE(PIPEBSTAT, pipeb_stats);
  907. irq_received = 1;
  908. }
  909. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  910. if (!irq_received)
  911. break;
  912. ret = IRQ_HANDLED;
  913. /* Consume port. Then clear IIR or we'll miss events */
  914. if ((I915_HAS_HOTPLUG(dev)) &&
  915. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  916. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  917. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  918. hotplug_status);
  919. if (hotplug_status & dev_priv->hotplug_supported_mask)
  920. queue_work(dev_priv->wq,
  921. &dev_priv->hotplug_work);
  922. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  923. I915_READ(PORT_HOTPLUG_STAT);
  924. }
  925. I915_WRITE(IIR, iir);
  926. new_iir = I915_READ(IIR); /* Flush posted writes */
  927. if (dev->primary->master) {
  928. master_priv = dev->primary->master->driver_priv;
  929. if (master_priv->sarea_priv)
  930. master_priv->sarea_priv->last_dispatch =
  931. READ_BREADCRUMB(dev_priv);
  932. }
  933. if (iir & I915_USER_INTERRUPT)
  934. notify_ring(dev, &dev_priv->ring[RCS]);
  935. if (iir & I915_BSD_USER_INTERRUPT)
  936. notify_ring(dev, &dev_priv->ring[VCS]);
  937. if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
  938. intel_prepare_page_flip(dev, 0);
  939. if (dev_priv->flip_pending_is_done)
  940. intel_finish_page_flip_plane(dev, 0);
  941. }
  942. if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
  943. intel_prepare_page_flip(dev, 1);
  944. if (dev_priv->flip_pending_is_done)
  945. intel_finish_page_flip_plane(dev, 1);
  946. }
  947. if (pipea_stats & vblank_status) {
  948. vblank++;
  949. drm_handle_vblank(dev, 0);
  950. if (!dev_priv->flip_pending_is_done) {
  951. i915_pageflip_stall_check(dev, 0);
  952. intel_finish_page_flip(dev, 0);
  953. }
  954. }
  955. if (pipeb_stats & vblank_status) {
  956. vblank++;
  957. drm_handle_vblank(dev, 1);
  958. if (!dev_priv->flip_pending_is_done) {
  959. i915_pageflip_stall_check(dev, 1);
  960. intel_finish_page_flip(dev, 1);
  961. }
  962. }
  963. if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
  964. (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
  965. (iir & I915_ASLE_INTERRUPT))
  966. intel_opregion_asle_intr(dev);
  967. /* With MSI, interrupts are only generated when iir
  968. * transitions from zero to nonzero. If another bit got
  969. * set while we were handling the existing iir bits, then
  970. * we would never get another interrupt.
  971. *
  972. * This is fine on non-MSI as well, as if we hit this path
  973. * we avoid exiting the interrupt handler only to generate
  974. * another one.
  975. *
  976. * Note that for MSI this could cause a stray interrupt report
  977. * if an interrupt landed in the time between writing IIR and
  978. * the posting read. This should be rare enough to never
  979. * trigger the 99% of 100,000 interrupts test for disabling
  980. * stray interrupts.
  981. */
  982. iir = new_iir;
  983. }
  984. return ret;
  985. }
  986. static int i915_emit_irq(struct drm_device * dev)
  987. {
  988. drm_i915_private_t *dev_priv = dev->dev_private;
  989. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  990. i915_kernel_lost_context(dev);
  991. DRM_DEBUG_DRIVER("\n");
  992. dev_priv->counter++;
  993. if (dev_priv->counter > 0x7FFFFFFFUL)
  994. dev_priv->counter = 1;
  995. if (master_priv->sarea_priv)
  996. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  997. if (BEGIN_LP_RING(4) == 0) {
  998. OUT_RING(MI_STORE_DWORD_INDEX);
  999. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  1000. OUT_RING(dev_priv->counter);
  1001. OUT_RING(MI_USER_INTERRUPT);
  1002. ADVANCE_LP_RING();
  1003. }
  1004. return dev_priv->counter;
  1005. }
  1006. void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
  1007. {
  1008. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1009. struct intel_ring_buffer *ring = LP_RING(dev_priv);
  1010. if (dev_priv->trace_irq_seqno == 0 &&
  1011. ring->irq_get(ring))
  1012. dev_priv->trace_irq_seqno = seqno;
  1013. }
  1014. static int i915_wait_irq(struct drm_device * dev, int irq_nr)
  1015. {
  1016. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1017. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  1018. int ret = 0;
  1019. struct intel_ring_buffer *ring = LP_RING(dev_priv);
  1020. DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
  1021. READ_BREADCRUMB(dev_priv));
  1022. if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
  1023. if (master_priv->sarea_priv)
  1024. master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  1025. return 0;
  1026. }
  1027. if (master_priv->sarea_priv)
  1028. master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  1029. ret = -ENODEV;
  1030. if (ring->irq_get(ring)) {
  1031. DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
  1032. READ_BREADCRUMB(dev_priv) >= irq_nr);
  1033. ring->irq_put(ring);
  1034. }
  1035. if (ret == -EBUSY) {
  1036. DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
  1037. READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
  1038. }
  1039. return ret;
  1040. }
  1041. /* Needs the lock as it touches the ring.
  1042. */
  1043. int i915_irq_emit(struct drm_device *dev, void *data,
  1044. struct drm_file *file_priv)
  1045. {
  1046. drm_i915_private_t *dev_priv = dev->dev_private;
  1047. drm_i915_irq_emit_t *emit = data;
  1048. int result;
  1049. if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
  1050. DRM_ERROR("called with no initialization\n");
  1051. return -EINVAL;
  1052. }
  1053. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  1054. mutex_lock(&dev->struct_mutex);
  1055. result = i915_emit_irq(dev);
  1056. mutex_unlock(&dev->struct_mutex);
  1057. if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
  1058. DRM_ERROR("copy_to_user\n");
  1059. return -EFAULT;
  1060. }
  1061. return 0;
  1062. }
  1063. /* Doesn't need the hardware lock.
  1064. */
  1065. int i915_irq_wait(struct drm_device *dev, void *data,
  1066. struct drm_file *file_priv)
  1067. {
  1068. drm_i915_private_t *dev_priv = dev->dev_private;
  1069. drm_i915_irq_wait_t *irqwait = data;
  1070. if (!dev_priv) {
  1071. DRM_ERROR("called with no initialization\n");
  1072. return -EINVAL;
  1073. }
  1074. return i915_wait_irq(dev, irqwait->irq_seq);
  1075. }
  1076. /* Called from drm generic code, passed 'crtc' which
  1077. * we use as a pipe index
  1078. */
  1079. int i915_enable_vblank(struct drm_device *dev, int pipe)
  1080. {
  1081. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1082. unsigned long irqflags;
  1083. if (!i915_pipe_enabled(dev, pipe))
  1084. return -EINVAL;
  1085. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1086. if (HAS_PCH_SPLIT(dev))
  1087. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  1088. DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
  1089. else if (INTEL_INFO(dev)->gen >= 4)
  1090. i915_enable_pipestat(dev_priv, pipe,
  1091. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1092. else
  1093. i915_enable_pipestat(dev_priv, pipe,
  1094. PIPE_VBLANK_INTERRUPT_ENABLE);
  1095. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1096. return 0;
  1097. }
  1098. /* Called from drm generic code, passed 'crtc' which
  1099. * we use as a pipe index
  1100. */
  1101. void i915_disable_vblank(struct drm_device *dev, int pipe)
  1102. {
  1103. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1104. unsigned long irqflags;
  1105. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1106. if (HAS_PCH_SPLIT(dev))
  1107. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  1108. DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
  1109. else
  1110. i915_disable_pipestat(dev_priv, pipe,
  1111. PIPE_VBLANK_INTERRUPT_ENABLE |
  1112. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1113. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1114. }
  1115. void i915_enable_interrupt (struct drm_device *dev)
  1116. {
  1117. struct drm_i915_private *dev_priv = dev->dev_private;
  1118. if (!HAS_PCH_SPLIT(dev))
  1119. intel_opregion_enable_asle(dev);
  1120. dev_priv->irq_enabled = 1;
  1121. }
  1122. /* Set the vblank monitor pipe
  1123. */
  1124. int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  1125. struct drm_file *file_priv)
  1126. {
  1127. drm_i915_private_t *dev_priv = dev->dev_private;
  1128. if (!dev_priv) {
  1129. DRM_ERROR("called with no initialization\n");
  1130. return -EINVAL;
  1131. }
  1132. return 0;
  1133. }
  1134. int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  1135. struct drm_file *file_priv)
  1136. {
  1137. drm_i915_private_t *dev_priv = dev->dev_private;
  1138. drm_i915_vblank_pipe_t *pipe = data;
  1139. if (!dev_priv) {
  1140. DRM_ERROR("called with no initialization\n");
  1141. return -EINVAL;
  1142. }
  1143. pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  1144. return 0;
  1145. }
  1146. /**
  1147. * Schedule buffer swap at given vertical blank.
  1148. */
  1149. int i915_vblank_swap(struct drm_device *dev, void *data,
  1150. struct drm_file *file_priv)
  1151. {
  1152. /* The delayed swap mechanism was fundamentally racy, and has been
  1153. * removed. The model was that the client requested a delayed flip/swap
  1154. * from the kernel, then waited for vblank before continuing to perform
  1155. * rendering. The problem was that the kernel might wake the client
  1156. * up before it dispatched the vblank swap (since the lock has to be
  1157. * held while touching the ringbuffer), in which case the client would
  1158. * clear and start the next frame before the swap occurred, and
  1159. * flicker would occur in addition to likely missing the vblank.
  1160. *
  1161. * In the absence of this ioctl, userland falls back to a correct path
  1162. * of waiting for a vblank, then dispatching the swap on its own.
  1163. * Context switching to userland and back is plenty fast enough for
  1164. * meeting the requirements of vblank swapping.
  1165. */
  1166. return -EINVAL;
  1167. }
  1168. static u32
  1169. ring_last_seqno(struct intel_ring_buffer *ring)
  1170. {
  1171. return list_entry(ring->request_list.prev,
  1172. struct drm_i915_gem_request, list)->seqno;
  1173. }
  1174. static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
  1175. {
  1176. if (list_empty(&ring->request_list) ||
  1177. i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
  1178. /* Issue a wake-up to catch stuck h/w. */
  1179. if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
  1180. DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
  1181. ring->name,
  1182. ring->waiting_seqno,
  1183. ring->get_seqno(ring));
  1184. wake_up_all(&ring->irq_queue);
  1185. *err = true;
  1186. }
  1187. return true;
  1188. }
  1189. return false;
  1190. }
  1191. static bool kick_ring(struct intel_ring_buffer *ring)
  1192. {
  1193. struct drm_device *dev = ring->dev;
  1194. struct drm_i915_private *dev_priv = dev->dev_private;
  1195. u32 tmp = I915_READ_CTL(ring);
  1196. if (tmp & RING_WAIT) {
  1197. DRM_ERROR("Kicking stuck wait on %s\n",
  1198. ring->name);
  1199. I915_WRITE_CTL(ring, tmp);
  1200. return true;
  1201. }
  1202. if (IS_GEN6(dev) &&
  1203. (tmp & RING_WAIT_SEMAPHORE)) {
  1204. DRM_ERROR("Kicking stuck semaphore on %s\n",
  1205. ring->name);
  1206. I915_WRITE_CTL(ring, tmp);
  1207. return true;
  1208. }
  1209. return false;
  1210. }
  1211. /**
  1212. * This is called when the chip hasn't reported back with completed
  1213. * batchbuffers in a long time. The first time this is called we simply record
  1214. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  1215. * again, we assume the chip is wedged and try to fix it.
  1216. */
  1217. void i915_hangcheck_elapsed(unsigned long data)
  1218. {
  1219. struct drm_device *dev = (struct drm_device *)data;
  1220. drm_i915_private_t *dev_priv = dev->dev_private;
  1221. uint32_t acthd, instdone, instdone1;
  1222. bool err = false;
  1223. /* If all work is done then ACTHD clearly hasn't advanced. */
  1224. if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
  1225. i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
  1226. i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
  1227. dev_priv->hangcheck_count = 0;
  1228. if (err)
  1229. goto repeat;
  1230. return;
  1231. }
  1232. if (INTEL_INFO(dev)->gen < 4) {
  1233. acthd = I915_READ(ACTHD);
  1234. instdone = I915_READ(INSTDONE);
  1235. instdone1 = 0;
  1236. } else {
  1237. acthd = I915_READ(ACTHD_I965);
  1238. instdone = I915_READ(INSTDONE_I965);
  1239. instdone1 = I915_READ(INSTDONE1);
  1240. }
  1241. if (dev_priv->last_acthd == acthd &&
  1242. dev_priv->last_instdone == instdone &&
  1243. dev_priv->last_instdone1 == instdone1) {
  1244. if (dev_priv->hangcheck_count++ > 1) {
  1245. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  1246. if (!IS_GEN2(dev)) {
  1247. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1248. * If so we can simply poke the RB_WAIT bit
  1249. * and break the hang. This should work on
  1250. * all but the second generation chipsets.
  1251. */
  1252. if (kick_ring(&dev_priv->ring[RCS]))
  1253. goto repeat;
  1254. if (HAS_BSD(dev) &&
  1255. kick_ring(&dev_priv->ring[VCS]))
  1256. goto repeat;
  1257. if (HAS_BLT(dev) &&
  1258. kick_ring(&dev_priv->ring[BCS]))
  1259. goto repeat;
  1260. }
  1261. i915_handle_error(dev, true);
  1262. return;
  1263. }
  1264. } else {
  1265. dev_priv->hangcheck_count = 0;
  1266. dev_priv->last_acthd = acthd;
  1267. dev_priv->last_instdone = instdone;
  1268. dev_priv->last_instdone1 = instdone1;
  1269. }
  1270. repeat:
  1271. /* Reset timer case chip hangs without another request being added */
  1272. mod_timer(&dev_priv->hangcheck_timer,
  1273. jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
  1274. }
  1275. /* drm_dma.h hooks
  1276. */
  1277. static void ironlake_irq_preinstall(struct drm_device *dev)
  1278. {
  1279. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1280. I915_WRITE(HWSTAM, 0xeffe);
  1281. /* XXX hotplug from PCH */
  1282. I915_WRITE(DEIMR, 0xffffffff);
  1283. I915_WRITE(DEIER, 0x0);
  1284. POSTING_READ(DEIER);
  1285. /* and GT */
  1286. I915_WRITE(GTIMR, 0xffffffff);
  1287. I915_WRITE(GTIER, 0x0);
  1288. POSTING_READ(GTIER);
  1289. /* south display irq */
  1290. I915_WRITE(SDEIMR, 0xffffffff);
  1291. I915_WRITE(SDEIER, 0x0);
  1292. POSTING_READ(SDEIER);
  1293. }
  1294. static int ironlake_irq_postinstall(struct drm_device *dev)
  1295. {
  1296. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1297. /* enable kind of interrupts always enabled */
  1298. u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  1299. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
  1300. u32 render_irqs;
  1301. u32 hotplug_mask;
  1302. dev_priv->irq_mask = ~display_mask;
  1303. /* should always can generate irq */
  1304. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1305. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1306. I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
  1307. POSTING_READ(DEIER);
  1308. dev_priv->gt_irq_mask = ~0;
  1309. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1310. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1311. if (IS_GEN6(dev)) {
  1312. I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_USER_INTERRUPT);
  1313. I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_USER_INTERRUPT);
  1314. I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
  1315. }
  1316. if (IS_GEN6(dev))
  1317. render_irqs =
  1318. GT_USER_INTERRUPT |
  1319. GT_GEN6_BSD_USER_INTERRUPT |
  1320. GT_BLT_USER_INTERRUPT;
  1321. else
  1322. render_irqs =
  1323. GT_USER_INTERRUPT |
  1324. GT_BSD_USER_INTERRUPT;
  1325. I915_WRITE(GTIER, render_irqs);
  1326. POSTING_READ(GTIER);
  1327. if (HAS_PCH_CPT(dev)) {
  1328. hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT |
  1329. SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
  1330. } else {
  1331. hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
  1332. SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
  1333. }
  1334. dev_priv->pch_irq_mask = ~hotplug_mask;
  1335. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1336. I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
  1337. I915_WRITE(SDEIER, hotplug_mask);
  1338. POSTING_READ(SDEIER);
  1339. if (IS_IRONLAKE_M(dev)) {
  1340. /* Clear & enable PCU event interrupts */
  1341. I915_WRITE(DEIIR, DE_PCU_EVENT);
  1342. I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
  1343. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  1344. }
  1345. return 0;
  1346. }
  1347. void i915_driver_irq_preinstall(struct drm_device * dev)
  1348. {
  1349. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1350. atomic_set(&dev_priv->irq_received, 0);
  1351. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  1352. INIT_WORK(&dev_priv->error_work, i915_error_work_func);
  1353. if (HAS_PCH_SPLIT(dev)) {
  1354. ironlake_irq_preinstall(dev);
  1355. return;
  1356. }
  1357. if (I915_HAS_HOTPLUG(dev)) {
  1358. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1359. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1360. }
  1361. I915_WRITE(HWSTAM, 0xeffe);
  1362. I915_WRITE(PIPEASTAT, 0);
  1363. I915_WRITE(PIPEBSTAT, 0);
  1364. I915_WRITE(IMR, 0xffffffff);
  1365. I915_WRITE(IER, 0x0);
  1366. POSTING_READ(IER);
  1367. }
  1368. /*
  1369. * Must be called after intel_modeset_init or hotplug interrupts won't be
  1370. * enabled correctly.
  1371. */
  1372. int i915_driver_irq_postinstall(struct drm_device *dev)
  1373. {
  1374. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1375. u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
  1376. u32 error_mask;
  1377. DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
  1378. if (HAS_BSD(dev))
  1379. DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
  1380. if (HAS_BLT(dev))
  1381. DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
  1382. dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  1383. if (HAS_PCH_SPLIT(dev))
  1384. return ironlake_irq_postinstall(dev);
  1385. /* Unmask the interrupts that we always want on. */
  1386. dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
  1387. dev_priv->pipestat[0] = 0;
  1388. dev_priv->pipestat[1] = 0;
  1389. if (I915_HAS_HOTPLUG(dev)) {
  1390. /* Enable in IER... */
  1391. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  1392. /* and unmask in IMR */
  1393. dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  1394. }
  1395. /*
  1396. * Enable some error detection, note the instruction error mask
  1397. * bit is reserved, so we leave it masked.
  1398. */
  1399. if (IS_G4X(dev)) {
  1400. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  1401. GM45_ERROR_MEM_PRIV |
  1402. GM45_ERROR_CP_PRIV |
  1403. I915_ERROR_MEMORY_REFRESH);
  1404. } else {
  1405. error_mask = ~(I915_ERROR_PAGE_TABLE |
  1406. I915_ERROR_MEMORY_REFRESH);
  1407. }
  1408. I915_WRITE(EMR, error_mask);
  1409. I915_WRITE(IMR, dev_priv->irq_mask);
  1410. I915_WRITE(IER, enable_mask);
  1411. POSTING_READ(IER);
  1412. if (I915_HAS_HOTPLUG(dev)) {
  1413. u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  1414. /* Note HDMI and DP share bits */
  1415. if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
  1416. hotplug_en |= HDMIB_HOTPLUG_INT_EN;
  1417. if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
  1418. hotplug_en |= HDMIC_HOTPLUG_INT_EN;
  1419. if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
  1420. hotplug_en |= HDMID_HOTPLUG_INT_EN;
  1421. if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
  1422. hotplug_en |= SDVOC_HOTPLUG_INT_EN;
  1423. if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
  1424. hotplug_en |= SDVOB_HOTPLUG_INT_EN;
  1425. if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
  1426. hotplug_en |= CRT_HOTPLUG_INT_EN;
  1427. /* Programming the CRT detection parameters tends
  1428. to generate a spurious hotplug event about three
  1429. seconds later. So just do it once.
  1430. */
  1431. if (IS_G4X(dev))
  1432. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  1433. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  1434. }
  1435. /* Ignore TV since it's buggy */
  1436. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  1437. }
  1438. intel_opregion_enable_asle(dev);
  1439. return 0;
  1440. }
  1441. static void ironlake_irq_uninstall(struct drm_device *dev)
  1442. {
  1443. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1444. I915_WRITE(HWSTAM, 0xffffffff);
  1445. I915_WRITE(DEIMR, 0xffffffff);
  1446. I915_WRITE(DEIER, 0x0);
  1447. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1448. I915_WRITE(GTIMR, 0xffffffff);
  1449. I915_WRITE(GTIER, 0x0);
  1450. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1451. }
  1452. void i915_driver_irq_uninstall(struct drm_device * dev)
  1453. {
  1454. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1455. if (!dev_priv)
  1456. return;
  1457. dev_priv->vblank_pipe = 0;
  1458. if (HAS_PCH_SPLIT(dev)) {
  1459. ironlake_irq_uninstall(dev);
  1460. return;
  1461. }
  1462. if (I915_HAS_HOTPLUG(dev)) {
  1463. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1464. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1465. }
  1466. I915_WRITE(HWSTAM, 0xffffffff);
  1467. I915_WRITE(PIPEASTAT, 0);
  1468. I915_WRITE(PIPEBSTAT, 0);
  1469. I915_WRITE(IMR, 0xffffffff);
  1470. I915_WRITE(IER, 0x0);
  1471. I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
  1472. I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
  1473. I915_WRITE(IIR, I915_READ(IIR));
  1474. }