main.c 59 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. if (!ath_drain_all_txq(sc, retry_tx))
  170. ret = false;
  171. if (!flush) {
  172. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  173. ath_rx_tasklet(sc, 1, true);
  174. ath_rx_tasklet(sc, 1, false);
  175. } else {
  176. ath_flushrecv(sc);
  177. }
  178. return ret;
  179. }
  180. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. struct ath_common *common = ath9k_hw_common(ah);
  184. unsigned long flags;
  185. if (ath_startrecv(sc) != 0) {
  186. ath_err(common, "Unable to restart recv logic\n");
  187. return false;
  188. }
  189. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  190. sc->config.txpowlimit, &sc->curtxpow);
  191. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  192. ath9k_hw_set_interrupts(ah);
  193. ath9k_hw_enable_interrupts(ah);
  194. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  195. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  196. goto work;
  197. ath9k_set_beacon(sc);
  198. if (ah->opmode == NL80211_IFTYPE_STATION &&
  199. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  200. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  201. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  202. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  203. }
  204. work:
  205. ath_restart_work(sc);
  206. }
  207. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  208. ath_ant_comb_update(sc);
  209. ieee80211_wake_queues(sc->hw);
  210. return true;
  211. }
  212. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  213. bool retry_tx)
  214. {
  215. struct ath_hw *ah = sc->sc_ah;
  216. struct ath_common *common = ath9k_hw_common(ah);
  217. struct ath9k_hw_cal_data *caldata = NULL;
  218. bool fastcc = true;
  219. bool flush = false;
  220. int r;
  221. __ath_cancel_work(sc);
  222. spin_lock_bh(&sc->sc_pcu_lock);
  223. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  224. fastcc = false;
  225. caldata = &sc->caldata;
  226. }
  227. if (!hchan) {
  228. fastcc = false;
  229. flush = true;
  230. hchan = ah->curchan;
  231. }
  232. if (!ath_prepare_reset(sc, retry_tx, flush))
  233. fastcc = false;
  234. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  235. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  236. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  237. if (r) {
  238. ath_err(common,
  239. "Unable to reset channel, reset status %d\n", r);
  240. goto out;
  241. }
  242. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  243. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  244. ath9k_mci_set_txpower(sc, true, false);
  245. if (!ath_complete_reset(sc, true))
  246. r = -EIO;
  247. out:
  248. spin_unlock_bh(&sc->sc_pcu_lock);
  249. return r;
  250. }
  251. /*
  252. * Set/change channels. If the channel is really being changed, it's done
  253. * by reseting the chip. To accomplish this we must first cleanup any pending
  254. * DMA, then restart stuff.
  255. */
  256. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  257. struct ath9k_channel *hchan)
  258. {
  259. int r;
  260. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  261. return -EIO;
  262. r = ath_reset_internal(sc, hchan, false);
  263. return r;
  264. }
  265. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  266. struct ieee80211_vif *vif)
  267. {
  268. struct ath_node *an;
  269. u8 density;
  270. an = (struct ath_node *)sta->drv_priv;
  271. #ifdef CONFIG_ATH9K_DEBUGFS
  272. spin_lock(&sc->nodes_lock);
  273. list_add(&an->list, &sc->nodes);
  274. spin_unlock(&sc->nodes_lock);
  275. #endif
  276. an->sta = sta;
  277. an->vif = vif;
  278. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  279. ath_tx_node_init(sc, an);
  280. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  281. sta->ht_cap.ampdu_factor);
  282. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  283. an->mpdudensity = density;
  284. }
  285. }
  286. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  287. {
  288. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  289. #ifdef CONFIG_ATH9K_DEBUGFS
  290. spin_lock(&sc->nodes_lock);
  291. list_del(&an->list);
  292. spin_unlock(&sc->nodes_lock);
  293. an->sta = NULL;
  294. #endif
  295. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  296. ath_tx_node_cleanup(sc, an);
  297. }
  298. void ath9k_tasklet(unsigned long data)
  299. {
  300. struct ath_softc *sc = (struct ath_softc *)data;
  301. struct ath_hw *ah = sc->sc_ah;
  302. struct ath_common *common = ath9k_hw_common(ah);
  303. enum ath_reset_type type;
  304. unsigned long flags;
  305. u32 status = sc->intrstatus;
  306. u32 rxmask;
  307. ath9k_ps_wakeup(sc);
  308. spin_lock(&sc->sc_pcu_lock);
  309. if ((status & ATH9K_INT_FATAL) ||
  310. (status & ATH9K_INT_BB_WATCHDOG)) {
  311. if (status & ATH9K_INT_FATAL)
  312. type = RESET_TYPE_FATAL_INT;
  313. else
  314. type = RESET_TYPE_BB_WATCHDOG;
  315. ath9k_queue_reset(sc, type);
  316. goto out;
  317. }
  318. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  319. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  320. /*
  321. * TSF sync does not look correct; remain awake to sync with
  322. * the next Beacon.
  323. */
  324. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  325. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  326. }
  327. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  328. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  329. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  330. ATH9K_INT_RXORN);
  331. else
  332. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  333. if (status & rxmask) {
  334. /* Check for high priority Rx first */
  335. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  336. (status & ATH9K_INT_RXHP))
  337. ath_rx_tasklet(sc, 0, true);
  338. ath_rx_tasklet(sc, 0, false);
  339. }
  340. if (status & ATH9K_INT_TX) {
  341. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  342. ath_tx_edma_tasklet(sc);
  343. else
  344. ath_tx_tasklet(sc);
  345. }
  346. ath9k_btcoex_handle_interrupt(sc, status);
  347. out:
  348. /* re-enable hardware interrupt */
  349. ath9k_hw_enable_interrupts(ah);
  350. spin_unlock(&sc->sc_pcu_lock);
  351. ath9k_ps_restore(sc);
  352. }
  353. irqreturn_t ath_isr(int irq, void *dev)
  354. {
  355. #define SCHED_INTR ( \
  356. ATH9K_INT_FATAL | \
  357. ATH9K_INT_BB_WATCHDOG | \
  358. ATH9K_INT_RXORN | \
  359. ATH9K_INT_RXEOL | \
  360. ATH9K_INT_RX | \
  361. ATH9K_INT_RXLP | \
  362. ATH9K_INT_RXHP | \
  363. ATH9K_INT_TX | \
  364. ATH9K_INT_BMISS | \
  365. ATH9K_INT_CST | \
  366. ATH9K_INT_TSFOOR | \
  367. ATH9K_INT_GENTIMER | \
  368. ATH9K_INT_MCI)
  369. struct ath_softc *sc = dev;
  370. struct ath_hw *ah = sc->sc_ah;
  371. struct ath_common *common = ath9k_hw_common(ah);
  372. enum ath9k_int status;
  373. bool sched = false;
  374. /*
  375. * The hardware is not ready/present, don't
  376. * touch anything. Note this can happen early
  377. * on if the IRQ is shared.
  378. */
  379. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  380. return IRQ_NONE;
  381. /* shared irq, not for us */
  382. if (!ath9k_hw_intrpend(ah))
  383. return IRQ_NONE;
  384. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  385. ath9k_hw_kill_interrupts(ah);
  386. return IRQ_HANDLED;
  387. }
  388. /*
  389. * Figure out the reason(s) for the interrupt. Note
  390. * that the hal returns a pseudo-ISR that may include
  391. * bits we haven't explicitly enabled so we mask the
  392. * value to insure we only process bits we requested.
  393. */
  394. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  395. status &= ah->imask; /* discard unasked-for bits */
  396. /*
  397. * If there are no status bits set, then this interrupt was not
  398. * for me (should have been caught above).
  399. */
  400. if (!status)
  401. return IRQ_NONE;
  402. /* Cache the status */
  403. sc->intrstatus = status;
  404. if (status & SCHED_INTR)
  405. sched = true;
  406. #ifdef CONFIG_PM_SLEEP
  407. if (status & ATH9K_INT_BMISS) {
  408. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  409. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  410. atomic_inc(&sc->wow_got_bmiss_intr);
  411. atomic_dec(&sc->wow_sleep_proc_intr);
  412. }
  413. ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
  414. }
  415. #endif
  416. /*
  417. * If a FATAL or RXORN interrupt is received, we have to reset the
  418. * chip immediately.
  419. */
  420. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  421. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  422. goto chip_reset;
  423. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  424. (status & ATH9K_INT_BB_WATCHDOG)) {
  425. spin_lock(&common->cc_lock);
  426. ath_hw_cycle_counters_update(common);
  427. ar9003_hw_bb_watchdog_dbg_info(ah);
  428. spin_unlock(&common->cc_lock);
  429. goto chip_reset;
  430. }
  431. if (status & ATH9K_INT_SWBA)
  432. tasklet_schedule(&sc->bcon_tasklet);
  433. if (status & ATH9K_INT_TXURN)
  434. ath9k_hw_updatetxtriglevel(ah, true);
  435. if (status & ATH9K_INT_RXEOL) {
  436. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  437. ath9k_hw_set_interrupts(ah);
  438. }
  439. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  440. if (status & ATH9K_INT_TIM_TIMER) {
  441. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  442. goto chip_reset;
  443. /* Clear RxAbort bit so that we can
  444. * receive frames */
  445. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  446. spin_lock(&sc->sc_pm_lock);
  447. ath9k_hw_setrxabort(sc->sc_ah, 0);
  448. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  449. spin_unlock(&sc->sc_pm_lock);
  450. }
  451. chip_reset:
  452. ath_debug_stat_interrupt(sc, status);
  453. if (sched) {
  454. /* turn off every interrupt */
  455. ath9k_hw_disable_interrupts(ah);
  456. tasklet_schedule(&sc->intr_tq);
  457. }
  458. return IRQ_HANDLED;
  459. #undef SCHED_INTR
  460. }
  461. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  462. {
  463. int r;
  464. ath9k_ps_wakeup(sc);
  465. r = ath_reset_internal(sc, NULL, retry_tx);
  466. if (retry_tx) {
  467. int i;
  468. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  469. if (ATH_TXQ_SETUP(sc, i)) {
  470. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  471. ath_txq_schedule(sc, &sc->tx.txq[i]);
  472. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  473. }
  474. }
  475. }
  476. ath9k_ps_restore(sc);
  477. return r;
  478. }
  479. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  480. {
  481. #ifdef CONFIG_ATH9K_DEBUGFS
  482. RESET_STAT_INC(sc, type);
  483. #endif
  484. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  485. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  486. }
  487. void ath_reset_work(struct work_struct *work)
  488. {
  489. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  490. ath_reset(sc, true);
  491. }
  492. /**********************/
  493. /* mac80211 callbacks */
  494. /**********************/
  495. static int ath9k_start(struct ieee80211_hw *hw)
  496. {
  497. struct ath_softc *sc = hw->priv;
  498. struct ath_hw *ah = sc->sc_ah;
  499. struct ath_common *common = ath9k_hw_common(ah);
  500. struct ieee80211_channel *curchan = hw->conf.channel;
  501. struct ath9k_channel *init_channel;
  502. int r;
  503. ath_dbg(common, CONFIG,
  504. "Starting driver with initial channel: %d MHz\n",
  505. curchan->center_freq);
  506. ath9k_ps_wakeup(sc);
  507. mutex_lock(&sc->mutex);
  508. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  509. /* Reset SERDES registers */
  510. ath9k_hw_configpcipowersave(ah, false);
  511. /*
  512. * The basic interface to setting the hardware in a good
  513. * state is ``reset''. On return the hardware is known to
  514. * be powered up and with interrupts disabled. This must
  515. * be followed by initialization of the appropriate bits
  516. * and then setup of the interrupt mask.
  517. */
  518. spin_lock_bh(&sc->sc_pcu_lock);
  519. atomic_set(&ah->intr_ref_cnt, -1);
  520. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  521. if (r) {
  522. ath_err(common,
  523. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  524. r, curchan->center_freq);
  525. ah->reset_power_on = false;
  526. }
  527. /* Setup our intr mask. */
  528. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  529. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  530. ATH9K_INT_GLOBAL;
  531. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  532. ah->imask |= ATH9K_INT_RXHP |
  533. ATH9K_INT_RXLP |
  534. ATH9K_INT_BB_WATCHDOG;
  535. else
  536. ah->imask |= ATH9K_INT_RX;
  537. ah->imask |= ATH9K_INT_GTT;
  538. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  539. ah->imask |= ATH9K_INT_CST;
  540. ath_mci_enable(sc);
  541. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  542. sc->sc_ah->is_monitoring = false;
  543. if (!ath_complete_reset(sc, false))
  544. ah->reset_power_on = false;
  545. if (ah->led_pin >= 0) {
  546. ath9k_hw_cfg_output(ah, ah->led_pin,
  547. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  548. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  549. }
  550. /*
  551. * Reset key cache to sane defaults (all entries cleared) instead of
  552. * semi-random values after suspend/resume.
  553. */
  554. ath9k_cmn_init_crypto(sc->sc_ah);
  555. spin_unlock_bh(&sc->sc_pcu_lock);
  556. mutex_unlock(&sc->mutex);
  557. ath9k_ps_restore(sc);
  558. return 0;
  559. }
  560. static void ath9k_tx(struct ieee80211_hw *hw,
  561. struct ieee80211_tx_control *control,
  562. struct sk_buff *skb)
  563. {
  564. struct ath_softc *sc = hw->priv;
  565. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  566. struct ath_tx_control txctl;
  567. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  568. unsigned long flags;
  569. if (sc->ps_enabled) {
  570. /*
  571. * mac80211 does not set PM field for normal data frames, so we
  572. * need to update that based on the current PS mode.
  573. */
  574. if (ieee80211_is_data(hdr->frame_control) &&
  575. !ieee80211_is_nullfunc(hdr->frame_control) &&
  576. !ieee80211_has_pm(hdr->frame_control)) {
  577. ath_dbg(common, PS,
  578. "Add PM=1 for a TX frame while in PS mode\n");
  579. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  580. }
  581. }
  582. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  583. /*
  584. * We are using PS-Poll and mac80211 can request TX while in
  585. * power save mode. Need to wake up hardware for the TX to be
  586. * completed and if needed, also for RX of buffered frames.
  587. */
  588. ath9k_ps_wakeup(sc);
  589. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  590. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  591. ath9k_hw_setrxabort(sc->sc_ah, 0);
  592. if (ieee80211_is_pspoll(hdr->frame_control)) {
  593. ath_dbg(common, PS,
  594. "Sending PS-Poll to pick a buffered frame\n");
  595. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  596. } else {
  597. ath_dbg(common, PS, "Wake up to complete TX\n");
  598. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  599. }
  600. /*
  601. * The actual restore operation will happen only after
  602. * the ps_flags bit is cleared. We are just dropping
  603. * the ps_usecount here.
  604. */
  605. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  606. ath9k_ps_restore(sc);
  607. }
  608. /*
  609. * Cannot tx while the hardware is in full sleep, it first needs a full
  610. * chip reset to recover from that
  611. */
  612. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  613. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  614. goto exit;
  615. }
  616. memset(&txctl, 0, sizeof(struct ath_tx_control));
  617. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  618. txctl.sta = control->sta;
  619. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  620. if (ath_tx_start(hw, skb, &txctl) != 0) {
  621. ath_dbg(common, XMIT, "TX failed\n");
  622. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  623. goto exit;
  624. }
  625. return;
  626. exit:
  627. ieee80211_free_txskb(hw, skb);
  628. }
  629. static void ath9k_stop(struct ieee80211_hw *hw)
  630. {
  631. struct ath_softc *sc = hw->priv;
  632. struct ath_hw *ah = sc->sc_ah;
  633. struct ath_common *common = ath9k_hw_common(ah);
  634. bool prev_idle;
  635. mutex_lock(&sc->mutex);
  636. ath_cancel_work(sc);
  637. del_timer_sync(&sc->rx_poll_timer);
  638. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  639. ath_dbg(common, ANY, "Device not present\n");
  640. mutex_unlock(&sc->mutex);
  641. return;
  642. }
  643. /* Ensure HW is awake when we try to shut it down. */
  644. ath9k_ps_wakeup(sc);
  645. spin_lock_bh(&sc->sc_pcu_lock);
  646. /* prevent tasklets to enable interrupts once we disable them */
  647. ah->imask &= ~ATH9K_INT_GLOBAL;
  648. /* make sure h/w will not generate any interrupt
  649. * before setting the invalid flag. */
  650. ath9k_hw_disable_interrupts(ah);
  651. spin_unlock_bh(&sc->sc_pcu_lock);
  652. /* we can now sync irq and kill any running tasklets, since we already
  653. * disabled interrupts and not holding a spin lock */
  654. synchronize_irq(sc->irq);
  655. tasklet_kill(&sc->intr_tq);
  656. tasklet_kill(&sc->bcon_tasklet);
  657. prev_idle = sc->ps_idle;
  658. sc->ps_idle = true;
  659. spin_lock_bh(&sc->sc_pcu_lock);
  660. if (ah->led_pin >= 0) {
  661. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  662. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  663. }
  664. ath_prepare_reset(sc, false, true);
  665. if (sc->rx.frag) {
  666. dev_kfree_skb_any(sc->rx.frag);
  667. sc->rx.frag = NULL;
  668. }
  669. if (!ah->curchan)
  670. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  671. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  672. ath9k_hw_phy_disable(ah);
  673. ath9k_hw_configpcipowersave(ah, true);
  674. spin_unlock_bh(&sc->sc_pcu_lock);
  675. ath9k_ps_restore(sc);
  676. set_bit(SC_OP_INVALID, &sc->sc_flags);
  677. sc->ps_idle = prev_idle;
  678. mutex_unlock(&sc->mutex);
  679. ath_dbg(common, CONFIG, "Driver halt\n");
  680. }
  681. bool ath9k_uses_beacons(int type)
  682. {
  683. switch (type) {
  684. case NL80211_IFTYPE_AP:
  685. case NL80211_IFTYPE_ADHOC:
  686. case NL80211_IFTYPE_MESH_POINT:
  687. return true;
  688. default:
  689. return false;
  690. }
  691. }
  692. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  693. {
  694. struct ath9k_vif_iter_data *iter_data = data;
  695. int i;
  696. if (iter_data->hw_macaddr)
  697. for (i = 0; i < ETH_ALEN; i++)
  698. iter_data->mask[i] &=
  699. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  700. switch (vif->type) {
  701. case NL80211_IFTYPE_AP:
  702. iter_data->naps++;
  703. break;
  704. case NL80211_IFTYPE_STATION:
  705. iter_data->nstations++;
  706. break;
  707. case NL80211_IFTYPE_ADHOC:
  708. iter_data->nadhocs++;
  709. break;
  710. case NL80211_IFTYPE_MESH_POINT:
  711. iter_data->nmeshes++;
  712. break;
  713. case NL80211_IFTYPE_WDS:
  714. iter_data->nwds++;
  715. break;
  716. default:
  717. break;
  718. }
  719. }
  720. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  721. {
  722. struct ath_softc *sc = data;
  723. struct ath_vif *avp = (void *)vif->drv_priv;
  724. if (vif->type != NL80211_IFTYPE_STATION)
  725. return;
  726. if (avp->primary_sta_vif)
  727. ath9k_set_assoc_state(sc, vif);
  728. }
  729. /* Called with sc->mutex held. */
  730. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  731. struct ieee80211_vif *vif,
  732. struct ath9k_vif_iter_data *iter_data)
  733. {
  734. struct ath_softc *sc = hw->priv;
  735. struct ath_hw *ah = sc->sc_ah;
  736. struct ath_common *common = ath9k_hw_common(ah);
  737. /*
  738. * Use the hardware MAC address as reference, the hardware uses it
  739. * together with the BSSID mask when matching addresses.
  740. */
  741. memset(iter_data, 0, sizeof(*iter_data));
  742. iter_data->hw_macaddr = common->macaddr;
  743. memset(&iter_data->mask, 0xff, ETH_ALEN);
  744. if (vif)
  745. ath9k_vif_iter(iter_data, vif->addr, vif);
  746. /* Get list of all active MAC addresses */
  747. ieee80211_iterate_active_interfaces_atomic(
  748. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  749. ath9k_vif_iter, iter_data);
  750. }
  751. /* Called with sc->mutex held. */
  752. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  753. struct ieee80211_vif *vif)
  754. {
  755. struct ath_softc *sc = hw->priv;
  756. struct ath_hw *ah = sc->sc_ah;
  757. struct ath_common *common = ath9k_hw_common(ah);
  758. struct ath9k_vif_iter_data iter_data;
  759. enum nl80211_iftype old_opmode = ah->opmode;
  760. ath9k_calculate_iter_data(hw, vif, &iter_data);
  761. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  762. ath_hw_setbssidmask(common);
  763. if (iter_data.naps > 0) {
  764. ath9k_hw_set_tsfadjust(ah, true);
  765. ah->opmode = NL80211_IFTYPE_AP;
  766. } else {
  767. ath9k_hw_set_tsfadjust(ah, false);
  768. if (iter_data.nmeshes)
  769. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  770. else if (iter_data.nwds)
  771. ah->opmode = NL80211_IFTYPE_AP;
  772. else if (iter_data.nadhocs)
  773. ah->opmode = NL80211_IFTYPE_ADHOC;
  774. else
  775. ah->opmode = NL80211_IFTYPE_STATION;
  776. }
  777. ath9k_hw_setopmode(ah);
  778. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  779. ah->imask |= ATH9K_INT_TSFOOR;
  780. else
  781. ah->imask &= ~ATH9K_INT_TSFOOR;
  782. ath9k_hw_set_interrupts(ah);
  783. /*
  784. * If we are changing the opmode to STATION,
  785. * a beacon sync needs to be done.
  786. */
  787. if (ah->opmode == NL80211_IFTYPE_STATION &&
  788. old_opmode == NL80211_IFTYPE_AP &&
  789. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  790. ieee80211_iterate_active_interfaces_atomic(
  791. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  792. ath9k_sta_vif_iter, sc);
  793. }
  794. }
  795. static int ath9k_add_interface(struct ieee80211_hw *hw,
  796. struct ieee80211_vif *vif)
  797. {
  798. struct ath_softc *sc = hw->priv;
  799. struct ath_hw *ah = sc->sc_ah;
  800. struct ath_common *common = ath9k_hw_common(ah);
  801. mutex_lock(&sc->mutex);
  802. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  803. sc->nvifs++;
  804. ath9k_ps_wakeup(sc);
  805. ath9k_calculate_summary_state(hw, vif);
  806. ath9k_ps_restore(sc);
  807. if (ath9k_uses_beacons(vif->type))
  808. ath9k_beacon_assign_slot(sc, vif);
  809. mutex_unlock(&sc->mutex);
  810. return 0;
  811. }
  812. static int ath9k_change_interface(struct ieee80211_hw *hw,
  813. struct ieee80211_vif *vif,
  814. enum nl80211_iftype new_type,
  815. bool p2p)
  816. {
  817. struct ath_softc *sc = hw->priv;
  818. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  819. ath_dbg(common, CONFIG, "Change Interface\n");
  820. mutex_lock(&sc->mutex);
  821. if (ath9k_uses_beacons(vif->type))
  822. ath9k_beacon_remove_slot(sc, vif);
  823. vif->type = new_type;
  824. vif->p2p = p2p;
  825. ath9k_ps_wakeup(sc);
  826. ath9k_calculate_summary_state(hw, vif);
  827. ath9k_ps_restore(sc);
  828. if (ath9k_uses_beacons(vif->type))
  829. ath9k_beacon_assign_slot(sc, vif);
  830. mutex_unlock(&sc->mutex);
  831. return 0;
  832. }
  833. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  834. struct ieee80211_vif *vif)
  835. {
  836. struct ath_softc *sc = hw->priv;
  837. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  838. ath_dbg(common, CONFIG, "Detach Interface\n");
  839. mutex_lock(&sc->mutex);
  840. sc->nvifs--;
  841. if (ath9k_uses_beacons(vif->type))
  842. ath9k_beacon_remove_slot(sc, vif);
  843. ath9k_ps_wakeup(sc);
  844. ath9k_calculate_summary_state(hw, NULL);
  845. ath9k_ps_restore(sc);
  846. mutex_unlock(&sc->mutex);
  847. }
  848. static void ath9k_enable_ps(struct ath_softc *sc)
  849. {
  850. struct ath_hw *ah = sc->sc_ah;
  851. struct ath_common *common = ath9k_hw_common(ah);
  852. sc->ps_enabled = true;
  853. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  854. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  855. ah->imask |= ATH9K_INT_TIM_TIMER;
  856. ath9k_hw_set_interrupts(ah);
  857. }
  858. ath9k_hw_setrxabort(ah, 1);
  859. }
  860. ath_dbg(common, PS, "PowerSave enabled\n");
  861. }
  862. static void ath9k_disable_ps(struct ath_softc *sc)
  863. {
  864. struct ath_hw *ah = sc->sc_ah;
  865. struct ath_common *common = ath9k_hw_common(ah);
  866. sc->ps_enabled = false;
  867. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  868. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  869. ath9k_hw_setrxabort(ah, 0);
  870. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  871. PS_WAIT_FOR_CAB |
  872. PS_WAIT_FOR_PSPOLL_DATA |
  873. PS_WAIT_FOR_TX_ACK);
  874. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  875. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  876. ath9k_hw_set_interrupts(ah);
  877. }
  878. }
  879. ath_dbg(common, PS, "PowerSave disabled\n");
  880. }
  881. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  882. {
  883. struct ath_softc *sc = hw->priv;
  884. struct ath_hw *ah = sc->sc_ah;
  885. struct ath_common *common = ath9k_hw_common(ah);
  886. struct ieee80211_conf *conf = &hw->conf;
  887. bool reset_channel = false;
  888. ath9k_ps_wakeup(sc);
  889. mutex_lock(&sc->mutex);
  890. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  891. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  892. if (sc->ps_idle) {
  893. ath_cancel_work(sc);
  894. ath9k_stop_btcoex(sc);
  895. } else {
  896. ath9k_start_btcoex(sc);
  897. /*
  898. * The chip needs a reset to properly wake up from
  899. * full sleep
  900. */
  901. reset_channel = ah->chip_fullsleep;
  902. }
  903. }
  904. /*
  905. * We just prepare to enable PS. We have to wait until our AP has
  906. * ACK'd our null data frame to disable RX otherwise we'll ignore
  907. * those ACKs and end up retransmitting the same null data frames.
  908. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  909. */
  910. if (changed & IEEE80211_CONF_CHANGE_PS) {
  911. unsigned long flags;
  912. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  913. if (conf->flags & IEEE80211_CONF_PS)
  914. ath9k_enable_ps(sc);
  915. else
  916. ath9k_disable_ps(sc);
  917. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  918. }
  919. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  920. if (conf->flags & IEEE80211_CONF_MONITOR) {
  921. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  922. sc->sc_ah->is_monitoring = true;
  923. } else {
  924. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  925. sc->sc_ah->is_monitoring = false;
  926. }
  927. }
  928. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  929. struct ieee80211_channel *curchan = hw->conf.channel;
  930. int pos = curchan->hw_value;
  931. int old_pos = -1;
  932. unsigned long flags;
  933. if (ah->curchan)
  934. old_pos = ah->curchan - &ah->channels[0];
  935. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  936. curchan->center_freq, conf->channel_type);
  937. /* update survey stats for the old channel before switching */
  938. spin_lock_irqsave(&common->cc_lock, flags);
  939. ath_update_survey_stats(sc);
  940. spin_unlock_irqrestore(&common->cc_lock, flags);
  941. /*
  942. * Preserve the current channel values, before updating
  943. * the same channel
  944. */
  945. if (ah->curchan && (old_pos == pos))
  946. ath9k_hw_getnf(ah, ah->curchan);
  947. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  948. curchan, conf->channel_type);
  949. /*
  950. * If the operating channel changes, change the survey in-use flags
  951. * along with it.
  952. * Reset the survey data for the new channel, unless we're switching
  953. * back to the operating channel from an off-channel operation.
  954. */
  955. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  956. sc->cur_survey != &sc->survey[pos]) {
  957. if (sc->cur_survey)
  958. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  959. sc->cur_survey = &sc->survey[pos];
  960. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  961. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  962. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  963. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  964. }
  965. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  966. ath_err(common, "Unable to set channel\n");
  967. mutex_unlock(&sc->mutex);
  968. ath9k_ps_restore(sc);
  969. return -EINVAL;
  970. }
  971. /*
  972. * The most recent snapshot of channel->noisefloor for the old
  973. * channel is only available after the hardware reset. Copy it to
  974. * the survey stats now.
  975. */
  976. if (old_pos >= 0)
  977. ath_update_survey_nf(sc, old_pos);
  978. }
  979. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  980. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  981. sc->config.txpowlimit = 2 * conf->power_level;
  982. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  983. sc->config.txpowlimit, &sc->curtxpow);
  984. }
  985. mutex_unlock(&sc->mutex);
  986. ath9k_ps_restore(sc);
  987. return 0;
  988. }
  989. #define SUPPORTED_FILTERS \
  990. (FIF_PROMISC_IN_BSS | \
  991. FIF_ALLMULTI | \
  992. FIF_CONTROL | \
  993. FIF_PSPOLL | \
  994. FIF_OTHER_BSS | \
  995. FIF_BCN_PRBRESP_PROMISC | \
  996. FIF_PROBE_REQ | \
  997. FIF_FCSFAIL)
  998. /* FIXME: sc->sc_full_reset ? */
  999. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1000. unsigned int changed_flags,
  1001. unsigned int *total_flags,
  1002. u64 multicast)
  1003. {
  1004. struct ath_softc *sc = hw->priv;
  1005. u32 rfilt;
  1006. changed_flags &= SUPPORTED_FILTERS;
  1007. *total_flags &= SUPPORTED_FILTERS;
  1008. sc->rx.rxfilter = *total_flags;
  1009. ath9k_ps_wakeup(sc);
  1010. rfilt = ath_calcrxfilter(sc);
  1011. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1012. ath9k_ps_restore(sc);
  1013. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1014. rfilt);
  1015. }
  1016. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1017. struct ieee80211_vif *vif,
  1018. struct ieee80211_sta *sta)
  1019. {
  1020. struct ath_softc *sc = hw->priv;
  1021. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1022. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1023. struct ieee80211_key_conf ps_key = { };
  1024. ath_node_attach(sc, sta, vif);
  1025. if (vif->type != NL80211_IFTYPE_AP &&
  1026. vif->type != NL80211_IFTYPE_AP_VLAN)
  1027. return 0;
  1028. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1029. return 0;
  1030. }
  1031. static void ath9k_del_ps_key(struct ath_softc *sc,
  1032. struct ieee80211_vif *vif,
  1033. struct ieee80211_sta *sta)
  1034. {
  1035. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1036. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1037. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1038. if (!an->ps_key)
  1039. return;
  1040. ath_key_delete(common, &ps_key);
  1041. }
  1042. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1043. struct ieee80211_vif *vif,
  1044. struct ieee80211_sta *sta)
  1045. {
  1046. struct ath_softc *sc = hw->priv;
  1047. ath9k_del_ps_key(sc, vif, sta);
  1048. ath_node_detach(sc, sta);
  1049. return 0;
  1050. }
  1051. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1052. struct ieee80211_vif *vif,
  1053. enum sta_notify_cmd cmd,
  1054. struct ieee80211_sta *sta)
  1055. {
  1056. struct ath_softc *sc = hw->priv;
  1057. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1058. if (!sta->ht_cap.ht_supported)
  1059. return;
  1060. switch (cmd) {
  1061. case STA_NOTIFY_SLEEP:
  1062. an->sleeping = true;
  1063. ath_tx_aggr_sleep(sta, sc, an);
  1064. break;
  1065. case STA_NOTIFY_AWAKE:
  1066. an->sleeping = false;
  1067. ath_tx_aggr_wakeup(sc, an);
  1068. break;
  1069. }
  1070. }
  1071. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1072. struct ieee80211_vif *vif, u16 queue,
  1073. const struct ieee80211_tx_queue_params *params)
  1074. {
  1075. struct ath_softc *sc = hw->priv;
  1076. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1077. struct ath_txq *txq;
  1078. struct ath9k_tx_queue_info qi;
  1079. int ret = 0;
  1080. if (queue >= WME_NUM_AC)
  1081. return 0;
  1082. txq = sc->tx.txq_map[queue];
  1083. ath9k_ps_wakeup(sc);
  1084. mutex_lock(&sc->mutex);
  1085. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1086. qi.tqi_aifs = params->aifs;
  1087. qi.tqi_cwmin = params->cw_min;
  1088. qi.tqi_cwmax = params->cw_max;
  1089. qi.tqi_burstTime = params->txop * 32;
  1090. ath_dbg(common, CONFIG,
  1091. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1092. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1093. params->cw_max, params->txop);
  1094. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1095. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1096. if (ret)
  1097. ath_err(common, "TXQ Update failed\n");
  1098. mutex_unlock(&sc->mutex);
  1099. ath9k_ps_restore(sc);
  1100. return ret;
  1101. }
  1102. static int ath9k_set_key(struct ieee80211_hw *hw,
  1103. enum set_key_cmd cmd,
  1104. struct ieee80211_vif *vif,
  1105. struct ieee80211_sta *sta,
  1106. struct ieee80211_key_conf *key)
  1107. {
  1108. struct ath_softc *sc = hw->priv;
  1109. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1110. int ret = 0;
  1111. if (ath9k_modparam_nohwcrypt)
  1112. return -ENOSPC;
  1113. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1114. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1115. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1116. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1117. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1118. /*
  1119. * For now, disable hw crypto for the RSN IBSS group keys. This
  1120. * could be optimized in the future to use a modified key cache
  1121. * design to support per-STA RX GTK, but until that gets
  1122. * implemented, use of software crypto for group addressed
  1123. * frames is a acceptable to allow RSN IBSS to be used.
  1124. */
  1125. return -EOPNOTSUPP;
  1126. }
  1127. mutex_lock(&sc->mutex);
  1128. ath9k_ps_wakeup(sc);
  1129. ath_dbg(common, CONFIG, "Set HW Key\n");
  1130. switch (cmd) {
  1131. case SET_KEY:
  1132. if (sta)
  1133. ath9k_del_ps_key(sc, vif, sta);
  1134. ret = ath_key_config(common, vif, sta, key);
  1135. if (ret >= 0) {
  1136. key->hw_key_idx = ret;
  1137. /* push IV and Michael MIC generation to stack */
  1138. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1139. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1140. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1141. if (sc->sc_ah->sw_mgmt_crypto &&
  1142. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1143. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1144. ret = 0;
  1145. }
  1146. break;
  1147. case DISABLE_KEY:
  1148. ath_key_delete(common, key);
  1149. break;
  1150. default:
  1151. ret = -EINVAL;
  1152. }
  1153. ath9k_ps_restore(sc);
  1154. mutex_unlock(&sc->mutex);
  1155. return ret;
  1156. }
  1157. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1158. struct ieee80211_vif *vif)
  1159. {
  1160. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1161. struct ath_vif *avp = (void *)vif->drv_priv;
  1162. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1163. unsigned long flags;
  1164. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1165. avp->primary_sta_vif = true;
  1166. /*
  1167. * Set the AID, BSSID and do beacon-sync only when
  1168. * the HW opmode is STATION.
  1169. *
  1170. * But the primary bit is set above in any case.
  1171. */
  1172. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1173. return;
  1174. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1175. common->curaid = bss_conf->aid;
  1176. ath9k_hw_write_associd(sc->sc_ah);
  1177. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1178. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1179. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1180. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1181. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1182. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1183. ath9k_mci_update_wlan_channels(sc, false);
  1184. ath_dbg(common, CONFIG,
  1185. "Primary Station interface: %pM, BSSID: %pM\n",
  1186. vif->addr, common->curbssid);
  1187. }
  1188. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1189. {
  1190. struct ath_softc *sc = data;
  1191. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1192. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1193. return;
  1194. if (bss_conf->assoc)
  1195. ath9k_set_assoc_state(sc, vif);
  1196. }
  1197. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1198. struct ieee80211_vif *vif,
  1199. struct ieee80211_bss_conf *bss_conf,
  1200. u32 changed)
  1201. {
  1202. #define CHECK_ANI \
  1203. (BSS_CHANGED_ASSOC | \
  1204. BSS_CHANGED_IBSS | \
  1205. BSS_CHANGED_BEACON_ENABLED)
  1206. struct ath_softc *sc = hw->priv;
  1207. struct ath_hw *ah = sc->sc_ah;
  1208. struct ath_common *common = ath9k_hw_common(ah);
  1209. struct ath_vif *avp = (void *)vif->drv_priv;
  1210. int slottime;
  1211. ath9k_ps_wakeup(sc);
  1212. mutex_lock(&sc->mutex);
  1213. if (changed & BSS_CHANGED_ASSOC) {
  1214. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1215. bss_conf->bssid, bss_conf->assoc);
  1216. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1217. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1218. avp->primary_sta_vif = false;
  1219. if (ah->opmode == NL80211_IFTYPE_STATION)
  1220. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1221. }
  1222. ieee80211_iterate_active_interfaces_atomic(
  1223. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1224. ath9k_bss_assoc_iter, sc);
  1225. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1226. ah->opmode == NL80211_IFTYPE_STATION) {
  1227. memset(common->curbssid, 0, ETH_ALEN);
  1228. common->curaid = 0;
  1229. ath9k_hw_write_associd(sc->sc_ah);
  1230. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1231. ath9k_mci_update_wlan_channels(sc, true);
  1232. }
  1233. }
  1234. if (changed & BSS_CHANGED_IBSS) {
  1235. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1236. common->curaid = bss_conf->aid;
  1237. ath9k_hw_write_associd(sc->sc_ah);
  1238. }
  1239. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1240. (changed & BSS_CHANGED_BEACON_INT)) {
  1241. if (ah->opmode == NL80211_IFTYPE_AP &&
  1242. bss_conf->enable_beacon)
  1243. ath9k_set_tsfadjust(sc, vif);
  1244. if (ath9k_allow_beacon_config(sc, vif))
  1245. ath9k_beacon_config(sc, vif, changed);
  1246. }
  1247. if (changed & BSS_CHANGED_ERP_SLOT) {
  1248. if (bss_conf->use_short_slot)
  1249. slottime = 9;
  1250. else
  1251. slottime = 20;
  1252. if (vif->type == NL80211_IFTYPE_AP) {
  1253. /*
  1254. * Defer update, so that connected stations can adjust
  1255. * their settings at the same time.
  1256. * See beacon.c for more details
  1257. */
  1258. sc->beacon.slottime = slottime;
  1259. sc->beacon.updateslot = UPDATE;
  1260. } else {
  1261. ah->slottime = slottime;
  1262. ath9k_hw_init_global_settings(ah);
  1263. }
  1264. }
  1265. if (changed & CHECK_ANI)
  1266. ath_check_ani(sc);
  1267. mutex_unlock(&sc->mutex);
  1268. ath9k_ps_restore(sc);
  1269. #undef CHECK_ANI
  1270. }
  1271. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1272. {
  1273. struct ath_softc *sc = hw->priv;
  1274. u64 tsf;
  1275. mutex_lock(&sc->mutex);
  1276. ath9k_ps_wakeup(sc);
  1277. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1278. ath9k_ps_restore(sc);
  1279. mutex_unlock(&sc->mutex);
  1280. return tsf;
  1281. }
  1282. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1283. struct ieee80211_vif *vif,
  1284. u64 tsf)
  1285. {
  1286. struct ath_softc *sc = hw->priv;
  1287. mutex_lock(&sc->mutex);
  1288. ath9k_ps_wakeup(sc);
  1289. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1290. ath9k_ps_restore(sc);
  1291. mutex_unlock(&sc->mutex);
  1292. }
  1293. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1294. {
  1295. struct ath_softc *sc = hw->priv;
  1296. mutex_lock(&sc->mutex);
  1297. ath9k_ps_wakeup(sc);
  1298. ath9k_hw_reset_tsf(sc->sc_ah);
  1299. ath9k_ps_restore(sc);
  1300. mutex_unlock(&sc->mutex);
  1301. }
  1302. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1303. struct ieee80211_vif *vif,
  1304. enum ieee80211_ampdu_mlme_action action,
  1305. struct ieee80211_sta *sta,
  1306. u16 tid, u16 *ssn, u8 buf_size)
  1307. {
  1308. struct ath_softc *sc = hw->priv;
  1309. int ret = 0;
  1310. local_bh_disable();
  1311. switch (action) {
  1312. case IEEE80211_AMPDU_RX_START:
  1313. break;
  1314. case IEEE80211_AMPDU_RX_STOP:
  1315. break;
  1316. case IEEE80211_AMPDU_TX_START:
  1317. ath9k_ps_wakeup(sc);
  1318. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1319. if (!ret)
  1320. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1321. ath9k_ps_restore(sc);
  1322. break;
  1323. case IEEE80211_AMPDU_TX_STOP:
  1324. ath9k_ps_wakeup(sc);
  1325. ath_tx_aggr_stop(sc, sta, tid);
  1326. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1327. ath9k_ps_restore(sc);
  1328. break;
  1329. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1330. ath9k_ps_wakeup(sc);
  1331. ath_tx_aggr_resume(sc, sta, tid);
  1332. ath9k_ps_restore(sc);
  1333. break;
  1334. default:
  1335. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1336. }
  1337. local_bh_enable();
  1338. return ret;
  1339. }
  1340. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1341. struct survey_info *survey)
  1342. {
  1343. struct ath_softc *sc = hw->priv;
  1344. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1345. struct ieee80211_supported_band *sband;
  1346. struct ieee80211_channel *chan;
  1347. unsigned long flags;
  1348. int pos;
  1349. spin_lock_irqsave(&common->cc_lock, flags);
  1350. if (idx == 0)
  1351. ath_update_survey_stats(sc);
  1352. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1353. if (sband && idx >= sband->n_channels) {
  1354. idx -= sband->n_channels;
  1355. sband = NULL;
  1356. }
  1357. if (!sband)
  1358. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1359. if (!sband || idx >= sband->n_channels) {
  1360. spin_unlock_irqrestore(&common->cc_lock, flags);
  1361. return -ENOENT;
  1362. }
  1363. chan = &sband->channels[idx];
  1364. pos = chan->hw_value;
  1365. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1366. survey->channel = chan;
  1367. spin_unlock_irqrestore(&common->cc_lock, flags);
  1368. return 0;
  1369. }
  1370. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1371. {
  1372. struct ath_softc *sc = hw->priv;
  1373. struct ath_hw *ah = sc->sc_ah;
  1374. mutex_lock(&sc->mutex);
  1375. ah->coverage_class = coverage_class;
  1376. ath9k_ps_wakeup(sc);
  1377. ath9k_hw_init_global_settings(ah);
  1378. ath9k_ps_restore(sc);
  1379. mutex_unlock(&sc->mutex);
  1380. }
  1381. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1382. {
  1383. struct ath_softc *sc = hw->priv;
  1384. struct ath_hw *ah = sc->sc_ah;
  1385. struct ath_common *common = ath9k_hw_common(ah);
  1386. int timeout = 200; /* ms */
  1387. int i, j;
  1388. bool drain_txq;
  1389. mutex_lock(&sc->mutex);
  1390. cancel_delayed_work_sync(&sc->tx_complete_work);
  1391. if (ah->ah_flags & AH_UNPLUGGED) {
  1392. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1393. mutex_unlock(&sc->mutex);
  1394. return;
  1395. }
  1396. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1397. ath_dbg(common, ANY, "Device not present\n");
  1398. mutex_unlock(&sc->mutex);
  1399. return;
  1400. }
  1401. for (j = 0; j < timeout; j++) {
  1402. bool npend = false;
  1403. if (j)
  1404. usleep_range(1000, 2000);
  1405. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1406. if (!ATH_TXQ_SETUP(sc, i))
  1407. continue;
  1408. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1409. if (npend)
  1410. break;
  1411. }
  1412. if (!npend)
  1413. break;
  1414. }
  1415. if (drop) {
  1416. ath9k_ps_wakeup(sc);
  1417. spin_lock_bh(&sc->sc_pcu_lock);
  1418. drain_txq = ath_drain_all_txq(sc, false);
  1419. spin_unlock_bh(&sc->sc_pcu_lock);
  1420. if (!drain_txq)
  1421. ath_reset(sc, false);
  1422. ath9k_ps_restore(sc);
  1423. ieee80211_wake_queues(hw);
  1424. }
  1425. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1426. mutex_unlock(&sc->mutex);
  1427. }
  1428. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1429. {
  1430. struct ath_softc *sc = hw->priv;
  1431. int i;
  1432. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1433. if (!ATH_TXQ_SETUP(sc, i))
  1434. continue;
  1435. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1436. return true;
  1437. }
  1438. return false;
  1439. }
  1440. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1441. {
  1442. struct ath_softc *sc = hw->priv;
  1443. struct ath_hw *ah = sc->sc_ah;
  1444. struct ieee80211_vif *vif;
  1445. struct ath_vif *avp;
  1446. struct ath_buf *bf;
  1447. struct ath_tx_status ts;
  1448. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1449. int status;
  1450. vif = sc->beacon.bslot[0];
  1451. if (!vif)
  1452. return 0;
  1453. if (!vif->bss_conf.enable_beacon)
  1454. return 0;
  1455. avp = (void *)vif->drv_priv;
  1456. if (!sc->beacon.tx_processed && !edma) {
  1457. tasklet_disable(&sc->bcon_tasklet);
  1458. bf = avp->av_bcbuf;
  1459. if (!bf || !bf->bf_mpdu)
  1460. goto skip;
  1461. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1462. if (status == -EINPROGRESS)
  1463. goto skip;
  1464. sc->beacon.tx_processed = true;
  1465. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1466. skip:
  1467. tasklet_enable(&sc->bcon_tasklet);
  1468. }
  1469. return sc->beacon.tx_last;
  1470. }
  1471. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1472. struct ieee80211_low_level_stats *stats)
  1473. {
  1474. struct ath_softc *sc = hw->priv;
  1475. struct ath_hw *ah = sc->sc_ah;
  1476. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1477. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1478. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1479. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1480. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1481. return 0;
  1482. }
  1483. static u32 fill_chainmask(u32 cap, u32 new)
  1484. {
  1485. u32 filled = 0;
  1486. int i;
  1487. for (i = 0; cap && new; i++, cap >>= 1) {
  1488. if (!(cap & BIT(0)))
  1489. continue;
  1490. if (new & BIT(0))
  1491. filled |= BIT(i);
  1492. new >>= 1;
  1493. }
  1494. return filled;
  1495. }
  1496. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1497. {
  1498. switch (val & 0x7) {
  1499. case 0x1:
  1500. case 0x3:
  1501. case 0x7:
  1502. return true;
  1503. case 0x2:
  1504. return (ah->caps.rx_chainmask == 1);
  1505. default:
  1506. return false;
  1507. }
  1508. }
  1509. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1510. {
  1511. struct ath_softc *sc = hw->priv;
  1512. struct ath_hw *ah = sc->sc_ah;
  1513. if (ah->caps.rx_chainmask != 1)
  1514. rx_ant |= tx_ant;
  1515. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1516. return -EINVAL;
  1517. sc->ant_rx = rx_ant;
  1518. sc->ant_tx = tx_ant;
  1519. if (ah->caps.rx_chainmask == 1)
  1520. return 0;
  1521. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1522. if (AR_SREV_9100(ah))
  1523. ah->rxchainmask = 0x7;
  1524. else
  1525. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1526. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1527. ath9k_reload_chainmask_settings(sc);
  1528. return 0;
  1529. }
  1530. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1531. {
  1532. struct ath_softc *sc = hw->priv;
  1533. *tx_ant = sc->ant_tx;
  1534. *rx_ant = sc->ant_rx;
  1535. return 0;
  1536. }
  1537. #ifdef CONFIG_ATH9K_DEBUGFS
  1538. /* Ethtool support for get-stats */
  1539. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1540. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1541. "tx_pkts_nic",
  1542. "tx_bytes_nic",
  1543. "rx_pkts_nic",
  1544. "rx_bytes_nic",
  1545. AMKSTR(d_tx_pkts),
  1546. AMKSTR(d_tx_bytes),
  1547. AMKSTR(d_tx_mpdus_queued),
  1548. AMKSTR(d_tx_mpdus_completed),
  1549. AMKSTR(d_tx_mpdu_xretries),
  1550. AMKSTR(d_tx_aggregates),
  1551. AMKSTR(d_tx_ampdus_queued_hw),
  1552. AMKSTR(d_tx_ampdus_queued_sw),
  1553. AMKSTR(d_tx_ampdus_completed),
  1554. AMKSTR(d_tx_ampdu_retries),
  1555. AMKSTR(d_tx_ampdu_xretries),
  1556. AMKSTR(d_tx_fifo_underrun),
  1557. AMKSTR(d_tx_op_exceeded),
  1558. AMKSTR(d_tx_timer_expiry),
  1559. AMKSTR(d_tx_desc_cfg_err),
  1560. AMKSTR(d_tx_data_underrun),
  1561. AMKSTR(d_tx_delim_underrun),
  1562. "d_rx_decrypt_crc_err",
  1563. "d_rx_phy_err",
  1564. "d_rx_mic_err",
  1565. "d_rx_pre_delim_crc_err",
  1566. "d_rx_post_delim_crc_err",
  1567. "d_rx_decrypt_busy_err",
  1568. "d_rx_phyerr_radar",
  1569. "d_rx_phyerr_ofdm_timing",
  1570. "d_rx_phyerr_cck_timing",
  1571. };
  1572. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1573. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1574. struct ieee80211_vif *vif,
  1575. u32 sset, u8 *data)
  1576. {
  1577. if (sset == ETH_SS_STATS)
  1578. memcpy(data, *ath9k_gstrings_stats,
  1579. sizeof(ath9k_gstrings_stats));
  1580. }
  1581. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1582. struct ieee80211_vif *vif, int sset)
  1583. {
  1584. if (sset == ETH_SS_STATS)
  1585. return ATH9K_SSTATS_LEN;
  1586. return 0;
  1587. }
  1588. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1589. #define AWDATA(elem) \
  1590. do { \
  1591. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1592. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1593. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1594. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1595. } while (0)
  1596. #define AWDATA_RX(elem) \
  1597. do { \
  1598. data[i++] = sc->debug.stats.rxstats.elem; \
  1599. } while (0)
  1600. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1601. struct ieee80211_vif *vif,
  1602. struct ethtool_stats *stats, u64 *data)
  1603. {
  1604. struct ath_softc *sc = hw->priv;
  1605. int i = 0;
  1606. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1607. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1608. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1609. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1610. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1611. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1612. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1613. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1614. AWDATA_RX(rx_pkts_all);
  1615. AWDATA_RX(rx_bytes_all);
  1616. AWDATA(tx_pkts_all);
  1617. AWDATA(tx_bytes_all);
  1618. AWDATA(queued);
  1619. AWDATA(completed);
  1620. AWDATA(xretries);
  1621. AWDATA(a_aggr);
  1622. AWDATA(a_queued_hw);
  1623. AWDATA(a_queued_sw);
  1624. AWDATA(a_completed);
  1625. AWDATA(a_retries);
  1626. AWDATA(a_xretries);
  1627. AWDATA(fifo_underrun);
  1628. AWDATA(xtxop);
  1629. AWDATA(timer_exp);
  1630. AWDATA(desc_cfg_err);
  1631. AWDATA(data_underrun);
  1632. AWDATA(delim_underrun);
  1633. AWDATA_RX(decrypt_crc_err);
  1634. AWDATA_RX(phy_err);
  1635. AWDATA_RX(mic_err);
  1636. AWDATA_RX(pre_delim_crc_err);
  1637. AWDATA_RX(post_delim_crc_err);
  1638. AWDATA_RX(decrypt_busy_err);
  1639. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1640. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1641. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1642. WARN_ON(i != ATH9K_SSTATS_LEN);
  1643. }
  1644. /* End of ethtool get-stats functions */
  1645. #endif
  1646. #ifdef CONFIG_PM_SLEEP
  1647. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1648. struct cfg80211_wowlan *wowlan,
  1649. u32 *wow_triggers)
  1650. {
  1651. if (wowlan->disconnect)
  1652. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1653. AH_WOW_BEACON_MISS;
  1654. if (wowlan->magic_pkt)
  1655. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1656. if (wowlan->n_patterns)
  1657. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1658. sc->wow_enabled = *wow_triggers;
  1659. }
  1660. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1661. {
  1662. struct ath_hw *ah = sc->sc_ah;
  1663. struct ath_common *common = ath9k_hw_common(ah);
  1664. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1665. int pattern_count = 0;
  1666. int i, byte_cnt;
  1667. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1668. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1669. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1670. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1671. /*
  1672. * Create Dissassociate / Deauthenticate packet filter
  1673. *
  1674. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1675. * +--------------+----------+---------+--------+--------+----
  1676. * + Frame Control+ Duration + DA + SA + BSSID +
  1677. * +--------------+----------+---------+--------+--------+----
  1678. *
  1679. * The above is the management frame format for disassociate/
  1680. * deauthenticate pattern, from this we need to match the first byte
  1681. * of 'Frame Control' and DA, SA, and BSSID fields
  1682. * (skipping 2nd byte of FC and Duration feild.
  1683. *
  1684. * Disassociate pattern
  1685. * --------------------
  1686. * Frame control = 00 00 1010
  1687. * DA, SA, BSSID = x:x:x:x:x:x
  1688. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1689. * | x:x:x:x:x:x -- 22 bytes
  1690. *
  1691. * Deauthenticate pattern
  1692. * ----------------------
  1693. * Frame control = 00 00 1100
  1694. * DA, SA, BSSID = x:x:x:x:x:x
  1695. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1696. * | x:x:x:x:x:x -- 22 bytes
  1697. */
  1698. /* Create Disassociate Pattern first */
  1699. byte_cnt = 0;
  1700. /* Fill out the mask with all FF's */
  1701. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1702. dis_deauth_mask[i] = 0xff;
  1703. /* copy the first byte of frame control field */
  1704. dis_deauth_pattern[byte_cnt] = 0xa0;
  1705. byte_cnt++;
  1706. /* skip 2nd byte of frame control and Duration field */
  1707. byte_cnt += 3;
  1708. /*
  1709. * need not match the destination mac address, it can be a broadcast
  1710. * mac address or an unicast to this station
  1711. */
  1712. byte_cnt += 6;
  1713. /* copy the source mac address */
  1714. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1715. byte_cnt += 6;
  1716. /* copy the bssid, its same as the source mac address */
  1717. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1718. /* Create Disassociate pattern mask */
  1719. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1720. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1721. /*
  1722. * for AR9280, because of hardware limitation, the
  1723. * first 4 bytes have to be matched for all patterns.
  1724. * the mask for disassociation and de-auth pattern
  1725. * matching need to enable the first 4 bytes.
  1726. * also the duration field needs to be filled.
  1727. */
  1728. dis_deauth_mask[0] = 0xf0;
  1729. /*
  1730. * fill in duration field
  1731. FIXME: what is the exact value ?
  1732. */
  1733. dis_deauth_pattern[2] = 0xff;
  1734. dis_deauth_pattern[3] = 0xff;
  1735. } else {
  1736. dis_deauth_mask[0] = 0xfe;
  1737. }
  1738. dis_deauth_mask[1] = 0x03;
  1739. dis_deauth_mask[2] = 0xc0;
  1740. } else {
  1741. dis_deauth_mask[0] = 0xef;
  1742. dis_deauth_mask[1] = 0x3f;
  1743. dis_deauth_mask[2] = 0x00;
  1744. dis_deauth_mask[3] = 0xfc;
  1745. }
  1746. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1747. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1748. pattern_count, byte_cnt);
  1749. pattern_count++;
  1750. /*
  1751. * for de-authenticate pattern, only the first byte of the frame
  1752. * control field gets changed from 0xA0 to 0xC0
  1753. */
  1754. dis_deauth_pattern[0] = 0xC0;
  1755. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1756. pattern_count, byte_cnt);
  1757. }
  1758. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1759. struct cfg80211_wowlan *wowlan)
  1760. {
  1761. struct ath_hw *ah = sc->sc_ah;
  1762. struct ath9k_wow_pattern *wow_pattern = NULL;
  1763. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1764. int mask_len;
  1765. s8 i = 0;
  1766. if (!wowlan->n_patterns)
  1767. return;
  1768. /*
  1769. * Add the new user configured patterns
  1770. */
  1771. for (i = 0; i < wowlan->n_patterns; i++) {
  1772. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1773. if (!wow_pattern)
  1774. return;
  1775. /*
  1776. * TODO: convert the generic user space pattern to
  1777. * appropriate chip specific/802.11 pattern.
  1778. */
  1779. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1780. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1781. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1782. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1783. patterns[i].pattern_len);
  1784. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1785. wow_pattern->pattern_len = patterns[i].pattern_len;
  1786. /*
  1787. * just need to take care of deauth and disssoc pattern,
  1788. * make sure we don't overwrite them.
  1789. */
  1790. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1791. wow_pattern->mask_bytes,
  1792. i + 2,
  1793. wow_pattern->pattern_len);
  1794. kfree(wow_pattern);
  1795. }
  1796. }
  1797. static int ath9k_suspend(struct ieee80211_hw *hw,
  1798. struct cfg80211_wowlan *wowlan)
  1799. {
  1800. struct ath_softc *sc = hw->priv;
  1801. struct ath_hw *ah = sc->sc_ah;
  1802. struct ath_common *common = ath9k_hw_common(ah);
  1803. u32 wow_triggers_enabled = 0;
  1804. int ret = 0;
  1805. mutex_lock(&sc->mutex);
  1806. ath_cancel_work(sc);
  1807. ath_stop_ani(sc);
  1808. del_timer_sync(&sc->rx_poll_timer);
  1809. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1810. ath_dbg(common, ANY, "Device not present\n");
  1811. ret = -EINVAL;
  1812. goto fail_wow;
  1813. }
  1814. if (WARN_ON(!wowlan)) {
  1815. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1816. ret = -EINVAL;
  1817. goto fail_wow;
  1818. }
  1819. if (!device_can_wakeup(sc->dev)) {
  1820. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1821. ret = 1;
  1822. goto fail_wow;
  1823. }
  1824. /*
  1825. * none of the sta vifs are associated
  1826. * and we are not currently handling multivif
  1827. * cases, for instance we have to seperately
  1828. * configure 'keep alive frame' for each
  1829. * STA.
  1830. */
  1831. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1832. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1833. ret = 1;
  1834. goto fail_wow;
  1835. }
  1836. if (sc->nvifs > 1) {
  1837. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1838. ret = 1;
  1839. goto fail_wow;
  1840. }
  1841. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1842. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1843. wow_triggers_enabled);
  1844. ath9k_ps_wakeup(sc);
  1845. ath9k_stop_btcoex(sc);
  1846. /*
  1847. * Enable wake up on recieving disassoc/deauth
  1848. * frame by default.
  1849. */
  1850. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1851. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1852. ath9k_wow_add_pattern(sc, wowlan);
  1853. spin_lock_bh(&sc->sc_pcu_lock);
  1854. /*
  1855. * To avoid false wake, we enable beacon miss interrupt only
  1856. * when we go to sleep. We save the current interrupt mask
  1857. * so we can restore it after the system wakes up
  1858. */
  1859. sc->wow_intr_before_sleep = ah->imask;
  1860. ah->imask &= ~ATH9K_INT_GLOBAL;
  1861. ath9k_hw_disable_interrupts(ah);
  1862. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1863. ath9k_hw_set_interrupts(ah);
  1864. ath9k_hw_enable_interrupts(ah);
  1865. spin_unlock_bh(&sc->sc_pcu_lock);
  1866. /*
  1867. * we can now sync irq and kill any running tasklets, since we already
  1868. * disabled interrupts and not holding a spin lock
  1869. */
  1870. synchronize_irq(sc->irq);
  1871. tasklet_kill(&sc->intr_tq);
  1872. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1873. ath9k_ps_restore(sc);
  1874. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1875. atomic_inc(&sc->wow_sleep_proc_intr);
  1876. fail_wow:
  1877. mutex_unlock(&sc->mutex);
  1878. return ret;
  1879. }
  1880. static int ath9k_resume(struct ieee80211_hw *hw)
  1881. {
  1882. struct ath_softc *sc = hw->priv;
  1883. struct ath_hw *ah = sc->sc_ah;
  1884. struct ath_common *common = ath9k_hw_common(ah);
  1885. u32 wow_status;
  1886. mutex_lock(&sc->mutex);
  1887. ath9k_ps_wakeup(sc);
  1888. spin_lock_bh(&sc->sc_pcu_lock);
  1889. ath9k_hw_disable_interrupts(ah);
  1890. ah->imask = sc->wow_intr_before_sleep;
  1891. ath9k_hw_set_interrupts(ah);
  1892. ath9k_hw_enable_interrupts(ah);
  1893. spin_unlock_bh(&sc->sc_pcu_lock);
  1894. wow_status = ath9k_hw_wow_wakeup(ah);
  1895. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1896. /*
  1897. * some devices may not pick beacon miss
  1898. * as the reason they woke up so we add
  1899. * that here for that shortcoming.
  1900. */
  1901. wow_status |= AH_WOW_BEACON_MISS;
  1902. atomic_dec(&sc->wow_got_bmiss_intr);
  1903. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1904. }
  1905. atomic_dec(&sc->wow_sleep_proc_intr);
  1906. if (wow_status) {
  1907. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1908. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1909. }
  1910. ath_restart_work(sc);
  1911. ath9k_start_btcoex(sc);
  1912. ath9k_ps_restore(sc);
  1913. mutex_unlock(&sc->mutex);
  1914. return 0;
  1915. }
  1916. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1917. {
  1918. struct ath_softc *sc = hw->priv;
  1919. mutex_lock(&sc->mutex);
  1920. device_init_wakeup(sc->dev, 1);
  1921. device_set_wakeup_enable(sc->dev, enabled);
  1922. mutex_unlock(&sc->mutex);
  1923. }
  1924. #endif
  1925. struct ieee80211_ops ath9k_ops = {
  1926. .tx = ath9k_tx,
  1927. .start = ath9k_start,
  1928. .stop = ath9k_stop,
  1929. .add_interface = ath9k_add_interface,
  1930. .change_interface = ath9k_change_interface,
  1931. .remove_interface = ath9k_remove_interface,
  1932. .config = ath9k_config,
  1933. .configure_filter = ath9k_configure_filter,
  1934. .sta_add = ath9k_sta_add,
  1935. .sta_remove = ath9k_sta_remove,
  1936. .sta_notify = ath9k_sta_notify,
  1937. .conf_tx = ath9k_conf_tx,
  1938. .bss_info_changed = ath9k_bss_info_changed,
  1939. .set_key = ath9k_set_key,
  1940. .get_tsf = ath9k_get_tsf,
  1941. .set_tsf = ath9k_set_tsf,
  1942. .reset_tsf = ath9k_reset_tsf,
  1943. .ampdu_action = ath9k_ampdu_action,
  1944. .get_survey = ath9k_get_survey,
  1945. .rfkill_poll = ath9k_rfkill_poll_state,
  1946. .set_coverage_class = ath9k_set_coverage_class,
  1947. .flush = ath9k_flush,
  1948. .tx_frames_pending = ath9k_tx_frames_pending,
  1949. .tx_last_beacon = ath9k_tx_last_beacon,
  1950. .get_stats = ath9k_get_stats,
  1951. .set_antenna = ath9k_set_antenna,
  1952. .get_antenna = ath9k_get_antenna,
  1953. #ifdef CONFIG_PM_SLEEP
  1954. .suspend = ath9k_suspend,
  1955. .resume = ath9k_resume,
  1956. .set_wakeup = ath9k_set_wakeup,
  1957. #endif
  1958. #ifdef CONFIG_ATH9K_DEBUGFS
  1959. .get_et_sset_count = ath9k_get_et_sset_count,
  1960. .get_et_stats = ath9k_get_et_stats,
  1961. .get_et_strings = ath9k_get_et_strings,
  1962. #endif
  1963. };