pci.c 103 KB

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  1. /*
  2. * PCI Bus Services, see include/linux/pci.h for further explanation.
  3. *
  4. * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
  5. * David Mosberger-Tang
  6. *
  7. * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/pci.h>
  13. #include <linux/pm.h>
  14. #include <linux/slab.h>
  15. #include <linux/module.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/string.h>
  18. #include <linux/log2.h>
  19. #include <linux/pci-aspm.h>
  20. #include <linux/pm_wakeup.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <asm-generic/pci-bridge.h>
  25. #include <asm/setup.h>
  26. #include "pci.h"
  27. const char *pci_power_names[] = {
  28. "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
  29. };
  30. EXPORT_SYMBOL_GPL(pci_power_names);
  31. int isa_dma_bridge_buggy;
  32. EXPORT_SYMBOL(isa_dma_bridge_buggy);
  33. int pci_pci_problems;
  34. EXPORT_SYMBOL(pci_pci_problems);
  35. unsigned int pci_pm_d3_delay;
  36. static void pci_pme_list_scan(struct work_struct *work);
  37. static LIST_HEAD(pci_pme_list);
  38. static DEFINE_MUTEX(pci_pme_list_mutex);
  39. static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
  40. struct pci_pme_device {
  41. struct list_head list;
  42. struct pci_dev *dev;
  43. };
  44. #define PME_TIMEOUT 1000 /* How long between PME checks */
  45. static void pci_dev_d3_sleep(struct pci_dev *dev)
  46. {
  47. unsigned int delay = dev->d3_delay;
  48. if (delay < pci_pm_d3_delay)
  49. delay = pci_pm_d3_delay;
  50. msleep(delay);
  51. }
  52. #ifdef CONFIG_PCI_DOMAINS
  53. int pci_domains_supported = 1;
  54. #endif
  55. #define DEFAULT_CARDBUS_IO_SIZE (256)
  56. #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
  57. /* pci=cbmemsize=nnM,cbiosize=nn can override this */
  58. unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
  59. unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
  60. #define DEFAULT_HOTPLUG_IO_SIZE (256)
  61. #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
  62. /* pci=hpmemsize=nnM,hpiosize=nn can override this */
  63. unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
  64. unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
  65. enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
  66. /*
  67. * The default CLS is used if arch didn't set CLS explicitly and not
  68. * all pci devices agree on the same value. Arch can override either
  69. * the dfl or actual value as it sees fit. Don't forget this is
  70. * measured in 32-bit words, not bytes.
  71. */
  72. u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
  73. u8 pci_cache_line_size;
  74. /*
  75. * If we set up a device for bus mastering, we need to check the latency
  76. * timer as certain BIOSes forget to set it properly.
  77. */
  78. unsigned int pcibios_max_latency = 255;
  79. /* If set, the PCIe ARI capability will not be used. */
  80. static bool pcie_ari_disabled;
  81. /**
  82. * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  83. * @bus: pointer to PCI bus structure to search
  84. *
  85. * Given a PCI bus, returns the highest PCI bus number present in the set
  86. * including the given PCI bus and its list of child PCI buses.
  87. */
  88. unsigned char pci_bus_max_busnr(struct pci_bus* bus)
  89. {
  90. struct list_head *tmp;
  91. unsigned char max, n;
  92. max = bus->busn_res.end;
  93. list_for_each(tmp, &bus->children) {
  94. n = pci_bus_max_busnr(pci_bus_b(tmp));
  95. if(n > max)
  96. max = n;
  97. }
  98. return max;
  99. }
  100. EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
  101. #ifdef CONFIG_HAS_IOMEM
  102. void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
  103. {
  104. /*
  105. * Make sure the BAR is actually a memory resource, not an IO resource
  106. */
  107. if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
  108. WARN_ON(1);
  109. return NULL;
  110. }
  111. return ioremap_nocache(pci_resource_start(pdev, bar),
  112. pci_resource_len(pdev, bar));
  113. }
  114. EXPORT_SYMBOL_GPL(pci_ioremap_bar);
  115. #endif
  116. #define PCI_FIND_CAP_TTL 48
  117. static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
  118. u8 pos, int cap, int *ttl)
  119. {
  120. u8 id;
  121. while ((*ttl)--) {
  122. pci_bus_read_config_byte(bus, devfn, pos, &pos);
  123. if (pos < 0x40)
  124. break;
  125. pos &= ~3;
  126. pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
  127. &id);
  128. if (id == 0xff)
  129. break;
  130. if (id == cap)
  131. return pos;
  132. pos += PCI_CAP_LIST_NEXT;
  133. }
  134. return 0;
  135. }
  136. static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
  137. u8 pos, int cap)
  138. {
  139. int ttl = PCI_FIND_CAP_TTL;
  140. return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
  141. }
  142. int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
  143. {
  144. return __pci_find_next_cap(dev->bus, dev->devfn,
  145. pos + PCI_CAP_LIST_NEXT, cap);
  146. }
  147. EXPORT_SYMBOL_GPL(pci_find_next_capability);
  148. static int __pci_bus_find_cap_start(struct pci_bus *bus,
  149. unsigned int devfn, u8 hdr_type)
  150. {
  151. u16 status;
  152. pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
  153. if (!(status & PCI_STATUS_CAP_LIST))
  154. return 0;
  155. switch (hdr_type) {
  156. case PCI_HEADER_TYPE_NORMAL:
  157. case PCI_HEADER_TYPE_BRIDGE:
  158. return PCI_CAPABILITY_LIST;
  159. case PCI_HEADER_TYPE_CARDBUS:
  160. return PCI_CB_CAPABILITY_LIST;
  161. default:
  162. return 0;
  163. }
  164. return 0;
  165. }
  166. /**
  167. * pci_find_capability - query for devices' capabilities
  168. * @dev: PCI device to query
  169. * @cap: capability code
  170. *
  171. * Tell if a device supports a given PCI capability.
  172. * Returns the address of the requested capability structure within the
  173. * device's PCI configuration space or 0 in case the device does not
  174. * support it. Possible values for @cap:
  175. *
  176. * %PCI_CAP_ID_PM Power Management
  177. * %PCI_CAP_ID_AGP Accelerated Graphics Port
  178. * %PCI_CAP_ID_VPD Vital Product Data
  179. * %PCI_CAP_ID_SLOTID Slot Identification
  180. * %PCI_CAP_ID_MSI Message Signalled Interrupts
  181. * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
  182. * %PCI_CAP_ID_PCIX PCI-X
  183. * %PCI_CAP_ID_EXP PCI Express
  184. */
  185. int pci_find_capability(struct pci_dev *dev, int cap)
  186. {
  187. int pos;
  188. pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
  189. if (pos)
  190. pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
  191. return pos;
  192. }
  193. /**
  194. * pci_bus_find_capability - query for devices' capabilities
  195. * @bus: the PCI bus to query
  196. * @devfn: PCI device to query
  197. * @cap: capability code
  198. *
  199. * Like pci_find_capability() but works for pci devices that do not have a
  200. * pci_dev structure set up yet.
  201. *
  202. * Returns the address of the requested capability structure within the
  203. * device's PCI configuration space or 0 in case the device does not
  204. * support it.
  205. */
  206. int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
  207. {
  208. int pos;
  209. u8 hdr_type;
  210. pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
  211. pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
  212. if (pos)
  213. pos = __pci_find_next_cap(bus, devfn, pos, cap);
  214. return pos;
  215. }
  216. /**
  217. * pci_find_next_ext_capability - Find an extended capability
  218. * @dev: PCI device to query
  219. * @start: address at which to start looking (0 to start at beginning of list)
  220. * @cap: capability code
  221. *
  222. * Returns the address of the next matching extended capability structure
  223. * within the device's PCI configuration space or 0 if the device does
  224. * not support it. Some capabilities can occur several times, e.g., the
  225. * vendor-specific capability, and this provides a way to find them all.
  226. */
  227. int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
  228. {
  229. u32 header;
  230. int ttl;
  231. int pos = PCI_CFG_SPACE_SIZE;
  232. /* minimum 8 bytes per capability */
  233. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  234. if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
  235. return 0;
  236. if (start)
  237. pos = start;
  238. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  239. return 0;
  240. /*
  241. * If we have no capabilities, this is indicated by cap ID,
  242. * cap version and next pointer all being 0.
  243. */
  244. if (header == 0)
  245. return 0;
  246. while (ttl-- > 0) {
  247. if (PCI_EXT_CAP_ID(header) == cap && pos != start)
  248. return pos;
  249. pos = PCI_EXT_CAP_NEXT(header);
  250. if (pos < PCI_CFG_SPACE_SIZE)
  251. break;
  252. if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
  253. break;
  254. }
  255. return 0;
  256. }
  257. EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
  258. /**
  259. * pci_find_ext_capability - Find an extended capability
  260. * @dev: PCI device to query
  261. * @cap: capability code
  262. *
  263. * Returns the address of the requested extended capability structure
  264. * within the device's PCI configuration space or 0 if the device does
  265. * not support it. Possible values for @cap:
  266. *
  267. * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
  268. * %PCI_EXT_CAP_ID_VC Virtual Channel
  269. * %PCI_EXT_CAP_ID_DSN Device Serial Number
  270. * %PCI_EXT_CAP_ID_PWR Power Budgeting
  271. */
  272. int pci_find_ext_capability(struct pci_dev *dev, int cap)
  273. {
  274. return pci_find_next_ext_capability(dev, 0, cap);
  275. }
  276. EXPORT_SYMBOL_GPL(pci_find_ext_capability);
  277. static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
  278. {
  279. int rc, ttl = PCI_FIND_CAP_TTL;
  280. u8 cap, mask;
  281. if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
  282. mask = HT_3BIT_CAP_MASK;
  283. else
  284. mask = HT_5BIT_CAP_MASK;
  285. pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
  286. PCI_CAP_ID_HT, &ttl);
  287. while (pos) {
  288. rc = pci_read_config_byte(dev, pos + 3, &cap);
  289. if (rc != PCIBIOS_SUCCESSFUL)
  290. return 0;
  291. if ((cap & mask) == ht_cap)
  292. return pos;
  293. pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
  294. pos + PCI_CAP_LIST_NEXT,
  295. PCI_CAP_ID_HT, &ttl);
  296. }
  297. return 0;
  298. }
  299. /**
  300. * pci_find_next_ht_capability - query a device's Hypertransport capabilities
  301. * @dev: PCI device to query
  302. * @pos: Position from which to continue searching
  303. * @ht_cap: Hypertransport capability code
  304. *
  305. * To be used in conjunction with pci_find_ht_capability() to search for
  306. * all capabilities matching @ht_cap. @pos should always be a value returned
  307. * from pci_find_ht_capability().
  308. *
  309. * NB. To be 100% safe against broken PCI devices, the caller should take
  310. * steps to avoid an infinite loop.
  311. */
  312. int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
  313. {
  314. return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
  315. }
  316. EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
  317. /**
  318. * pci_find_ht_capability - query a device's Hypertransport capabilities
  319. * @dev: PCI device to query
  320. * @ht_cap: Hypertransport capability code
  321. *
  322. * Tell if a device supports a given Hypertransport capability.
  323. * Returns an address within the device's PCI configuration space
  324. * or 0 in case the device does not support the request capability.
  325. * The address points to the PCI capability, of type PCI_CAP_ID_HT,
  326. * which has a Hypertransport capability matching @ht_cap.
  327. */
  328. int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
  329. {
  330. int pos;
  331. pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
  332. if (pos)
  333. pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
  334. return pos;
  335. }
  336. EXPORT_SYMBOL_GPL(pci_find_ht_capability);
  337. /**
  338. * pci_find_parent_resource - return resource region of parent bus of given region
  339. * @dev: PCI device structure contains resources to be searched
  340. * @res: child resource record for which parent is sought
  341. *
  342. * For given resource region of given device, return the resource
  343. * region of parent bus the given region is contained in or where
  344. * it should be allocated from.
  345. */
  346. struct resource *
  347. pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
  348. {
  349. const struct pci_bus *bus = dev->bus;
  350. int i;
  351. struct resource *best = NULL, *r;
  352. pci_bus_for_each_resource(bus, r, i) {
  353. if (!r)
  354. continue;
  355. if (res->start && !(res->start >= r->start && res->end <= r->end))
  356. continue; /* Not contained */
  357. if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
  358. continue; /* Wrong type */
  359. if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
  360. return r; /* Exact match */
  361. /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
  362. if (r->flags & IORESOURCE_PREFETCH)
  363. continue;
  364. /* .. but we can put a prefetchable resource inside a non-prefetchable one */
  365. if (!best)
  366. best = r;
  367. }
  368. return best;
  369. }
  370. /**
  371. * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
  372. * @dev: PCI device to have its BARs restored
  373. *
  374. * Restore the BAR values for a given device, so as to make it
  375. * accessible by its driver.
  376. */
  377. static void
  378. pci_restore_bars(struct pci_dev *dev)
  379. {
  380. int i;
  381. for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
  382. pci_update_resource(dev, i);
  383. }
  384. static struct pci_platform_pm_ops *pci_platform_pm;
  385. int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
  386. {
  387. if (!ops->is_manageable || !ops->set_state || !ops->choose_state
  388. || !ops->sleep_wake)
  389. return -EINVAL;
  390. pci_platform_pm = ops;
  391. return 0;
  392. }
  393. static inline bool platform_pci_power_manageable(struct pci_dev *dev)
  394. {
  395. return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
  396. }
  397. static inline int platform_pci_set_power_state(struct pci_dev *dev,
  398. pci_power_t t)
  399. {
  400. return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
  401. }
  402. static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
  403. {
  404. return pci_platform_pm ?
  405. pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
  406. }
  407. static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
  408. {
  409. return pci_platform_pm ?
  410. pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
  411. }
  412. static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
  413. {
  414. return pci_platform_pm ?
  415. pci_platform_pm->run_wake(dev, enable) : -ENODEV;
  416. }
  417. /**
  418. * pci_raw_set_power_state - Use PCI PM registers to set the power state of
  419. * given PCI device
  420. * @dev: PCI device to handle.
  421. * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
  422. *
  423. * RETURN VALUE:
  424. * -EINVAL if the requested state is invalid.
  425. * -EIO if device does not support PCI PM or its PM capabilities register has a
  426. * wrong version, or device doesn't support the requested state.
  427. * 0 if device already is in the requested state.
  428. * 0 if device's power state has been successfully changed.
  429. */
  430. static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
  431. {
  432. u16 pmcsr;
  433. bool need_restore = false;
  434. /* Check if we're already there */
  435. if (dev->current_state == state)
  436. return 0;
  437. if (!dev->pm_cap)
  438. return -EIO;
  439. if (state < PCI_D0 || state > PCI_D3hot)
  440. return -EINVAL;
  441. /* Validate current state:
  442. * Can enter D0 from any state, but if we can only go deeper
  443. * to sleep if we're already in a low power state
  444. */
  445. if (state != PCI_D0 && dev->current_state <= PCI_D3cold
  446. && dev->current_state > state) {
  447. dev_err(&dev->dev, "invalid power transition "
  448. "(from state %d to %d)\n", dev->current_state, state);
  449. return -EINVAL;
  450. }
  451. /* check if this device supports the desired state */
  452. if ((state == PCI_D1 && !dev->d1_support)
  453. || (state == PCI_D2 && !dev->d2_support))
  454. return -EIO;
  455. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  456. /* If we're (effectively) in D3, force entire word to 0.
  457. * This doesn't affect PME_Status, disables PME_En, and
  458. * sets PowerState to 0.
  459. */
  460. switch (dev->current_state) {
  461. case PCI_D0:
  462. case PCI_D1:
  463. case PCI_D2:
  464. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  465. pmcsr |= state;
  466. break;
  467. case PCI_D3hot:
  468. case PCI_D3cold:
  469. case PCI_UNKNOWN: /* Boot-up */
  470. if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
  471. && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
  472. need_restore = true;
  473. /* Fall-through: force to D0 */
  474. default:
  475. pmcsr = 0;
  476. break;
  477. }
  478. /* enter specified state */
  479. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
  480. /* Mandatory power management transition delays */
  481. /* see PCI PM 1.1 5.6.1 table 18 */
  482. if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
  483. pci_dev_d3_sleep(dev);
  484. else if (state == PCI_D2 || dev->current_state == PCI_D2)
  485. udelay(PCI_PM_D2_DELAY);
  486. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  487. dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
  488. if (dev->current_state != state && printk_ratelimit())
  489. dev_info(&dev->dev, "Refused to change power state, "
  490. "currently in D%d\n", dev->current_state);
  491. /*
  492. * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
  493. * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
  494. * from D3hot to D0 _may_ perform an internal reset, thereby
  495. * going to "D0 Uninitialized" rather than "D0 Initialized".
  496. * For example, at least some versions of the 3c905B and the
  497. * 3c556B exhibit this behaviour.
  498. *
  499. * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
  500. * devices in a D3hot state at boot. Consequently, we need to
  501. * restore at least the BARs so that the device will be
  502. * accessible to its driver.
  503. */
  504. if (need_restore)
  505. pci_restore_bars(dev);
  506. if (dev->bus->self)
  507. pcie_aspm_pm_state_change(dev->bus->self);
  508. return 0;
  509. }
  510. /**
  511. * pci_update_current_state - Read PCI power state of given device from its
  512. * PCI PM registers and cache it
  513. * @dev: PCI device to handle.
  514. * @state: State to cache in case the device doesn't have the PM capability
  515. */
  516. void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
  517. {
  518. if (dev->pm_cap) {
  519. u16 pmcsr;
  520. /*
  521. * Configuration space is not accessible for device in
  522. * D3cold, so just keep or set D3cold for safety
  523. */
  524. if (dev->current_state == PCI_D3cold)
  525. return;
  526. if (state == PCI_D3cold) {
  527. dev->current_state = PCI_D3cold;
  528. return;
  529. }
  530. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  531. dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
  532. } else {
  533. dev->current_state = state;
  534. }
  535. }
  536. /**
  537. * pci_power_up - Put the given device into D0 forcibly
  538. * @dev: PCI device to power up
  539. */
  540. void pci_power_up(struct pci_dev *dev)
  541. {
  542. if (platform_pci_power_manageable(dev))
  543. platform_pci_set_power_state(dev, PCI_D0);
  544. pci_raw_set_power_state(dev, PCI_D0);
  545. pci_update_current_state(dev, PCI_D0);
  546. }
  547. /**
  548. * pci_platform_power_transition - Use platform to change device power state
  549. * @dev: PCI device to handle.
  550. * @state: State to put the device into.
  551. */
  552. static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
  553. {
  554. int error;
  555. if (platform_pci_power_manageable(dev)) {
  556. error = platform_pci_set_power_state(dev, state);
  557. if (!error)
  558. pci_update_current_state(dev, state);
  559. } else
  560. error = -ENODEV;
  561. if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
  562. dev->current_state = PCI_D0;
  563. return error;
  564. }
  565. /**
  566. * __pci_start_power_transition - Start power transition of a PCI device
  567. * @dev: PCI device to handle.
  568. * @state: State to put the device into.
  569. */
  570. static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
  571. {
  572. if (state == PCI_D0) {
  573. pci_platform_power_transition(dev, PCI_D0);
  574. /*
  575. * Mandatory power management transition delays, see
  576. * PCI Express Base Specification Revision 2.0 Section
  577. * 6.6.1: Conventional Reset. Do not delay for
  578. * devices powered on/off by corresponding bridge,
  579. * because have already delayed for the bridge.
  580. */
  581. if (dev->runtime_d3cold) {
  582. msleep(dev->d3cold_delay);
  583. /*
  584. * When powering on a bridge from D3cold, the
  585. * whole hierarchy may be powered on into
  586. * D0uninitialized state, resume them to give
  587. * them a chance to suspend again
  588. */
  589. pci_wakeup_bus(dev->subordinate);
  590. }
  591. }
  592. }
  593. /**
  594. * __pci_dev_set_current_state - Set current state of a PCI device
  595. * @dev: Device to handle
  596. * @data: pointer to state to be set
  597. */
  598. static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
  599. {
  600. pci_power_t state = *(pci_power_t *)data;
  601. dev->current_state = state;
  602. return 0;
  603. }
  604. /**
  605. * __pci_bus_set_current_state - Walk given bus and set current state of devices
  606. * @bus: Top bus of the subtree to walk.
  607. * @state: state to be set
  608. */
  609. static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
  610. {
  611. if (bus)
  612. pci_walk_bus(bus, __pci_dev_set_current_state, &state);
  613. }
  614. /**
  615. * __pci_complete_power_transition - Complete power transition of a PCI device
  616. * @dev: PCI device to handle.
  617. * @state: State to put the device into.
  618. *
  619. * This function should not be called directly by device drivers.
  620. */
  621. int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
  622. {
  623. int ret;
  624. if (state <= PCI_D0)
  625. return -EINVAL;
  626. ret = pci_platform_power_transition(dev, state);
  627. /* Power off the bridge may power off the whole hierarchy */
  628. if (!ret && state == PCI_D3cold)
  629. __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
  630. return ret;
  631. }
  632. EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
  633. /**
  634. * pci_set_power_state - Set the power state of a PCI device
  635. * @dev: PCI device to handle.
  636. * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
  637. *
  638. * Transition a device to a new power state, using the platform firmware and/or
  639. * the device's PCI PM registers.
  640. *
  641. * RETURN VALUE:
  642. * -EINVAL if the requested state is invalid.
  643. * -EIO if device does not support PCI PM or its PM capabilities register has a
  644. * wrong version, or device doesn't support the requested state.
  645. * 0 if device already is in the requested state.
  646. * 0 if device's power state has been successfully changed.
  647. */
  648. int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
  649. {
  650. int error;
  651. /* bound the state we're entering */
  652. if (state > PCI_D3cold)
  653. state = PCI_D3cold;
  654. else if (state < PCI_D0)
  655. state = PCI_D0;
  656. else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
  657. /*
  658. * If the device or the parent bridge do not support PCI PM,
  659. * ignore the request if we're doing anything other than putting
  660. * it into D0 (which would only happen on boot).
  661. */
  662. return 0;
  663. /* Check if we're already there */
  664. if (dev->current_state == state)
  665. return 0;
  666. __pci_start_power_transition(dev, state);
  667. /* This device is quirked not to be put into D3, so
  668. don't put it in D3 */
  669. if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
  670. return 0;
  671. /*
  672. * To put device in D3cold, we put device into D3hot in native
  673. * way, then put device into D3cold with platform ops
  674. */
  675. error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
  676. PCI_D3hot : state);
  677. if (!__pci_complete_power_transition(dev, state))
  678. error = 0;
  679. /*
  680. * When aspm_policy is "powersave" this call ensures
  681. * that ASPM is configured.
  682. */
  683. if (!error && dev->bus->self)
  684. pcie_aspm_powersave_config_link(dev->bus->self);
  685. return error;
  686. }
  687. /**
  688. * pci_choose_state - Choose the power state of a PCI device
  689. * @dev: PCI device to be suspended
  690. * @state: target sleep state for the whole system. This is the value
  691. * that is passed to suspend() function.
  692. *
  693. * Returns PCI power state suitable for given device and given system
  694. * message.
  695. */
  696. pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
  697. {
  698. pci_power_t ret;
  699. if (!pci_find_capability(dev, PCI_CAP_ID_PM))
  700. return PCI_D0;
  701. ret = platform_pci_choose_state(dev);
  702. if (ret != PCI_POWER_ERROR)
  703. return ret;
  704. switch (state.event) {
  705. case PM_EVENT_ON:
  706. return PCI_D0;
  707. case PM_EVENT_FREEZE:
  708. case PM_EVENT_PRETHAW:
  709. /* REVISIT both freeze and pre-thaw "should" use D0 */
  710. case PM_EVENT_SUSPEND:
  711. case PM_EVENT_HIBERNATE:
  712. return PCI_D3hot;
  713. default:
  714. dev_info(&dev->dev, "unrecognized suspend event %d\n",
  715. state.event);
  716. BUG();
  717. }
  718. return PCI_D0;
  719. }
  720. EXPORT_SYMBOL(pci_choose_state);
  721. #define PCI_EXP_SAVE_REGS 7
  722. static struct pci_cap_saved_state *pci_find_saved_cap(
  723. struct pci_dev *pci_dev, char cap)
  724. {
  725. struct pci_cap_saved_state *tmp;
  726. hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
  727. if (tmp->cap.cap_nr == cap)
  728. return tmp;
  729. }
  730. return NULL;
  731. }
  732. static int pci_save_pcie_state(struct pci_dev *dev)
  733. {
  734. int i = 0;
  735. struct pci_cap_saved_state *save_state;
  736. u16 *cap;
  737. if (!pci_is_pcie(dev))
  738. return 0;
  739. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
  740. if (!save_state) {
  741. dev_err(&dev->dev, "buffer not found in %s\n", __func__);
  742. return -ENOMEM;
  743. }
  744. cap = (u16 *)&save_state->cap.data[0];
  745. pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
  746. pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
  747. pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
  748. pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
  749. pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
  750. pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
  751. pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
  752. return 0;
  753. }
  754. static void pci_restore_pcie_state(struct pci_dev *dev)
  755. {
  756. int i = 0;
  757. struct pci_cap_saved_state *save_state;
  758. u16 *cap;
  759. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
  760. if (!save_state)
  761. return;
  762. cap = (u16 *)&save_state->cap.data[0];
  763. pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
  764. pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
  765. pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
  766. pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
  767. pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
  768. pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
  769. pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
  770. }
  771. static int pci_save_pcix_state(struct pci_dev *dev)
  772. {
  773. int pos;
  774. struct pci_cap_saved_state *save_state;
  775. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  776. if (pos <= 0)
  777. return 0;
  778. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
  779. if (!save_state) {
  780. dev_err(&dev->dev, "buffer not found in %s\n", __func__);
  781. return -ENOMEM;
  782. }
  783. pci_read_config_word(dev, pos + PCI_X_CMD,
  784. (u16 *)save_state->cap.data);
  785. return 0;
  786. }
  787. static void pci_restore_pcix_state(struct pci_dev *dev)
  788. {
  789. int i = 0, pos;
  790. struct pci_cap_saved_state *save_state;
  791. u16 *cap;
  792. save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
  793. pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  794. if (!save_state || pos <= 0)
  795. return;
  796. cap = (u16 *)&save_state->cap.data[0];
  797. pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
  798. }
  799. /**
  800. * pci_save_state - save the PCI configuration space of a device before suspending
  801. * @dev: - PCI device that we're dealing with
  802. */
  803. int
  804. pci_save_state(struct pci_dev *dev)
  805. {
  806. int i;
  807. /* XXX: 100% dword access ok here? */
  808. for (i = 0; i < 16; i++)
  809. pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
  810. dev->state_saved = true;
  811. if ((i = pci_save_pcie_state(dev)) != 0)
  812. return i;
  813. if ((i = pci_save_pcix_state(dev)) != 0)
  814. return i;
  815. return 0;
  816. }
  817. static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
  818. u32 saved_val, int retry)
  819. {
  820. u32 val;
  821. pci_read_config_dword(pdev, offset, &val);
  822. if (val == saved_val)
  823. return;
  824. for (;;) {
  825. dev_dbg(&pdev->dev, "restoring config space at offset "
  826. "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
  827. pci_write_config_dword(pdev, offset, saved_val);
  828. if (retry-- <= 0)
  829. return;
  830. pci_read_config_dword(pdev, offset, &val);
  831. if (val == saved_val)
  832. return;
  833. mdelay(1);
  834. }
  835. }
  836. static void pci_restore_config_space_range(struct pci_dev *pdev,
  837. int start, int end, int retry)
  838. {
  839. int index;
  840. for (index = end; index >= start; index--)
  841. pci_restore_config_dword(pdev, 4 * index,
  842. pdev->saved_config_space[index],
  843. retry);
  844. }
  845. static void pci_restore_config_space(struct pci_dev *pdev)
  846. {
  847. if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
  848. pci_restore_config_space_range(pdev, 10, 15, 0);
  849. /* Restore BARs before the command register. */
  850. pci_restore_config_space_range(pdev, 4, 9, 10);
  851. pci_restore_config_space_range(pdev, 0, 3, 0);
  852. } else {
  853. pci_restore_config_space_range(pdev, 0, 15, 0);
  854. }
  855. }
  856. /**
  857. * pci_restore_state - Restore the saved state of a PCI device
  858. * @dev: - PCI device that we're dealing with
  859. */
  860. void pci_restore_state(struct pci_dev *dev)
  861. {
  862. if (!dev->state_saved)
  863. return;
  864. /* PCI Express register must be restored first */
  865. pci_restore_pcie_state(dev);
  866. pci_restore_ats_state(dev);
  867. pci_restore_config_space(dev);
  868. pci_restore_pcix_state(dev);
  869. pci_restore_msi_state(dev);
  870. pci_restore_iov_state(dev);
  871. dev->state_saved = false;
  872. }
  873. struct pci_saved_state {
  874. u32 config_space[16];
  875. struct pci_cap_saved_data cap[0];
  876. };
  877. /**
  878. * pci_store_saved_state - Allocate and return an opaque struct containing
  879. * the device saved state.
  880. * @dev: PCI device that we're dealing with
  881. *
  882. * Rerturn NULL if no state or error.
  883. */
  884. struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
  885. {
  886. struct pci_saved_state *state;
  887. struct pci_cap_saved_state *tmp;
  888. struct pci_cap_saved_data *cap;
  889. size_t size;
  890. if (!dev->state_saved)
  891. return NULL;
  892. size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
  893. hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
  894. size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
  895. state = kzalloc(size, GFP_KERNEL);
  896. if (!state)
  897. return NULL;
  898. memcpy(state->config_space, dev->saved_config_space,
  899. sizeof(state->config_space));
  900. cap = state->cap;
  901. hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
  902. size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
  903. memcpy(cap, &tmp->cap, len);
  904. cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
  905. }
  906. /* Empty cap_save terminates list */
  907. return state;
  908. }
  909. EXPORT_SYMBOL_GPL(pci_store_saved_state);
  910. /**
  911. * pci_load_saved_state - Reload the provided save state into struct pci_dev.
  912. * @dev: PCI device that we're dealing with
  913. * @state: Saved state returned from pci_store_saved_state()
  914. */
  915. int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
  916. {
  917. struct pci_cap_saved_data *cap;
  918. dev->state_saved = false;
  919. if (!state)
  920. return 0;
  921. memcpy(dev->saved_config_space, state->config_space,
  922. sizeof(state->config_space));
  923. cap = state->cap;
  924. while (cap->size) {
  925. struct pci_cap_saved_state *tmp;
  926. tmp = pci_find_saved_cap(dev, cap->cap_nr);
  927. if (!tmp || tmp->cap.size != cap->size)
  928. return -EINVAL;
  929. memcpy(tmp->cap.data, cap->data, tmp->cap.size);
  930. cap = (struct pci_cap_saved_data *)((u8 *)cap +
  931. sizeof(struct pci_cap_saved_data) + cap->size);
  932. }
  933. dev->state_saved = true;
  934. return 0;
  935. }
  936. EXPORT_SYMBOL_GPL(pci_load_saved_state);
  937. /**
  938. * pci_load_and_free_saved_state - Reload the save state pointed to by state,
  939. * and free the memory allocated for it.
  940. * @dev: PCI device that we're dealing with
  941. * @state: Pointer to saved state returned from pci_store_saved_state()
  942. */
  943. int pci_load_and_free_saved_state(struct pci_dev *dev,
  944. struct pci_saved_state **state)
  945. {
  946. int ret = pci_load_saved_state(dev, *state);
  947. kfree(*state);
  948. *state = NULL;
  949. return ret;
  950. }
  951. EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
  952. static int do_pci_enable_device(struct pci_dev *dev, int bars)
  953. {
  954. int err;
  955. err = pci_set_power_state(dev, PCI_D0);
  956. if (err < 0 && err != -EIO)
  957. return err;
  958. err = pcibios_enable_device(dev, bars);
  959. if (err < 0)
  960. return err;
  961. pci_fixup_device(pci_fixup_enable, dev);
  962. return 0;
  963. }
  964. /**
  965. * pci_reenable_device - Resume abandoned device
  966. * @dev: PCI device to be resumed
  967. *
  968. * Note this function is a backend of pci_default_resume and is not supposed
  969. * to be called by normal code, write proper resume handler and use it instead.
  970. */
  971. int pci_reenable_device(struct pci_dev *dev)
  972. {
  973. if (pci_is_enabled(dev))
  974. return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
  975. return 0;
  976. }
  977. static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
  978. {
  979. int err;
  980. int i, bars = 0;
  981. /*
  982. * Power state could be unknown at this point, either due to a fresh
  983. * boot or a device removal call. So get the current power state
  984. * so that things like MSI message writing will behave as expected
  985. * (e.g. if the device really is in D0 at enable time).
  986. */
  987. if (dev->pm_cap) {
  988. u16 pmcsr;
  989. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  990. dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
  991. }
  992. if (atomic_inc_return(&dev->enable_cnt) > 1)
  993. return 0; /* already enabled */
  994. /* only skip sriov related */
  995. for (i = 0; i <= PCI_ROM_RESOURCE; i++)
  996. if (dev->resource[i].flags & flags)
  997. bars |= (1 << i);
  998. for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
  999. if (dev->resource[i].flags & flags)
  1000. bars |= (1 << i);
  1001. err = do_pci_enable_device(dev, bars);
  1002. if (err < 0)
  1003. atomic_dec(&dev->enable_cnt);
  1004. return err;
  1005. }
  1006. /**
  1007. * pci_enable_device_io - Initialize a device for use with IO space
  1008. * @dev: PCI device to be initialized
  1009. *
  1010. * Initialize device before it's used by a driver. Ask low-level code
  1011. * to enable I/O resources. Wake up the device if it was suspended.
  1012. * Beware, this function can fail.
  1013. */
  1014. int pci_enable_device_io(struct pci_dev *dev)
  1015. {
  1016. return pci_enable_device_flags(dev, IORESOURCE_IO);
  1017. }
  1018. /**
  1019. * pci_enable_device_mem - Initialize a device for use with Memory space
  1020. * @dev: PCI device to be initialized
  1021. *
  1022. * Initialize device before it's used by a driver. Ask low-level code
  1023. * to enable Memory resources. Wake up the device if it was suspended.
  1024. * Beware, this function can fail.
  1025. */
  1026. int pci_enable_device_mem(struct pci_dev *dev)
  1027. {
  1028. return pci_enable_device_flags(dev, IORESOURCE_MEM);
  1029. }
  1030. /**
  1031. * pci_enable_device - Initialize device before it's used by a driver.
  1032. * @dev: PCI device to be initialized
  1033. *
  1034. * Initialize device before it's used by a driver. Ask low-level code
  1035. * to enable I/O and memory. Wake up the device if it was suspended.
  1036. * Beware, this function can fail.
  1037. *
  1038. * Note we don't actually enable the device many times if we call
  1039. * this function repeatedly (we just increment the count).
  1040. */
  1041. int pci_enable_device(struct pci_dev *dev)
  1042. {
  1043. return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
  1044. }
  1045. /*
  1046. * Managed PCI resources. This manages device on/off, intx/msi/msix
  1047. * on/off and BAR regions. pci_dev itself records msi/msix status, so
  1048. * there's no need to track it separately. pci_devres is initialized
  1049. * when a device is enabled using managed PCI device enable interface.
  1050. */
  1051. struct pci_devres {
  1052. unsigned int enabled:1;
  1053. unsigned int pinned:1;
  1054. unsigned int orig_intx:1;
  1055. unsigned int restore_intx:1;
  1056. u32 region_mask;
  1057. };
  1058. static void pcim_release(struct device *gendev, void *res)
  1059. {
  1060. struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
  1061. struct pci_devres *this = res;
  1062. int i;
  1063. if (dev->msi_enabled)
  1064. pci_disable_msi(dev);
  1065. if (dev->msix_enabled)
  1066. pci_disable_msix(dev);
  1067. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  1068. if (this->region_mask & (1 << i))
  1069. pci_release_region(dev, i);
  1070. if (this->restore_intx)
  1071. pci_intx(dev, this->orig_intx);
  1072. if (this->enabled && !this->pinned)
  1073. pci_disable_device(dev);
  1074. }
  1075. static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
  1076. {
  1077. struct pci_devres *dr, *new_dr;
  1078. dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
  1079. if (dr)
  1080. return dr;
  1081. new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
  1082. if (!new_dr)
  1083. return NULL;
  1084. return devres_get(&pdev->dev, new_dr, NULL, NULL);
  1085. }
  1086. static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
  1087. {
  1088. if (pci_is_managed(pdev))
  1089. return devres_find(&pdev->dev, pcim_release, NULL, NULL);
  1090. return NULL;
  1091. }
  1092. /**
  1093. * pcim_enable_device - Managed pci_enable_device()
  1094. * @pdev: PCI device to be initialized
  1095. *
  1096. * Managed pci_enable_device().
  1097. */
  1098. int pcim_enable_device(struct pci_dev *pdev)
  1099. {
  1100. struct pci_devres *dr;
  1101. int rc;
  1102. dr = get_pci_dr(pdev);
  1103. if (unlikely(!dr))
  1104. return -ENOMEM;
  1105. if (dr->enabled)
  1106. return 0;
  1107. rc = pci_enable_device(pdev);
  1108. if (!rc) {
  1109. pdev->is_managed = 1;
  1110. dr->enabled = 1;
  1111. }
  1112. return rc;
  1113. }
  1114. /**
  1115. * pcim_pin_device - Pin managed PCI device
  1116. * @pdev: PCI device to pin
  1117. *
  1118. * Pin managed PCI device @pdev. Pinned device won't be disabled on
  1119. * driver detach. @pdev must have been enabled with
  1120. * pcim_enable_device().
  1121. */
  1122. void pcim_pin_device(struct pci_dev *pdev)
  1123. {
  1124. struct pci_devres *dr;
  1125. dr = find_pci_dr(pdev);
  1126. WARN_ON(!dr || !dr->enabled);
  1127. if (dr)
  1128. dr->pinned = 1;
  1129. }
  1130. /*
  1131. * pcibios_add_device - provide arch specific hooks when adding device dev
  1132. * @dev: the PCI device being added
  1133. *
  1134. * Permits the platform to provide architecture specific functionality when
  1135. * devices are added. This is the default implementation. Architecture
  1136. * implementations can override this.
  1137. */
  1138. int __weak pcibios_add_device (struct pci_dev *dev)
  1139. {
  1140. return 0;
  1141. }
  1142. /**
  1143. * pcibios_disable_device - disable arch specific PCI resources for device dev
  1144. * @dev: the PCI device to disable
  1145. *
  1146. * Disables architecture specific PCI resources for the device. This
  1147. * is the default implementation. Architecture implementations can
  1148. * override this.
  1149. */
  1150. void __weak pcibios_disable_device (struct pci_dev *dev) {}
  1151. static void do_pci_disable_device(struct pci_dev *dev)
  1152. {
  1153. u16 pci_command;
  1154. pci_read_config_word(dev, PCI_COMMAND, &pci_command);
  1155. if (pci_command & PCI_COMMAND_MASTER) {
  1156. pci_command &= ~PCI_COMMAND_MASTER;
  1157. pci_write_config_word(dev, PCI_COMMAND, pci_command);
  1158. }
  1159. pcibios_disable_device(dev);
  1160. }
  1161. /**
  1162. * pci_disable_enabled_device - Disable device without updating enable_cnt
  1163. * @dev: PCI device to disable
  1164. *
  1165. * NOTE: This function is a backend of PCI power management routines and is
  1166. * not supposed to be called drivers.
  1167. */
  1168. void pci_disable_enabled_device(struct pci_dev *dev)
  1169. {
  1170. if (pci_is_enabled(dev))
  1171. do_pci_disable_device(dev);
  1172. }
  1173. /**
  1174. * pci_disable_device - Disable PCI device after use
  1175. * @dev: PCI device to be disabled
  1176. *
  1177. * Signal to the system that the PCI device is not in use by the system
  1178. * anymore. This only involves disabling PCI bus-mastering, if active.
  1179. *
  1180. * Note we don't actually disable the device until all callers of
  1181. * pci_enable_device() have called pci_disable_device().
  1182. */
  1183. void
  1184. pci_disable_device(struct pci_dev *dev)
  1185. {
  1186. struct pci_devres *dr;
  1187. dr = find_pci_dr(dev);
  1188. if (dr)
  1189. dr->enabled = 0;
  1190. dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
  1191. "disabling already-disabled device");
  1192. if (atomic_dec_return(&dev->enable_cnt) != 0)
  1193. return;
  1194. do_pci_disable_device(dev);
  1195. dev->is_busmaster = 0;
  1196. }
  1197. /**
  1198. * pcibios_set_pcie_reset_state - set reset state for device dev
  1199. * @dev: the PCIe device reset
  1200. * @state: Reset state to enter into
  1201. *
  1202. *
  1203. * Sets the PCIe reset state for the device. This is the default
  1204. * implementation. Architecture implementations can override this.
  1205. */
  1206. int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
  1207. enum pcie_reset_state state)
  1208. {
  1209. return -EINVAL;
  1210. }
  1211. /**
  1212. * pci_set_pcie_reset_state - set reset state for device dev
  1213. * @dev: the PCIe device reset
  1214. * @state: Reset state to enter into
  1215. *
  1216. *
  1217. * Sets the PCI reset state for the device.
  1218. */
  1219. int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  1220. {
  1221. return pcibios_set_pcie_reset_state(dev, state);
  1222. }
  1223. /**
  1224. * pci_check_pme_status - Check if given device has generated PME.
  1225. * @dev: Device to check.
  1226. *
  1227. * Check the PME status of the device and if set, clear it and clear PME enable
  1228. * (if set). Return 'true' if PME status and PME enable were both set or
  1229. * 'false' otherwise.
  1230. */
  1231. bool pci_check_pme_status(struct pci_dev *dev)
  1232. {
  1233. int pmcsr_pos;
  1234. u16 pmcsr;
  1235. bool ret = false;
  1236. if (!dev->pm_cap)
  1237. return false;
  1238. pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
  1239. pci_read_config_word(dev, pmcsr_pos, &pmcsr);
  1240. if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
  1241. return false;
  1242. /* Clear PME status. */
  1243. pmcsr |= PCI_PM_CTRL_PME_STATUS;
  1244. if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
  1245. /* Disable PME to avoid interrupt flood. */
  1246. pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
  1247. ret = true;
  1248. }
  1249. pci_write_config_word(dev, pmcsr_pos, pmcsr);
  1250. return ret;
  1251. }
  1252. /**
  1253. * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
  1254. * @dev: Device to handle.
  1255. * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
  1256. *
  1257. * Check if @dev has generated PME and queue a resume request for it in that
  1258. * case.
  1259. */
  1260. static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
  1261. {
  1262. if (pme_poll_reset && dev->pme_poll)
  1263. dev->pme_poll = false;
  1264. if (pci_check_pme_status(dev)) {
  1265. pci_wakeup_event(dev);
  1266. pm_request_resume(&dev->dev);
  1267. }
  1268. return 0;
  1269. }
  1270. /**
  1271. * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
  1272. * @bus: Top bus of the subtree to walk.
  1273. */
  1274. void pci_pme_wakeup_bus(struct pci_bus *bus)
  1275. {
  1276. if (bus)
  1277. pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
  1278. }
  1279. /**
  1280. * pci_wakeup - Wake up a PCI device
  1281. * @pci_dev: Device to handle.
  1282. * @ign: ignored parameter
  1283. */
  1284. static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
  1285. {
  1286. pci_wakeup_event(pci_dev);
  1287. pm_request_resume(&pci_dev->dev);
  1288. return 0;
  1289. }
  1290. /**
  1291. * pci_wakeup_bus - Walk given bus and wake up devices on it
  1292. * @bus: Top bus of the subtree to walk.
  1293. */
  1294. void pci_wakeup_bus(struct pci_bus *bus)
  1295. {
  1296. if (bus)
  1297. pci_walk_bus(bus, pci_wakeup, NULL);
  1298. }
  1299. /**
  1300. * pci_pme_capable - check the capability of PCI device to generate PME#
  1301. * @dev: PCI device to handle.
  1302. * @state: PCI state from which device will issue PME#.
  1303. */
  1304. bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
  1305. {
  1306. if (!dev->pm_cap)
  1307. return false;
  1308. return !!(dev->pme_support & (1 << state));
  1309. }
  1310. static void pci_pme_list_scan(struct work_struct *work)
  1311. {
  1312. struct pci_pme_device *pme_dev, *n;
  1313. mutex_lock(&pci_pme_list_mutex);
  1314. if (!list_empty(&pci_pme_list)) {
  1315. list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
  1316. if (pme_dev->dev->pme_poll) {
  1317. struct pci_dev *bridge;
  1318. bridge = pme_dev->dev->bus->self;
  1319. /*
  1320. * If bridge is in low power state, the
  1321. * configuration space of subordinate devices
  1322. * may be not accessible
  1323. */
  1324. if (bridge && bridge->current_state != PCI_D0)
  1325. continue;
  1326. pci_pme_wakeup(pme_dev->dev, NULL);
  1327. } else {
  1328. list_del(&pme_dev->list);
  1329. kfree(pme_dev);
  1330. }
  1331. }
  1332. if (!list_empty(&pci_pme_list))
  1333. schedule_delayed_work(&pci_pme_work,
  1334. msecs_to_jiffies(PME_TIMEOUT));
  1335. }
  1336. mutex_unlock(&pci_pme_list_mutex);
  1337. }
  1338. /**
  1339. * pci_pme_active - enable or disable PCI device's PME# function
  1340. * @dev: PCI device to handle.
  1341. * @enable: 'true' to enable PME# generation; 'false' to disable it.
  1342. *
  1343. * The caller must verify that the device is capable of generating PME# before
  1344. * calling this function with @enable equal to 'true'.
  1345. */
  1346. void pci_pme_active(struct pci_dev *dev, bool enable)
  1347. {
  1348. u16 pmcsr;
  1349. if (!dev->pme_support)
  1350. return;
  1351. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  1352. /* Clear PME_Status by writing 1 to it and enable PME# */
  1353. pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
  1354. if (!enable)
  1355. pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
  1356. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
  1357. /*
  1358. * PCI (as opposed to PCIe) PME requires that the device have
  1359. * its PME# line hooked up correctly. Not all hardware vendors
  1360. * do this, so the PME never gets delivered and the device
  1361. * remains asleep. The easiest way around this is to
  1362. * periodically walk the list of suspended devices and check
  1363. * whether any have their PME flag set. The assumption is that
  1364. * we'll wake up often enough anyway that this won't be a huge
  1365. * hit, and the power savings from the devices will still be a
  1366. * win.
  1367. *
  1368. * Although PCIe uses in-band PME message instead of PME# line
  1369. * to report PME, PME does not work for some PCIe devices in
  1370. * reality. For example, there are devices that set their PME
  1371. * status bits, but don't really bother to send a PME message;
  1372. * there are PCI Express Root Ports that don't bother to
  1373. * trigger interrupts when they receive PME messages from the
  1374. * devices below. So PME poll is used for PCIe devices too.
  1375. */
  1376. if (dev->pme_poll) {
  1377. struct pci_pme_device *pme_dev;
  1378. if (enable) {
  1379. pme_dev = kmalloc(sizeof(struct pci_pme_device),
  1380. GFP_KERNEL);
  1381. if (!pme_dev)
  1382. goto out;
  1383. pme_dev->dev = dev;
  1384. mutex_lock(&pci_pme_list_mutex);
  1385. list_add(&pme_dev->list, &pci_pme_list);
  1386. if (list_is_singular(&pci_pme_list))
  1387. schedule_delayed_work(&pci_pme_work,
  1388. msecs_to_jiffies(PME_TIMEOUT));
  1389. mutex_unlock(&pci_pme_list_mutex);
  1390. } else {
  1391. mutex_lock(&pci_pme_list_mutex);
  1392. list_for_each_entry(pme_dev, &pci_pme_list, list) {
  1393. if (pme_dev->dev == dev) {
  1394. list_del(&pme_dev->list);
  1395. kfree(pme_dev);
  1396. break;
  1397. }
  1398. }
  1399. mutex_unlock(&pci_pme_list_mutex);
  1400. }
  1401. }
  1402. out:
  1403. dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
  1404. }
  1405. /**
  1406. * __pci_enable_wake - enable PCI device as wakeup event source
  1407. * @dev: PCI device affected
  1408. * @state: PCI state from which device will issue wakeup events
  1409. * @runtime: True if the events are to be generated at run time
  1410. * @enable: True to enable event generation; false to disable
  1411. *
  1412. * This enables the device as a wakeup event source, or disables it.
  1413. * When such events involves platform-specific hooks, those hooks are
  1414. * called automatically by this routine.
  1415. *
  1416. * Devices with legacy power management (no standard PCI PM capabilities)
  1417. * always require such platform hooks.
  1418. *
  1419. * RETURN VALUE:
  1420. * 0 is returned on success
  1421. * -EINVAL is returned if device is not supposed to wake up the system
  1422. * Error code depending on the platform is returned if both the platform and
  1423. * the native mechanism fail to enable the generation of wake-up events
  1424. */
  1425. int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
  1426. bool runtime, bool enable)
  1427. {
  1428. int ret = 0;
  1429. if (enable && !runtime && !device_may_wakeup(&dev->dev))
  1430. return -EINVAL;
  1431. /* Don't do the same thing twice in a row for one device. */
  1432. if (!!enable == !!dev->wakeup_prepared)
  1433. return 0;
  1434. /*
  1435. * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
  1436. * Anderson we should be doing PME# wake enable followed by ACPI wake
  1437. * enable. To disable wake-up we call the platform first, for symmetry.
  1438. */
  1439. if (enable) {
  1440. int error;
  1441. if (pci_pme_capable(dev, state))
  1442. pci_pme_active(dev, true);
  1443. else
  1444. ret = 1;
  1445. error = runtime ? platform_pci_run_wake(dev, true) :
  1446. platform_pci_sleep_wake(dev, true);
  1447. if (ret)
  1448. ret = error;
  1449. if (!ret)
  1450. dev->wakeup_prepared = true;
  1451. } else {
  1452. if (runtime)
  1453. platform_pci_run_wake(dev, false);
  1454. else
  1455. platform_pci_sleep_wake(dev, false);
  1456. pci_pme_active(dev, false);
  1457. dev->wakeup_prepared = false;
  1458. }
  1459. return ret;
  1460. }
  1461. EXPORT_SYMBOL(__pci_enable_wake);
  1462. /**
  1463. * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
  1464. * @dev: PCI device to prepare
  1465. * @enable: True to enable wake-up event generation; false to disable
  1466. *
  1467. * Many drivers want the device to wake up the system from D3_hot or D3_cold
  1468. * and this function allows them to set that up cleanly - pci_enable_wake()
  1469. * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
  1470. * ordering constraints.
  1471. *
  1472. * This function only returns error code if the device is not capable of
  1473. * generating PME# from both D3_hot and D3_cold, and the platform is unable to
  1474. * enable wake-up power for it.
  1475. */
  1476. int pci_wake_from_d3(struct pci_dev *dev, bool enable)
  1477. {
  1478. return pci_pme_capable(dev, PCI_D3cold) ?
  1479. pci_enable_wake(dev, PCI_D3cold, enable) :
  1480. pci_enable_wake(dev, PCI_D3hot, enable);
  1481. }
  1482. /**
  1483. * pci_target_state - find an appropriate low power state for a given PCI dev
  1484. * @dev: PCI device
  1485. *
  1486. * Use underlying platform code to find a supported low power state for @dev.
  1487. * If the platform can't manage @dev, return the deepest state from which it
  1488. * can generate wake events, based on any available PME info.
  1489. */
  1490. pci_power_t pci_target_state(struct pci_dev *dev)
  1491. {
  1492. pci_power_t target_state = PCI_D3hot;
  1493. if (platform_pci_power_manageable(dev)) {
  1494. /*
  1495. * Call the platform to choose the target state of the device
  1496. * and enable wake-up from this state if supported.
  1497. */
  1498. pci_power_t state = platform_pci_choose_state(dev);
  1499. switch (state) {
  1500. case PCI_POWER_ERROR:
  1501. case PCI_UNKNOWN:
  1502. break;
  1503. case PCI_D1:
  1504. case PCI_D2:
  1505. if (pci_no_d1d2(dev))
  1506. break;
  1507. default:
  1508. target_state = state;
  1509. }
  1510. } else if (!dev->pm_cap) {
  1511. target_state = PCI_D0;
  1512. } else if (device_may_wakeup(&dev->dev)) {
  1513. /*
  1514. * Find the deepest state from which the device can generate
  1515. * wake-up events, make it the target state and enable device
  1516. * to generate PME#.
  1517. */
  1518. if (dev->pme_support) {
  1519. while (target_state
  1520. && !(dev->pme_support & (1 << target_state)))
  1521. target_state--;
  1522. }
  1523. }
  1524. return target_state;
  1525. }
  1526. /**
  1527. * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
  1528. * @dev: Device to handle.
  1529. *
  1530. * Choose the power state appropriate for the device depending on whether
  1531. * it can wake up the system and/or is power manageable by the platform
  1532. * (PCI_D3hot is the default) and put the device into that state.
  1533. */
  1534. int pci_prepare_to_sleep(struct pci_dev *dev)
  1535. {
  1536. pci_power_t target_state = pci_target_state(dev);
  1537. int error;
  1538. if (target_state == PCI_POWER_ERROR)
  1539. return -EIO;
  1540. /* D3cold during system suspend/hibernate is not supported */
  1541. if (target_state > PCI_D3hot)
  1542. target_state = PCI_D3hot;
  1543. pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
  1544. error = pci_set_power_state(dev, target_state);
  1545. if (error)
  1546. pci_enable_wake(dev, target_state, false);
  1547. return error;
  1548. }
  1549. /**
  1550. * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
  1551. * @dev: Device to handle.
  1552. *
  1553. * Disable device's system wake-up capability and put it into D0.
  1554. */
  1555. int pci_back_from_sleep(struct pci_dev *dev)
  1556. {
  1557. pci_enable_wake(dev, PCI_D0, false);
  1558. return pci_set_power_state(dev, PCI_D0);
  1559. }
  1560. /**
  1561. * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
  1562. * @dev: PCI device being suspended.
  1563. *
  1564. * Prepare @dev to generate wake-up events at run time and put it into a low
  1565. * power state.
  1566. */
  1567. int pci_finish_runtime_suspend(struct pci_dev *dev)
  1568. {
  1569. pci_power_t target_state = pci_target_state(dev);
  1570. int error;
  1571. if (target_state == PCI_POWER_ERROR)
  1572. return -EIO;
  1573. dev->runtime_d3cold = target_state == PCI_D3cold;
  1574. __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
  1575. error = pci_set_power_state(dev, target_state);
  1576. if (error) {
  1577. __pci_enable_wake(dev, target_state, true, false);
  1578. dev->runtime_d3cold = false;
  1579. }
  1580. return error;
  1581. }
  1582. /**
  1583. * pci_dev_run_wake - Check if device can generate run-time wake-up events.
  1584. * @dev: Device to check.
  1585. *
  1586. * Return true if the device itself is cabable of generating wake-up events
  1587. * (through the platform or using the native PCIe PME) or if the device supports
  1588. * PME and one of its upstream bridges can generate wake-up events.
  1589. */
  1590. bool pci_dev_run_wake(struct pci_dev *dev)
  1591. {
  1592. struct pci_bus *bus = dev->bus;
  1593. if (device_run_wake(&dev->dev))
  1594. return true;
  1595. if (!dev->pme_support)
  1596. return false;
  1597. while (bus->parent) {
  1598. struct pci_dev *bridge = bus->self;
  1599. if (device_run_wake(&bridge->dev))
  1600. return true;
  1601. bus = bus->parent;
  1602. }
  1603. /* We have reached the root bus. */
  1604. if (bus->bridge)
  1605. return device_run_wake(bus->bridge);
  1606. return false;
  1607. }
  1608. EXPORT_SYMBOL_GPL(pci_dev_run_wake);
  1609. void pci_config_pm_runtime_get(struct pci_dev *pdev)
  1610. {
  1611. struct device *dev = &pdev->dev;
  1612. struct device *parent = dev->parent;
  1613. if (parent)
  1614. pm_runtime_get_sync(parent);
  1615. pm_runtime_get_noresume(dev);
  1616. /*
  1617. * pdev->current_state is set to PCI_D3cold during suspending,
  1618. * so wait until suspending completes
  1619. */
  1620. pm_runtime_barrier(dev);
  1621. /*
  1622. * Only need to resume devices in D3cold, because config
  1623. * registers are still accessible for devices suspended but
  1624. * not in D3cold.
  1625. */
  1626. if (pdev->current_state == PCI_D3cold)
  1627. pm_runtime_resume(dev);
  1628. }
  1629. void pci_config_pm_runtime_put(struct pci_dev *pdev)
  1630. {
  1631. struct device *dev = &pdev->dev;
  1632. struct device *parent = dev->parent;
  1633. pm_runtime_put(dev);
  1634. if (parent)
  1635. pm_runtime_put_sync(parent);
  1636. }
  1637. /**
  1638. * pci_pm_init - Initialize PM functions of given PCI device
  1639. * @dev: PCI device to handle.
  1640. */
  1641. void pci_pm_init(struct pci_dev *dev)
  1642. {
  1643. int pm;
  1644. u16 pmc;
  1645. pm_runtime_forbid(&dev->dev);
  1646. pm_runtime_set_active(&dev->dev);
  1647. pm_runtime_enable(&dev->dev);
  1648. device_enable_async_suspend(&dev->dev);
  1649. dev->wakeup_prepared = false;
  1650. dev->pm_cap = 0;
  1651. dev->pme_support = 0;
  1652. /* find PCI PM capability in list */
  1653. pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  1654. if (!pm)
  1655. return;
  1656. /* Check device's ability to generate PME# */
  1657. pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
  1658. if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
  1659. dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
  1660. pmc & PCI_PM_CAP_VER_MASK);
  1661. return;
  1662. }
  1663. dev->pm_cap = pm;
  1664. dev->d3_delay = PCI_PM_D3_WAIT;
  1665. dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
  1666. dev->d3cold_allowed = true;
  1667. dev->d1_support = false;
  1668. dev->d2_support = false;
  1669. if (!pci_no_d1d2(dev)) {
  1670. if (pmc & PCI_PM_CAP_D1)
  1671. dev->d1_support = true;
  1672. if (pmc & PCI_PM_CAP_D2)
  1673. dev->d2_support = true;
  1674. if (dev->d1_support || dev->d2_support)
  1675. dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
  1676. dev->d1_support ? " D1" : "",
  1677. dev->d2_support ? " D2" : "");
  1678. }
  1679. pmc &= PCI_PM_CAP_PME_MASK;
  1680. if (pmc) {
  1681. dev_printk(KERN_DEBUG, &dev->dev,
  1682. "PME# supported from%s%s%s%s%s\n",
  1683. (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
  1684. (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
  1685. (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
  1686. (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
  1687. (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
  1688. dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
  1689. dev->pme_poll = true;
  1690. /*
  1691. * Make device's PM flags reflect the wake-up capability, but
  1692. * let the user space enable it to wake up the system as needed.
  1693. */
  1694. device_set_wakeup_capable(&dev->dev, true);
  1695. /* Disable the PME# generation functionality */
  1696. pci_pme_active(dev, false);
  1697. }
  1698. }
  1699. static void pci_add_saved_cap(struct pci_dev *pci_dev,
  1700. struct pci_cap_saved_state *new_cap)
  1701. {
  1702. hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
  1703. }
  1704. /**
  1705. * pci_add_save_buffer - allocate buffer for saving given capability registers
  1706. * @dev: the PCI device
  1707. * @cap: the capability to allocate the buffer for
  1708. * @size: requested size of the buffer
  1709. */
  1710. static int pci_add_cap_save_buffer(
  1711. struct pci_dev *dev, char cap, unsigned int size)
  1712. {
  1713. int pos;
  1714. struct pci_cap_saved_state *save_state;
  1715. pos = pci_find_capability(dev, cap);
  1716. if (pos <= 0)
  1717. return 0;
  1718. save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
  1719. if (!save_state)
  1720. return -ENOMEM;
  1721. save_state->cap.cap_nr = cap;
  1722. save_state->cap.size = size;
  1723. pci_add_saved_cap(dev, save_state);
  1724. return 0;
  1725. }
  1726. /**
  1727. * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
  1728. * @dev: the PCI device
  1729. */
  1730. void pci_allocate_cap_save_buffers(struct pci_dev *dev)
  1731. {
  1732. int error;
  1733. error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
  1734. PCI_EXP_SAVE_REGS * sizeof(u16));
  1735. if (error)
  1736. dev_err(&dev->dev,
  1737. "unable to preallocate PCI Express save buffer\n");
  1738. error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
  1739. if (error)
  1740. dev_err(&dev->dev,
  1741. "unable to preallocate PCI-X save buffer\n");
  1742. }
  1743. void pci_free_cap_save_buffers(struct pci_dev *dev)
  1744. {
  1745. struct pci_cap_saved_state *tmp;
  1746. struct hlist_node *n;
  1747. hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
  1748. kfree(tmp);
  1749. }
  1750. /**
  1751. * pci_configure_ari - enable or disable ARI forwarding
  1752. * @dev: the PCI device
  1753. *
  1754. * If @dev and its upstream bridge both support ARI, enable ARI in the
  1755. * bridge. Otherwise, disable ARI in the bridge.
  1756. */
  1757. void pci_configure_ari(struct pci_dev *dev)
  1758. {
  1759. u32 cap;
  1760. struct pci_dev *bridge;
  1761. if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
  1762. return;
  1763. bridge = dev->bus->self;
  1764. if (!bridge)
  1765. return;
  1766. pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
  1767. if (!(cap & PCI_EXP_DEVCAP2_ARI))
  1768. return;
  1769. if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
  1770. pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
  1771. PCI_EXP_DEVCTL2_ARI);
  1772. bridge->ari_enabled = 1;
  1773. } else {
  1774. pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
  1775. PCI_EXP_DEVCTL2_ARI);
  1776. bridge->ari_enabled = 0;
  1777. }
  1778. }
  1779. /**
  1780. * pci_enable_ido - enable ID-based Ordering on a device
  1781. * @dev: the PCI device
  1782. * @type: which types of IDO to enable
  1783. *
  1784. * Enable ID-based ordering on @dev. @type can contain the bits
  1785. * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
  1786. * which types of transactions are allowed to be re-ordered.
  1787. */
  1788. void pci_enable_ido(struct pci_dev *dev, unsigned long type)
  1789. {
  1790. u16 ctrl = 0;
  1791. if (type & PCI_EXP_IDO_REQUEST)
  1792. ctrl |= PCI_EXP_IDO_REQ_EN;
  1793. if (type & PCI_EXP_IDO_COMPLETION)
  1794. ctrl |= PCI_EXP_IDO_CMP_EN;
  1795. if (ctrl)
  1796. pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
  1797. }
  1798. EXPORT_SYMBOL(pci_enable_ido);
  1799. /**
  1800. * pci_disable_ido - disable ID-based ordering on a device
  1801. * @dev: the PCI device
  1802. * @type: which types of IDO to disable
  1803. */
  1804. void pci_disable_ido(struct pci_dev *dev, unsigned long type)
  1805. {
  1806. u16 ctrl = 0;
  1807. if (type & PCI_EXP_IDO_REQUEST)
  1808. ctrl |= PCI_EXP_IDO_REQ_EN;
  1809. if (type & PCI_EXP_IDO_COMPLETION)
  1810. ctrl |= PCI_EXP_IDO_CMP_EN;
  1811. if (ctrl)
  1812. pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
  1813. }
  1814. EXPORT_SYMBOL(pci_disable_ido);
  1815. /**
  1816. * pci_enable_obff - enable optimized buffer flush/fill
  1817. * @dev: PCI device
  1818. * @type: type of signaling to use
  1819. *
  1820. * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
  1821. * signaling if possible, falling back to message signaling only if
  1822. * WAKE# isn't supported. @type should indicate whether the PCIe link
  1823. * be brought out of L0s or L1 to send the message. It should be either
  1824. * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
  1825. *
  1826. * If your device can benefit from receiving all messages, even at the
  1827. * power cost of bringing the link back up from a low power state, use
  1828. * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
  1829. * preferred type).
  1830. *
  1831. * RETURNS:
  1832. * Zero on success, appropriate error number on failure.
  1833. */
  1834. int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
  1835. {
  1836. u32 cap;
  1837. u16 ctrl;
  1838. int ret;
  1839. pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
  1840. if (!(cap & PCI_EXP_OBFF_MASK))
  1841. return -ENOTSUPP; /* no OBFF support at all */
  1842. /* Make sure the topology supports OBFF as well */
  1843. if (dev->bus->self) {
  1844. ret = pci_enable_obff(dev->bus->self, type);
  1845. if (ret)
  1846. return ret;
  1847. }
  1848. pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
  1849. if (cap & PCI_EXP_OBFF_WAKE)
  1850. ctrl |= PCI_EXP_OBFF_WAKE_EN;
  1851. else {
  1852. switch (type) {
  1853. case PCI_EXP_OBFF_SIGNAL_L0:
  1854. if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
  1855. ctrl |= PCI_EXP_OBFF_MSGA_EN;
  1856. break;
  1857. case PCI_EXP_OBFF_SIGNAL_ALWAYS:
  1858. ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
  1859. ctrl |= PCI_EXP_OBFF_MSGB_EN;
  1860. break;
  1861. default:
  1862. WARN(1, "bad OBFF signal type\n");
  1863. return -ENOTSUPP;
  1864. }
  1865. }
  1866. pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
  1867. return 0;
  1868. }
  1869. EXPORT_SYMBOL(pci_enable_obff);
  1870. /**
  1871. * pci_disable_obff - disable optimized buffer flush/fill
  1872. * @dev: PCI device
  1873. *
  1874. * Disable OBFF on @dev.
  1875. */
  1876. void pci_disable_obff(struct pci_dev *dev)
  1877. {
  1878. pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
  1879. }
  1880. EXPORT_SYMBOL(pci_disable_obff);
  1881. /**
  1882. * pci_ltr_supported - check whether a device supports LTR
  1883. * @dev: PCI device
  1884. *
  1885. * RETURNS:
  1886. * True if @dev supports latency tolerance reporting, false otherwise.
  1887. */
  1888. static bool pci_ltr_supported(struct pci_dev *dev)
  1889. {
  1890. u32 cap;
  1891. pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
  1892. return cap & PCI_EXP_DEVCAP2_LTR;
  1893. }
  1894. /**
  1895. * pci_enable_ltr - enable latency tolerance reporting
  1896. * @dev: PCI device
  1897. *
  1898. * Enable LTR on @dev if possible, which means enabling it first on
  1899. * upstream ports.
  1900. *
  1901. * RETURNS:
  1902. * Zero on success, errno on failure.
  1903. */
  1904. int pci_enable_ltr(struct pci_dev *dev)
  1905. {
  1906. int ret;
  1907. /* Only primary function can enable/disable LTR */
  1908. if (PCI_FUNC(dev->devfn) != 0)
  1909. return -EINVAL;
  1910. if (!pci_ltr_supported(dev))
  1911. return -ENOTSUPP;
  1912. /* Enable upstream ports first */
  1913. if (dev->bus->self) {
  1914. ret = pci_enable_ltr(dev->bus->self);
  1915. if (ret)
  1916. return ret;
  1917. }
  1918. return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
  1919. }
  1920. EXPORT_SYMBOL(pci_enable_ltr);
  1921. /**
  1922. * pci_disable_ltr - disable latency tolerance reporting
  1923. * @dev: PCI device
  1924. */
  1925. void pci_disable_ltr(struct pci_dev *dev)
  1926. {
  1927. /* Only primary function can enable/disable LTR */
  1928. if (PCI_FUNC(dev->devfn) != 0)
  1929. return;
  1930. if (!pci_ltr_supported(dev))
  1931. return;
  1932. pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
  1933. }
  1934. EXPORT_SYMBOL(pci_disable_ltr);
  1935. static int __pci_ltr_scale(int *val)
  1936. {
  1937. int scale = 0;
  1938. while (*val > 1023) {
  1939. *val = (*val + 31) / 32;
  1940. scale++;
  1941. }
  1942. return scale;
  1943. }
  1944. /**
  1945. * pci_set_ltr - set LTR latency values
  1946. * @dev: PCI device
  1947. * @snoop_lat_ns: snoop latency in nanoseconds
  1948. * @nosnoop_lat_ns: nosnoop latency in nanoseconds
  1949. *
  1950. * Figure out the scale and set the LTR values accordingly.
  1951. */
  1952. int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
  1953. {
  1954. int pos, ret, snoop_scale, nosnoop_scale;
  1955. u16 val;
  1956. if (!pci_ltr_supported(dev))
  1957. return -ENOTSUPP;
  1958. snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
  1959. nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
  1960. if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
  1961. nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
  1962. return -EINVAL;
  1963. if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
  1964. (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
  1965. return -EINVAL;
  1966. pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
  1967. if (!pos)
  1968. return -ENOTSUPP;
  1969. val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
  1970. ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
  1971. if (ret != 4)
  1972. return -EIO;
  1973. val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
  1974. ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
  1975. if (ret != 4)
  1976. return -EIO;
  1977. return 0;
  1978. }
  1979. EXPORT_SYMBOL(pci_set_ltr);
  1980. static int pci_acs_enable;
  1981. /**
  1982. * pci_request_acs - ask for ACS to be enabled if supported
  1983. */
  1984. void pci_request_acs(void)
  1985. {
  1986. pci_acs_enable = 1;
  1987. }
  1988. /**
  1989. * pci_enable_acs - enable ACS if hardware support it
  1990. * @dev: the PCI device
  1991. */
  1992. void pci_enable_acs(struct pci_dev *dev)
  1993. {
  1994. int pos;
  1995. u16 cap;
  1996. u16 ctrl;
  1997. if (!pci_acs_enable)
  1998. return;
  1999. pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
  2000. if (!pos)
  2001. return;
  2002. pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
  2003. pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
  2004. /* Source Validation */
  2005. ctrl |= (cap & PCI_ACS_SV);
  2006. /* P2P Request Redirect */
  2007. ctrl |= (cap & PCI_ACS_RR);
  2008. /* P2P Completion Redirect */
  2009. ctrl |= (cap & PCI_ACS_CR);
  2010. /* Upstream Forwarding */
  2011. ctrl |= (cap & PCI_ACS_UF);
  2012. pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
  2013. }
  2014. /**
  2015. * pci_acs_enabled - test ACS against required flags for a given device
  2016. * @pdev: device to test
  2017. * @acs_flags: required PCI ACS flags
  2018. *
  2019. * Return true if the device supports the provided flags. Automatically
  2020. * filters out flags that are not implemented on multifunction devices.
  2021. */
  2022. bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
  2023. {
  2024. int pos, ret;
  2025. u16 ctrl;
  2026. ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
  2027. if (ret >= 0)
  2028. return ret > 0;
  2029. if (!pci_is_pcie(pdev))
  2030. return false;
  2031. /* Filter out flags not applicable to multifunction */
  2032. if (pdev->multifunction)
  2033. acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
  2034. PCI_ACS_EC | PCI_ACS_DT);
  2035. if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
  2036. pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
  2037. pdev->multifunction) {
  2038. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
  2039. if (!pos)
  2040. return false;
  2041. pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
  2042. if ((ctrl & acs_flags) != acs_flags)
  2043. return false;
  2044. }
  2045. return true;
  2046. }
  2047. /**
  2048. * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
  2049. * @start: starting downstream device
  2050. * @end: ending upstream device or NULL to search to the root bus
  2051. * @acs_flags: required flags
  2052. *
  2053. * Walk up a device tree from start to end testing PCI ACS support. If
  2054. * any step along the way does not support the required flags, return false.
  2055. */
  2056. bool pci_acs_path_enabled(struct pci_dev *start,
  2057. struct pci_dev *end, u16 acs_flags)
  2058. {
  2059. struct pci_dev *pdev, *parent = start;
  2060. do {
  2061. pdev = parent;
  2062. if (!pci_acs_enabled(pdev, acs_flags))
  2063. return false;
  2064. if (pci_is_root_bus(pdev->bus))
  2065. return (end == NULL);
  2066. parent = pdev->bus->self;
  2067. } while (pdev != end);
  2068. return true;
  2069. }
  2070. /**
  2071. * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
  2072. * @dev: the PCI device
  2073. * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
  2074. *
  2075. * Perform INTx swizzling for a device behind one level of bridge. This is
  2076. * required by section 9.1 of the PCI-to-PCI bridge specification for devices
  2077. * behind bridges on add-in cards. For devices with ARI enabled, the slot
  2078. * number is always 0 (see the Implementation Note in section 2.2.8.1 of
  2079. * the PCI Express Base Specification, Revision 2.1)
  2080. */
  2081. u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
  2082. {
  2083. int slot;
  2084. if (pci_ari_enabled(dev->bus))
  2085. slot = 0;
  2086. else
  2087. slot = PCI_SLOT(dev->devfn);
  2088. return (((pin - 1) + slot) % 4) + 1;
  2089. }
  2090. int
  2091. pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
  2092. {
  2093. u8 pin;
  2094. pin = dev->pin;
  2095. if (!pin)
  2096. return -1;
  2097. while (!pci_is_root_bus(dev->bus)) {
  2098. pin = pci_swizzle_interrupt_pin(dev, pin);
  2099. dev = dev->bus->self;
  2100. }
  2101. *bridge = dev;
  2102. return pin;
  2103. }
  2104. /**
  2105. * pci_common_swizzle - swizzle INTx all the way to root bridge
  2106. * @dev: the PCI device
  2107. * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
  2108. *
  2109. * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
  2110. * bridges all the way up to a PCI root bus.
  2111. */
  2112. u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
  2113. {
  2114. u8 pin = *pinp;
  2115. while (!pci_is_root_bus(dev->bus)) {
  2116. pin = pci_swizzle_interrupt_pin(dev, pin);
  2117. dev = dev->bus->self;
  2118. }
  2119. *pinp = pin;
  2120. return PCI_SLOT(dev->devfn);
  2121. }
  2122. /**
  2123. * pci_release_region - Release a PCI bar
  2124. * @pdev: PCI device whose resources were previously reserved by pci_request_region
  2125. * @bar: BAR to release
  2126. *
  2127. * Releases the PCI I/O and memory resources previously reserved by a
  2128. * successful call to pci_request_region. Call this function only
  2129. * after all use of the PCI regions has ceased.
  2130. */
  2131. void pci_release_region(struct pci_dev *pdev, int bar)
  2132. {
  2133. struct pci_devres *dr;
  2134. if (pci_resource_len(pdev, bar) == 0)
  2135. return;
  2136. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
  2137. release_region(pci_resource_start(pdev, bar),
  2138. pci_resource_len(pdev, bar));
  2139. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
  2140. release_mem_region(pci_resource_start(pdev, bar),
  2141. pci_resource_len(pdev, bar));
  2142. dr = find_pci_dr(pdev);
  2143. if (dr)
  2144. dr->region_mask &= ~(1 << bar);
  2145. }
  2146. /**
  2147. * __pci_request_region - Reserved PCI I/O and memory resource
  2148. * @pdev: PCI device whose resources are to be reserved
  2149. * @bar: BAR to be reserved
  2150. * @res_name: Name to be associated with resource.
  2151. * @exclusive: whether the region access is exclusive or not
  2152. *
  2153. * Mark the PCI region associated with PCI device @pdev BR @bar as
  2154. * being reserved by owner @res_name. Do not access any
  2155. * address inside the PCI regions unless this call returns
  2156. * successfully.
  2157. *
  2158. * If @exclusive is set, then the region is marked so that userspace
  2159. * is explicitly not allowed to map the resource via /dev/mem or
  2160. * sysfs MMIO access.
  2161. *
  2162. * Returns 0 on success, or %EBUSY on error. A warning
  2163. * message is also printed on failure.
  2164. */
  2165. static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
  2166. int exclusive)
  2167. {
  2168. struct pci_devres *dr;
  2169. if (pci_resource_len(pdev, bar) == 0)
  2170. return 0;
  2171. if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
  2172. if (!request_region(pci_resource_start(pdev, bar),
  2173. pci_resource_len(pdev, bar), res_name))
  2174. goto err_out;
  2175. }
  2176. else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
  2177. if (!__request_mem_region(pci_resource_start(pdev, bar),
  2178. pci_resource_len(pdev, bar), res_name,
  2179. exclusive))
  2180. goto err_out;
  2181. }
  2182. dr = find_pci_dr(pdev);
  2183. if (dr)
  2184. dr->region_mask |= 1 << bar;
  2185. return 0;
  2186. err_out:
  2187. dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
  2188. &pdev->resource[bar]);
  2189. return -EBUSY;
  2190. }
  2191. /**
  2192. * pci_request_region - Reserve PCI I/O and memory resource
  2193. * @pdev: PCI device whose resources are to be reserved
  2194. * @bar: BAR to be reserved
  2195. * @res_name: Name to be associated with resource
  2196. *
  2197. * Mark the PCI region associated with PCI device @pdev BAR @bar as
  2198. * being reserved by owner @res_name. Do not access any
  2199. * address inside the PCI regions unless this call returns
  2200. * successfully.
  2201. *
  2202. * Returns 0 on success, or %EBUSY on error. A warning
  2203. * message is also printed on failure.
  2204. */
  2205. int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
  2206. {
  2207. return __pci_request_region(pdev, bar, res_name, 0);
  2208. }
  2209. /**
  2210. * pci_request_region_exclusive - Reserved PCI I/O and memory resource
  2211. * @pdev: PCI device whose resources are to be reserved
  2212. * @bar: BAR to be reserved
  2213. * @res_name: Name to be associated with resource.
  2214. *
  2215. * Mark the PCI region associated with PCI device @pdev BR @bar as
  2216. * being reserved by owner @res_name. Do not access any
  2217. * address inside the PCI regions unless this call returns
  2218. * successfully.
  2219. *
  2220. * Returns 0 on success, or %EBUSY on error. A warning
  2221. * message is also printed on failure.
  2222. *
  2223. * The key difference that _exclusive makes it that userspace is
  2224. * explicitly not allowed to map the resource via /dev/mem or
  2225. * sysfs.
  2226. */
  2227. int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
  2228. {
  2229. return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
  2230. }
  2231. /**
  2232. * pci_release_selected_regions - Release selected PCI I/O and memory resources
  2233. * @pdev: PCI device whose resources were previously reserved
  2234. * @bars: Bitmask of BARs to be released
  2235. *
  2236. * Release selected PCI I/O and memory resources previously reserved.
  2237. * Call this function only after all use of the PCI regions has ceased.
  2238. */
  2239. void pci_release_selected_regions(struct pci_dev *pdev, int bars)
  2240. {
  2241. int i;
  2242. for (i = 0; i < 6; i++)
  2243. if (bars & (1 << i))
  2244. pci_release_region(pdev, i);
  2245. }
  2246. static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
  2247. const char *res_name, int excl)
  2248. {
  2249. int i;
  2250. for (i = 0; i < 6; i++)
  2251. if (bars & (1 << i))
  2252. if (__pci_request_region(pdev, i, res_name, excl))
  2253. goto err_out;
  2254. return 0;
  2255. err_out:
  2256. while(--i >= 0)
  2257. if (bars & (1 << i))
  2258. pci_release_region(pdev, i);
  2259. return -EBUSY;
  2260. }
  2261. /**
  2262. * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
  2263. * @pdev: PCI device whose resources are to be reserved
  2264. * @bars: Bitmask of BARs to be requested
  2265. * @res_name: Name to be associated with resource
  2266. */
  2267. int pci_request_selected_regions(struct pci_dev *pdev, int bars,
  2268. const char *res_name)
  2269. {
  2270. return __pci_request_selected_regions(pdev, bars, res_name, 0);
  2271. }
  2272. int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
  2273. int bars, const char *res_name)
  2274. {
  2275. return __pci_request_selected_regions(pdev, bars, res_name,
  2276. IORESOURCE_EXCLUSIVE);
  2277. }
  2278. /**
  2279. * pci_release_regions - Release reserved PCI I/O and memory resources
  2280. * @pdev: PCI device whose resources were previously reserved by pci_request_regions
  2281. *
  2282. * Releases all PCI I/O and memory resources previously reserved by a
  2283. * successful call to pci_request_regions. Call this function only
  2284. * after all use of the PCI regions has ceased.
  2285. */
  2286. void pci_release_regions(struct pci_dev *pdev)
  2287. {
  2288. pci_release_selected_regions(pdev, (1 << 6) - 1);
  2289. }
  2290. /**
  2291. * pci_request_regions - Reserved PCI I/O and memory resources
  2292. * @pdev: PCI device whose resources are to be reserved
  2293. * @res_name: Name to be associated with resource.
  2294. *
  2295. * Mark all PCI regions associated with PCI device @pdev as
  2296. * being reserved by owner @res_name. Do not access any
  2297. * address inside the PCI regions unless this call returns
  2298. * successfully.
  2299. *
  2300. * Returns 0 on success, or %EBUSY on error. A warning
  2301. * message is also printed on failure.
  2302. */
  2303. int pci_request_regions(struct pci_dev *pdev, const char *res_name)
  2304. {
  2305. return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
  2306. }
  2307. /**
  2308. * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
  2309. * @pdev: PCI device whose resources are to be reserved
  2310. * @res_name: Name to be associated with resource.
  2311. *
  2312. * Mark all PCI regions associated with PCI device @pdev as
  2313. * being reserved by owner @res_name. Do not access any
  2314. * address inside the PCI regions unless this call returns
  2315. * successfully.
  2316. *
  2317. * pci_request_regions_exclusive() will mark the region so that
  2318. * /dev/mem and the sysfs MMIO access will not be allowed.
  2319. *
  2320. * Returns 0 on success, or %EBUSY on error. A warning
  2321. * message is also printed on failure.
  2322. */
  2323. int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
  2324. {
  2325. return pci_request_selected_regions_exclusive(pdev,
  2326. ((1 << 6) - 1), res_name);
  2327. }
  2328. static void __pci_set_master(struct pci_dev *dev, bool enable)
  2329. {
  2330. u16 old_cmd, cmd;
  2331. pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
  2332. if (enable)
  2333. cmd = old_cmd | PCI_COMMAND_MASTER;
  2334. else
  2335. cmd = old_cmd & ~PCI_COMMAND_MASTER;
  2336. if (cmd != old_cmd) {
  2337. dev_dbg(&dev->dev, "%s bus mastering\n",
  2338. enable ? "enabling" : "disabling");
  2339. pci_write_config_word(dev, PCI_COMMAND, cmd);
  2340. }
  2341. dev->is_busmaster = enable;
  2342. }
  2343. /**
  2344. * pcibios_setup - process "pci=" kernel boot arguments
  2345. * @str: string used to pass in "pci=" kernel boot arguments
  2346. *
  2347. * Process kernel boot arguments. This is the default implementation.
  2348. * Architecture specific implementations can override this as necessary.
  2349. */
  2350. char * __weak __init pcibios_setup(char *str)
  2351. {
  2352. return str;
  2353. }
  2354. /**
  2355. * pcibios_set_master - enable PCI bus-mastering for device dev
  2356. * @dev: the PCI device to enable
  2357. *
  2358. * Enables PCI bus-mastering for the device. This is the default
  2359. * implementation. Architecture specific implementations can override
  2360. * this if necessary.
  2361. */
  2362. void __weak pcibios_set_master(struct pci_dev *dev)
  2363. {
  2364. u8 lat;
  2365. /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
  2366. if (pci_is_pcie(dev))
  2367. return;
  2368. pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
  2369. if (lat < 16)
  2370. lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
  2371. else if (lat > pcibios_max_latency)
  2372. lat = pcibios_max_latency;
  2373. else
  2374. return;
  2375. dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
  2376. pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
  2377. }
  2378. /**
  2379. * pci_set_master - enables bus-mastering for device dev
  2380. * @dev: the PCI device to enable
  2381. *
  2382. * Enables bus-mastering on the device and calls pcibios_set_master()
  2383. * to do the needed arch specific settings.
  2384. */
  2385. void pci_set_master(struct pci_dev *dev)
  2386. {
  2387. __pci_set_master(dev, true);
  2388. pcibios_set_master(dev);
  2389. }
  2390. /**
  2391. * pci_clear_master - disables bus-mastering for device dev
  2392. * @dev: the PCI device to disable
  2393. */
  2394. void pci_clear_master(struct pci_dev *dev)
  2395. {
  2396. __pci_set_master(dev, false);
  2397. }
  2398. /**
  2399. * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
  2400. * @dev: the PCI device for which MWI is to be enabled
  2401. *
  2402. * Helper function for pci_set_mwi.
  2403. * Originally copied from drivers/net/acenic.c.
  2404. * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
  2405. *
  2406. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  2407. */
  2408. int pci_set_cacheline_size(struct pci_dev *dev)
  2409. {
  2410. u8 cacheline_size;
  2411. if (!pci_cache_line_size)
  2412. return -EINVAL;
  2413. /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
  2414. equal to or multiple of the right value. */
  2415. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  2416. if (cacheline_size >= pci_cache_line_size &&
  2417. (cacheline_size % pci_cache_line_size) == 0)
  2418. return 0;
  2419. /* Write the correct value. */
  2420. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
  2421. /* Read it back. */
  2422. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
  2423. if (cacheline_size == pci_cache_line_size)
  2424. return 0;
  2425. dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
  2426. "supported\n", pci_cache_line_size << 2);
  2427. return -EINVAL;
  2428. }
  2429. EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
  2430. #ifdef PCI_DISABLE_MWI
  2431. int pci_set_mwi(struct pci_dev *dev)
  2432. {
  2433. return 0;
  2434. }
  2435. int pci_try_set_mwi(struct pci_dev *dev)
  2436. {
  2437. return 0;
  2438. }
  2439. void pci_clear_mwi(struct pci_dev *dev)
  2440. {
  2441. }
  2442. #else
  2443. /**
  2444. * pci_set_mwi - enables memory-write-invalidate PCI transaction
  2445. * @dev: the PCI device for which MWI is enabled
  2446. *
  2447. * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
  2448. *
  2449. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  2450. */
  2451. int
  2452. pci_set_mwi(struct pci_dev *dev)
  2453. {
  2454. int rc;
  2455. u16 cmd;
  2456. rc = pci_set_cacheline_size(dev);
  2457. if (rc)
  2458. return rc;
  2459. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  2460. if (! (cmd & PCI_COMMAND_INVALIDATE)) {
  2461. dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
  2462. cmd |= PCI_COMMAND_INVALIDATE;
  2463. pci_write_config_word(dev, PCI_COMMAND, cmd);
  2464. }
  2465. return 0;
  2466. }
  2467. /**
  2468. * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
  2469. * @dev: the PCI device for which MWI is enabled
  2470. *
  2471. * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
  2472. * Callers are not required to check the return value.
  2473. *
  2474. * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
  2475. */
  2476. int pci_try_set_mwi(struct pci_dev *dev)
  2477. {
  2478. int rc = pci_set_mwi(dev);
  2479. return rc;
  2480. }
  2481. /**
  2482. * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
  2483. * @dev: the PCI device to disable
  2484. *
  2485. * Disables PCI Memory-Write-Invalidate transaction on the device
  2486. */
  2487. void
  2488. pci_clear_mwi(struct pci_dev *dev)
  2489. {
  2490. u16 cmd;
  2491. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  2492. if (cmd & PCI_COMMAND_INVALIDATE) {
  2493. cmd &= ~PCI_COMMAND_INVALIDATE;
  2494. pci_write_config_word(dev, PCI_COMMAND, cmd);
  2495. }
  2496. }
  2497. #endif /* ! PCI_DISABLE_MWI */
  2498. /**
  2499. * pci_intx - enables/disables PCI INTx for device dev
  2500. * @pdev: the PCI device to operate on
  2501. * @enable: boolean: whether to enable or disable PCI INTx
  2502. *
  2503. * Enables/disables PCI INTx for device dev
  2504. */
  2505. void
  2506. pci_intx(struct pci_dev *pdev, int enable)
  2507. {
  2508. u16 pci_command, new;
  2509. pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
  2510. if (enable) {
  2511. new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
  2512. } else {
  2513. new = pci_command | PCI_COMMAND_INTX_DISABLE;
  2514. }
  2515. if (new != pci_command) {
  2516. struct pci_devres *dr;
  2517. pci_write_config_word(pdev, PCI_COMMAND, new);
  2518. dr = find_pci_dr(pdev);
  2519. if (dr && !dr->restore_intx) {
  2520. dr->restore_intx = 1;
  2521. dr->orig_intx = !enable;
  2522. }
  2523. }
  2524. }
  2525. /**
  2526. * pci_intx_mask_supported - probe for INTx masking support
  2527. * @dev: the PCI device to operate on
  2528. *
  2529. * Check if the device dev support INTx masking via the config space
  2530. * command word.
  2531. */
  2532. bool pci_intx_mask_supported(struct pci_dev *dev)
  2533. {
  2534. bool mask_supported = false;
  2535. u16 orig, new;
  2536. if (dev->broken_intx_masking)
  2537. return false;
  2538. pci_cfg_access_lock(dev);
  2539. pci_read_config_word(dev, PCI_COMMAND, &orig);
  2540. pci_write_config_word(dev, PCI_COMMAND,
  2541. orig ^ PCI_COMMAND_INTX_DISABLE);
  2542. pci_read_config_word(dev, PCI_COMMAND, &new);
  2543. /*
  2544. * There's no way to protect against hardware bugs or detect them
  2545. * reliably, but as long as we know what the value should be, let's
  2546. * go ahead and check it.
  2547. */
  2548. if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
  2549. dev_err(&dev->dev, "Command register changed from "
  2550. "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
  2551. } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
  2552. mask_supported = true;
  2553. pci_write_config_word(dev, PCI_COMMAND, orig);
  2554. }
  2555. pci_cfg_access_unlock(dev);
  2556. return mask_supported;
  2557. }
  2558. EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
  2559. static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
  2560. {
  2561. struct pci_bus *bus = dev->bus;
  2562. bool mask_updated = true;
  2563. u32 cmd_status_dword;
  2564. u16 origcmd, newcmd;
  2565. unsigned long flags;
  2566. bool irq_pending;
  2567. /*
  2568. * We do a single dword read to retrieve both command and status.
  2569. * Document assumptions that make this possible.
  2570. */
  2571. BUILD_BUG_ON(PCI_COMMAND % 4);
  2572. BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
  2573. raw_spin_lock_irqsave(&pci_lock, flags);
  2574. bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
  2575. irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
  2576. /*
  2577. * Check interrupt status register to see whether our device
  2578. * triggered the interrupt (when masking) or the next IRQ is
  2579. * already pending (when unmasking).
  2580. */
  2581. if (mask != irq_pending) {
  2582. mask_updated = false;
  2583. goto done;
  2584. }
  2585. origcmd = cmd_status_dword;
  2586. newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
  2587. if (mask)
  2588. newcmd |= PCI_COMMAND_INTX_DISABLE;
  2589. if (newcmd != origcmd)
  2590. bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
  2591. done:
  2592. raw_spin_unlock_irqrestore(&pci_lock, flags);
  2593. return mask_updated;
  2594. }
  2595. /**
  2596. * pci_check_and_mask_intx - mask INTx on pending interrupt
  2597. * @dev: the PCI device to operate on
  2598. *
  2599. * Check if the device dev has its INTx line asserted, mask it and
  2600. * return true in that case. False is returned if not interrupt was
  2601. * pending.
  2602. */
  2603. bool pci_check_and_mask_intx(struct pci_dev *dev)
  2604. {
  2605. return pci_check_and_set_intx_mask(dev, true);
  2606. }
  2607. EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
  2608. /**
  2609. * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
  2610. * @dev: the PCI device to operate on
  2611. *
  2612. * Check if the device dev has its INTx line asserted, unmask it if not
  2613. * and return true. False is returned and the mask remains active if
  2614. * there was still an interrupt pending.
  2615. */
  2616. bool pci_check_and_unmask_intx(struct pci_dev *dev)
  2617. {
  2618. return pci_check_and_set_intx_mask(dev, false);
  2619. }
  2620. EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
  2621. /**
  2622. * pci_msi_off - disables any msi or msix capabilities
  2623. * @dev: the PCI device to operate on
  2624. *
  2625. * If you want to use msi see pci_enable_msi and friends.
  2626. * This is a lower level primitive that allows us to disable
  2627. * msi operation at the device level.
  2628. */
  2629. void pci_msi_off(struct pci_dev *dev)
  2630. {
  2631. int pos;
  2632. u16 control;
  2633. pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
  2634. if (pos) {
  2635. pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
  2636. control &= ~PCI_MSI_FLAGS_ENABLE;
  2637. pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
  2638. }
  2639. pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  2640. if (pos) {
  2641. pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
  2642. control &= ~PCI_MSIX_FLAGS_ENABLE;
  2643. pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
  2644. }
  2645. }
  2646. EXPORT_SYMBOL_GPL(pci_msi_off);
  2647. int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
  2648. {
  2649. return dma_set_max_seg_size(&dev->dev, size);
  2650. }
  2651. EXPORT_SYMBOL(pci_set_dma_max_seg_size);
  2652. int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
  2653. {
  2654. return dma_set_seg_boundary(&dev->dev, mask);
  2655. }
  2656. EXPORT_SYMBOL(pci_set_dma_seg_boundary);
  2657. static int pcie_flr(struct pci_dev *dev, int probe)
  2658. {
  2659. int i;
  2660. u32 cap;
  2661. u16 status;
  2662. pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
  2663. if (!(cap & PCI_EXP_DEVCAP_FLR))
  2664. return -ENOTTY;
  2665. if (probe)
  2666. return 0;
  2667. /* Wait for Transaction Pending bit clean */
  2668. for (i = 0; i < 4; i++) {
  2669. if (i)
  2670. msleep((1 << (i - 1)) * 100);
  2671. pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
  2672. if (!(status & PCI_EXP_DEVSTA_TRPND))
  2673. goto clear;
  2674. }
  2675. dev_err(&dev->dev, "transaction is not cleared; "
  2676. "proceeding with reset anyway\n");
  2677. clear:
  2678. pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
  2679. msleep(100);
  2680. return 0;
  2681. }
  2682. static int pci_af_flr(struct pci_dev *dev, int probe)
  2683. {
  2684. int i;
  2685. int pos;
  2686. u8 cap;
  2687. u8 status;
  2688. pos = pci_find_capability(dev, PCI_CAP_ID_AF);
  2689. if (!pos)
  2690. return -ENOTTY;
  2691. pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
  2692. if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
  2693. return -ENOTTY;
  2694. if (probe)
  2695. return 0;
  2696. /* Wait for Transaction Pending bit clean */
  2697. for (i = 0; i < 4; i++) {
  2698. if (i)
  2699. msleep((1 << (i - 1)) * 100);
  2700. pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
  2701. if (!(status & PCI_AF_STATUS_TP))
  2702. goto clear;
  2703. }
  2704. dev_err(&dev->dev, "transaction is not cleared; "
  2705. "proceeding with reset anyway\n");
  2706. clear:
  2707. pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
  2708. msleep(100);
  2709. return 0;
  2710. }
  2711. /**
  2712. * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
  2713. * @dev: Device to reset.
  2714. * @probe: If set, only check if the device can be reset this way.
  2715. *
  2716. * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
  2717. * unset, it will be reinitialized internally when going from PCI_D3hot to
  2718. * PCI_D0. If that's the case and the device is not in a low-power state
  2719. * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
  2720. *
  2721. * NOTE: This causes the caller to sleep for twice the device power transition
  2722. * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
  2723. * by devault (i.e. unless the @dev's d3_delay field has a different value).
  2724. * Moreover, only devices in D0 can be reset by this function.
  2725. */
  2726. static int pci_pm_reset(struct pci_dev *dev, int probe)
  2727. {
  2728. u16 csr;
  2729. if (!dev->pm_cap)
  2730. return -ENOTTY;
  2731. pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
  2732. if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
  2733. return -ENOTTY;
  2734. if (probe)
  2735. return 0;
  2736. if (dev->current_state != PCI_D0)
  2737. return -EINVAL;
  2738. csr &= ~PCI_PM_CTRL_STATE_MASK;
  2739. csr |= PCI_D3hot;
  2740. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
  2741. pci_dev_d3_sleep(dev);
  2742. csr &= ~PCI_PM_CTRL_STATE_MASK;
  2743. csr |= PCI_D0;
  2744. pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
  2745. pci_dev_d3_sleep(dev);
  2746. return 0;
  2747. }
  2748. static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
  2749. {
  2750. u16 ctrl;
  2751. struct pci_dev *pdev;
  2752. if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
  2753. return -ENOTTY;
  2754. list_for_each_entry(pdev, &dev->bus->devices, bus_list)
  2755. if (pdev != dev)
  2756. return -ENOTTY;
  2757. if (probe)
  2758. return 0;
  2759. pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
  2760. ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
  2761. pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
  2762. msleep(100);
  2763. ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
  2764. pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
  2765. msleep(100);
  2766. return 0;
  2767. }
  2768. static int __pci_dev_reset(struct pci_dev *dev, int probe)
  2769. {
  2770. int rc;
  2771. might_sleep();
  2772. rc = pci_dev_specific_reset(dev, probe);
  2773. if (rc != -ENOTTY)
  2774. goto done;
  2775. rc = pcie_flr(dev, probe);
  2776. if (rc != -ENOTTY)
  2777. goto done;
  2778. rc = pci_af_flr(dev, probe);
  2779. if (rc != -ENOTTY)
  2780. goto done;
  2781. rc = pci_pm_reset(dev, probe);
  2782. if (rc != -ENOTTY)
  2783. goto done;
  2784. rc = pci_parent_bus_reset(dev, probe);
  2785. done:
  2786. return rc;
  2787. }
  2788. static int pci_dev_reset(struct pci_dev *dev, int probe)
  2789. {
  2790. int rc;
  2791. if (!probe) {
  2792. pci_cfg_access_lock(dev);
  2793. /* block PM suspend, driver probe, etc. */
  2794. device_lock(&dev->dev);
  2795. }
  2796. rc = __pci_dev_reset(dev, probe);
  2797. if (!probe) {
  2798. device_unlock(&dev->dev);
  2799. pci_cfg_access_unlock(dev);
  2800. }
  2801. return rc;
  2802. }
  2803. /**
  2804. * __pci_reset_function - reset a PCI device function
  2805. * @dev: PCI device to reset
  2806. *
  2807. * Some devices allow an individual function to be reset without affecting
  2808. * other functions in the same device. The PCI device must be responsive
  2809. * to PCI config space in order to use this function.
  2810. *
  2811. * The device function is presumed to be unused when this function is called.
  2812. * Resetting the device will make the contents of PCI configuration space
  2813. * random, so any caller of this must be prepared to reinitialise the
  2814. * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
  2815. * etc.
  2816. *
  2817. * Returns 0 if the device function was successfully reset or negative if the
  2818. * device doesn't support resetting a single function.
  2819. */
  2820. int __pci_reset_function(struct pci_dev *dev)
  2821. {
  2822. return pci_dev_reset(dev, 0);
  2823. }
  2824. EXPORT_SYMBOL_GPL(__pci_reset_function);
  2825. /**
  2826. * __pci_reset_function_locked - reset a PCI device function while holding
  2827. * the @dev mutex lock.
  2828. * @dev: PCI device to reset
  2829. *
  2830. * Some devices allow an individual function to be reset without affecting
  2831. * other functions in the same device. The PCI device must be responsive
  2832. * to PCI config space in order to use this function.
  2833. *
  2834. * The device function is presumed to be unused and the caller is holding
  2835. * the device mutex lock when this function is called.
  2836. * Resetting the device will make the contents of PCI configuration space
  2837. * random, so any caller of this must be prepared to reinitialise the
  2838. * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
  2839. * etc.
  2840. *
  2841. * Returns 0 if the device function was successfully reset or negative if the
  2842. * device doesn't support resetting a single function.
  2843. */
  2844. int __pci_reset_function_locked(struct pci_dev *dev)
  2845. {
  2846. return __pci_dev_reset(dev, 0);
  2847. }
  2848. EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
  2849. /**
  2850. * pci_probe_reset_function - check whether the device can be safely reset
  2851. * @dev: PCI device to reset
  2852. *
  2853. * Some devices allow an individual function to be reset without affecting
  2854. * other functions in the same device. The PCI device must be responsive
  2855. * to PCI config space in order to use this function.
  2856. *
  2857. * Returns 0 if the device function can be reset or negative if the
  2858. * device doesn't support resetting a single function.
  2859. */
  2860. int pci_probe_reset_function(struct pci_dev *dev)
  2861. {
  2862. return pci_dev_reset(dev, 1);
  2863. }
  2864. /**
  2865. * pci_reset_function - quiesce and reset a PCI device function
  2866. * @dev: PCI device to reset
  2867. *
  2868. * Some devices allow an individual function to be reset without affecting
  2869. * other functions in the same device. The PCI device must be responsive
  2870. * to PCI config space in order to use this function.
  2871. *
  2872. * This function does not just reset the PCI portion of a device, but
  2873. * clears all the state associated with the device. This function differs
  2874. * from __pci_reset_function in that it saves and restores device state
  2875. * over the reset.
  2876. *
  2877. * Returns 0 if the device function was successfully reset or negative if the
  2878. * device doesn't support resetting a single function.
  2879. */
  2880. int pci_reset_function(struct pci_dev *dev)
  2881. {
  2882. int rc;
  2883. rc = pci_dev_reset(dev, 1);
  2884. if (rc)
  2885. return rc;
  2886. pci_save_state(dev);
  2887. /*
  2888. * both INTx and MSI are disabled after the Interrupt Disable bit
  2889. * is set and the Bus Master bit is cleared.
  2890. */
  2891. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
  2892. rc = pci_dev_reset(dev, 0);
  2893. pci_restore_state(dev);
  2894. return rc;
  2895. }
  2896. EXPORT_SYMBOL_GPL(pci_reset_function);
  2897. /**
  2898. * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
  2899. * @dev: PCI device to query
  2900. *
  2901. * Returns mmrbc: maximum designed memory read count in bytes
  2902. * or appropriate error value.
  2903. */
  2904. int pcix_get_max_mmrbc(struct pci_dev *dev)
  2905. {
  2906. int cap;
  2907. u32 stat;
  2908. cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  2909. if (!cap)
  2910. return -EINVAL;
  2911. if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
  2912. return -EINVAL;
  2913. return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
  2914. }
  2915. EXPORT_SYMBOL(pcix_get_max_mmrbc);
  2916. /**
  2917. * pcix_get_mmrbc - get PCI-X maximum memory read byte count
  2918. * @dev: PCI device to query
  2919. *
  2920. * Returns mmrbc: maximum memory read count in bytes
  2921. * or appropriate error value.
  2922. */
  2923. int pcix_get_mmrbc(struct pci_dev *dev)
  2924. {
  2925. int cap;
  2926. u16 cmd;
  2927. cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  2928. if (!cap)
  2929. return -EINVAL;
  2930. if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
  2931. return -EINVAL;
  2932. return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
  2933. }
  2934. EXPORT_SYMBOL(pcix_get_mmrbc);
  2935. /**
  2936. * pcix_set_mmrbc - set PCI-X maximum memory read byte count
  2937. * @dev: PCI device to query
  2938. * @mmrbc: maximum memory read count in bytes
  2939. * valid values are 512, 1024, 2048, 4096
  2940. *
  2941. * If possible sets maximum memory read byte count, some bridges have erratas
  2942. * that prevent this.
  2943. */
  2944. int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
  2945. {
  2946. int cap;
  2947. u32 stat, v, o;
  2948. u16 cmd;
  2949. if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
  2950. return -EINVAL;
  2951. v = ffs(mmrbc) - 10;
  2952. cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  2953. if (!cap)
  2954. return -EINVAL;
  2955. if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
  2956. return -EINVAL;
  2957. if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
  2958. return -E2BIG;
  2959. if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
  2960. return -EINVAL;
  2961. o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
  2962. if (o != v) {
  2963. if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
  2964. return -EIO;
  2965. cmd &= ~PCI_X_CMD_MAX_READ;
  2966. cmd |= v << 2;
  2967. if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
  2968. return -EIO;
  2969. }
  2970. return 0;
  2971. }
  2972. EXPORT_SYMBOL(pcix_set_mmrbc);
  2973. /**
  2974. * pcie_get_readrq - get PCI Express read request size
  2975. * @dev: PCI device to query
  2976. *
  2977. * Returns maximum memory read request in bytes
  2978. * or appropriate error value.
  2979. */
  2980. int pcie_get_readrq(struct pci_dev *dev)
  2981. {
  2982. u16 ctl;
  2983. pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
  2984. return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
  2985. }
  2986. EXPORT_SYMBOL(pcie_get_readrq);
  2987. /**
  2988. * pcie_set_readrq - set PCI Express maximum memory read request
  2989. * @dev: PCI device to query
  2990. * @rq: maximum memory read count in bytes
  2991. * valid values are 128, 256, 512, 1024, 2048, 4096
  2992. *
  2993. * If possible sets maximum memory read request in bytes
  2994. */
  2995. int pcie_set_readrq(struct pci_dev *dev, int rq)
  2996. {
  2997. u16 v;
  2998. if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
  2999. return -EINVAL;
  3000. /*
  3001. * If using the "performance" PCIe config, we clamp the
  3002. * read rq size to the max packet size to prevent the
  3003. * host bridge generating requests larger than we can
  3004. * cope with
  3005. */
  3006. if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
  3007. int mps = pcie_get_mps(dev);
  3008. if (mps < 0)
  3009. return mps;
  3010. if (mps < rq)
  3011. rq = mps;
  3012. }
  3013. v = (ffs(rq) - 8) << 12;
  3014. return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
  3015. PCI_EXP_DEVCTL_READRQ, v);
  3016. }
  3017. EXPORT_SYMBOL(pcie_set_readrq);
  3018. /**
  3019. * pcie_get_mps - get PCI Express maximum payload size
  3020. * @dev: PCI device to query
  3021. *
  3022. * Returns maximum payload size in bytes
  3023. * or appropriate error value.
  3024. */
  3025. int pcie_get_mps(struct pci_dev *dev)
  3026. {
  3027. u16 ctl;
  3028. pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
  3029. return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
  3030. }
  3031. /**
  3032. * pcie_set_mps - set PCI Express maximum payload size
  3033. * @dev: PCI device to query
  3034. * @mps: maximum payload size in bytes
  3035. * valid values are 128, 256, 512, 1024, 2048, 4096
  3036. *
  3037. * If possible sets maximum payload size
  3038. */
  3039. int pcie_set_mps(struct pci_dev *dev, int mps)
  3040. {
  3041. u16 v;
  3042. if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
  3043. return -EINVAL;
  3044. v = ffs(mps) - 8;
  3045. if (v > dev->pcie_mpss)
  3046. return -EINVAL;
  3047. v <<= 5;
  3048. return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
  3049. PCI_EXP_DEVCTL_PAYLOAD, v);
  3050. }
  3051. /**
  3052. * pci_select_bars - Make BAR mask from the type of resource
  3053. * @dev: the PCI device for which BAR mask is made
  3054. * @flags: resource type mask to be selected
  3055. *
  3056. * This helper routine makes bar mask from the type of resource.
  3057. */
  3058. int pci_select_bars(struct pci_dev *dev, unsigned long flags)
  3059. {
  3060. int i, bars = 0;
  3061. for (i = 0; i < PCI_NUM_RESOURCES; i++)
  3062. if (pci_resource_flags(dev, i) & flags)
  3063. bars |= (1 << i);
  3064. return bars;
  3065. }
  3066. /**
  3067. * pci_resource_bar - get position of the BAR associated with a resource
  3068. * @dev: the PCI device
  3069. * @resno: the resource number
  3070. * @type: the BAR type to be filled in
  3071. *
  3072. * Returns BAR position in config space, or 0 if the BAR is invalid.
  3073. */
  3074. int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
  3075. {
  3076. int reg;
  3077. if (resno < PCI_ROM_RESOURCE) {
  3078. *type = pci_bar_unknown;
  3079. return PCI_BASE_ADDRESS_0 + 4 * resno;
  3080. } else if (resno == PCI_ROM_RESOURCE) {
  3081. *type = pci_bar_mem32;
  3082. return dev->rom_base_reg;
  3083. } else if (resno < PCI_BRIDGE_RESOURCES) {
  3084. /* device specific resource */
  3085. reg = pci_iov_resource_bar(dev, resno, type);
  3086. if (reg)
  3087. return reg;
  3088. }
  3089. dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
  3090. return 0;
  3091. }
  3092. /* Some architectures require additional programming to enable VGA */
  3093. static arch_set_vga_state_t arch_set_vga_state;
  3094. void __init pci_register_set_vga_state(arch_set_vga_state_t func)
  3095. {
  3096. arch_set_vga_state = func; /* NULL disables */
  3097. }
  3098. static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
  3099. unsigned int command_bits, u32 flags)
  3100. {
  3101. if (arch_set_vga_state)
  3102. return arch_set_vga_state(dev, decode, command_bits,
  3103. flags);
  3104. return 0;
  3105. }
  3106. /**
  3107. * pci_set_vga_state - set VGA decode state on device and parents if requested
  3108. * @dev: the PCI device
  3109. * @decode: true = enable decoding, false = disable decoding
  3110. * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
  3111. * @flags: traverse ancestors and change bridges
  3112. * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
  3113. */
  3114. int pci_set_vga_state(struct pci_dev *dev, bool decode,
  3115. unsigned int command_bits, u32 flags)
  3116. {
  3117. struct pci_bus *bus;
  3118. struct pci_dev *bridge;
  3119. u16 cmd;
  3120. int rc;
  3121. WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
  3122. /* ARCH specific VGA enables */
  3123. rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
  3124. if (rc)
  3125. return rc;
  3126. if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
  3127. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  3128. if (decode == true)
  3129. cmd |= command_bits;
  3130. else
  3131. cmd &= ~command_bits;
  3132. pci_write_config_word(dev, PCI_COMMAND, cmd);
  3133. }
  3134. if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
  3135. return 0;
  3136. bus = dev->bus;
  3137. while (bus) {
  3138. bridge = bus->self;
  3139. if (bridge) {
  3140. pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
  3141. &cmd);
  3142. if (decode == true)
  3143. cmd |= PCI_BRIDGE_CTL_VGA;
  3144. else
  3145. cmd &= ~PCI_BRIDGE_CTL_VGA;
  3146. pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
  3147. cmd);
  3148. }
  3149. bus = bus->parent;
  3150. }
  3151. return 0;
  3152. }
  3153. #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
  3154. static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
  3155. static DEFINE_SPINLOCK(resource_alignment_lock);
  3156. /**
  3157. * pci_specified_resource_alignment - get resource alignment specified by user.
  3158. * @dev: the PCI device to get
  3159. *
  3160. * RETURNS: Resource alignment if it is specified.
  3161. * Zero if it is not specified.
  3162. */
  3163. static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
  3164. {
  3165. int seg, bus, slot, func, align_order, count;
  3166. resource_size_t align = 0;
  3167. char *p;
  3168. spin_lock(&resource_alignment_lock);
  3169. p = resource_alignment_param;
  3170. while (*p) {
  3171. count = 0;
  3172. if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
  3173. p[count] == '@') {
  3174. p += count + 1;
  3175. } else {
  3176. align_order = -1;
  3177. }
  3178. if (sscanf(p, "%x:%x:%x.%x%n",
  3179. &seg, &bus, &slot, &func, &count) != 4) {
  3180. seg = 0;
  3181. if (sscanf(p, "%x:%x.%x%n",
  3182. &bus, &slot, &func, &count) != 3) {
  3183. /* Invalid format */
  3184. printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
  3185. p);
  3186. break;
  3187. }
  3188. }
  3189. p += count;
  3190. if (seg == pci_domain_nr(dev->bus) &&
  3191. bus == dev->bus->number &&
  3192. slot == PCI_SLOT(dev->devfn) &&
  3193. func == PCI_FUNC(dev->devfn)) {
  3194. if (align_order == -1) {
  3195. align = PAGE_SIZE;
  3196. } else {
  3197. align = 1 << align_order;
  3198. }
  3199. /* Found */
  3200. break;
  3201. }
  3202. if (*p != ';' && *p != ',') {
  3203. /* End of param or invalid format */
  3204. break;
  3205. }
  3206. p++;
  3207. }
  3208. spin_unlock(&resource_alignment_lock);
  3209. return align;
  3210. }
  3211. /*
  3212. * This function disables memory decoding and releases memory resources
  3213. * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
  3214. * It also rounds up size to specified alignment.
  3215. * Later on, the kernel will assign page-aligned memory resource back
  3216. * to the device.
  3217. */
  3218. void pci_reassigndev_resource_alignment(struct pci_dev *dev)
  3219. {
  3220. int i;
  3221. struct resource *r;
  3222. resource_size_t align, size;
  3223. u16 command;
  3224. /* check if specified PCI is target device to reassign */
  3225. align = pci_specified_resource_alignment(dev);
  3226. if (!align)
  3227. return;
  3228. if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
  3229. (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
  3230. dev_warn(&dev->dev,
  3231. "Can't reassign resources to host bridge.\n");
  3232. return;
  3233. }
  3234. dev_info(&dev->dev,
  3235. "Disabling memory decoding and releasing memory resources.\n");
  3236. pci_read_config_word(dev, PCI_COMMAND, &command);
  3237. command &= ~PCI_COMMAND_MEMORY;
  3238. pci_write_config_word(dev, PCI_COMMAND, command);
  3239. for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
  3240. r = &dev->resource[i];
  3241. if (!(r->flags & IORESOURCE_MEM))
  3242. continue;
  3243. size = resource_size(r);
  3244. if (size < align) {
  3245. size = align;
  3246. dev_info(&dev->dev,
  3247. "Rounding up size of resource #%d to %#llx.\n",
  3248. i, (unsigned long long)size);
  3249. }
  3250. r->end = size - 1;
  3251. r->start = 0;
  3252. }
  3253. /* Need to disable bridge's resource window,
  3254. * to enable the kernel to reassign new resource
  3255. * window later on.
  3256. */
  3257. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
  3258. (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
  3259. for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
  3260. r = &dev->resource[i];
  3261. if (!(r->flags & IORESOURCE_MEM))
  3262. continue;
  3263. r->end = resource_size(r) - 1;
  3264. r->start = 0;
  3265. }
  3266. pci_disable_bridge_window(dev);
  3267. }
  3268. }
  3269. static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
  3270. {
  3271. if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
  3272. count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
  3273. spin_lock(&resource_alignment_lock);
  3274. strncpy(resource_alignment_param, buf, count);
  3275. resource_alignment_param[count] = '\0';
  3276. spin_unlock(&resource_alignment_lock);
  3277. return count;
  3278. }
  3279. static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
  3280. {
  3281. size_t count;
  3282. spin_lock(&resource_alignment_lock);
  3283. count = snprintf(buf, size, "%s", resource_alignment_param);
  3284. spin_unlock(&resource_alignment_lock);
  3285. return count;
  3286. }
  3287. static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
  3288. {
  3289. return pci_get_resource_alignment_param(buf, PAGE_SIZE);
  3290. }
  3291. static ssize_t pci_resource_alignment_store(struct bus_type *bus,
  3292. const char *buf, size_t count)
  3293. {
  3294. return pci_set_resource_alignment_param(buf, count);
  3295. }
  3296. BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
  3297. pci_resource_alignment_store);
  3298. static int __init pci_resource_alignment_sysfs_init(void)
  3299. {
  3300. return bus_create_file(&pci_bus_type,
  3301. &bus_attr_resource_alignment);
  3302. }
  3303. late_initcall(pci_resource_alignment_sysfs_init);
  3304. static void pci_no_domains(void)
  3305. {
  3306. #ifdef CONFIG_PCI_DOMAINS
  3307. pci_domains_supported = 0;
  3308. #endif
  3309. }
  3310. /**
  3311. * pci_ext_cfg_avail - can we access extended PCI config space?
  3312. *
  3313. * Returns 1 if we can access PCI extended config space (offsets
  3314. * greater than 0xff). This is the default implementation. Architecture
  3315. * implementations can override this.
  3316. */
  3317. int __weak pci_ext_cfg_avail(void)
  3318. {
  3319. return 1;
  3320. }
  3321. void __weak pci_fixup_cardbus(struct pci_bus *bus)
  3322. {
  3323. }
  3324. EXPORT_SYMBOL(pci_fixup_cardbus);
  3325. static int __init pci_setup(char *str)
  3326. {
  3327. while (str) {
  3328. char *k = strchr(str, ',');
  3329. if (k)
  3330. *k++ = 0;
  3331. if (*str && (str = pcibios_setup(str)) && *str) {
  3332. if (!strcmp(str, "nomsi")) {
  3333. pci_no_msi();
  3334. } else if (!strcmp(str, "noaer")) {
  3335. pci_no_aer();
  3336. } else if (!strncmp(str, "realloc=", 8)) {
  3337. pci_realloc_get_opt(str + 8);
  3338. } else if (!strncmp(str, "realloc", 7)) {
  3339. pci_realloc_get_opt("on");
  3340. } else if (!strcmp(str, "nodomains")) {
  3341. pci_no_domains();
  3342. } else if (!strncmp(str, "noari", 5)) {
  3343. pcie_ari_disabled = true;
  3344. } else if (!strncmp(str, "cbiosize=", 9)) {
  3345. pci_cardbus_io_size = memparse(str + 9, &str);
  3346. } else if (!strncmp(str, "cbmemsize=", 10)) {
  3347. pci_cardbus_mem_size = memparse(str + 10, &str);
  3348. } else if (!strncmp(str, "resource_alignment=", 19)) {
  3349. pci_set_resource_alignment_param(str + 19,
  3350. strlen(str + 19));
  3351. } else if (!strncmp(str, "ecrc=", 5)) {
  3352. pcie_ecrc_get_policy(str + 5);
  3353. } else if (!strncmp(str, "hpiosize=", 9)) {
  3354. pci_hotplug_io_size = memparse(str + 9, &str);
  3355. } else if (!strncmp(str, "hpmemsize=", 10)) {
  3356. pci_hotplug_mem_size = memparse(str + 10, &str);
  3357. } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
  3358. pcie_bus_config = PCIE_BUS_TUNE_OFF;
  3359. } else if (!strncmp(str, "pcie_bus_safe", 13)) {
  3360. pcie_bus_config = PCIE_BUS_SAFE;
  3361. } else if (!strncmp(str, "pcie_bus_perf", 13)) {
  3362. pcie_bus_config = PCIE_BUS_PERFORMANCE;
  3363. } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
  3364. pcie_bus_config = PCIE_BUS_PEER2PEER;
  3365. } else if (!strncmp(str, "pcie_scan_all", 13)) {
  3366. pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
  3367. } else {
  3368. printk(KERN_ERR "PCI: Unknown option `%s'\n",
  3369. str);
  3370. }
  3371. }
  3372. str = k;
  3373. }
  3374. return 0;
  3375. }
  3376. early_param("pci", pci_setup);
  3377. EXPORT_SYMBOL(pci_reenable_device);
  3378. EXPORT_SYMBOL(pci_enable_device_io);
  3379. EXPORT_SYMBOL(pci_enable_device_mem);
  3380. EXPORT_SYMBOL(pci_enable_device);
  3381. EXPORT_SYMBOL(pcim_enable_device);
  3382. EXPORT_SYMBOL(pcim_pin_device);
  3383. EXPORT_SYMBOL(pci_disable_device);
  3384. EXPORT_SYMBOL(pci_find_capability);
  3385. EXPORT_SYMBOL(pci_bus_find_capability);
  3386. EXPORT_SYMBOL(pci_release_regions);
  3387. EXPORT_SYMBOL(pci_request_regions);
  3388. EXPORT_SYMBOL(pci_request_regions_exclusive);
  3389. EXPORT_SYMBOL(pci_release_region);
  3390. EXPORT_SYMBOL(pci_request_region);
  3391. EXPORT_SYMBOL(pci_request_region_exclusive);
  3392. EXPORT_SYMBOL(pci_release_selected_regions);
  3393. EXPORT_SYMBOL(pci_request_selected_regions);
  3394. EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
  3395. EXPORT_SYMBOL(pci_set_master);
  3396. EXPORT_SYMBOL(pci_clear_master);
  3397. EXPORT_SYMBOL(pci_set_mwi);
  3398. EXPORT_SYMBOL(pci_try_set_mwi);
  3399. EXPORT_SYMBOL(pci_clear_mwi);
  3400. EXPORT_SYMBOL_GPL(pci_intx);
  3401. EXPORT_SYMBOL(pci_assign_resource);
  3402. EXPORT_SYMBOL(pci_find_parent_resource);
  3403. EXPORT_SYMBOL(pci_select_bars);
  3404. EXPORT_SYMBOL(pci_set_power_state);
  3405. EXPORT_SYMBOL(pci_save_state);
  3406. EXPORT_SYMBOL(pci_restore_state);
  3407. EXPORT_SYMBOL(pci_pme_capable);
  3408. EXPORT_SYMBOL(pci_pme_active);
  3409. EXPORT_SYMBOL(pci_wake_from_d3);
  3410. EXPORT_SYMBOL(pci_target_state);
  3411. EXPORT_SYMBOL(pci_prepare_to_sleep);
  3412. EXPORT_SYMBOL(pci_back_from_sleep);
  3413. EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);