exynos_drm_g2d.c 37 KB

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  1. /*
  2. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3. * Authors: Joonyoung Shim <jy0922.shim@samsung.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundationr
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/slab.h>
  17. #include <linux/workqueue.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/dma-attrs.h>
  20. #include <linux/of.h>
  21. #include <drm/drmP.h>
  22. #include <drm/exynos_drm.h>
  23. #include "exynos_drm_drv.h"
  24. #include "exynos_drm_gem.h"
  25. #include "exynos_drm_iommu.h"
  26. #define G2D_HW_MAJOR_VER 4
  27. #define G2D_HW_MINOR_VER 1
  28. /* vaild register range set from user: 0x0104 ~ 0x0880 */
  29. #define G2D_VALID_START 0x0104
  30. #define G2D_VALID_END 0x0880
  31. /* general registers */
  32. #define G2D_SOFT_RESET 0x0000
  33. #define G2D_INTEN 0x0004
  34. #define G2D_INTC_PEND 0x000C
  35. #define G2D_DMA_SFR_BASE_ADDR 0x0080
  36. #define G2D_DMA_COMMAND 0x0084
  37. #define G2D_DMA_STATUS 0x008C
  38. #define G2D_DMA_HOLD_CMD 0x0090
  39. /* command registers */
  40. #define G2D_BITBLT_START 0x0100
  41. /* registers for base address */
  42. #define G2D_SRC_BASE_ADDR 0x0304
  43. #define G2D_SRC_COLOR_MODE 0x030C
  44. #define G2D_SRC_LEFT_TOP 0x0310
  45. #define G2D_SRC_RIGHT_BOTTOM 0x0314
  46. #define G2D_SRC_PLANE2_BASE_ADDR 0x0318
  47. #define G2D_DST_BASE_ADDR 0x0404
  48. #define G2D_DST_COLOR_MODE 0x040C
  49. #define G2D_DST_LEFT_TOP 0x0410
  50. #define G2D_DST_RIGHT_BOTTOM 0x0414
  51. #define G2D_DST_PLANE2_BASE_ADDR 0x0418
  52. #define G2D_PAT_BASE_ADDR 0x0500
  53. #define G2D_MSK_BASE_ADDR 0x0520
  54. /* G2D_SOFT_RESET */
  55. #define G2D_SFRCLEAR (1 << 1)
  56. #define G2D_R (1 << 0)
  57. /* G2D_INTEN */
  58. #define G2D_INTEN_ACF (1 << 3)
  59. #define G2D_INTEN_UCF (1 << 2)
  60. #define G2D_INTEN_GCF (1 << 1)
  61. #define G2D_INTEN_SCF (1 << 0)
  62. /* G2D_INTC_PEND */
  63. #define G2D_INTP_ACMD_FIN (1 << 3)
  64. #define G2D_INTP_UCMD_FIN (1 << 2)
  65. #define G2D_INTP_GCMD_FIN (1 << 1)
  66. #define G2D_INTP_SCMD_FIN (1 << 0)
  67. /* G2D_DMA_COMMAND */
  68. #define G2D_DMA_HALT (1 << 2)
  69. #define G2D_DMA_CONTINUE (1 << 1)
  70. #define G2D_DMA_START (1 << 0)
  71. /* G2D_DMA_STATUS */
  72. #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17)
  73. #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1)
  74. #define G2D_DMA_DONE (1 << 0)
  75. #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17
  76. /* G2D_DMA_HOLD_CMD */
  77. #define G2D_USER_HOLD (1 << 2)
  78. #define G2D_LIST_HOLD (1 << 1)
  79. #define G2D_BITBLT_HOLD (1 << 0)
  80. /* G2D_BITBLT_START */
  81. #define G2D_START_CASESEL (1 << 2)
  82. #define G2D_START_NHOLT (1 << 1)
  83. #define G2D_START_BITBLT (1 << 0)
  84. /* buffer color format */
  85. #define G2D_FMT_XRGB8888 0
  86. #define G2D_FMT_ARGB8888 1
  87. #define G2D_FMT_RGB565 2
  88. #define G2D_FMT_XRGB1555 3
  89. #define G2D_FMT_ARGB1555 4
  90. #define G2D_FMT_XRGB4444 5
  91. #define G2D_FMT_ARGB4444 6
  92. #define G2D_FMT_PACKED_RGB888 7
  93. #define G2D_FMT_A8 11
  94. #define G2D_FMT_L8 12
  95. /* buffer valid length */
  96. #define G2D_LEN_MIN 1
  97. #define G2D_LEN_MAX 8000
  98. #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4)
  99. #define G2D_CMDLIST_NUM 64
  100. #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM)
  101. #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2)
  102. /* maximum buffer pool size of userptr is 64MB as default */
  103. #define MAX_POOL (64 * 1024 * 1024)
  104. enum {
  105. BUF_TYPE_GEM = 1,
  106. BUF_TYPE_USERPTR,
  107. };
  108. enum g2d_reg_type {
  109. REG_TYPE_NONE = -1,
  110. REG_TYPE_SRC,
  111. REG_TYPE_SRC_PLANE2,
  112. REG_TYPE_DST,
  113. REG_TYPE_DST_PLANE2,
  114. REG_TYPE_PAT,
  115. REG_TYPE_MSK,
  116. MAX_REG_TYPE_NR
  117. };
  118. /* cmdlist data structure */
  119. struct g2d_cmdlist {
  120. u32 head;
  121. unsigned long data[G2D_CMDLIST_DATA_NUM];
  122. u32 last; /* last data offset */
  123. };
  124. /*
  125. * A structure of buffer description
  126. *
  127. * @format: color format
  128. * @left_x: the x coordinates of left top corner
  129. * @top_y: the y coordinates of left top corner
  130. * @right_x: the x coordinates of right bottom corner
  131. * @bottom_y: the y coordinates of right bottom corner
  132. *
  133. */
  134. struct g2d_buf_desc {
  135. unsigned int format;
  136. unsigned int left_x;
  137. unsigned int top_y;
  138. unsigned int right_x;
  139. unsigned int bottom_y;
  140. };
  141. /*
  142. * A structure of buffer information
  143. *
  144. * @map_nr: manages the number of mapped buffers
  145. * @reg_types: stores regitster type in the order of requested command
  146. * @handles: stores buffer handle in its reg_type position
  147. * @types: stores buffer type in its reg_type position
  148. * @descs: stores buffer description in its reg_type position
  149. *
  150. */
  151. struct g2d_buf_info {
  152. unsigned int map_nr;
  153. enum g2d_reg_type reg_types[MAX_REG_TYPE_NR];
  154. unsigned long handles[MAX_REG_TYPE_NR];
  155. unsigned int types[MAX_REG_TYPE_NR];
  156. struct g2d_buf_desc descs[MAX_REG_TYPE_NR];
  157. };
  158. struct drm_exynos_pending_g2d_event {
  159. struct drm_pending_event base;
  160. struct drm_exynos_g2d_event event;
  161. };
  162. struct g2d_cmdlist_userptr {
  163. struct list_head list;
  164. dma_addr_t dma_addr;
  165. unsigned long userptr;
  166. unsigned long size;
  167. struct page **pages;
  168. unsigned int npages;
  169. struct sg_table *sgt;
  170. struct vm_area_struct *vma;
  171. atomic_t refcount;
  172. bool in_pool;
  173. bool out_of_list;
  174. };
  175. struct g2d_cmdlist_node {
  176. struct list_head list;
  177. struct g2d_cmdlist *cmdlist;
  178. dma_addr_t dma_addr;
  179. struct g2d_buf_info buf_info;
  180. struct drm_exynos_pending_g2d_event *event;
  181. };
  182. struct g2d_runqueue_node {
  183. struct list_head list;
  184. struct list_head run_cmdlist;
  185. struct list_head event_list;
  186. struct drm_file *filp;
  187. pid_t pid;
  188. struct completion complete;
  189. int async;
  190. };
  191. struct g2d_data {
  192. struct device *dev;
  193. struct clk *gate_clk;
  194. void __iomem *regs;
  195. int irq;
  196. struct workqueue_struct *g2d_workq;
  197. struct work_struct runqueue_work;
  198. struct exynos_drm_subdrv subdrv;
  199. bool suspended;
  200. /* cmdlist */
  201. struct g2d_cmdlist_node *cmdlist_node;
  202. struct list_head free_cmdlist;
  203. struct mutex cmdlist_mutex;
  204. dma_addr_t cmdlist_pool;
  205. void *cmdlist_pool_virt;
  206. struct dma_attrs cmdlist_dma_attrs;
  207. /* runqueue*/
  208. struct g2d_runqueue_node *runqueue_node;
  209. struct list_head runqueue;
  210. struct mutex runqueue_mutex;
  211. struct kmem_cache *runqueue_slab;
  212. unsigned long current_pool;
  213. unsigned long max_pool;
  214. };
  215. static int g2d_init_cmdlist(struct g2d_data *g2d)
  216. {
  217. struct device *dev = g2d->dev;
  218. struct g2d_cmdlist_node *node = g2d->cmdlist_node;
  219. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  220. int nr;
  221. int ret;
  222. struct g2d_buf_info *buf_info;
  223. init_dma_attrs(&g2d->cmdlist_dma_attrs);
  224. dma_set_attr(DMA_ATTR_WRITE_COMBINE, &g2d->cmdlist_dma_attrs);
  225. g2d->cmdlist_pool_virt = dma_alloc_attrs(subdrv->drm_dev->dev,
  226. G2D_CMDLIST_POOL_SIZE,
  227. &g2d->cmdlist_pool, GFP_KERNEL,
  228. &g2d->cmdlist_dma_attrs);
  229. if (!g2d->cmdlist_pool_virt) {
  230. dev_err(dev, "failed to allocate dma memory\n");
  231. return -ENOMEM;
  232. }
  233. node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL);
  234. if (!node) {
  235. dev_err(dev, "failed to allocate memory\n");
  236. ret = -ENOMEM;
  237. goto err;
  238. }
  239. for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) {
  240. unsigned int i;
  241. node[nr].cmdlist =
  242. g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE;
  243. node[nr].dma_addr =
  244. g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE;
  245. buf_info = &node[nr].buf_info;
  246. for (i = 0; i < MAX_REG_TYPE_NR; i++)
  247. buf_info->reg_types[i] = REG_TYPE_NONE;
  248. list_add_tail(&node[nr].list, &g2d->free_cmdlist);
  249. }
  250. return 0;
  251. err:
  252. dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE,
  253. g2d->cmdlist_pool_virt,
  254. g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs);
  255. return ret;
  256. }
  257. static void g2d_fini_cmdlist(struct g2d_data *g2d)
  258. {
  259. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  260. kfree(g2d->cmdlist_node);
  261. dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE,
  262. g2d->cmdlist_pool_virt,
  263. g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs);
  264. }
  265. static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d)
  266. {
  267. struct device *dev = g2d->dev;
  268. struct g2d_cmdlist_node *node;
  269. mutex_lock(&g2d->cmdlist_mutex);
  270. if (list_empty(&g2d->free_cmdlist)) {
  271. dev_err(dev, "there is no free cmdlist\n");
  272. mutex_unlock(&g2d->cmdlist_mutex);
  273. return NULL;
  274. }
  275. node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node,
  276. list);
  277. list_del_init(&node->list);
  278. mutex_unlock(&g2d->cmdlist_mutex);
  279. return node;
  280. }
  281. static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node)
  282. {
  283. mutex_lock(&g2d->cmdlist_mutex);
  284. list_move_tail(&node->list, &g2d->free_cmdlist);
  285. mutex_unlock(&g2d->cmdlist_mutex);
  286. }
  287. static void g2d_add_cmdlist_to_inuse(struct exynos_drm_g2d_private *g2d_priv,
  288. struct g2d_cmdlist_node *node)
  289. {
  290. struct g2d_cmdlist_node *lnode;
  291. if (list_empty(&g2d_priv->inuse_cmdlist))
  292. goto add_to_list;
  293. /* this links to base address of new cmdlist */
  294. lnode = list_entry(g2d_priv->inuse_cmdlist.prev,
  295. struct g2d_cmdlist_node, list);
  296. lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr;
  297. add_to_list:
  298. list_add_tail(&node->list, &g2d_priv->inuse_cmdlist);
  299. if (node->event)
  300. list_add_tail(&node->event->base.link, &g2d_priv->event_list);
  301. }
  302. static void g2d_userptr_put_dma_addr(struct drm_device *drm_dev,
  303. unsigned long obj,
  304. bool force)
  305. {
  306. struct g2d_cmdlist_userptr *g2d_userptr =
  307. (struct g2d_cmdlist_userptr *)obj;
  308. if (!obj)
  309. return;
  310. if (force)
  311. goto out;
  312. atomic_dec(&g2d_userptr->refcount);
  313. if (atomic_read(&g2d_userptr->refcount) > 0)
  314. return;
  315. if (g2d_userptr->in_pool)
  316. return;
  317. out:
  318. exynos_gem_unmap_sgt_from_dma(drm_dev, g2d_userptr->sgt,
  319. DMA_BIDIRECTIONAL);
  320. exynos_gem_put_pages_to_userptr(g2d_userptr->pages,
  321. g2d_userptr->npages,
  322. g2d_userptr->vma);
  323. if (!g2d_userptr->out_of_list)
  324. list_del_init(&g2d_userptr->list);
  325. sg_free_table(g2d_userptr->sgt);
  326. kfree(g2d_userptr->sgt);
  327. drm_free_large(g2d_userptr->pages);
  328. kfree(g2d_userptr);
  329. }
  330. static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev,
  331. unsigned long userptr,
  332. unsigned long size,
  333. struct drm_file *filp,
  334. unsigned long *obj)
  335. {
  336. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  337. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  338. struct g2d_cmdlist_userptr *g2d_userptr;
  339. struct g2d_data *g2d;
  340. struct page **pages;
  341. struct sg_table *sgt;
  342. struct vm_area_struct *vma;
  343. unsigned long start, end;
  344. unsigned int npages, offset;
  345. int ret;
  346. if (!size) {
  347. DRM_ERROR("invalid userptr size.\n");
  348. return ERR_PTR(-EINVAL);
  349. }
  350. g2d = dev_get_drvdata(g2d_priv->dev);
  351. /* check if userptr already exists in userptr_list. */
  352. list_for_each_entry(g2d_userptr, &g2d_priv->userptr_list, list) {
  353. if (g2d_userptr->userptr == userptr) {
  354. /*
  355. * also check size because there could be same address
  356. * and different size.
  357. */
  358. if (g2d_userptr->size == size) {
  359. atomic_inc(&g2d_userptr->refcount);
  360. *obj = (unsigned long)g2d_userptr;
  361. return &g2d_userptr->dma_addr;
  362. }
  363. /*
  364. * at this moment, maybe g2d dma is accessing this
  365. * g2d_userptr memory region so just remove this
  366. * g2d_userptr object from userptr_list not to be
  367. * referred again and also except it the userptr
  368. * pool to be released after the dma access completion.
  369. */
  370. g2d_userptr->out_of_list = true;
  371. g2d_userptr->in_pool = false;
  372. list_del_init(&g2d_userptr->list);
  373. break;
  374. }
  375. }
  376. g2d_userptr = kzalloc(sizeof(*g2d_userptr), GFP_KERNEL);
  377. if (!g2d_userptr) {
  378. DRM_ERROR("failed to allocate g2d_userptr.\n");
  379. return ERR_PTR(-ENOMEM);
  380. }
  381. atomic_set(&g2d_userptr->refcount, 1);
  382. start = userptr & PAGE_MASK;
  383. offset = userptr & ~PAGE_MASK;
  384. end = PAGE_ALIGN(userptr + size);
  385. npages = (end - start) >> PAGE_SHIFT;
  386. g2d_userptr->npages = npages;
  387. pages = drm_calloc_large(npages, sizeof(struct page *));
  388. if (!pages) {
  389. DRM_ERROR("failed to allocate pages.\n");
  390. ret = -ENOMEM;
  391. goto err_free;
  392. }
  393. vma = find_vma(current->mm, userptr);
  394. if (!vma) {
  395. DRM_ERROR("failed to get vm region.\n");
  396. ret = -EFAULT;
  397. goto err_free_pages;
  398. }
  399. if (vma->vm_end < userptr + size) {
  400. DRM_ERROR("vma is too small.\n");
  401. ret = -EFAULT;
  402. goto err_free_pages;
  403. }
  404. g2d_userptr->vma = exynos_gem_get_vma(vma);
  405. if (!g2d_userptr->vma) {
  406. DRM_ERROR("failed to copy vma.\n");
  407. ret = -ENOMEM;
  408. goto err_free_pages;
  409. }
  410. g2d_userptr->size = size;
  411. ret = exynos_gem_get_pages_from_userptr(start & PAGE_MASK,
  412. npages, pages, vma);
  413. if (ret < 0) {
  414. DRM_ERROR("failed to get user pages from userptr.\n");
  415. goto err_put_vma;
  416. }
  417. g2d_userptr->pages = pages;
  418. sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
  419. if (!sgt) {
  420. DRM_ERROR("failed to allocate sg table.\n");
  421. ret = -ENOMEM;
  422. goto err_free_userptr;
  423. }
  424. ret = sg_alloc_table_from_pages(sgt, pages, npages, offset,
  425. size, GFP_KERNEL);
  426. if (ret < 0) {
  427. DRM_ERROR("failed to get sgt from pages.\n");
  428. goto err_free_sgt;
  429. }
  430. g2d_userptr->sgt = sgt;
  431. ret = exynos_gem_map_sgt_with_dma(drm_dev, g2d_userptr->sgt,
  432. DMA_BIDIRECTIONAL);
  433. if (ret < 0) {
  434. DRM_ERROR("failed to map sgt with dma region.\n");
  435. goto err_sg_free_table;
  436. }
  437. g2d_userptr->dma_addr = sgt->sgl[0].dma_address;
  438. g2d_userptr->userptr = userptr;
  439. list_add_tail(&g2d_userptr->list, &g2d_priv->userptr_list);
  440. if (g2d->current_pool + (npages << PAGE_SHIFT) < g2d->max_pool) {
  441. g2d->current_pool += npages << PAGE_SHIFT;
  442. g2d_userptr->in_pool = true;
  443. }
  444. *obj = (unsigned long)g2d_userptr;
  445. return &g2d_userptr->dma_addr;
  446. err_sg_free_table:
  447. sg_free_table(sgt);
  448. err_free_sgt:
  449. kfree(sgt);
  450. err_free_userptr:
  451. exynos_gem_put_pages_to_userptr(g2d_userptr->pages,
  452. g2d_userptr->npages,
  453. g2d_userptr->vma);
  454. err_put_vma:
  455. exynos_gem_put_vma(g2d_userptr->vma);
  456. err_free_pages:
  457. drm_free_large(pages);
  458. err_free:
  459. kfree(g2d_userptr);
  460. return ERR_PTR(ret);
  461. }
  462. static void g2d_userptr_free_all(struct drm_device *drm_dev,
  463. struct g2d_data *g2d,
  464. struct drm_file *filp)
  465. {
  466. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  467. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  468. struct g2d_cmdlist_userptr *g2d_userptr, *n;
  469. list_for_each_entry_safe(g2d_userptr, n, &g2d_priv->userptr_list, list)
  470. if (g2d_userptr->in_pool)
  471. g2d_userptr_put_dma_addr(drm_dev,
  472. (unsigned long)g2d_userptr,
  473. true);
  474. g2d->current_pool = 0;
  475. }
  476. static enum g2d_reg_type g2d_get_reg_type(int reg_offset)
  477. {
  478. enum g2d_reg_type reg_type;
  479. switch (reg_offset) {
  480. case G2D_SRC_BASE_ADDR:
  481. case G2D_SRC_COLOR_MODE:
  482. case G2D_SRC_LEFT_TOP:
  483. case G2D_SRC_RIGHT_BOTTOM:
  484. reg_type = REG_TYPE_SRC;
  485. break;
  486. case G2D_SRC_PLANE2_BASE_ADDR:
  487. reg_type = REG_TYPE_SRC_PLANE2;
  488. break;
  489. case G2D_DST_BASE_ADDR:
  490. case G2D_DST_COLOR_MODE:
  491. case G2D_DST_LEFT_TOP:
  492. case G2D_DST_RIGHT_BOTTOM:
  493. reg_type = REG_TYPE_DST;
  494. break;
  495. case G2D_DST_PLANE2_BASE_ADDR:
  496. reg_type = REG_TYPE_DST_PLANE2;
  497. break;
  498. case G2D_PAT_BASE_ADDR:
  499. reg_type = REG_TYPE_PAT;
  500. break;
  501. case G2D_MSK_BASE_ADDR:
  502. reg_type = REG_TYPE_MSK;
  503. break;
  504. default:
  505. reg_type = REG_TYPE_NONE;
  506. DRM_ERROR("Unknown register offset![%d]\n", reg_offset);
  507. break;
  508. };
  509. return reg_type;
  510. }
  511. static unsigned long g2d_get_buf_bpp(unsigned int format)
  512. {
  513. unsigned long bpp;
  514. switch (format) {
  515. case G2D_FMT_XRGB8888:
  516. case G2D_FMT_ARGB8888:
  517. bpp = 4;
  518. break;
  519. case G2D_FMT_RGB565:
  520. case G2D_FMT_XRGB1555:
  521. case G2D_FMT_ARGB1555:
  522. case G2D_FMT_XRGB4444:
  523. case G2D_FMT_ARGB4444:
  524. bpp = 2;
  525. break;
  526. case G2D_FMT_PACKED_RGB888:
  527. bpp = 3;
  528. break;
  529. default:
  530. bpp = 1;
  531. break;
  532. }
  533. return bpp;
  534. }
  535. static bool g2d_check_buf_desc_is_valid(struct g2d_buf_desc *buf_desc,
  536. enum g2d_reg_type reg_type,
  537. unsigned long size)
  538. {
  539. unsigned int width, height;
  540. unsigned long area;
  541. /*
  542. * check source and destination buffers only.
  543. * so the others are always valid.
  544. */
  545. if (reg_type != REG_TYPE_SRC && reg_type != REG_TYPE_DST)
  546. return true;
  547. width = buf_desc->right_x - buf_desc->left_x;
  548. if (width < G2D_LEN_MIN || width > G2D_LEN_MAX) {
  549. DRM_ERROR("width[%u] is out of range!\n", width);
  550. return false;
  551. }
  552. height = buf_desc->bottom_y - buf_desc->top_y;
  553. if (height < G2D_LEN_MIN || height > G2D_LEN_MAX) {
  554. DRM_ERROR("height[%u] is out of range!\n", height);
  555. return false;
  556. }
  557. area = (unsigned long)width * (unsigned long)height *
  558. g2d_get_buf_bpp(buf_desc->format);
  559. if (area > size) {
  560. DRM_ERROR("area[%lu] is out of range[%lu]!\n", area, size);
  561. return false;
  562. }
  563. return true;
  564. }
  565. static int g2d_map_cmdlist_gem(struct g2d_data *g2d,
  566. struct g2d_cmdlist_node *node,
  567. struct drm_device *drm_dev,
  568. struct drm_file *file)
  569. {
  570. struct g2d_cmdlist *cmdlist = node->cmdlist;
  571. struct g2d_buf_info *buf_info = &node->buf_info;
  572. int offset;
  573. int ret;
  574. int i;
  575. for (i = 0; i < buf_info->map_nr; i++) {
  576. struct g2d_buf_desc *buf_desc;
  577. enum g2d_reg_type reg_type;
  578. int reg_pos;
  579. unsigned long handle;
  580. dma_addr_t *addr;
  581. reg_pos = cmdlist->last - 2 * (i + 1);
  582. offset = cmdlist->data[reg_pos];
  583. handle = cmdlist->data[reg_pos + 1];
  584. reg_type = g2d_get_reg_type(offset);
  585. if (reg_type == REG_TYPE_NONE) {
  586. ret = -EFAULT;
  587. goto err;
  588. }
  589. buf_desc = &buf_info->descs[reg_type];
  590. if (buf_info->types[reg_type] == BUF_TYPE_GEM) {
  591. unsigned long size;
  592. size = exynos_drm_gem_get_size(drm_dev, handle, file);
  593. if (!size) {
  594. ret = -EFAULT;
  595. goto err;
  596. }
  597. if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type,
  598. size)) {
  599. ret = -EFAULT;
  600. goto err;
  601. }
  602. addr = exynos_drm_gem_get_dma_addr(drm_dev, handle,
  603. file);
  604. if (IS_ERR(addr)) {
  605. ret = -EFAULT;
  606. goto err;
  607. }
  608. } else {
  609. struct drm_exynos_g2d_userptr g2d_userptr;
  610. if (copy_from_user(&g2d_userptr, (void __user *)handle,
  611. sizeof(struct drm_exynos_g2d_userptr))) {
  612. ret = -EFAULT;
  613. goto err;
  614. }
  615. if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type,
  616. g2d_userptr.size)) {
  617. ret = -EFAULT;
  618. goto err;
  619. }
  620. addr = g2d_userptr_get_dma_addr(drm_dev,
  621. g2d_userptr.userptr,
  622. g2d_userptr.size,
  623. file,
  624. &handle);
  625. if (IS_ERR(addr)) {
  626. ret = -EFAULT;
  627. goto err;
  628. }
  629. }
  630. cmdlist->data[reg_pos + 1] = *addr;
  631. buf_info->reg_types[i] = reg_type;
  632. buf_info->handles[reg_type] = handle;
  633. }
  634. return 0;
  635. err:
  636. buf_info->map_nr = i;
  637. return ret;
  638. }
  639. static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d,
  640. struct g2d_cmdlist_node *node,
  641. struct drm_file *filp)
  642. {
  643. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  644. struct g2d_buf_info *buf_info = &node->buf_info;
  645. int i;
  646. for (i = 0; i < buf_info->map_nr; i++) {
  647. struct g2d_buf_desc *buf_desc;
  648. enum g2d_reg_type reg_type;
  649. unsigned long handle;
  650. reg_type = buf_info->reg_types[i];
  651. buf_desc = &buf_info->descs[reg_type];
  652. handle = buf_info->handles[reg_type];
  653. if (buf_info->types[reg_type] == BUF_TYPE_GEM)
  654. exynos_drm_gem_put_dma_addr(subdrv->drm_dev, handle,
  655. filp);
  656. else
  657. g2d_userptr_put_dma_addr(subdrv->drm_dev, handle,
  658. false);
  659. buf_info->reg_types[i] = REG_TYPE_NONE;
  660. buf_info->handles[reg_type] = 0;
  661. buf_info->types[reg_type] = 0;
  662. memset(buf_desc, 0x00, sizeof(*buf_desc));
  663. }
  664. buf_info->map_nr = 0;
  665. }
  666. static void g2d_dma_start(struct g2d_data *g2d,
  667. struct g2d_runqueue_node *runqueue_node)
  668. {
  669. struct g2d_cmdlist_node *node =
  670. list_first_entry(&runqueue_node->run_cmdlist,
  671. struct g2d_cmdlist_node, list);
  672. int ret;
  673. ret = pm_runtime_get_sync(g2d->dev);
  674. if (ret < 0)
  675. return;
  676. writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
  677. writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
  678. }
  679. static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d)
  680. {
  681. struct g2d_runqueue_node *runqueue_node;
  682. if (list_empty(&g2d->runqueue))
  683. return NULL;
  684. runqueue_node = list_first_entry(&g2d->runqueue,
  685. struct g2d_runqueue_node, list);
  686. list_del_init(&runqueue_node->list);
  687. return runqueue_node;
  688. }
  689. static void g2d_free_runqueue_node(struct g2d_data *g2d,
  690. struct g2d_runqueue_node *runqueue_node)
  691. {
  692. struct g2d_cmdlist_node *node;
  693. if (!runqueue_node)
  694. return;
  695. mutex_lock(&g2d->cmdlist_mutex);
  696. /*
  697. * commands in run_cmdlist have been completed so unmap all gem
  698. * objects in each command node so that they are unreferenced.
  699. */
  700. list_for_each_entry(node, &runqueue_node->run_cmdlist, list)
  701. g2d_unmap_cmdlist_gem(g2d, node, runqueue_node->filp);
  702. list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist);
  703. mutex_unlock(&g2d->cmdlist_mutex);
  704. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  705. }
  706. static void g2d_exec_runqueue(struct g2d_data *g2d)
  707. {
  708. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  709. if (g2d->runqueue_node)
  710. g2d_dma_start(g2d, g2d->runqueue_node);
  711. }
  712. static void g2d_runqueue_worker(struct work_struct *work)
  713. {
  714. struct g2d_data *g2d = container_of(work, struct g2d_data,
  715. runqueue_work);
  716. mutex_lock(&g2d->runqueue_mutex);
  717. pm_runtime_put_sync(g2d->dev);
  718. complete(&g2d->runqueue_node->complete);
  719. if (g2d->runqueue_node->async)
  720. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  721. if (g2d->suspended)
  722. g2d->runqueue_node = NULL;
  723. else
  724. g2d_exec_runqueue(g2d);
  725. mutex_unlock(&g2d->runqueue_mutex);
  726. }
  727. static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no)
  728. {
  729. struct drm_device *drm_dev = g2d->subdrv.drm_dev;
  730. struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node;
  731. struct drm_exynos_pending_g2d_event *e;
  732. struct timeval now;
  733. unsigned long flags;
  734. if (list_empty(&runqueue_node->event_list))
  735. return;
  736. e = list_first_entry(&runqueue_node->event_list,
  737. struct drm_exynos_pending_g2d_event, base.link);
  738. do_gettimeofday(&now);
  739. e->event.tv_sec = now.tv_sec;
  740. e->event.tv_usec = now.tv_usec;
  741. e->event.cmdlist_no = cmdlist_no;
  742. spin_lock_irqsave(&drm_dev->event_lock, flags);
  743. list_move_tail(&e->base.link, &e->base.file_priv->event_list);
  744. wake_up_interruptible(&e->base.file_priv->event_wait);
  745. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  746. }
  747. static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
  748. {
  749. struct g2d_data *g2d = dev_id;
  750. u32 pending;
  751. pending = readl_relaxed(g2d->regs + G2D_INTC_PEND);
  752. if (pending)
  753. writel_relaxed(pending, g2d->regs + G2D_INTC_PEND);
  754. if (pending & G2D_INTP_GCMD_FIN) {
  755. u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS);
  756. cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >>
  757. G2D_DMA_LIST_DONE_COUNT_OFFSET;
  758. g2d_finish_event(g2d, cmdlist_no);
  759. writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD);
  760. if (!(pending & G2D_INTP_ACMD_FIN)) {
  761. writel_relaxed(G2D_DMA_CONTINUE,
  762. g2d->regs + G2D_DMA_COMMAND);
  763. }
  764. }
  765. if (pending & G2D_INTP_ACMD_FIN)
  766. queue_work(g2d->g2d_workq, &g2d->runqueue_work);
  767. return IRQ_HANDLED;
  768. }
  769. static int g2d_check_reg_offset(struct device *dev,
  770. struct g2d_cmdlist_node *node,
  771. int nr, bool for_addr)
  772. {
  773. struct g2d_cmdlist *cmdlist = node->cmdlist;
  774. int reg_offset;
  775. int index;
  776. int i;
  777. for (i = 0; i < nr; i++) {
  778. struct g2d_buf_info *buf_info = &node->buf_info;
  779. struct g2d_buf_desc *buf_desc;
  780. enum g2d_reg_type reg_type;
  781. unsigned long value;
  782. index = cmdlist->last - 2 * (i + 1);
  783. reg_offset = cmdlist->data[index] & ~0xfffff000;
  784. if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END)
  785. goto err;
  786. if (reg_offset % 4)
  787. goto err;
  788. switch (reg_offset) {
  789. case G2D_SRC_BASE_ADDR:
  790. case G2D_SRC_PLANE2_BASE_ADDR:
  791. case G2D_DST_BASE_ADDR:
  792. case G2D_DST_PLANE2_BASE_ADDR:
  793. case G2D_PAT_BASE_ADDR:
  794. case G2D_MSK_BASE_ADDR:
  795. if (!for_addr)
  796. goto err;
  797. reg_type = g2d_get_reg_type(reg_offset);
  798. if (reg_type == REG_TYPE_NONE)
  799. goto err;
  800. /* check userptr buffer type. */
  801. if ((cmdlist->data[index] & ~0x7fffffff) >> 31) {
  802. buf_info->types[reg_type] = BUF_TYPE_USERPTR;
  803. cmdlist->data[index] &= ~G2D_BUF_USERPTR;
  804. } else
  805. buf_info->types[reg_type] = BUF_TYPE_GEM;
  806. break;
  807. case G2D_SRC_COLOR_MODE:
  808. case G2D_DST_COLOR_MODE:
  809. if (for_addr)
  810. goto err;
  811. reg_type = g2d_get_reg_type(reg_offset);
  812. if (reg_type == REG_TYPE_NONE)
  813. goto err;
  814. buf_desc = &buf_info->descs[reg_type];
  815. value = cmdlist->data[index + 1];
  816. buf_desc->format = value & 0xf;
  817. break;
  818. case G2D_SRC_LEFT_TOP:
  819. case G2D_DST_LEFT_TOP:
  820. if (for_addr)
  821. goto err;
  822. reg_type = g2d_get_reg_type(reg_offset);
  823. if (reg_type == REG_TYPE_NONE)
  824. goto err;
  825. buf_desc = &buf_info->descs[reg_type];
  826. value = cmdlist->data[index + 1];
  827. buf_desc->left_x = value & 0x1fff;
  828. buf_desc->top_y = (value & 0x1fff0000) >> 16;
  829. break;
  830. case G2D_SRC_RIGHT_BOTTOM:
  831. case G2D_DST_RIGHT_BOTTOM:
  832. if (for_addr)
  833. goto err;
  834. reg_type = g2d_get_reg_type(reg_offset);
  835. if (reg_type == REG_TYPE_NONE)
  836. goto err;
  837. buf_desc = &buf_info->descs[reg_type];
  838. value = cmdlist->data[index + 1];
  839. buf_desc->right_x = value & 0x1fff;
  840. buf_desc->bottom_y = (value & 0x1fff0000) >> 16;
  841. break;
  842. default:
  843. if (for_addr)
  844. goto err;
  845. break;
  846. }
  847. }
  848. return 0;
  849. err:
  850. dev_err(dev, "Bad register offset: 0x%lx\n", cmdlist->data[index]);
  851. return -EINVAL;
  852. }
  853. /* ioctl functions */
  854. int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data,
  855. struct drm_file *file)
  856. {
  857. struct drm_exynos_g2d_get_ver *ver = data;
  858. ver->major = G2D_HW_MAJOR_VER;
  859. ver->minor = G2D_HW_MINOR_VER;
  860. return 0;
  861. }
  862. EXPORT_SYMBOL_GPL(exynos_g2d_get_ver_ioctl);
  863. int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data,
  864. struct drm_file *file)
  865. {
  866. struct drm_exynos_file_private *file_priv = file->driver_priv;
  867. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  868. struct device *dev = g2d_priv->dev;
  869. struct g2d_data *g2d;
  870. struct drm_exynos_g2d_set_cmdlist *req = data;
  871. struct drm_exynos_g2d_cmd *cmd;
  872. struct drm_exynos_pending_g2d_event *e;
  873. struct g2d_cmdlist_node *node;
  874. struct g2d_cmdlist *cmdlist;
  875. unsigned long flags;
  876. int size;
  877. int ret;
  878. if (!dev)
  879. return -ENODEV;
  880. g2d = dev_get_drvdata(dev);
  881. if (!g2d)
  882. return -EFAULT;
  883. node = g2d_get_cmdlist(g2d);
  884. if (!node)
  885. return -ENOMEM;
  886. node->event = NULL;
  887. if (req->event_type != G2D_EVENT_NOT) {
  888. spin_lock_irqsave(&drm_dev->event_lock, flags);
  889. if (file->event_space < sizeof(e->event)) {
  890. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  891. ret = -ENOMEM;
  892. goto err;
  893. }
  894. file->event_space -= sizeof(e->event);
  895. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  896. e = kzalloc(sizeof(*node->event), GFP_KERNEL);
  897. if (!e) {
  898. dev_err(dev, "failed to allocate event\n");
  899. spin_lock_irqsave(&drm_dev->event_lock, flags);
  900. file->event_space += sizeof(e->event);
  901. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  902. ret = -ENOMEM;
  903. goto err;
  904. }
  905. e->event.base.type = DRM_EXYNOS_G2D_EVENT;
  906. e->event.base.length = sizeof(e->event);
  907. e->event.user_data = req->user_data;
  908. e->base.event = &e->event.base;
  909. e->base.file_priv = file;
  910. e->base.destroy = (void (*) (struct drm_pending_event *)) kfree;
  911. node->event = e;
  912. }
  913. cmdlist = node->cmdlist;
  914. cmdlist->last = 0;
  915. /*
  916. * If don't clear SFR registers, the cmdlist is affected by register
  917. * values of previous cmdlist. G2D hw executes SFR clear command and
  918. * a next command at the same time then the next command is ignored and
  919. * is executed rightly from next next command, so needs a dummy command
  920. * to next command of SFR clear command.
  921. */
  922. cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET;
  923. cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR;
  924. cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR;
  925. cmdlist->data[cmdlist->last++] = 0;
  926. /*
  927. * 'LIST_HOLD' command should be set to the DMA_HOLD_CMD_REG
  928. * and GCF bit should be set to INTEN register if user wants
  929. * G2D interrupt event once current command list execution is
  930. * finished.
  931. * Otherwise only ACF bit should be set to INTEN register so
  932. * that one interrupt is occured after all command lists
  933. * have been completed.
  934. */
  935. if (node->event) {
  936. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  937. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF | G2D_INTEN_GCF;
  938. cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD;
  939. cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD;
  940. } else {
  941. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  942. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF;
  943. }
  944. /* Check size of cmdlist: last 2 is about G2D_BITBLT_START */
  945. size = cmdlist->last + req->cmd_nr * 2 + req->cmd_buf_nr * 2 + 2;
  946. if (size > G2D_CMDLIST_DATA_NUM) {
  947. dev_err(dev, "cmdlist size is too big\n");
  948. ret = -EINVAL;
  949. goto err_free_event;
  950. }
  951. cmd = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd;
  952. if (copy_from_user(cmdlist->data + cmdlist->last,
  953. (void __user *)cmd,
  954. sizeof(*cmd) * req->cmd_nr)) {
  955. ret = -EFAULT;
  956. goto err_free_event;
  957. }
  958. cmdlist->last += req->cmd_nr * 2;
  959. ret = g2d_check_reg_offset(dev, node, req->cmd_nr, false);
  960. if (ret < 0)
  961. goto err_free_event;
  962. node->buf_info.map_nr = req->cmd_buf_nr;
  963. if (req->cmd_buf_nr) {
  964. struct drm_exynos_g2d_cmd *cmd_buf;
  965. cmd_buf = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd_buf;
  966. if (copy_from_user(cmdlist->data + cmdlist->last,
  967. (void __user *)cmd_buf,
  968. sizeof(*cmd_buf) * req->cmd_buf_nr)) {
  969. ret = -EFAULT;
  970. goto err_free_event;
  971. }
  972. cmdlist->last += req->cmd_buf_nr * 2;
  973. ret = g2d_check_reg_offset(dev, node, req->cmd_buf_nr, true);
  974. if (ret < 0)
  975. goto err_free_event;
  976. ret = g2d_map_cmdlist_gem(g2d, node, drm_dev, file);
  977. if (ret < 0)
  978. goto err_unmap;
  979. }
  980. cmdlist->data[cmdlist->last++] = G2D_BITBLT_START;
  981. cmdlist->data[cmdlist->last++] = G2D_START_BITBLT;
  982. /* head */
  983. cmdlist->head = cmdlist->last / 2;
  984. /* tail */
  985. cmdlist->data[cmdlist->last] = 0;
  986. g2d_add_cmdlist_to_inuse(g2d_priv, node);
  987. return 0;
  988. err_unmap:
  989. g2d_unmap_cmdlist_gem(g2d, node, file);
  990. err_free_event:
  991. if (node->event) {
  992. spin_lock_irqsave(&drm_dev->event_lock, flags);
  993. file->event_space += sizeof(e->event);
  994. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  995. kfree(node->event);
  996. }
  997. err:
  998. g2d_put_cmdlist(g2d, node);
  999. return ret;
  1000. }
  1001. EXPORT_SYMBOL_GPL(exynos_g2d_set_cmdlist_ioctl);
  1002. int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data,
  1003. struct drm_file *file)
  1004. {
  1005. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1006. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  1007. struct device *dev = g2d_priv->dev;
  1008. struct g2d_data *g2d;
  1009. struct drm_exynos_g2d_exec *req = data;
  1010. struct g2d_runqueue_node *runqueue_node;
  1011. struct list_head *run_cmdlist;
  1012. struct list_head *event_list;
  1013. if (!dev)
  1014. return -ENODEV;
  1015. g2d = dev_get_drvdata(dev);
  1016. if (!g2d)
  1017. return -EFAULT;
  1018. runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL);
  1019. if (!runqueue_node) {
  1020. dev_err(dev, "failed to allocate memory\n");
  1021. return -ENOMEM;
  1022. }
  1023. run_cmdlist = &runqueue_node->run_cmdlist;
  1024. event_list = &runqueue_node->event_list;
  1025. INIT_LIST_HEAD(run_cmdlist);
  1026. INIT_LIST_HEAD(event_list);
  1027. init_completion(&runqueue_node->complete);
  1028. runqueue_node->async = req->async;
  1029. list_splice_init(&g2d_priv->inuse_cmdlist, run_cmdlist);
  1030. list_splice_init(&g2d_priv->event_list, event_list);
  1031. if (list_empty(run_cmdlist)) {
  1032. dev_err(dev, "there is no inuse cmdlist\n");
  1033. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  1034. return -EPERM;
  1035. }
  1036. mutex_lock(&g2d->runqueue_mutex);
  1037. runqueue_node->pid = current->pid;
  1038. runqueue_node->filp = file;
  1039. list_add_tail(&runqueue_node->list, &g2d->runqueue);
  1040. if (!g2d->runqueue_node)
  1041. g2d_exec_runqueue(g2d);
  1042. mutex_unlock(&g2d->runqueue_mutex);
  1043. if (runqueue_node->async)
  1044. goto out;
  1045. wait_for_completion(&runqueue_node->complete);
  1046. g2d_free_runqueue_node(g2d, runqueue_node);
  1047. out:
  1048. return 0;
  1049. }
  1050. EXPORT_SYMBOL_GPL(exynos_g2d_exec_ioctl);
  1051. static int g2d_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
  1052. {
  1053. struct g2d_data *g2d;
  1054. int ret;
  1055. g2d = dev_get_drvdata(dev);
  1056. if (!g2d)
  1057. return -EFAULT;
  1058. /* allocate dma-aware cmdlist buffer. */
  1059. ret = g2d_init_cmdlist(g2d);
  1060. if (ret < 0) {
  1061. dev_err(dev, "cmdlist init failed\n");
  1062. return ret;
  1063. }
  1064. if (!is_drm_iommu_supported(drm_dev))
  1065. return 0;
  1066. ret = drm_iommu_attach_device(drm_dev, dev);
  1067. if (ret < 0) {
  1068. dev_err(dev, "failed to enable iommu.\n");
  1069. g2d_fini_cmdlist(g2d);
  1070. }
  1071. return ret;
  1072. }
  1073. static void g2d_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
  1074. {
  1075. if (!is_drm_iommu_supported(drm_dev))
  1076. return;
  1077. drm_iommu_detach_device(drm_dev, dev);
  1078. }
  1079. static int g2d_open(struct drm_device *drm_dev, struct device *dev,
  1080. struct drm_file *file)
  1081. {
  1082. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1083. struct exynos_drm_g2d_private *g2d_priv;
  1084. g2d_priv = kzalloc(sizeof(*g2d_priv), GFP_KERNEL);
  1085. if (!g2d_priv) {
  1086. dev_err(dev, "failed to allocate g2d private data\n");
  1087. return -ENOMEM;
  1088. }
  1089. g2d_priv->dev = dev;
  1090. file_priv->g2d_priv = g2d_priv;
  1091. INIT_LIST_HEAD(&g2d_priv->inuse_cmdlist);
  1092. INIT_LIST_HEAD(&g2d_priv->event_list);
  1093. INIT_LIST_HEAD(&g2d_priv->userptr_list);
  1094. return 0;
  1095. }
  1096. static void g2d_close(struct drm_device *drm_dev, struct device *dev,
  1097. struct drm_file *file)
  1098. {
  1099. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1100. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  1101. struct g2d_data *g2d;
  1102. struct g2d_cmdlist_node *node, *n;
  1103. if (!dev)
  1104. return;
  1105. g2d = dev_get_drvdata(dev);
  1106. if (!g2d)
  1107. return;
  1108. mutex_lock(&g2d->cmdlist_mutex);
  1109. list_for_each_entry_safe(node, n, &g2d_priv->inuse_cmdlist, list) {
  1110. /*
  1111. * unmap all gem objects not completed.
  1112. *
  1113. * P.S. if current process was terminated forcely then
  1114. * there may be some commands in inuse_cmdlist so unmap
  1115. * them.
  1116. */
  1117. g2d_unmap_cmdlist_gem(g2d, node, file);
  1118. list_move_tail(&node->list, &g2d->free_cmdlist);
  1119. }
  1120. mutex_unlock(&g2d->cmdlist_mutex);
  1121. /* release all g2d_userptr in pool. */
  1122. g2d_userptr_free_all(drm_dev, g2d, file);
  1123. kfree(file_priv->g2d_priv);
  1124. }
  1125. static int g2d_probe(struct platform_device *pdev)
  1126. {
  1127. struct device *dev = &pdev->dev;
  1128. struct resource *res;
  1129. struct g2d_data *g2d;
  1130. struct exynos_drm_subdrv *subdrv;
  1131. int ret;
  1132. g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL);
  1133. if (!g2d) {
  1134. dev_err(dev, "failed to allocate driver data\n");
  1135. return -ENOMEM;
  1136. }
  1137. g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab",
  1138. sizeof(struct g2d_runqueue_node), 0, 0, NULL);
  1139. if (!g2d->runqueue_slab)
  1140. return -ENOMEM;
  1141. g2d->dev = dev;
  1142. g2d->g2d_workq = create_singlethread_workqueue("g2d");
  1143. if (!g2d->g2d_workq) {
  1144. dev_err(dev, "failed to create workqueue\n");
  1145. ret = -EINVAL;
  1146. goto err_destroy_slab;
  1147. }
  1148. INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker);
  1149. INIT_LIST_HEAD(&g2d->free_cmdlist);
  1150. INIT_LIST_HEAD(&g2d->runqueue);
  1151. mutex_init(&g2d->cmdlist_mutex);
  1152. mutex_init(&g2d->runqueue_mutex);
  1153. g2d->gate_clk = devm_clk_get(dev, "fimg2d");
  1154. if (IS_ERR(g2d->gate_clk)) {
  1155. dev_err(dev, "failed to get gate clock\n");
  1156. ret = PTR_ERR(g2d->gate_clk);
  1157. goto err_destroy_workqueue;
  1158. }
  1159. pm_runtime_enable(dev);
  1160. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1161. g2d->regs = devm_ioremap_resource(dev, res);
  1162. if (IS_ERR(g2d->regs)) {
  1163. ret = PTR_ERR(g2d->regs);
  1164. goto err_put_clk;
  1165. }
  1166. g2d->irq = platform_get_irq(pdev, 0);
  1167. if (g2d->irq < 0) {
  1168. dev_err(dev, "failed to get irq\n");
  1169. ret = g2d->irq;
  1170. goto err_put_clk;
  1171. }
  1172. ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0,
  1173. "drm_g2d", g2d);
  1174. if (ret < 0) {
  1175. dev_err(dev, "irq request failed\n");
  1176. goto err_put_clk;
  1177. }
  1178. g2d->max_pool = MAX_POOL;
  1179. platform_set_drvdata(pdev, g2d);
  1180. subdrv = &g2d->subdrv;
  1181. subdrv->dev = dev;
  1182. subdrv->probe = g2d_subdrv_probe;
  1183. subdrv->remove = g2d_subdrv_remove;
  1184. subdrv->open = g2d_open;
  1185. subdrv->close = g2d_close;
  1186. ret = exynos_drm_subdrv_register(subdrv);
  1187. if (ret < 0) {
  1188. dev_err(dev, "failed to register drm g2d device\n");
  1189. goto err_put_clk;
  1190. }
  1191. dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n",
  1192. G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER);
  1193. return 0;
  1194. err_put_clk:
  1195. pm_runtime_disable(dev);
  1196. err_destroy_workqueue:
  1197. destroy_workqueue(g2d->g2d_workq);
  1198. err_destroy_slab:
  1199. kmem_cache_destroy(g2d->runqueue_slab);
  1200. return ret;
  1201. }
  1202. static int g2d_remove(struct platform_device *pdev)
  1203. {
  1204. struct g2d_data *g2d = platform_get_drvdata(pdev);
  1205. cancel_work_sync(&g2d->runqueue_work);
  1206. exynos_drm_subdrv_unregister(&g2d->subdrv);
  1207. while (g2d->runqueue_node) {
  1208. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  1209. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  1210. }
  1211. pm_runtime_disable(&pdev->dev);
  1212. g2d_fini_cmdlist(g2d);
  1213. destroy_workqueue(g2d->g2d_workq);
  1214. kmem_cache_destroy(g2d->runqueue_slab);
  1215. return 0;
  1216. }
  1217. #ifdef CONFIG_PM_SLEEP
  1218. static int g2d_suspend(struct device *dev)
  1219. {
  1220. struct g2d_data *g2d = dev_get_drvdata(dev);
  1221. mutex_lock(&g2d->runqueue_mutex);
  1222. g2d->suspended = true;
  1223. mutex_unlock(&g2d->runqueue_mutex);
  1224. while (g2d->runqueue_node)
  1225. /* FIXME: good range? */
  1226. usleep_range(500, 1000);
  1227. flush_work(&g2d->runqueue_work);
  1228. return 0;
  1229. }
  1230. static int g2d_resume(struct device *dev)
  1231. {
  1232. struct g2d_data *g2d = dev_get_drvdata(dev);
  1233. g2d->suspended = false;
  1234. g2d_exec_runqueue(g2d);
  1235. return 0;
  1236. }
  1237. #endif
  1238. #ifdef CONFIG_PM_RUNTIME
  1239. static int g2d_runtime_suspend(struct device *dev)
  1240. {
  1241. struct g2d_data *g2d = dev_get_drvdata(dev);
  1242. clk_disable_unprepare(g2d->gate_clk);
  1243. return 0;
  1244. }
  1245. static int g2d_runtime_resume(struct device *dev)
  1246. {
  1247. struct g2d_data *g2d = dev_get_drvdata(dev);
  1248. int ret;
  1249. ret = clk_prepare_enable(g2d->gate_clk);
  1250. if (ret < 0)
  1251. dev_warn(dev, "failed to enable clock.\n");
  1252. return ret;
  1253. }
  1254. #endif
  1255. static const struct dev_pm_ops g2d_pm_ops = {
  1256. SET_SYSTEM_SLEEP_PM_OPS(g2d_suspend, g2d_resume)
  1257. SET_RUNTIME_PM_OPS(g2d_runtime_suspend, g2d_runtime_resume, NULL)
  1258. };
  1259. #ifdef CONFIG_OF
  1260. static const struct of_device_id exynos_g2d_match[] = {
  1261. { .compatible = "samsung,exynos5250-g2d" },
  1262. {},
  1263. };
  1264. #endif
  1265. struct platform_driver g2d_driver = {
  1266. .probe = g2d_probe,
  1267. .remove = g2d_remove,
  1268. .driver = {
  1269. .name = "s5p-g2d",
  1270. .owner = THIS_MODULE,
  1271. .pm = &g2d_pm_ops,
  1272. .of_match_table = of_match_ptr(exynos_g2d_match),
  1273. },
  1274. };