r8a66597-udc.c 41 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/err.h>
  29. #include <linux/slab.h>
  30. #include <linux/usb/ch9.h>
  31. #include <linux/usb/gadget.h>
  32. #include "r8a66597-udc.h"
  33. #define DRIVER_VERSION "2009-08-18"
  34. static const char udc_name[] = "r8a66597_udc";
  35. static const char *r8a66597_ep_name[] = {
  36. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  37. "ep8", "ep9",
  38. };
  39. static void disable_controller(struct r8a66597 *r8a66597);
  40. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  41. static void irq_packet_write(struct r8a66597_ep *ep,
  42. struct r8a66597_request *req);
  43. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  44. gfp_t gfp_flags);
  45. static void transfer_complete(struct r8a66597_ep *ep,
  46. struct r8a66597_request *req, int status);
  47. /*-------------------------------------------------------------------------*/
  48. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  49. {
  50. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  51. }
  52. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  53. unsigned long reg)
  54. {
  55. u16 tmp;
  56. tmp = r8a66597_read(r8a66597, INTENB0);
  57. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  58. INTENB0);
  59. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  60. r8a66597_write(r8a66597, tmp, INTENB0);
  61. }
  62. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  63. unsigned long reg)
  64. {
  65. u16 tmp;
  66. tmp = r8a66597_read(r8a66597, INTENB0);
  67. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  68. INTENB0);
  69. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  70. r8a66597_write(r8a66597, tmp, INTENB0);
  71. }
  72. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  73. {
  74. r8a66597_bset(r8a66597, CTRE, INTENB0);
  75. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  76. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  77. }
  78. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  79. __releases(r8a66597->lock)
  80. __acquires(r8a66597->lock)
  81. {
  82. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  83. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  84. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  85. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  86. spin_unlock(&r8a66597->lock);
  87. r8a66597->driver->disconnect(&r8a66597->gadget);
  88. spin_lock(&r8a66597->lock);
  89. disable_controller(r8a66597);
  90. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  91. }
  92. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  93. {
  94. u16 pid = 0;
  95. unsigned long offset;
  96. if (pipenum == 0)
  97. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  98. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  99. offset = get_pipectr_addr(pipenum);
  100. pid = r8a66597_read(r8a66597, offset) & PID;
  101. } else
  102. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  103. return pid;
  104. }
  105. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  106. u16 pid)
  107. {
  108. unsigned long offset;
  109. if (pipenum == 0)
  110. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  111. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  112. offset = get_pipectr_addr(pipenum);
  113. r8a66597_mdfy(r8a66597, pid, PID, offset);
  114. } else
  115. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  116. }
  117. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  118. {
  119. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  120. }
  121. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  122. {
  123. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  124. }
  125. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  126. {
  127. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  128. }
  129. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  130. {
  131. u16 ret = 0;
  132. unsigned long offset;
  133. if (pipenum == 0)
  134. ret = r8a66597_read(r8a66597, DCPCTR);
  135. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  136. offset = get_pipectr_addr(pipenum);
  137. ret = r8a66597_read(r8a66597, offset);
  138. } else
  139. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  140. return ret;
  141. }
  142. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  143. {
  144. unsigned long offset;
  145. pipe_stop(r8a66597, pipenum);
  146. if (pipenum == 0)
  147. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  148. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  149. offset = get_pipectr_addr(pipenum);
  150. r8a66597_bset(r8a66597, SQCLR, offset);
  151. } else
  152. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  153. }
  154. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  155. {
  156. u16 tmp;
  157. int size;
  158. if (pipenum == 0) {
  159. tmp = r8a66597_read(r8a66597, DCPCFG);
  160. if ((tmp & R8A66597_CNTMD) != 0)
  161. size = 256;
  162. else {
  163. tmp = r8a66597_read(r8a66597, DCPMAXP);
  164. size = tmp & MAXP;
  165. }
  166. } else {
  167. r8a66597_write(r8a66597, pipenum, PIPESEL);
  168. tmp = r8a66597_read(r8a66597, PIPECFG);
  169. if ((tmp & R8A66597_CNTMD) != 0) {
  170. tmp = r8a66597_read(r8a66597, PIPEBUF);
  171. size = ((tmp >> 10) + 1) * 64;
  172. } else {
  173. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  174. size = tmp & MXPS;
  175. }
  176. }
  177. return size;
  178. }
  179. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  180. {
  181. if (r8a66597->pdata->on_chip)
  182. return MBW_32;
  183. else
  184. return MBW_16;
  185. }
  186. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  187. {
  188. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  189. if (ep->use_dma)
  190. return;
  191. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  192. ndelay(450);
  193. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  194. }
  195. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  196. struct r8a66597_pipe_info *info)
  197. {
  198. u16 bufnum = 0, buf_bsize = 0;
  199. u16 pipecfg = 0;
  200. if (info->pipe == 0)
  201. return -EINVAL;
  202. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  203. if (info->dir_in)
  204. pipecfg |= R8A66597_DIR;
  205. pipecfg |= info->type;
  206. pipecfg |= info->epnum;
  207. switch (info->type) {
  208. case R8A66597_INT:
  209. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  210. buf_bsize = 0;
  211. break;
  212. case R8A66597_BULK:
  213. /* isochronous pipes may be used as bulk pipes */
  214. if (info->pipe > R8A66597_BASE_PIPENUM_BULK)
  215. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  216. else
  217. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  218. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  219. buf_bsize = 7;
  220. pipecfg |= R8A66597_DBLB;
  221. if (!info->dir_in)
  222. pipecfg |= R8A66597_SHTNAK;
  223. break;
  224. case R8A66597_ISO:
  225. bufnum = R8A66597_BASE_BUFNUM +
  226. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  227. buf_bsize = 7;
  228. break;
  229. }
  230. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  231. pr_err(KERN_ERR "r8a66597 pipe memory is insufficient\n");
  232. return -ENOMEM;
  233. }
  234. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  235. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  236. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  237. if (info->interval)
  238. info->interval--;
  239. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  240. return 0;
  241. }
  242. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  243. struct r8a66597_pipe_info *info)
  244. {
  245. if (info->pipe == 0)
  246. return;
  247. if (is_bulk_pipe(info->pipe))
  248. r8a66597->bulk--;
  249. else if (is_interrupt_pipe(info->pipe))
  250. r8a66597->interrupt--;
  251. else if (is_isoc_pipe(info->pipe)) {
  252. r8a66597->isochronous--;
  253. if (info->type == R8A66597_BULK)
  254. r8a66597->bulk--;
  255. } else
  256. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  257. info->pipe);
  258. }
  259. static void pipe_initialize(struct r8a66597_ep *ep)
  260. {
  261. struct r8a66597 *r8a66597 = ep->r8a66597;
  262. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  263. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  264. r8a66597_write(r8a66597, 0, ep->pipectr);
  265. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  266. if (ep->use_dma) {
  267. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  268. ndelay(450);
  269. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  270. }
  271. }
  272. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  273. struct r8a66597_ep *ep,
  274. const struct usb_endpoint_descriptor *desc,
  275. u16 pipenum, int dma)
  276. {
  277. ep->use_dma = 0;
  278. ep->fifoaddr = CFIFO;
  279. ep->fifosel = CFIFOSEL;
  280. ep->fifoctr = CFIFOCTR;
  281. ep->fifotrn = 0;
  282. ep->pipectr = get_pipectr_addr(pipenum);
  283. ep->pipenum = pipenum;
  284. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  285. r8a66597->pipenum2ep[pipenum] = ep;
  286. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  287. = ep;
  288. INIT_LIST_HEAD(&ep->queue);
  289. }
  290. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  291. {
  292. struct r8a66597 *r8a66597 = ep->r8a66597;
  293. u16 pipenum = ep->pipenum;
  294. if (pipenum == 0)
  295. return;
  296. if (ep->use_dma)
  297. r8a66597->num_dma--;
  298. ep->pipenum = 0;
  299. ep->busy = 0;
  300. ep->use_dma = 0;
  301. }
  302. static int alloc_pipe_config(struct r8a66597_ep *ep,
  303. const struct usb_endpoint_descriptor *desc)
  304. {
  305. struct r8a66597 *r8a66597 = ep->r8a66597;
  306. struct r8a66597_pipe_info info;
  307. int dma = 0;
  308. unsigned char *counter;
  309. int ret;
  310. ep->desc = desc;
  311. if (ep->pipenum) /* already allocated pipe */
  312. return 0;
  313. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  314. case USB_ENDPOINT_XFER_BULK:
  315. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  316. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  317. printk(KERN_ERR "bulk pipe is insufficient\n");
  318. return -ENODEV;
  319. } else {
  320. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  321. + r8a66597->isochronous;
  322. counter = &r8a66597->isochronous;
  323. }
  324. } else {
  325. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  326. counter = &r8a66597->bulk;
  327. }
  328. info.type = R8A66597_BULK;
  329. dma = 1;
  330. break;
  331. case USB_ENDPOINT_XFER_INT:
  332. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  333. printk(KERN_ERR "interrupt pipe is insufficient\n");
  334. return -ENODEV;
  335. }
  336. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  337. info.type = R8A66597_INT;
  338. counter = &r8a66597->interrupt;
  339. break;
  340. case USB_ENDPOINT_XFER_ISOC:
  341. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  342. printk(KERN_ERR "isochronous pipe is insufficient\n");
  343. return -ENODEV;
  344. }
  345. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  346. info.type = R8A66597_ISO;
  347. counter = &r8a66597->isochronous;
  348. break;
  349. default:
  350. printk(KERN_ERR "unexpect xfer type\n");
  351. return -EINVAL;
  352. }
  353. ep->type = info.type;
  354. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  355. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  356. info.interval = desc->bInterval;
  357. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  358. info.dir_in = 1;
  359. else
  360. info.dir_in = 0;
  361. ret = pipe_buffer_setting(r8a66597, &info);
  362. if (ret < 0) {
  363. printk(KERN_ERR "pipe_buffer_setting fail\n");
  364. return ret;
  365. }
  366. (*counter)++;
  367. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  368. r8a66597->bulk++;
  369. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  370. pipe_initialize(ep);
  371. return 0;
  372. }
  373. static int free_pipe_config(struct r8a66597_ep *ep)
  374. {
  375. struct r8a66597 *r8a66597 = ep->r8a66597;
  376. struct r8a66597_pipe_info info;
  377. info.pipe = ep->pipenum;
  378. info.type = ep->type;
  379. pipe_buffer_release(r8a66597, &info);
  380. r8a66597_ep_release(ep);
  381. return 0;
  382. }
  383. /*-------------------------------------------------------------------------*/
  384. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  385. {
  386. enable_irq_ready(r8a66597, pipenum);
  387. enable_irq_nrdy(r8a66597, pipenum);
  388. }
  389. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  390. {
  391. disable_irq_ready(r8a66597, pipenum);
  392. disable_irq_nrdy(r8a66597, pipenum);
  393. }
  394. /* if complete is true, gadget driver complete function is not call */
  395. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  396. {
  397. r8a66597->ep[0].internal_ccpl = ccpl;
  398. pipe_start(r8a66597, 0);
  399. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  400. }
  401. static void start_ep0_write(struct r8a66597_ep *ep,
  402. struct r8a66597_request *req)
  403. {
  404. struct r8a66597 *r8a66597 = ep->r8a66597;
  405. pipe_change(r8a66597, ep->pipenum);
  406. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  407. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  408. if (req->req.length == 0) {
  409. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  410. pipe_start(r8a66597, 0);
  411. transfer_complete(ep, req, 0);
  412. } else {
  413. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  414. irq_ep0_write(ep, req);
  415. }
  416. }
  417. static void start_packet_write(struct r8a66597_ep *ep,
  418. struct r8a66597_request *req)
  419. {
  420. struct r8a66597 *r8a66597 = ep->r8a66597;
  421. u16 tmp;
  422. pipe_change(r8a66597, ep->pipenum);
  423. disable_irq_empty(r8a66597, ep->pipenum);
  424. pipe_start(r8a66597, ep->pipenum);
  425. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  426. if (unlikely((tmp & FRDY) == 0))
  427. pipe_irq_enable(r8a66597, ep->pipenum);
  428. else
  429. irq_packet_write(ep, req);
  430. }
  431. static void start_packet_read(struct r8a66597_ep *ep,
  432. struct r8a66597_request *req)
  433. {
  434. struct r8a66597 *r8a66597 = ep->r8a66597;
  435. u16 pipenum = ep->pipenum;
  436. if (ep->pipenum == 0) {
  437. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  438. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  439. pipe_start(r8a66597, pipenum);
  440. pipe_irq_enable(r8a66597, pipenum);
  441. } else {
  442. if (ep->use_dma) {
  443. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  444. pipe_change(r8a66597, pipenum);
  445. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  446. r8a66597_write(r8a66597,
  447. (req->req.length + ep->ep.maxpacket - 1)
  448. / ep->ep.maxpacket,
  449. ep->fifotrn);
  450. }
  451. pipe_start(r8a66597, pipenum); /* trigger once */
  452. pipe_irq_enable(r8a66597, pipenum);
  453. }
  454. }
  455. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  456. {
  457. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  458. start_packet_write(ep, req);
  459. else
  460. start_packet_read(ep, req);
  461. }
  462. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  463. {
  464. u16 ctsq;
  465. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  466. switch (ctsq) {
  467. case CS_RDDS:
  468. start_ep0_write(ep, req);
  469. break;
  470. case CS_WRDS:
  471. start_packet_read(ep, req);
  472. break;
  473. case CS_WRND:
  474. control_end(ep->r8a66597, 0);
  475. break;
  476. default:
  477. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  478. break;
  479. }
  480. }
  481. static void init_controller(struct r8a66597 *r8a66597)
  482. {
  483. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  484. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  485. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  486. if (r8a66597->pdata->on_chip) {
  487. r8a66597_bset(r8a66597, 0x04, SYSCFG1);
  488. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  489. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  490. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  491. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  492. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  493. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  494. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  495. DMA0CFG);
  496. } else {
  497. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  498. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  499. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  500. XTAL, SYSCFG0);
  501. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  502. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  503. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  504. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  505. msleep(3);
  506. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  507. msleep(1);
  508. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  509. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  510. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  511. DMA0CFG);
  512. }
  513. }
  514. static void disable_controller(struct r8a66597 *r8a66597)
  515. {
  516. if (r8a66597->pdata->on_chip) {
  517. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  518. /* disable interrupts */
  519. r8a66597_write(r8a66597, 0, INTENB0);
  520. r8a66597_write(r8a66597, 0, INTENB1);
  521. r8a66597_write(r8a66597, 0, BRDYENB);
  522. r8a66597_write(r8a66597, 0, BEMPENB);
  523. r8a66597_write(r8a66597, 0, NRDYENB);
  524. /* clear status */
  525. r8a66597_write(r8a66597, 0, BRDYSTS);
  526. r8a66597_write(r8a66597, 0, NRDYSTS);
  527. r8a66597_write(r8a66597, 0, BEMPSTS);
  528. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  529. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  530. } else {
  531. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  532. udelay(1);
  533. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  534. udelay(1);
  535. udelay(1);
  536. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  537. }
  538. }
  539. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  540. {
  541. u16 tmp;
  542. if (!r8a66597->pdata->on_chip) {
  543. tmp = r8a66597_read(r8a66597, SYSCFG0);
  544. if (!(tmp & XCKE))
  545. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  546. }
  547. }
  548. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  549. {
  550. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  551. }
  552. /*-------------------------------------------------------------------------*/
  553. static void transfer_complete(struct r8a66597_ep *ep,
  554. struct r8a66597_request *req, int status)
  555. __releases(r8a66597->lock)
  556. __acquires(r8a66597->lock)
  557. {
  558. int restart = 0;
  559. if (unlikely(ep->pipenum == 0)) {
  560. if (ep->internal_ccpl) {
  561. ep->internal_ccpl = 0;
  562. return;
  563. }
  564. }
  565. list_del_init(&req->queue);
  566. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  567. req->req.status = -ESHUTDOWN;
  568. else
  569. req->req.status = status;
  570. if (!list_empty(&ep->queue))
  571. restart = 1;
  572. spin_unlock(&ep->r8a66597->lock);
  573. req->req.complete(&ep->ep, &req->req);
  574. spin_lock(&ep->r8a66597->lock);
  575. if (restart) {
  576. req = get_request_from_ep(ep);
  577. if (ep->desc)
  578. start_packet(ep, req);
  579. }
  580. }
  581. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  582. {
  583. int i;
  584. u16 tmp;
  585. unsigned bufsize;
  586. size_t size;
  587. void *buf;
  588. u16 pipenum = ep->pipenum;
  589. struct r8a66597 *r8a66597 = ep->r8a66597;
  590. pipe_change(r8a66597, pipenum);
  591. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  592. i = 0;
  593. do {
  594. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  595. if (i++ > 100000) {
  596. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  597. "conflict. please power off this controller.");
  598. return;
  599. }
  600. ndelay(1);
  601. } while ((tmp & FRDY) == 0);
  602. /* prepare parameters */
  603. bufsize = get_buffer_size(r8a66597, pipenum);
  604. buf = req->req.buf + req->req.actual;
  605. size = min(bufsize, req->req.length - req->req.actual);
  606. /* write fifo */
  607. if (req->req.buf) {
  608. if (size > 0)
  609. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  610. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  611. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  612. }
  613. /* update parameters */
  614. req->req.actual += size;
  615. /* check transfer finish */
  616. if ((!req->req.zero && (req->req.actual == req->req.length))
  617. || (size % ep->ep.maxpacket)
  618. || (size == 0)) {
  619. disable_irq_ready(r8a66597, pipenum);
  620. disable_irq_empty(r8a66597, pipenum);
  621. } else {
  622. disable_irq_ready(r8a66597, pipenum);
  623. enable_irq_empty(r8a66597, pipenum);
  624. }
  625. pipe_start(r8a66597, pipenum);
  626. }
  627. static void irq_packet_write(struct r8a66597_ep *ep,
  628. struct r8a66597_request *req)
  629. {
  630. u16 tmp;
  631. unsigned bufsize;
  632. size_t size;
  633. void *buf;
  634. u16 pipenum = ep->pipenum;
  635. struct r8a66597 *r8a66597 = ep->r8a66597;
  636. pipe_change(r8a66597, pipenum);
  637. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  638. if (unlikely((tmp & FRDY) == 0)) {
  639. pipe_stop(r8a66597, pipenum);
  640. pipe_irq_disable(r8a66597, pipenum);
  641. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  642. return;
  643. }
  644. /* prepare parameters */
  645. bufsize = get_buffer_size(r8a66597, pipenum);
  646. buf = req->req.buf + req->req.actual;
  647. size = min(bufsize, req->req.length - req->req.actual);
  648. /* write fifo */
  649. if (req->req.buf) {
  650. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  651. if ((size == 0)
  652. || ((size % ep->ep.maxpacket) != 0)
  653. || ((bufsize != ep->ep.maxpacket)
  654. && (bufsize > size)))
  655. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  656. }
  657. /* update parameters */
  658. req->req.actual += size;
  659. /* check transfer finish */
  660. if ((!req->req.zero && (req->req.actual == req->req.length))
  661. || (size % ep->ep.maxpacket)
  662. || (size == 0)) {
  663. disable_irq_ready(r8a66597, pipenum);
  664. enable_irq_empty(r8a66597, pipenum);
  665. } else {
  666. disable_irq_empty(r8a66597, pipenum);
  667. pipe_irq_enable(r8a66597, pipenum);
  668. }
  669. }
  670. static void irq_packet_read(struct r8a66597_ep *ep,
  671. struct r8a66597_request *req)
  672. {
  673. u16 tmp;
  674. int rcv_len, bufsize, req_len;
  675. int size;
  676. void *buf;
  677. u16 pipenum = ep->pipenum;
  678. struct r8a66597 *r8a66597 = ep->r8a66597;
  679. int finish = 0;
  680. pipe_change(r8a66597, pipenum);
  681. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  682. if (unlikely((tmp & FRDY) == 0)) {
  683. req->req.status = -EPIPE;
  684. pipe_stop(r8a66597, pipenum);
  685. pipe_irq_disable(r8a66597, pipenum);
  686. printk(KERN_ERR "read fifo not ready");
  687. return;
  688. }
  689. /* prepare parameters */
  690. rcv_len = tmp & DTLN;
  691. bufsize = get_buffer_size(r8a66597, pipenum);
  692. buf = req->req.buf + req->req.actual;
  693. req_len = req->req.length - req->req.actual;
  694. if (rcv_len < bufsize)
  695. size = min(rcv_len, req_len);
  696. else
  697. size = min(bufsize, req_len);
  698. /* update parameters */
  699. req->req.actual += size;
  700. /* check transfer finish */
  701. if ((!req->req.zero && (req->req.actual == req->req.length))
  702. || (size % ep->ep.maxpacket)
  703. || (size == 0)) {
  704. pipe_stop(r8a66597, pipenum);
  705. pipe_irq_disable(r8a66597, pipenum);
  706. finish = 1;
  707. }
  708. /* read fifo */
  709. if (req->req.buf) {
  710. if (size == 0)
  711. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  712. else
  713. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  714. }
  715. if ((ep->pipenum != 0) && finish)
  716. transfer_complete(ep, req, 0);
  717. }
  718. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  719. {
  720. u16 check;
  721. u16 pipenum;
  722. struct r8a66597_ep *ep;
  723. struct r8a66597_request *req;
  724. if ((status & BRDY0) && (enb & BRDY0)) {
  725. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  726. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  727. ep = &r8a66597->ep[0];
  728. req = get_request_from_ep(ep);
  729. irq_packet_read(ep, req);
  730. } else {
  731. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  732. check = 1 << pipenum;
  733. if ((status & check) && (enb & check)) {
  734. r8a66597_write(r8a66597, ~check, BRDYSTS);
  735. ep = r8a66597->pipenum2ep[pipenum];
  736. req = get_request_from_ep(ep);
  737. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  738. irq_packet_write(ep, req);
  739. else
  740. irq_packet_read(ep, req);
  741. }
  742. }
  743. }
  744. }
  745. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  746. {
  747. u16 tmp;
  748. u16 check;
  749. u16 pipenum;
  750. struct r8a66597_ep *ep;
  751. struct r8a66597_request *req;
  752. if ((status & BEMP0) && (enb & BEMP0)) {
  753. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  754. ep = &r8a66597->ep[0];
  755. req = get_request_from_ep(ep);
  756. irq_ep0_write(ep, req);
  757. } else {
  758. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  759. check = 1 << pipenum;
  760. if ((status & check) && (enb & check)) {
  761. r8a66597_write(r8a66597, ~check, BEMPSTS);
  762. tmp = control_reg_get(r8a66597, pipenum);
  763. if ((tmp & INBUFM) == 0) {
  764. disable_irq_empty(r8a66597, pipenum);
  765. pipe_irq_disable(r8a66597, pipenum);
  766. pipe_stop(r8a66597, pipenum);
  767. ep = r8a66597->pipenum2ep[pipenum];
  768. req = get_request_from_ep(ep);
  769. if (!list_empty(&ep->queue))
  770. transfer_complete(ep, req, 0);
  771. }
  772. }
  773. }
  774. }
  775. }
  776. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  777. __releases(r8a66597->lock)
  778. __acquires(r8a66597->lock)
  779. {
  780. struct r8a66597_ep *ep;
  781. u16 pid;
  782. u16 status = 0;
  783. u16 w_index = le16_to_cpu(ctrl->wIndex);
  784. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  785. case USB_RECIP_DEVICE:
  786. status = 1 << USB_DEVICE_SELF_POWERED;
  787. break;
  788. case USB_RECIP_INTERFACE:
  789. status = 0;
  790. break;
  791. case USB_RECIP_ENDPOINT:
  792. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  793. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  794. if (pid == PID_STALL)
  795. status = 1 << USB_ENDPOINT_HALT;
  796. else
  797. status = 0;
  798. break;
  799. default:
  800. pipe_stall(r8a66597, 0);
  801. return; /* exit */
  802. }
  803. r8a66597->ep0_data = cpu_to_le16(status);
  804. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  805. r8a66597->ep0_req->length = 2;
  806. /* AV: what happens if we get called again before that gets through? */
  807. spin_unlock(&r8a66597->lock);
  808. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  809. spin_lock(&r8a66597->lock);
  810. }
  811. static void clear_feature(struct r8a66597 *r8a66597,
  812. struct usb_ctrlrequest *ctrl)
  813. {
  814. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  815. case USB_RECIP_DEVICE:
  816. control_end(r8a66597, 1);
  817. break;
  818. case USB_RECIP_INTERFACE:
  819. control_end(r8a66597, 1);
  820. break;
  821. case USB_RECIP_ENDPOINT: {
  822. struct r8a66597_ep *ep;
  823. struct r8a66597_request *req;
  824. u16 w_index = le16_to_cpu(ctrl->wIndex);
  825. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  826. if (!ep->wedge) {
  827. pipe_stop(r8a66597, ep->pipenum);
  828. control_reg_sqclr(r8a66597, ep->pipenum);
  829. spin_unlock(&r8a66597->lock);
  830. usb_ep_clear_halt(&ep->ep);
  831. spin_lock(&r8a66597->lock);
  832. }
  833. control_end(r8a66597, 1);
  834. req = get_request_from_ep(ep);
  835. if (ep->busy) {
  836. ep->busy = 0;
  837. if (list_empty(&ep->queue))
  838. break;
  839. start_packet(ep, req);
  840. } else if (!list_empty(&ep->queue))
  841. pipe_start(r8a66597, ep->pipenum);
  842. }
  843. break;
  844. default:
  845. pipe_stall(r8a66597, 0);
  846. break;
  847. }
  848. }
  849. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  850. {
  851. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  852. case USB_RECIP_DEVICE:
  853. control_end(r8a66597, 1);
  854. break;
  855. case USB_RECIP_INTERFACE:
  856. control_end(r8a66597, 1);
  857. break;
  858. case USB_RECIP_ENDPOINT: {
  859. struct r8a66597_ep *ep;
  860. u16 w_index = le16_to_cpu(ctrl->wIndex);
  861. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  862. pipe_stall(r8a66597, ep->pipenum);
  863. control_end(r8a66597, 1);
  864. }
  865. break;
  866. default:
  867. pipe_stall(r8a66597, 0);
  868. break;
  869. }
  870. }
  871. /* if return value is true, call class driver's setup() */
  872. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  873. {
  874. u16 *p = (u16 *)ctrl;
  875. unsigned long offset = USBREQ;
  876. int i, ret = 0;
  877. /* read fifo */
  878. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  879. for (i = 0; i < 4; i++)
  880. p[i] = r8a66597_read(r8a66597, offset + i*2);
  881. /* check request */
  882. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  883. switch (ctrl->bRequest) {
  884. case USB_REQ_GET_STATUS:
  885. get_status(r8a66597, ctrl);
  886. break;
  887. case USB_REQ_CLEAR_FEATURE:
  888. clear_feature(r8a66597, ctrl);
  889. break;
  890. case USB_REQ_SET_FEATURE:
  891. set_feature(r8a66597, ctrl);
  892. break;
  893. default:
  894. ret = 1;
  895. break;
  896. }
  897. } else
  898. ret = 1;
  899. return ret;
  900. }
  901. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  902. {
  903. u16 speed = get_usb_speed(r8a66597);
  904. switch (speed) {
  905. case HSMODE:
  906. r8a66597->gadget.speed = USB_SPEED_HIGH;
  907. break;
  908. case FSMODE:
  909. r8a66597->gadget.speed = USB_SPEED_FULL;
  910. break;
  911. default:
  912. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  913. printk(KERN_ERR "USB speed unknown\n");
  914. }
  915. }
  916. static void irq_device_state(struct r8a66597 *r8a66597)
  917. {
  918. u16 dvsq;
  919. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  920. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  921. if (dvsq == DS_DFLT) {
  922. /* bus reset */
  923. r8a66597->driver->disconnect(&r8a66597->gadget);
  924. r8a66597_update_usb_speed(r8a66597);
  925. }
  926. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  927. r8a66597_update_usb_speed(r8a66597);
  928. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  929. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  930. r8a66597_update_usb_speed(r8a66597);
  931. r8a66597->old_dvsq = dvsq;
  932. }
  933. static void irq_control_stage(struct r8a66597 *r8a66597)
  934. __releases(r8a66597->lock)
  935. __acquires(r8a66597->lock)
  936. {
  937. struct usb_ctrlrequest ctrl;
  938. u16 ctsq;
  939. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  940. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  941. switch (ctsq) {
  942. case CS_IDST: {
  943. struct r8a66597_ep *ep;
  944. struct r8a66597_request *req;
  945. ep = &r8a66597->ep[0];
  946. req = get_request_from_ep(ep);
  947. transfer_complete(ep, req, 0);
  948. }
  949. break;
  950. case CS_RDDS:
  951. case CS_WRDS:
  952. case CS_WRND:
  953. if (setup_packet(r8a66597, &ctrl)) {
  954. spin_unlock(&r8a66597->lock);
  955. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  956. < 0)
  957. pipe_stall(r8a66597, 0);
  958. spin_lock(&r8a66597->lock);
  959. }
  960. break;
  961. case CS_RDSS:
  962. case CS_WRSS:
  963. control_end(r8a66597, 0);
  964. break;
  965. default:
  966. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  967. break;
  968. }
  969. }
  970. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  971. {
  972. struct r8a66597 *r8a66597 = _r8a66597;
  973. u16 intsts0;
  974. u16 intenb0;
  975. u16 brdysts, nrdysts, bempsts;
  976. u16 brdyenb, nrdyenb, bempenb;
  977. u16 savepipe;
  978. u16 mask0;
  979. spin_lock(&r8a66597->lock);
  980. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  981. intenb0 = r8a66597_read(r8a66597, INTENB0);
  982. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  983. mask0 = intsts0 & intenb0;
  984. if (mask0) {
  985. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  986. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  987. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  988. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  989. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  990. bempenb = r8a66597_read(r8a66597, BEMPENB);
  991. if (mask0 & VBINT) {
  992. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  993. INTSTS0);
  994. r8a66597_start_xclock(r8a66597);
  995. /* start vbus sampling */
  996. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  997. & VBSTS;
  998. r8a66597->scount = R8A66597_MAX_SAMPLING;
  999. mod_timer(&r8a66597->timer,
  1000. jiffies + msecs_to_jiffies(50));
  1001. }
  1002. if (intsts0 & DVSQ)
  1003. irq_device_state(r8a66597);
  1004. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1005. && (brdysts & brdyenb))
  1006. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1007. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1008. && (bempsts & bempenb))
  1009. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1010. if (intsts0 & CTRT)
  1011. irq_control_stage(r8a66597);
  1012. }
  1013. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1014. spin_unlock(&r8a66597->lock);
  1015. return IRQ_HANDLED;
  1016. }
  1017. static void r8a66597_timer(unsigned long _r8a66597)
  1018. {
  1019. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1020. unsigned long flags;
  1021. u16 tmp;
  1022. spin_lock_irqsave(&r8a66597->lock, flags);
  1023. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1024. if (r8a66597->scount > 0) {
  1025. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1026. if (tmp == r8a66597->old_vbus) {
  1027. r8a66597->scount--;
  1028. if (r8a66597->scount == 0) {
  1029. if (tmp == VBSTS)
  1030. r8a66597_usb_connect(r8a66597);
  1031. else
  1032. r8a66597_usb_disconnect(r8a66597);
  1033. } else {
  1034. mod_timer(&r8a66597->timer,
  1035. jiffies + msecs_to_jiffies(50));
  1036. }
  1037. } else {
  1038. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1039. r8a66597->old_vbus = tmp;
  1040. mod_timer(&r8a66597->timer,
  1041. jiffies + msecs_to_jiffies(50));
  1042. }
  1043. }
  1044. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1045. }
  1046. /*-------------------------------------------------------------------------*/
  1047. static int r8a66597_enable(struct usb_ep *_ep,
  1048. const struct usb_endpoint_descriptor *desc)
  1049. {
  1050. struct r8a66597_ep *ep;
  1051. ep = container_of(_ep, struct r8a66597_ep, ep);
  1052. return alloc_pipe_config(ep, desc);
  1053. }
  1054. static int r8a66597_disable(struct usb_ep *_ep)
  1055. {
  1056. struct r8a66597_ep *ep;
  1057. struct r8a66597_request *req;
  1058. unsigned long flags;
  1059. ep = container_of(_ep, struct r8a66597_ep, ep);
  1060. BUG_ON(!ep);
  1061. while (!list_empty(&ep->queue)) {
  1062. req = get_request_from_ep(ep);
  1063. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1064. transfer_complete(ep, req, -ECONNRESET);
  1065. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1066. }
  1067. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1068. return free_pipe_config(ep);
  1069. }
  1070. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1071. gfp_t gfp_flags)
  1072. {
  1073. struct r8a66597_request *req;
  1074. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1075. if (!req)
  1076. return NULL;
  1077. INIT_LIST_HEAD(&req->queue);
  1078. return &req->req;
  1079. }
  1080. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1081. {
  1082. struct r8a66597_request *req;
  1083. req = container_of(_req, struct r8a66597_request, req);
  1084. kfree(req);
  1085. }
  1086. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1087. gfp_t gfp_flags)
  1088. {
  1089. struct r8a66597_ep *ep;
  1090. struct r8a66597_request *req;
  1091. unsigned long flags;
  1092. int request = 0;
  1093. ep = container_of(_ep, struct r8a66597_ep, ep);
  1094. req = container_of(_req, struct r8a66597_request, req);
  1095. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1096. return -ESHUTDOWN;
  1097. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1098. if (list_empty(&ep->queue))
  1099. request = 1;
  1100. list_add_tail(&req->queue, &ep->queue);
  1101. req->req.actual = 0;
  1102. req->req.status = -EINPROGRESS;
  1103. if (ep->desc == NULL) /* control */
  1104. start_ep0(ep, req);
  1105. else {
  1106. if (request && !ep->busy)
  1107. start_packet(ep, req);
  1108. }
  1109. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1110. return 0;
  1111. }
  1112. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1113. {
  1114. struct r8a66597_ep *ep;
  1115. struct r8a66597_request *req;
  1116. unsigned long flags;
  1117. ep = container_of(_ep, struct r8a66597_ep, ep);
  1118. req = container_of(_req, struct r8a66597_request, req);
  1119. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1120. if (!list_empty(&ep->queue))
  1121. transfer_complete(ep, req, -ECONNRESET);
  1122. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1123. return 0;
  1124. }
  1125. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1126. {
  1127. struct r8a66597_ep *ep;
  1128. struct r8a66597_request *req;
  1129. unsigned long flags;
  1130. int ret = 0;
  1131. ep = container_of(_ep, struct r8a66597_ep, ep);
  1132. req = get_request_from_ep(ep);
  1133. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1134. if (!list_empty(&ep->queue)) {
  1135. ret = -EAGAIN;
  1136. goto out;
  1137. }
  1138. if (value) {
  1139. ep->busy = 1;
  1140. pipe_stall(ep->r8a66597, ep->pipenum);
  1141. } else {
  1142. ep->busy = 0;
  1143. ep->wedge = 0;
  1144. pipe_stop(ep->r8a66597, ep->pipenum);
  1145. }
  1146. out:
  1147. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1148. return ret;
  1149. }
  1150. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1151. {
  1152. struct r8a66597_ep *ep;
  1153. unsigned long flags;
  1154. ep = container_of(_ep, struct r8a66597_ep, ep);
  1155. if (!ep || !ep->desc)
  1156. return -EINVAL;
  1157. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1158. ep->wedge = 1;
  1159. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1160. return usb_ep_set_halt(_ep);
  1161. }
  1162. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1163. {
  1164. struct r8a66597_ep *ep;
  1165. unsigned long flags;
  1166. ep = container_of(_ep, struct r8a66597_ep, ep);
  1167. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1168. if (list_empty(&ep->queue) && !ep->busy) {
  1169. pipe_stop(ep->r8a66597, ep->pipenum);
  1170. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1171. }
  1172. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1173. }
  1174. static struct usb_ep_ops r8a66597_ep_ops = {
  1175. .enable = r8a66597_enable,
  1176. .disable = r8a66597_disable,
  1177. .alloc_request = r8a66597_alloc_request,
  1178. .free_request = r8a66597_free_request,
  1179. .queue = r8a66597_queue,
  1180. .dequeue = r8a66597_dequeue,
  1181. .set_halt = r8a66597_set_halt,
  1182. .set_wedge = r8a66597_set_wedge,
  1183. .fifo_flush = r8a66597_fifo_flush,
  1184. };
  1185. /*-------------------------------------------------------------------------*/
  1186. static struct r8a66597 *the_controller;
  1187. int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
  1188. int (*bind)(struct usb_gadget *))
  1189. {
  1190. struct r8a66597 *r8a66597 = the_controller;
  1191. int retval;
  1192. if (!driver
  1193. || driver->speed != USB_SPEED_HIGH
  1194. || !bind
  1195. || !driver->setup)
  1196. return -EINVAL;
  1197. if (!r8a66597)
  1198. return -ENODEV;
  1199. if (r8a66597->driver)
  1200. return -EBUSY;
  1201. /* hook up the driver */
  1202. driver->driver.bus = NULL;
  1203. r8a66597->driver = driver;
  1204. r8a66597->gadget.dev.driver = &driver->driver;
  1205. retval = device_add(&r8a66597->gadget.dev);
  1206. if (retval) {
  1207. printk(KERN_ERR "device_add error (%d)\n", retval);
  1208. goto error;
  1209. }
  1210. retval = bind(&r8a66597->gadget);
  1211. if (retval) {
  1212. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1213. device_del(&r8a66597->gadget.dev);
  1214. goto error;
  1215. }
  1216. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1217. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1218. r8a66597_start_xclock(r8a66597);
  1219. /* start vbus sampling */
  1220. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1221. INTSTS0) & VBSTS;
  1222. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1223. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1224. }
  1225. return 0;
  1226. error:
  1227. r8a66597->driver = NULL;
  1228. r8a66597->gadget.dev.driver = NULL;
  1229. return retval;
  1230. }
  1231. EXPORT_SYMBOL(usb_gadget_probe_driver);
  1232. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1233. {
  1234. struct r8a66597 *r8a66597 = the_controller;
  1235. unsigned long flags;
  1236. if (driver != r8a66597->driver || !driver->unbind)
  1237. return -EINVAL;
  1238. spin_lock_irqsave(&r8a66597->lock, flags);
  1239. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1240. r8a66597_usb_disconnect(r8a66597);
  1241. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1242. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1243. driver->unbind(&r8a66597->gadget);
  1244. init_controller(r8a66597);
  1245. disable_controller(r8a66597);
  1246. device_del(&r8a66597->gadget.dev);
  1247. r8a66597->driver = NULL;
  1248. return 0;
  1249. }
  1250. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1251. /*-------------------------------------------------------------------------*/
  1252. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1253. {
  1254. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1255. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1256. }
  1257. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1258. .get_frame = r8a66597_get_frame,
  1259. };
  1260. static int __exit r8a66597_remove(struct platform_device *pdev)
  1261. {
  1262. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1263. del_timer_sync(&r8a66597->timer);
  1264. iounmap(r8a66597->reg);
  1265. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1266. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1267. #ifdef CONFIG_HAVE_CLK
  1268. if (r8a66597->pdata->on_chip) {
  1269. clk_disable(r8a66597->clk);
  1270. clk_put(r8a66597->clk);
  1271. }
  1272. #endif
  1273. kfree(r8a66597);
  1274. return 0;
  1275. }
  1276. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1277. {
  1278. }
  1279. static int __init r8a66597_probe(struct platform_device *pdev)
  1280. {
  1281. #ifdef CONFIG_HAVE_CLK
  1282. char clk_name[8];
  1283. #endif
  1284. struct resource *res, *ires;
  1285. int irq;
  1286. void __iomem *reg = NULL;
  1287. struct r8a66597 *r8a66597 = NULL;
  1288. int ret = 0;
  1289. int i;
  1290. unsigned long irq_trigger;
  1291. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1292. if (!res) {
  1293. ret = -ENODEV;
  1294. printk(KERN_ERR "platform_get_resource error.\n");
  1295. goto clean_up;
  1296. }
  1297. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1298. irq = ires->start;
  1299. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1300. if (irq < 0) {
  1301. ret = -ENODEV;
  1302. printk(KERN_ERR "platform_get_irq error.\n");
  1303. goto clean_up;
  1304. }
  1305. reg = ioremap(res->start, resource_size(res));
  1306. if (reg == NULL) {
  1307. ret = -ENOMEM;
  1308. printk(KERN_ERR "ioremap error.\n");
  1309. goto clean_up;
  1310. }
  1311. /* initialize ucd */
  1312. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1313. if (r8a66597 == NULL) {
  1314. ret = -ENOMEM;
  1315. printk(KERN_ERR "kzalloc error\n");
  1316. goto clean_up;
  1317. }
  1318. spin_lock_init(&r8a66597->lock);
  1319. dev_set_drvdata(&pdev->dev, r8a66597);
  1320. r8a66597->pdata = pdev->dev.platform_data;
  1321. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1322. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1323. device_initialize(&r8a66597->gadget.dev);
  1324. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1325. r8a66597->gadget.is_dualspeed = 1;
  1326. r8a66597->gadget.dev.parent = &pdev->dev;
  1327. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1328. r8a66597->gadget.dev.release = pdev->dev.release;
  1329. r8a66597->gadget.name = udc_name;
  1330. init_timer(&r8a66597->timer);
  1331. r8a66597->timer.function = r8a66597_timer;
  1332. r8a66597->timer.data = (unsigned long)r8a66597;
  1333. r8a66597->reg = reg;
  1334. #ifdef CONFIG_HAVE_CLK
  1335. if (r8a66597->pdata->on_chip) {
  1336. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1337. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1338. if (IS_ERR(r8a66597->clk)) {
  1339. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1340. clk_name);
  1341. ret = PTR_ERR(r8a66597->clk);
  1342. goto clean_up;
  1343. }
  1344. clk_enable(r8a66597->clk);
  1345. }
  1346. #endif
  1347. disable_controller(r8a66597); /* make sure controller is disabled */
  1348. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1349. udc_name, r8a66597);
  1350. if (ret < 0) {
  1351. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1352. goto clean_up2;
  1353. }
  1354. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1355. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1356. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1357. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1358. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1359. if (i != 0) {
  1360. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1361. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1362. &r8a66597->gadget.ep_list);
  1363. }
  1364. ep->r8a66597 = r8a66597;
  1365. INIT_LIST_HEAD(&ep->queue);
  1366. ep->ep.name = r8a66597_ep_name[i];
  1367. ep->ep.ops = &r8a66597_ep_ops;
  1368. ep->ep.maxpacket = 512;
  1369. }
  1370. r8a66597->ep[0].ep.maxpacket = 64;
  1371. r8a66597->ep[0].pipenum = 0;
  1372. r8a66597->ep[0].fifoaddr = CFIFO;
  1373. r8a66597->ep[0].fifosel = CFIFOSEL;
  1374. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1375. r8a66597->ep[0].fifotrn = 0;
  1376. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1377. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1378. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1379. the_controller = r8a66597;
  1380. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1381. GFP_KERNEL);
  1382. if (r8a66597->ep0_req == NULL)
  1383. goto clean_up3;
  1384. r8a66597->ep0_req->complete = nop_completion;
  1385. init_controller(r8a66597);
  1386. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1387. return 0;
  1388. clean_up3:
  1389. free_irq(irq, r8a66597);
  1390. clean_up2:
  1391. #ifdef CONFIG_HAVE_CLK
  1392. if (r8a66597->pdata->on_chip) {
  1393. clk_disable(r8a66597->clk);
  1394. clk_put(r8a66597->clk);
  1395. }
  1396. #endif
  1397. clean_up:
  1398. if (r8a66597) {
  1399. if (r8a66597->ep0_req)
  1400. r8a66597_free_request(&r8a66597->ep[0].ep,
  1401. r8a66597->ep0_req);
  1402. kfree(r8a66597);
  1403. }
  1404. if (reg)
  1405. iounmap(reg);
  1406. return ret;
  1407. }
  1408. /*-------------------------------------------------------------------------*/
  1409. static struct platform_driver r8a66597_driver = {
  1410. .remove = __exit_p(r8a66597_remove),
  1411. .driver = {
  1412. .name = (char *) udc_name,
  1413. },
  1414. };
  1415. static int __init r8a66597_udc_init(void)
  1416. {
  1417. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1418. }
  1419. module_init(r8a66597_udc_init);
  1420. static void __exit r8a66597_udc_cleanup(void)
  1421. {
  1422. platform_driver_unregister(&r8a66597_driver);
  1423. }
  1424. module_exit(r8a66597_udc_cleanup);
  1425. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1426. MODULE_LICENSE("GPL");
  1427. MODULE_AUTHOR("Yoshihiro Shimoda");