tilcdc_drv.c 16 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include "tilcdc_drv.h"
  19. #include "tilcdc_regs.h"
  20. #include "tilcdc_tfp410.h"
  21. #include "tilcdc_slave.h"
  22. #include "tilcdc_panel.h"
  23. #include "drm_fb_helper.h"
  24. static LIST_HEAD(module_list);
  25. static bool slave_probing;
  26. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  27. const struct tilcdc_module_ops *funcs)
  28. {
  29. mod->name = name;
  30. mod->funcs = funcs;
  31. INIT_LIST_HEAD(&mod->list);
  32. list_add(&mod->list, &module_list);
  33. }
  34. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  35. {
  36. list_del(&mod->list);
  37. }
  38. void tilcdc_slave_probedefer(bool defered)
  39. {
  40. slave_probing = defered;
  41. }
  42. static struct of_device_id tilcdc_of_match[];
  43. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  44. struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
  45. {
  46. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  47. }
  48. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  49. {
  50. struct tilcdc_drm_private *priv = dev->dev_private;
  51. if (priv->fbdev)
  52. drm_fbdev_cma_hotplug_event(priv->fbdev);
  53. }
  54. static const struct drm_mode_config_funcs mode_config_funcs = {
  55. .fb_create = tilcdc_fb_create,
  56. .output_poll_changed = tilcdc_fb_output_poll_changed,
  57. };
  58. static int modeset_init(struct drm_device *dev)
  59. {
  60. struct tilcdc_drm_private *priv = dev->dev_private;
  61. struct tilcdc_module *mod;
  62. drm_mode_config_init(dev);
  63. priv->crtc = tilcdc_crtc_create(dev);
  64. list_for_each_entry(mod, &module_list, list) {
  65. DBG("loading module: %s", mod->name);
  66. mod->funcs->modeset_init(mod, dev);
  67. }
  68. if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
  69. /* oh nos! */
  70. dev_err(dev->dev, "no encoders/connectors found\n");
  71. return -ENXIO;
  72. }
  73. dev->mode_config.min_width = 0;
  74. dev->mode_config.min_height = 0;
  75. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  76. dev->mode_config.max_height = 2048;
  77. dev->mode_config.funcs = &mode_config_funcs;
  78. return 0;
  79. }
  80. #ifdef CONFIG_CPU_FREQ
  81. static int cpufreq_transition(struct notifier_block *nb,
  82. unsigned long val, void *data)
  83. {
  84. struct tilcdc_drm_private *priv = container_of(nb,
  85. struct tilcdc_drm_private, freq_transition);
  86. if (val == CPUFREQ_POSTCHANGE) {
  87. if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
  88. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  89. tilcdc_crtc_update_clk(priv->crtc);
  90. }
  91. }
  92. return 0;
  93. }
  94. #endif
  95. /*
  96. * DRM operations:
  97. */
  98. static int tilcdc_unload(struct drm_device *dev)
  99. {
  100. struct tilcdc_drm_private *priv = dev->dev_private;
  101. struct tilcdc_module *mod, *cur;
  102. drm_kms_helper_poll_fini(dev);
  103. drm_mode_config_cleanup(dev);
  104. drm_vblank_cleanup(dev);
  105. pm_runtime_get_sync(dev->dev);
  106. drm_irq_uninstall(dev);
  107. pm_runtime_put_sync(dev->dev);
  108. #ifdef CONFIG_CPU_FREQ
  109. cpufreq_unregister_notifier(&priv->freq_transition,
  110. CPUFREQ_TRANSITION_NOTIFIER);
  111. #endif
  112. if (priv->clk)
  113. clk_put(priv->clk);
  114. if (priv->mmio)
  115. iounmap(priv->mmio);
  116. flush_workqueue(priv->wq);
  117. destroy_workqueue(priv->wq);
  118. dev->dev_private = NULL;
  119. pm_runtime_disable(dev->dev);
  120. list_for_each_entry_safe(mod, cur, &module_list, list) {
  121. DBG("destroying module: %s", mod->name);
  122. mod->funcs->destroy(mod);
  123. }
  124. kfree(priv);
  125. return 0;
  126. }
  127. static int tilcdc_load(struct drm_device *dev, unsigned long flags)
  128. {
  129. struct platform_device *pdev = dev->platformdev;
  130. struct device_node *node = pdev->dev.of_node;
  131. struct tilcdc_drm_private *priv;
  132. struct tilcdc_module *mod;
  133. struct resource *res;
  134. u32 bpp = 0;
  135. int ret;
  136. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  137. if (!priv) {
  138. dev_err(dev->dev, "failed to allocate private data\n");
  139. return -ENOMEM;
  140. }
  141. dev->dev_private = priv;
  142. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  143. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  144. if (!res) {
  145. dev_err(dev->dev, "failed to get memory resource\n");
  146. ret = -EINVAL;
  147. goto fail;
  148. }
  149. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  150. if (!priv->mmio) {
  151. dev_err(dev->dev, "failed to ioremap\n");
  152. ret = -ENOMEM;
  153. goto fail;
  154. }
  155. priv->clk = clk_get(dev->dev, "fck");
  156. if (IS_ERR(priv->clk)) {
  157. dev_err(dev->dev, "failed to get functional clock\n");
  158. ret = -ENODEV;
  159. goto fail;
  160. }
  161. priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck");
  162. if (IS_ERR(priv->clk)) {
  163. dev_err(dev->dev, "failed to get display clock\n");
  164. ret = -ENODEV;
  165. goto fail;
  166. }
  167. #ifdef CONFIG_CPU_FREQ
  168. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  169. priv->freq_transition.notifier_call = cpufreq_transition;
  170. ret = cpufreq_register_notifier(&priv->freq_transition,
  171. CPUFREQ_TRANSITION_NOTIFIER);
  172. if (ret) {
  173. dev_err(dev->dev, "failed to register cpufreq notifier\n");
  174. goto fail;
  175. }
  176. #endif
  177. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  178. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  179. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  180. if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
  181. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
  182. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  183. if (of_property_read_u32(node, "ti,max-pixelclock",
  184. &priv->max_pixelclock))
  185. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  186. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  187. pm_runtime_enable(dev->dev);
  188. /* Determine LCD IP Version */
  189. pm_runtime_get_sync(dev->dev);
  190. switch (tilcdc_read(dev, LCDC_PID_REG)) {
  191. case 0x4c100102:
  192. priv->rev = 1;
  193. break;
  194. case 0x4f200800:
  195. case 0x4f201000:
  196. priv->rev = 2;
  197. break;
  198. default:
  199. dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
  200. "defaulting to LCD revision 1\n",
  201. tilcdc_read(dev, LCDC_PID_REG));
  202. priv->rev = 1;
  203. break;
  204. }
  205. pm_runtime_put_sync(dev->dev);
  206. ret = modeset_init(dev);
  207. if (ret < 0) {
  208. dev_err(dev->dev, "failed to initialize mode setting\n");
  209. goto fail;
  210. }
  211. ret = drm_vblank_init(dev, 1);
  212. if (ret < 0) {
  213. dev_err(dev->dev, "failed to initialize vblank\n");
  214. goto fail;
  215. }
  216. pm_runtime_get_sync(dev->dev);
  217. ret = drm_irq_install(dev);
  218. pm_runtime_put_sync(dev->dev);
  219. if (ret < 0) {
  220. dev_err(dev->dev, "failed to install IRQ handler\n");
  221. goto fail;
  222. }
  223. platform_set_drvdata(pdev, dev);
  224. list_for_each_entry(mod, &module_list, list) {
  225. DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
  226. bpp = mod->preferred_bpp;
  227. if (bpp > 0)
  228. break;
  229. }
  230. priv->fbdev = drm_fbdev_cma_init(dev, bpp,
  231. dev->mode_config.num_crtc,
  232. dev->mode_config.num_connector);
  233. drm_kms_helper_poll_init(dev);
  234. return 0;
  235. fail:
  236. tilcdc_unload(dev);
  237. return ret;
  238. }
  239. static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file)
  240. {
  241. struct tilcdc_drm_private *priv = dev->dev_private;
  242. tilcdc_crtc_cancel_page_flip(priv->crtc, file);
  243. }
  244. static void tilcdc_lastclose(struct drm_device *dev)
  245. {
  246. struct tilcdc_drm_private *priv = dev->dev_private;
  247. drm_fbdev_cma_restore_mode(priv->fbdev);
  248. }
  249. static irqreturn_t tilcdc_irq(DRM_IRQ_ARGS)
  250. {
  251. struct drm_device *dev = arg;
  252. struct tilcdc_drm_private *priv = dev->dev_private;
  253. return tilcdc_crtc_irq(priv->crtc);
  254. }
  255. static void tilcdc_irq_preinstall(struct drm_device *dev)
  256. {
  257. tilcdc_clear_irqstatus(dev, 0xffffffff);
  258. }
  259. static int tilcdc_irq_postinstall(struct drm_device *dev)
  260. {
  261. struct tilcdc_drm_private *priv = dev->dev_private;
  262. /* enable FIFO underflow irq: */
  263. if (priv->rev == 1)
  264. tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
  265. else
  266. tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA);
  267. return 0;
  268. }
  269. static void tilcdc_irq_uninstall(struct drm_device *dev)
  270. {
  271. struct tilcdc_drm_private *priv = dev->dev_private;
  272. /* disable irqs that we might have enabled: */
  273. if (priv->rev == 1) {
  274. tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
  275. LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
  276. tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
  277. } else {
  278. tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
  279. LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
  280. LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
  281. LCDC_FRAME_DONE);
  282. }
  283. }
  284. static void enable_vblank(struct drm_device *dev, bool enable)
  285. {
  286. struct tilcdc_drm_private *priv = dev->dev_private;
  287. u32 reg, mask;
  288. if (priv->rev == 1) {
  289. reg = LCDC_DMA_CTRL_REG;
  290. mask = LCDC_V1_END_OF_FRAME_INT_ENA;
  291. } else {
  292. reg = LCDC_INT_ENABLE_SET_REG;
  293. mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
  294. LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
  295. }
  296. if (enable)
  297. tilcdc_set(dev, reg, mask);
  298. else
  299. tilcdc_clear(dev, reg, mask);
  300. }
  301. static int tilcdc_enable_vblank(struct drm_device *dev, int crtc)
  302. {
  303. enable_vblank(dev, true);
  304. return 0;
  305. }
  306. static void tilcdc_disable_vblank(struct drm_device *dev, int crtc)
  307. {
  308. enable_vblank(dev, false);
  309. }
  310. #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
  311. static const struct {
  312. const char *name;
  313. uint8_t rev;
  314. uint8_t save;
  315. uint32_t reg;
  316. } registers[] = {
  317. #define REG(rev, save, reg) { #reg, rev, save, reg }
  318. /* exists in revision 1: */
  319. REG(1, false, LCDC_PID_REG),
  320. REG(1, true, LCDC_CTRL_REG),
  321. REG(1, false, LCDC_STAT_REG),
  322. REG(1, true, LCDC_RASTER_CTRL_REG),
  323. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  324. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  325. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  326. REG(1, true, LCDC_DMA_CTRL_REG),
  327. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  328. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  329. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  330. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  331. /* new in revision 2: */
  332. REG(2, false, LCDC_RAW_STAT_REG),
  333. REG(2, false, LCDC_MASKED_STAT_REG),
  334. REG(2, false, LCDC_INT_ENABLE_SET_REG),
  335. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  336. REG(2, false, LCDC_END_OF_INT_IND_REG),
  337. REG(2, true, LCDC_CLK_ENABLE_REG),
  338. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  339. #undef REG
  340. };
  341. #endif
  342. #ifdef CONFIG_DEBUG_FS
  343. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  344. {
  345. struct drm_info_node *node = (struct drm_info_node *) m->private;
  346. struct drm_device *dev = node->minor->dev;
  347. struct tilcdc_drm_private *priv = dev->dev_private;
  348. unsigned i;
  349. pm_runtime_get_sync(dev->dev);
  350. seq_printf(m, "revision: %d\n", priv->rev);
  351. for (i = 0; i < ARRAY_SIZE(registers); i++)
  352. if (priv->rev >= registers[i].rev)
  353. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  354. tilcdc_read(dev, registers[i].reg));
  355. pm_runtime_put_sync(dev->dev);
  356. return 0;
  357. }
  358. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  359. {
  360. struct drm_info_node *node = (struct drm_info_node *) m->private;
  361. struct drm_device *dev = node->minor->dev;
  362. return drm_mm_dump_table(m, dev->mm_private);
  363. }
  364. static struct drm_info_list tilcdc_debugfs_list[] = {
  365. { "regs", tilcdc_regs_show, 0 },
  366. { "mm", tilcdc_mm_show, 0 },
  367. { "fb", drm_fb_cma_debugfs_show, 0 },
  368. };
  369. static int tilcdc_debugfs_init(struct drm_minor *minor)
  370. {
  371. struct drm_device *dev = minor->dev;
  372. struct tilcdc_module *mod;
  373. int ret;
  374. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  375. ARRAY_SIZE(tilcdc_debugfs_list),
  376. minor->debugfs_root, minor);
  377. list_for_each_entry(mod, &module_list, list)
  378. if (mod->funcs->debugfs_init)
  379. mod->funcs->debugfs_init(mod, minor);
  380. if (ret) {
  381. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  382. return ret;
  383. }
  384. return ret;
  385. }
  386. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  387. {
  388. struct tilcdc_module *mod;
  389. drm_debugfs_remove_files(tilcdc_debugfs_list,
  390. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  391. list_for_each_entry(mod, &module_list, list)
  392. if (mod->funcs->debugfs_cleanup)
  393. mod->funcs->debugfs_cleanup(mod, minor);
  394. }
  395. #endif
  396. static const struct file_operations fops = {
  397. .owner = THIS_MODULE,
  398. .open = drm_open,
  399. .release = drm_release,
  400. .unlocked_ioctl = drm_ioctl,
  401. #ifdef CONFIG_COMPAT
  402. .compat_ioctl = drm_compat_ioctl,
  403. #endif
  404. .poll = drm_poll,
  405. .read = drm_read,
  406. .llseek = no_llseek,
  407. .mmap = drm_gem_cma_mmap,
  408. };
  409. static struct drm_driver tilcdc_driver = {
  410. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  411. .load = tilcdc_load,
  412. .unload = tilcdc_unload,
  413. .preclose = tilcdc_preclose,
  414. .lastclose = tilcdc_lastclose,
  415. .irq_handler = tilcdc_irq,
  416. .irq_preinstall = tilcdc_irq_preinstall,
  417. .irq_postinstall = tilcdc_irq_postinstall,
  418. .irq_uninstall = tilcdc_irq_uninstall,
  419. .get_vblank_counter = drm_vblank_count,
  420. .enable_vblank = tilcdc_enable_vblank,
  421. .disable_vblank = tilcdc_disable_vblank,
  422. .gem_free_object = drm_gem_cma_free_object,
  423. .gem_vm_ops = &drm_gem_cma_vm_ops,
  424. .dumb_create = drm_gem_cma_dumb_create,
  425. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  426. .dumb_destroy = drm_gem_dumb_destroy,
  427. #ifdef CONFIG_DEBUG_FS
  428. .debugfs_init = tilcdc_debugfs_init,
  429. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  430. #endif
  431. .fops = &fops,
  432. .name = "tilcdc",
  433. .desc = "TI LCD Controller DRM",
  434. .date = "20121205",
  435. .major = 1,
  436. .minor = 0,
  437. };
  438. /*
  439. * Power management:
  440. */
  441. #ifdef CONFIG_PM_SLEEP
  442. static int tilcdc_pm_suspend(struct device *dev)
  443. {
  444. struct drm_device *ddev = dev_get_drvdata(dev);
  445. struct tilcdc_drm_private *priv = ddev->dev_private;
  446. unsigned i, n = 0;
  447. drm_kms_helper_poll_disable(ddev);
  448. /* Save register state: */
  449. for (i = 0; i < ARRAY_SIZE(registers); i++)
  450. if (registers[i].save && (priv->rev >= registers[i].rev))
  451. priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
  452. return 0;
  453. }
  454. static int tilcdc_pm_resume(struct device *dev)
  455. {
  456. struct drm_device *ddev = dev_get_drvdata(dev);
  457. struct tilcdc_drm_private *priv = ddev->dev_private;
  458. unsigned i, n = 0;
  459. /* Restore register state: */
  460. for (i = 0; i < ARRAY_SIZE(registers); i++)
  461. if (registers[i].save && (priv->rev >= registers[i].rev))
  462. tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]);
  463. drm_kms_helper_poll_enable(ddev);
  464. return 0;
  465. }
  466. #endif
  467. static const struct dev_pm_ops tilcdc_pm_ops = {
  468. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  469. };
  470. /*
  471. * Platform driver:
  472. */
  473. static int tilcdc_pdev_probe(struct platform_device *pdev)
  474. {
  475. /* bail out early if no DT data: */
  476. if (!pdev->dev.of_node) {
  477. dev_err(&pdev->dev, "device-tree data is missing\n");
  478. return -ENXIO;
  479. }
  480. /* defer probing if slave is in deferred probing */
  481. if (slave_probing == true)
  482. return -EPROBE_DEFER;
  483. return drm_platform_init(&tilcdc_driver, pdev);
  484. }
  485. static int tilcdc_pdev_remove(struct platform_device *pdev)
  486. {
  487. drm_platform_exit(&tilcdc_driver, pdev);
  488. return 0;
  489. }
  490. static struct of_device_id tilcdc_of_match[] = {
  491. { .compatible = "ti,am33xx-tilcdc", },
  492. { },
  493. };
  494. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  495. static struct platform_driver tilcdc_platform_driver = {
  496. .probe = tilcdc_pdev_probe,
  497. .remove = tilcdc_pdev_remove,
  498. .driver = {
  499. .owner = THIS_MODULE,
  500. .name = "tilcdc",
  501. .pm = &tilcdc_pm_ops,
  502. .of_match_table = tilcdc_of_match,
  503. },
  504. };
  505. static int __init tilcdc_drm_init(void)
  506. {
  507. DBG("init");
  508. tilcdc_tfp410_init();
  509. tilcdc_slave_init();
  510. tilcdc_panel_init();
  511. return platform_driver_register(&tilcdc_platform_driver);
  512. }
  513. static void __exit tilcdc_drm_fini(void)
  514. {
  515. DBG("fini");
  516. tilcdc_tfp410_fini();
  517. tilcdc_slave_fini();
  518. tilcdc_panel_fini();
  519. platform_driver_unregister(&tilcdc_platform_driver);
  520. }
  521. late_initcall(tilcdc_drm_init);
  522. module_exit(tilcdc_drm_fini);
  523. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  524. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  525. MODULE_LICENSE("GPL");