tlb.c 4.6 KB

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  1. /*
  2. * TLB support routines.
  3. *
  4. * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
  5. * David Mosberger-Tang <davidm@hpl.hp.com>
  6. *
  7. * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
  8. * Modified RID allocation for SMP
  9. * Goutham Rao <goutham.rao@intel.com>
  10. * IPI based ptc implementation and A-step IPI implementation.
  11. */
  12. #include <linux/config.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/kernel.h>
  16. #include <linux/sched.h>
  17. #include <linux/smp.h>
  18. #include <linux/mm.h>
  19. #include <asm/delay.h>
  20. #include <asm/mmu_context.h>
  21. #include <asm/pgalloc.h>
  22. #include <asm/pal.h>
  23. #include <asm/tlbflush.h>
  24. static struct {
  25. unsigned long mask; /* mask of supported purge page-sizes */
  26. unsigned long max_bits; /* log2() of largest supported purge page-size */
  27. } purge;
  28. struct ia64_ctx ia64_ctx = {
  29. .lock = SPIN_LOCK_UNLOCKED,
  30. .next = 1,
  31. .limit = (1 << 15) - 1, /* start out with the safe (architected) limit */
  32. .max_ctx = ~0U
  33. };
  34. DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
  35. /*
  36. * Acquire the ia64_ctx.lock before calling this function!
  37. */
  38. void
  39. wrap_mmu_context (struct mm_struct *mm)
  40. {
  41. unsigned long tsk_context, max_ctx = ia64_ctx.max_ctx;
  42. struct task_struct *tsk;
  43. int i;
  44. if (ia64_ctx.next > max_ctx)
  45. ia64_ctx.next = 300; /* skip daemons */
  46. ia64_ctx.limit = max_ctx + 1;
  47. /*
  48. * Scan all the task's mm->context and set proper safe range
  49. */
  50. read_lock(&tasklist_lock);
  51. repeat:
  52. for_each_process(tsk) {
  53. if (!tsk->mm)
  54. continue;
  55. tsk_context = tsk->mm->context;
  56. if (tsk_context == ia64_ctx.next) {
  57. if (++ia64_ctx.next >= ia64_ctx.limit) {
  58. /* empty range: reset the range limit and start over */
  59. if (ia64_ctx.next > max_ctx)
  60. ia64_ctx.next = 300;
  61. ia64_ctx.limit = max_ctx + 1;
  62. goto repeat;
  63. }
  64. }
  65. if ((tsk_context > ia64_ctx.next) && (tsk_context < ia64_ctx.limit))
  66. ia64_ctx.limit = tsk_context;
  67. }
  68. read_unlock(&tasklist_lock);
  69. /* can't call flush_tlb_all() here because of race condition with O(1) scheduler [EF] */
  70. {
  71. int cpu = get_cpu(); /* prevent preemption/migration */
  72. for_each_online_cpu(i) {
  73. if (i != cpu)
  74. per_cpu(ia64_need_tlb_flush, i) = 1;
  75. }
  76. put_cpu();
  77. }
  78. local_flush_tlb_all();
  79. }
  80. void
  81. ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start, unsigned long end, unsigned long nbits)
  82. {
  83. static DEFINE_SPINLOCK(ptcg_lock);
  84. if (mm != current->active_mm) {
  85. flush_tlb_all();
  86. return;
  87. }
  88. /* HW requires global serialization of ptc.ga. */
  89. spin_lock(&ptcg_lock);
  90. {
  91. do {
  92. /*
  93. * Flush ALAT entries also.
  94. */
  95. ia64_ptcga(start, (nbits<<2));
  96. ia64_srlz_i();
  97. start += (1UL << nbits);
  98. } while (start < end);
  99. }
  100. spin_unlock(&ptcg_lock);
  101. }
  102. void
  103. local_flush_tlb_all (void)
  104. {
  105. unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
  106. addr = local_cpu_data->ptce_base;
  107. count0 = local_cpu_data->ptce_count[0];
  108. count1 = local_cpu_data->ptce_count[1];
  109. stride0 = local_cpu_data->ptce_stride[0];
  110. stride1 = local_cpu_data->ptce_stride[1];
  111. local_irq_save(flags);
  112. for (i = 0; i < count0; ++i) {
  113. for (j = 0; j < count1; ++j) {
  114. ia64_ptce(addr);
  115. addr += stride1;
  116. }
  117. addr += stride0;
  118. }
  119. local_irq_restore(flags);
  120. ia64_srlz_i(); /* srlz.i implies srlz.d */
  121. }
  122. void
  123. flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end)
  124. {
  125. struct mm_struct *mm = vma->vm_mm;
  126. unsigned long size = end - start;
  127. unsigned long nbits;
  128. #ifndef CONFIG_SMP
  129. if (mm != current->active_mm) {
  130. mm->context = 0;
  131. return;
  132. }
  133. #endif
  134. nbits = ia64_fls(size + 0xfff);
  135. while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits))
  136. ++nbits;
  137. if (nbits > purge.max_bits)
  138. nbits = purge.max_bits;
  139. start &= ~((1UL << nbits) - 1);
  140. # ifdef CONFIG_SMP
  141. platform_global_tlb_purge(mm, start, end, nbits);
  142. # else
  143. do {
  144. ia64_ptcl(start, (nbits<<2));
  145. start += (1UL << nbits);
  146. } while (start < end);
  147. # endif
  148. ia64_srlz_i(); /* srlz.i implies srlz.d */
  149. }
  150. EXPORT_SYMBOL(flush_tlb_range);
  151. void __devinit
  152. ia64_tlb_init (void)
  153. {
  154. ia64_ptce_info_t ptce_info;
  155. unsigned long tr_pgbits;
  156. long status;
  157. if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
  158. printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;"
  159. "defaulting to architected purge page-sizes.\n", status);
  160. purge.mask = 0x115557000UL;
  161. }
  162. purge.max_bits = ia64_fls(purge.mask);
  163. ia64_get_ptce(&ptce_info);
  164. local_cpu_data->ptce_base = ptce_info.base;
  165. local_cpu_data->ptce_count[0] = ptce_info.count[0];
  166. local_cpu_data->ptce_count[1] = ptce_info.count[1];
  167. local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
  168. local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
  169. local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
  170. }