advansys.c 497 KB

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  1. #define DRV_NAME "advansys"
  2. #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
  3. /*
  4. * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  5. *
  6. * Copyright (c) 1995-2000 Advanced System Products, Inc.
  7. * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
  8. * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
  9. * All Rights Reserved.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. */
  16. /*
  17. * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
  18. * changed its name to ConnectCom Solutions, Inc.
  19. * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
  20. */
  21. #include <linux/module.h>
  22. #include <linux/string.h>
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/ioport.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/delay.h>
  28. #include <linux/slab.h>
  29. #include <linux/mm.h>
  30. #include <linux/proc_fs.h>
  31. #include <linux/init.h>
  32. #include <linux/blkdev.h>
  33. #include <linux/isa.h>
  34. #include <linux/eisa.h>
  35. #include <linux/pci.h>
  36. #include <linux/spinlock.h>
  37. #include <linux/dma-mapping.h>
  38. #include <asm/io.h>
  39. #include <asm/system.h>
  40. #include <asm/dma.h>
  41. #include <scsi/scsi_cmnd.h>
  42. #include <scsi/scsi_device.h>
  43. #include <scsi/scsi_tcq.h>
  44. #include <scsi/scsi.h>
  45. #include <scsi/scsi_host.h>
  46. /* FIXME:
  47. *
  48. * 1. Although all of the necessary command mapping places have the
  49. * appropriate dma_map.. APIs, the driver still processes its internal
  50. * queue using bus_to_virt() and virt_to_bus() which are illegal under
  51. * the API. The entire queue processing structure will need to be
  52. * altered to fix this.
  53. * 2. Need to add memory mapping workaround. Test the memory mapping.
  54. * If it doesn't work revert to I/O port access. Can a test be done
  55. * safely?
  56. * 3. Handle an interrupt not working. Keep an interrupt counter in
  57. * the interrupt handler. In the timeout function if the interrupt
  58. * has not occurred then print a message and run in polled mode.
  59. * 4. Need to add support for target mode commands, cf. CAM XPT.
  60. * 5. check DMA mapping functions for failure
  61. * 6. Use scsi_transport_spi
  62. * 7. advansys_info is not safe against multiple simultaneous callers
  63. * 8. Kill boardp->id
  64. * 9. Add module_param to override ISA/VLB ioport array
  65. */
  66. #warning this driver is still not properly converted to the DMA API
  67. /* Enable driver /proc statistics. */
  68. #define ADVANSYS_STATS
  69. /* Enable driver tracing. */
  70. /* #define ADVANSYS_DEBUG */
  71. /*
  72. * Portable Data Types
  73. *
  74. * Any instance where a 32-bit long or pointer type is assumed
  75. * for precision or HW defined structures, the following define
  76. * types must be used. In Linux the char, short, and int types
  77. * are all consistent at 8, 16, and 32 bits respectively. Pointers
  78. * and long types are 64 bits on Alpha and UltraSPARC.
  79. */
  80. #define ASC_PADDR __u32 /* Physical/Bus address data type. */
  81. #define ASC_VADDR __u32 /* Virtual address data type. */
  82. #define ASC_DCNT __u32 /* Unsigned Data count type. */
  83. #define ASC_SDCNT __s32 /* Signed Data count type. */
  84. /*
  85. * These macros are used to convert a virtual address to a
  86. * 32-bit value. This currently can be used on Linux Alpha
  87. * which uses 64-bit virtual address but a 32-bit bus address.
  88. * This is likely to break in the future, but doing this now
  89. * will give us time to change the HW and FW to handle 64-bit
  90. * addresses.
  91. */
  92. #define ASC_VADDR_TO_U32 virt_to_bus
  93. #define ASC_U32_TO_VADDR bus_to_virt
  94. typedef unsigned char uchar;
  95. #ifndef TRUE
  96. #define TRUE (1)
  97. #endif
  98. #ifndef FALSE
  99. #define FALSE (0)
  100. #endif
  101. #define ERR (-1)
  102. #define UW_ERR (uint)(0xFFFF)
  103. #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
  104. #define PCI_VENDOR_ID_ASP 0x10cd
  105. #define PCI_DEVICE_ID_ASP_1200A 0x1100
  106. #define PCI_DEVICE_ID_ASP_ABP940 0x1200
  107. #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
  108. #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
  109. #define PCI_DEVICE_ID_38C0800_REV1 0x2500
  110. #define PCI_DEVICE_ID_38C1600_REV1 0x2700
  111. /*
  112. * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
  113. * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
  114. * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
  115. * SRB structure.
  116. */
  117. #define CC_VERY_LONG_SG_LIST 0
  118. #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
  119. #define PortAddr unsigned short /* port address size */
  120. #define inp(port) inb(port)
  121. #define outp(port, byte) outb((byte), (port))
  122. #define inpw(port) inw(port)
  123. #define outpw(port, word) outw((word), (port))
  124. #define ASC_MAX_SG_QUEUE 7
  125. #define ASC_MAX_SG_LIST 255
  126. #define ASC_CS_TYPE unsigned short
  127. #define ASC_IS_ISA (0x0001)
  128. #define ASC_IS_ISAPNP (0x0081)
  129. #define ASC_IS_EISA (0x0002)
  130. #define ASC_IS_PCI (0x0004)
  131. #define ASC_IS_PCI_ULTRA (0x0104)
  132. #define ASC_IS_PCMCIA (0x0008)
  133. #define ASC_IS_MCA (0x0020)
  134. #define ASC_IS_VL (0x0040)
  135. #define ASC_IS_WIDESCSI_16 (0x0100)
  136. #define ASC_IS_WIDESCSI_32 (0x0200)
  137. #define ASC_IS_BIG_ENDIAN (0x8000)
  138. #define ASC_CHIP_MIN_VER_VL (0x01)
  139. #define ASC_CHIP_MAX_VER_VL (0x07)
  140. #define ASC_CHIP_MIN_VER_PCI (0x09)
  141. #define ASC_CHIP_MAX_VER_PCI (0x0F)
  142. #define ASC_CHIP_VER_PCI_BIT (0x08)
  143. #define ASC_CHIP_MIN_VER_ISA (0x11)
  144. #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
  145. #define ASC_CHIP_MAX_VER_ISA (0x27)
  146. #define ASC_CHIP_VER_ISA_BIT (0x30)
  147. #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
  148. #define ASC_CHIP_VER_ASYN_BUG (0x21)
  149. #define ASC_CHIP_VER_PCI 0x08
  150. #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
  151. #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
  152. #define ASC_CHIP_MIN_VER_EISA (0x41)
  153. #define ASC_CHIP_MAX_VER_EISA (0x47)
  154. #define ASC_CHIP_VER_EISA_BIT (0x40)
  155. #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
  156. #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
  157. #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
  158. #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
  159. #define ASC_SCSI_ID_BITS 3
  160. #define ASC_SCSI_TIX_TYPE uchar
  161. #define ASC_ALL_DEVICE_BIT_SET 0xFF
  162. #define ASC_SCSI_BIT_ID_TYPE uchar
  163. #define ASC_MAX_TID 7
  164. #define ASC_MAX_LUN 7
  165. #define ASC_SCSI_WIDTH_BIT_SET 0xFF
  166. #define ASC_MAX_SENSE_LEN 32
  167. #define ASC_MIN_SENSE_LEN 14
  168. #define ASC_SCSI_RESET_HOLD_TIME_US 60
  169. /*
  170. * Narrow boards only support 12-byte commands, while wide boards
  171. * extend to 16-byte commands.
  172. */
  173. #define ASC_MAX_CDB_LEN 12
  174. #define ADV_MAX_CDB_LEN 16
  175. #define MS_SDTR_LEN 0x03
  176. #define MS_WDTR_LEN 0x02
  177. #define ASC_SG_LIST_PER_Q 7
  178. #define QS_FREE 0x00
  179. #define QS_READY 0x01
  180. #define QS_DISC1 0x02
  181. #define QS_DISC2 0x04
  182. #define QS_BUSY 0x08
  183. #define QS_ABORTED 0x40
  184. #define QS_DONE 0x80
  185. #define QC_NO_CALLBACK 0x01
  186. #define QC_SG_SWAP_QUEUE 0x02
  187. #define QC_SG_HEAD 0x04
  188. #define QC_DATA_IN 0x08
  189. #define QC_DATA_OUT 0x10
  190. #define QC_URGENT 0x20
  191. #define QC_MSG_OUT 0x40
  192. #define QC_REQ_SENSE 0x80
  193. #define QCSG_SG_XFER_LIST 0x02
  194. #define QCSG_SG_XFER_MORE 0x04
  195. #define QCSG_SG_XFER_END 0x08
  196. #define QD_IN_PROGRESS 0x00
  197. #define QD_NO_ERROR 0x01
  198. #define QD_ABORTED_BY_HOST 0x02
  199. #define QD_WITH_ERROR 0x04
  200. #define QD_INVALID_REQUEST 0x80
  201. #define QD_INVALID_HOST_NUM 0x81
  202. #define QD_INVALID_DEVICE 0x82
  203. #define QD_ERR_INTERNAL 0xFF
  204. #define QHSTA_NO_ERROR 0x00
  205. #define QHSTA_M_SEL_TIMEOUT 0x11
  206. #define QHSTA_M_DATA_OVER_RUN 0x12
  207. #define QHSTA_M_DATA_UNDER_RUN 0x12
  208. #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
  209. #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
  210. #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
  211. #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
  212. #define QHSTA_D_HOST_ABORT_FAILED 0x23
  213. #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
  214. #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
  215. #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
  216. #define QHSTA_M_WTM_TIMEOUT 0x41
  217. #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
  218. #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
  219. #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
  220. #define QHSTA_M_TARGET_STATUS_BUSY 0x45
  221. #define QHSTA_M_BAD_TAG_CODE 0x46
  222. #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
  223. #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
  224. #define QHSTA_D_LRAM_CMP_ERROR 0x81
  225. #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
  226. #define ASC_FLAG_SCSIQ_REQ 0x01
  227. #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
  228. #define ASC_FLAG_BIOS_ASYNC_IO 0x04
  229. #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
  230. #define ASC_FLAG_WIN16 0x10
  231. #define ASC_FLAG_WIN32 0x20
  232. #define ASC_FLAG_ISA_OVER_16MB 0x40
  233. #define ASC_FLAG_DOS_VM_CALLBACK 0x80
  234. #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
  235. #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
  236. #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
  237. #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
  238. #define ASC_SCSIQ_CPY_BEG 4
  239. #define ASC_SCSIQ_SGHD_CPY_BEG 2
  240. #define ASC_SCSIQ_B_FWD 0
  241. #define ASC_SCSIQ_B_BWD 1
  242. #define ASC_SCSIQ_B_STATUS 2
  243. #define ASC_SCSIQ_B_QNO 3
  244. #define ASC_SCSIQ_B_CNTL 4
  245. #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
  246. #define ASC_SCSIQ_D_DATA_ADDR 8
  247. #define ASC_SCSIQ_D_DATA_CNT 12
  248. #define ASC_SCSIQ_B_SENSE_LEN 20
  249. #define ASC_SCSIQ_DONE_INFO_BEG 22
  250. #define ASC_SCSIQ_D_SRBPTR 22
  251. #define ASC_SCSIQ_B_TARGET_IX 26
  252. #define ASC_SCSIQ_B_CDB_LEN 28
  253. #define ASC_SCSIQ_B_TAG_CODE 29
  254. #define ASC_SCSIQ_W_VM_ID 30
  255. #define ASC_SCSIQ_DONE_STATUS 32
  256. #define ASC_SCSIQ_HOST_STATUS 33
  257. #define ASC_SCSIQ_SCSI_STATUS 34
  258. #define ASC_SCSIQ_CDB_BEG 36
  259. #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
  260. #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
  261. #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
  262. #define ASC_SCSIQ_B_SG_WK_QP 49
  263. #define ASC_SCSIQ_B_SG_WK_IX 50
  264. #define ASC_SCSIQ_W_ALT_DC1 52
  265. #define ASC_SCSIQ_B_LIST_CNT 6
  266. #define ASC_SCSIQ_B_CUR_LIST_CNT 7
  267. #define ASC_SGQ_B_SG_CNTL 4
  268. #define ASC_SGQ_B_SG_HEAD_QP 5
  269. #define ASC_SGQ_B_SG_LIST_CNT 6
  270. #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
  271. #define ASC_SGQ_LIST_BEG 8
  272. #define ASC_DEF_SCSI1_QNG 4
  273. #define ASC_MAX_SCSI1_QNG 4
  274. #define ASC_DEF_SCSI2_QNG 16
  275. #define ASC_MAX_SCSI2_QNG 32
  276. #define ASC_TAG_CODE_MASK 0x23
  277. #define ASC_STOP_REQ_RISC_STOP 0x01
  278. #define ASC_STOP_ACK_RISC_STOP 0x03
  279. #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
  280. #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
  281. #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
  282. #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
  283. #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
  284. #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
  285. #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
  286. #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
  287. #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
  288. #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
  289. typedef struct asc_scsiq_1 {
  290. uchar status;
  291. uchar q_no;
  292. uchar cntl;
  293. uchar sg_queue_cnt;
  294. uchar target_id;
  295. uchar target_lun;
  296. ASC_PADDR data_addr;
  297. ASC_DCNT data_cnt;
  298. ASC_PADDR sense_addr;
  299. uchar sense_len;
  300. uchar extra_bytes;
  301. } ASC_SCSIQ_1;
  302. typedef struct asc_scsiq_2 {
  303. ASC_VADDR srb_ptr;
  304. uchar target_ix;
  305. uchar flag;
  306. uchar cdb_len;
  307. uchar tag_code;
  308. ushort vm_id;
  309. } ASC_SCSIQ_2;
  310. typedef struct asc_scsiq_3 {
  311. uchar done_stat;
  312. uchar host_stat;
  313. uchar scsi_stat;
  314. uchar scsi_msg;
  315. } ASC_SCSIQ_3;
  316. typedef struct asc_scsiq_4 {
  317. uchar cdb[ASC_MAX_CDB_LEN];
  318. uchar y_first_sg_list_qp;
  319. uchar y_working_sg_qp;
  320. uchar y_working_sg_ix;
  321. uchar y_res;
  322. ushort x_req_count;
  323. ushort x_reconnect_rtn;
  324. ASC_PADDR x_saved_data_addr;
  325. ASC_DCNT x_saved_data_cnt;
  326. } ASC_SCSIQ_4;
  327. typedef struct asc_q_done_info {
  328. ASC_SCSIQ_2 d2;
  329. ASC_SCSIQ_3 d3;
  330. uchar q_status;
  331. uchar q_no;
  332. uchar cntl;
  333. uchar sense_len;
  334. uchar extra_bytes;
  335. uchar res;
  336. ASC_DCNT remain_bytes;
  337. } ASC_QDONE_INFO;
  338. typedef struct asc_sg_list {
  339. ASC_PADDR addr;
  340. ASC_DCNT bytes;
  341. } ASC_SG_LIST;
  342. typedef struct asc_sg_head {
  343. ushort entry_cnt;
  344. ushort queue_cnt;
  345. ushort entry_to_copy;
  346. ushort res;
  347. ASC_SG_LIST sg_list[0];
  348. } ASC_SG_HEAD;
  349. typedef struct asc_scsi_q {
  350. ASC_SCSIQ_1 q1;
  351. ASC_SCSIQ_2 q2;
  352. uchar *cdbptr;
  353. ASC_SG_HEAD *sg_head;
  354. ushort remain_sg_entry_cnt;
  355. ushort next_sg_index;
  356. } ASC_SCSI_Q;
  357. typedef struct asc_scsi_req_q {
  358. ASC_SCSIQ_1 r1;
  359. ASC_SCSIQ_2 r2;
  360. uchar *cdbptr;
  361. ASC_SG_HEAD *sg_head;
  362. uchar *sense_ptr;
  363. ASC_SCSIQ_3 r3;
  364. uchar cdb[ASC_MAX_CDB_LEN];
  365. uchar sense[ASC_MIN_SENSE_LEN];
  366. } ASC_SCSI_REQ_Q;
  367. typedef struct asc_scsi_bios_req_q {
  368. ASC_SCSIQ_1 r1;
  369. ASC_SCSIQ_2 r2;
  370. uchar *cdbptr;
  371. ASC_SG_HEAD *sg_head;
  372. uchar *sense_ptr;
  373. ASC_SCSIQ_3 r3;
  374. uchar cdb[ASC_MAX_CDB_LEN];
  375. uchar sense[ASC_MIN_SENSE_LEN];
  376. } ASC_SCSI_BIOS_REQ_Q;
  377. typedef struct asc_risc_q {
  378. uchar fwd;
  379. uchar bwd;
  380. ASC_SCSIQ_1 i1;
  381. ASC_SCSIQ_2 i2;
  382. ASC_SCSIQ_3 i3;
  383. ASC_SCSIQ_4 i4;
  384. } ASC_RISC_Q;
  385. typedef struct asc_sg_list_q {
  386. uchar seq_no;
  387. uchar q_no;
  388. uchar cntl;
  389. uchar sg_head_qp;
  390. uchar sg_list_cnt;
  391. uchar sg_cur_list_cnt;
  392. } ASC_SG_LIST_Q;
  393. typedef struct asc_risc_sg_list_q {
  394. uchar fwd;
  395. uchar bwd;
  396. ASC_SG_LIST_Q sg;
  397. ASC_SG_LIST sg_list[7];
  398. } ASC_RISC_SG_LIST_Q;
  399. #define ASCQ_ERR_Q_STATUS 0x0D
  400. #define ASCQ_ERR_CUR_QNG 0x17
  401. #define ASCQ_ERR_SG_Q_LINKS 0x18
  402. #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
  403. #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
  404. #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
  405. /*
  406. * Warning code values are set in ASC_DVC_VAR 'warn_code'.
  407. */
  408. #define ASC_WARN_NO_ERROR 0x0000
  409. #define ASC_WARN_IO_PORT_ROTATE 0x0001
  410. #define ASC_WARN_EEPROM_CHKSUM 0x0002
  411. #define ASC_WARN_IRQ_MODIFIED 0x0004
  412. #define ASC_WARN_AUTO_CONFIG 0x0008
  413. #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
  414. #define ASC_WARN_EEPROM_RECOVER 0x0020
  415. #define ASC_WARN_CFG_MSW_RECOVER 0x0040
  416. /*
  417. * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
  418. */
  419. #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
  420. #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
  421. #define ASC_IERR_SET_PC_ADDR 0x0004
  422. #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
  423. #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
  424. #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
  425. #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
  426. #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
  427. #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
  428. #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
  429. #define ASC_IERR_NO_BUS_TYPE 0x0400
  430. #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
  431. #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
  432. #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
  433. #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
  434. #define ASC_MIN_TAG_Q_PER_DVC (0x04)
  435. #define ASC_MIN_FREE_Q (0x02)
  436. #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
  437. #define ASC_MAX_TOTAL_QNG 240
  438. #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
  439. #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
  440. #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
  441. #define ASC_MAX_INRAM_TAG_QNG 16
  442. #define ASC_IOADR_GAP 0x10
  443. #define ASC_MAX_SYN_XFER_NO 16
  444. #define ASC_SYN_MAX_OFFSET 0x0F
  445. #define ASC_DEF_SDTR_OFFSET 0x0F
  446. #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
  447. #define SYN_XFER_NS_0 25
  448. #define SYN_XFER_NS_1 30
  449. #define SYN_XFER_NS_2 35
  450. #define SYN_XFER_NS_3 40
  451. #define SYN_XFER_NS_4 50
  452. #define SYN_XFER_NS_5 60
  453. #define SYN_XFER_NS_6 70
  454. #define SYN_XFER_NS_7 85
  455. #define SYN_ULTRA_XFER_NS_0 12
  456. #define SYN_ULTRA_XFER_NS_1 19
  457. #define SYN_ULTRA_XFER_NS_2 25
  458. #define SYN_ULTRA_XFER_NS_3 32
  459. #define SYN_ULTRA_XFER_NS_4 38
  460. #define SYN_ULTRA_XFER_NS_5 44
  461. #define SYN_ULTRA_XFER_NS_6 50
  462. #define SYN_ULTRA_XFER_NS_7 57
  463. #define SYN_ULTRA_XFER_NS_8 63
  464. #define SYN_ULTRA_XFER_NS_9 69
  465. #define SYN_ULTRA_XFER_NS_10 75
  466. #define SYN_ULTRA_XFER_NS_11 82
  467. #define SYN_ULTRA_XFER_NS_12 88
  468. #define SYN_ULTRA_XFER_NS_13 94
  469. #define SYN_ULTRA_XFER_NS_14 100
  470. #define SYN_ULTRA_XFER_NS_15 107
  471. typedef struct ext_msg {
  472. uchar msg_type;
  473. uchar msg_len;
  474. uchar msg_req;
  475. union {
  476. struct {
  477. uchar sdtr_xfer_period;
  478. uchar sdtr_req_ack_offset;
  479. } sdtr;
  480. struct {
  481. uchar wdtr_width;
  482. } wdtr;
  483. struct {
  484. uchar mdp_b3;
  485. uchar mdp_b2;
  486. uchar mdp_b1;
  487. uchar mdp_b0;
  488. } mdp;
  489. } u_ext_msg;
  490. uchar res;
  491. } EXT_MSG;
  492. #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
  493. #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
  494. #define wdtr_width u_ext_msg.wdtr.wdtr_width
  495. #define mdp_b3 u_ext_msg.mdp_b3
  496. #define mdp_b2 u_ext_msg.mdp_b2
  497. #define mdp_b1 u_ext_msg.mdp_b1
  498. #define mdp_b0 u_ext_msg.mdp_b0
  499. typedef struct asc_dvc_cfg {
  500. ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
  501. ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
  502. ASC_SCSI_BIT_ID_TYPE disc_enable;
  503. ASC_SCSI_BIT_ID_TYPE sdtr_enable;
  504. uchar chip_scsi_id;
  505. uchar isa_dma_speed;
  506. uchar isa_dma_channel;
  507. uchar chip_version;
  508. ushort mcode_date;
  509. ushort mcode_version;
  510. uchar max_tag_qng[ASC_MAX_TID + 1];
  511. uchar *overrun_buf;
  512. uchar sdtr_period_offset[ASC_MAX_TID + 1];
  513. uchar adapter_info[6];
  514. } ASC_DVC_CFG;
  515. #define ASC_DEF_DVC_CNTL 0xFFFF
  516. #define ASC_DEF_CHIP_SCSI_ID 7
  517. #define ASC_DEF_ISA_DMA_SPEED 4
  518. #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
  519. #define ASC_INIT_STATE_END_GET_CFG 0x0002
  520. #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
  521. #define ASC_INIT_STATE_END_SET_CFG 0x0008
  522. #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
  523. #define ASC_INIT_STATE_END_LOAD_MC 0x0020
  524. #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
  525. #define ASC_INIT_STATE_END_INQUIRY 0x0080
  526. #define ASC_INIT_RESET_SCSI_DONE 0x0100
  527. #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
  528. #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
  529. #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
  530. #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
  531. #define ASC_MIN_TAGGED_CMD 7
  532. #define ASC_MAX_SCSI_RESET_WAIT 30
  533. struct asc_dvc_var; /* Forward Declaration. */
  534. typedef struct asc_dvc_var {
  535. PortAddr iop_base;
  536. ushort err_code;
  537. ushort dvc_cntl;
  538. ushort bug_fix_cntl;
  539. ushort bus_type;
  540. ASC_SCSI_BIT_ID_TYPE init_sdtr;
  541. ASC_SCSI_BIT_ID_TYPE sdtr_done;
  542. ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
  543. ASC_SCSI_BIT_ID_TYPE unit_not_ready;
  544. ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
  545. ASC_SCSI_BIT_ID_TYPE start_motor;
  546. uchar scsi_reset_wait;
  547. uchar chip_no;
  548. char is_in_int;
  549. uchar max_total_qng;
  550. uchar cur_total_qng;
  551. uchar in_critical_cnt;
  552. uchar last_q_shortage;
  553. ushort init_state;
  554. uchar cur_dvc_qng[ASC_MAX_TID + 1];
  555. uchar max_dvc_qng[ASC_MAX_TID + 1];
  556. ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
  557. ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
  558. uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
  559. ASC_DVC_CFG *cfg;
  560. ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
  561. char redo_scam;
  562. ushort res2;
  563. uchar dos_int13_table[ASC_MAX_TID + 1];
  564. ASC_DCNT max_dma_count;
  565. ASC_SCSI_BIT_ID_TYPE no_scam;
  566. ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
  567. uchar max_sdtr_index;
  568. uchar host_init_sdtr_index;
  569. struct asc_board *drv_ptr;
  570. ASC_DCNT uc_break;
  571. } ASC_DVC_VAR;
  572. typedef struct asc_dvc_inq_info {
  573. uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
  574. } ASC_DVC_INQ_INFO;
  575. typedef struct asc_cap_info {
  576. ASC_DCNT lba;
  577. ASC_DCNT blk_size;
  578. } ASC_CAP_INFO;
  579. typedef struct asc_cap_info_array {
  580. ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
  581. } ASC_CAP_INFO_ARRAY;
  582. #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
  583. #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
  584. #define ASC_CNTL_INITIATOR (ushort)0x0001
  585. #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
  586. #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
  587. #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
  588. #define ASC_CNTL_NO_SCAM (ushort)0x0010
  589. #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
  590. #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
  591. #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
  592. #define ASC_CNTL_RESET_SCSI (ushort)0x0200
  593. #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
  594. #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
  595. #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
  596. #define ASC_CNTL_BURST_MODE (ushort)0x2000
  597. #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
  598. #define ASC_EEP_DVC_CFG_BEG_VL 2
  599. #define ASC_EEP_MAX_DVC_ADDR_VL 15
  600. #define ASC_EEP_DVC_CFG_BEG 32
  601. #define ASC_EEP_MAX_DVC_ADDR 45
  602. #define ASC_EEP_MAX_RETRY 20
  603. /*
  604. * These macros keep the chip SCSI id and ISA DMA speed
  605. * bitfields in board order. C bitfields aren't portable
  606. * between big and little-endian platforms so they are
  607. * not used.
  608. */
  609. #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
  610. #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
  611. #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
  612. ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
  613. #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
  614. ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
  615. typedef struct asceep_config {
  616. ushort cfg_lsw;
  617. ushort cfg_msw;
  618. uchar init_sdtr;
  619. uchar disc_enable;
  620. uchar use_cmd_qng;
  621. uchar start_motor;
  622. uchar max_total_qng;
  623. uchar max_tag_qng;
  624. uchar bios_scan;
  625. uchar power_up_wait;
  626. uchar no_scam;
  627. uchar id_speed; /* low order 4 bits is chip scsi id */
  628. /* high order 4 bits is isa dma speed */
  629. uchar dos_int13_table[ASC_MAX_TID + 1];
  630. uchar adapter_info[6];
  631. ushort cntl;
  632. ushort chksum;
  633. } ASCEEP_CONFIG;
  634. #define ASC_EEP_CMD_READ 0x80
  635. #define ASC_EEP_CMD_WRITE 0x40
  636. #define ASC_EEP_CMD_WRITE_ABLE 0x30
  637. #define ASC_EEP_CMD_WRITE_DISABLE 0x00
  638. #define ASC_OVERRUN_BSIZE 0x00000048UL
  639. #define ASCV_MSGOUT_BEG 0x0000
  640. #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
  641. #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
  642. #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
  643. #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
  644. #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
  645. #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
  646. #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
  647. #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
  648. #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
  649. #define ASCV_BREAK_ADDR (ushort)0x0028
  650. #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
  651. #define ASCV_BREAK_CONTROL (ushort)0x002C
  652. #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
  653. #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
  654. #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
  655. #define ASCV_MCODE_SIZE_W (ushort)0x0034
  656. #define ASCV_STOP_CODE_B (ushort)0x0036
  657. #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
  658. #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
  659. #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
  660. #define ASCV_HALTCODE_W (ushort)0x0040
  661. #define ASCV_CHKSUM_W (ushort)0x0042
  662. #define ASCV_MC_DATE_W (ushort)0x0044
  663. #define ASCV_MC_VER_W (ushort)0x0046
  664. #define ASCV_NEXTRDY_B (ushort)0x0048
  665. #define ASCV_DONENEXT_B (ushort)0x0049
  666. #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
  667. #define ASCV_SCSIBUSY_B (ushort)0x004B
  668. #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
  669. #define ASCV_CURCDB_B (ushort)0x004D
  670. #define ASCV_RCLUN_B (ushort)0x004E
  671. #define ASCV_BUSY_QHEAD_B (ushort)0x004F
  672. #define ASCV_DISC1_QHEAD_B (ushort)0x0050
  673. #define ASCV_DISC_ENABLE_B (ushort)0x0052
  674. #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
  675. #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
  676. #define ASCV_MCODE_CNTL_B (ushort)0x0056
  677. #define ASCV_NULL_TARGET_B (ushort)0x0057
  678. #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
  679. #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
  680. #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
  681. #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
  682. #define ASCV_HOST_FLAG_B (ushort)0x005D
  683. #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
  684. #define ASCV_VER_SERIAL_B (ushort)0x0065
  685. #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
  686. #define ASCV_WTM_FLAG_B (ushort)0x0068
  687. #define ASCV_RISC_FLAG_B (ushort)0x006A
  688. #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
  689. #define ASC_HOST_FLAG_IN_ISR 0x01
  690. #define ASC_HOST_FLAG_ACK_INT 0x02
  691. #define ASC_RISC_FLAG_GEN_INT 0x01
  692. #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
  693. #define IOP_CTRL (0x0F)
  694. #define IOP_STATUS (0x0E)
  695. #define IOP_INT_ACK IOP_STATUS
  696. #define IOP_REG_IFC (0x0D)
  697. #define IOP_SYN_OFFSET (0x0B)
  698. #define IOP_EXTRA_CONTROL (0x0D)
  699. #define IOP_REG_PC (0x0C)
  700. #define IOP_RAM_ADDR (0x0A)
  701. #define IOP_RAM_DATA (0x08)
  702. #define IOP_EEP_DATA (0x06)
  703. #define IOP_EEP_CMD (0x07)
  704. #define IOP_VERSION (0x03)
  705. #define IOP_CONFIG_HIGH (0x04)
  706. #define IOP_CONFIG_LOW (0x02)
  707. #define IOP_SIG_BYTE (0x01)
  708. #define IOP_SIG_WORD (0x00)
  709. #define IOP_REG_DC1 (0x0E)
  710. #define IOP_REG_DC0 (0x0C)
  711. #define IOP_REG_SB (0x0B)
  712. #define IOP_REG_DA1 (0x0A)
  713. #define IOP_REG_DA0 (0x08)
  714. #define IOP_REG_SC (0x09)
  715. #define IOP_DMA_SPEED (0x07)
  716. #define IOP_REG_FLAG (0x07)
  717. #define IOP_FIFO_H (0x06)
  718. #define IOP_FIFO_L (0x04)
  719. #define IOP_REG_ID (0x05)
  720. #define IOP_REG_QP (0x03)
  721. #define IOP_REG_IH (0x02)
  722. #define IOP_REG_IX (0x01)
  723. #define IOP_REG_AX (0x00)
  724. #define IFC_REG_LOCK (0x00)
  725. #define IFC_REG_UNLOCK (0x09)
  726. #define IFC_WR_EN_FILTER (0x10)
  727. #define IFC_RD_NO_EEPROM (0x10)
  728. #define IFC_SLEW_RATE (0x20)
  729. #define IFC_ACT_NEG (0x40)
  730. #define IFC_INP_FILTER (0x80)
  731. #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
  732. #define SC_SEL (uchar)(0x80)
  733. #define SC_BSY (uchar)(0x40)
  734. #define SC_ACK (uchar)(0x20)
  735. #define SC_REQ (uchar)(0x10)
  736. #define SC_ATN (uchar)(0x08)
  737. #define SC_IO (uchar)(0x04)
  738. #define SC_CD (uchar)(0x02)
  739. #define SC_MSG (uchar)(0x01)
  740. #define SEC_SCSI_CTL (uchar)(0x80)
  741. #define SEC_ACTIVE_NEGATE (uchar)(0x40)
  742. #define SEC_SLEW_RATE (uchar)(0x20)
  743. #define SEC_ENABLE_FILTER (uchar)(0x10)
  744. #define ASC_HALT_EXTMSG_IN (ushort)0x8000
  745. #define ASC_HALT_CHK_CONDITION (ushort)0x8100
  746. #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
  747. #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
  748. #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
  749. #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
  750. #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
  751. #define ASC_MAX_QNO 0xF8
  752. #define ASC_DATA_SEC_BEG (ushort)0x0080
  753. #define ASC_DATA_SEC_END (ushort)0x0080
  754. #define ASC_CODE_SEC_BEG (ushort)0x0080
  755. #define ASC_CODE_SEC_END (ushort)0x0080
  756. #define ASC_QADR_BEG (0x4000)
  757. #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
  758. #define ASC_QADR_END (ushort)0x7FFF
  759. #define ASC_QLAST_ADR (ushort)0x7FC0
  760. #define ASC_QBLK_SIZE 0x40
  761. #define ASC_BIOS_DATA_QBEG 0xF8
  762. #define ASC_MIN_ACTIVE_QNO 0x01
  763. #define ASC_QLINK_END 0xFF
  764. #define ASC_EEPROM_WORDS 0x10
  765. #define ASC_MAX_MGS_LEN 0x10
  766. #define ASC_BIOS_ADDR_DEF 0xDC00
  767. #define ASC_BIOS_SIZE 0x3800
  768. #define ASC_BIOS_RAM_OFF 0x3800
  769. #define ASC_BIOS_RAM_SIZE 0x800
  770. #define ASC_BIOS_MIN_ADDR 0xC000
  771. #define ASC_BIOS_MAX_ADDR 0xEC00
  772. #define ASC_BIOS_BANK_SIZE 0x0400
  773. #define ASC_MCODE_START_ADDR 0x0080
  774. #define ASC_CFG0_HOST_INT_ON 0x0020
  775. #define ASC_CFG0_BIOS_ON 0x0040
  776. #define ASC_CFG0_VERA_BURST_ON 0x0080
  777. #define ASC_CFG0_SCSI_PARITY_ON 0x0800
  778. #define ASC_CFG1_SCSI_TARGET_ON 0x0080
  779. #define ASC_CFG1_LRAM_8BITS_ON 0x0800
  780. #define ASC_CFG_MSW_CLR_MASK 0x3080
  781. #define CSW_TEST1 (ASC_CS_TYPE)0x8000
  782. #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
  783. #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
  784. #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
  785. #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
  786. #define CSW_TEST2 (ASC_CS_TYPE)0x0400
  787. #define CSW_TEST3 (ASC_CS_TYPE)0x0200
  788. #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
  789. #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
  790. #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
  791. #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
  792. #define CSW_HALTED (ASC_CS_TYPE)0x0010
  793. #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
  794. #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
  795. #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
  796. #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
  797. #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
  798. #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
  799. #define CIW_TEST1 (ASC_CS_TYPE)0x0200
  800. #define CIW_TEST2 (ASC_CS_TYPE)0x0400
  801. #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
  802. #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
  803. #define CC_CHIP_RESET (uchar)0x80
  804. #define CC_SCSI_RESET (uchar)0x40
  805. #define CC_HALT (uchar)0x20
  806. #define CC_SINGLE_STEP (uchar)0x10
  807. #define CC_DMA_ABLE (uchar)0x08
  808. #define CC_TEST (uchar)0x04
  809. #define CC_BANK_ONE (uchar)0x02
  810. #define CC_DIAG (uchar)0x01
  811. #define ASC_1000_ID0W 0x04C1
  812. #define ASC_1000_ID0W_FIX 0x00C1
  813. #define ASC_1000_ID1B 0x25
  814. #define ASC_EISA_REV_IOP_MASK (0x0C83)
  815. #define ASC_EISA_CFG_IOP_MASK (0x0C86)
  816. #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
  817. #define INS_HALTINT (ushort)0x6281
  818. #define INS_HALT (ushort)0x6280
  819. #define INS_SINT (ushort)0x6200
  820. #define INS_RFLAG_WTM (ushort)0x7380
  821. #define ASC_MC_SAVE_CODE_WSIZE 0x500
  822. #define ASC_MC_SAVE_DATA_WSIZE 0x40
  823. typedef struct asc_mc_saved {
  824. ushort data[ASC_MC_SAVE_DATA_WSIZE];
  825. ushort code[ASC_MC_SAVE_CODE_WSIZE];
  826. } ASC_MC_SAVED;
  827. #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
  828. #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
  829. #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
  830. #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
  831. #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
  832. #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
  833. #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
  834. #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
  835. #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
  836. #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
  837. #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
  838. #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
  839. #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
  840. #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
  841. #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
  842. #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
  843. #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
  844. #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
  845. #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
  846. #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
  847. #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
  848. #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
  849. #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
  850. #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
  851. #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
  852. #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
  853. #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
  854. #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
  855. #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
  856. #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
  857. #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
  858. #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
  859. #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
  860. #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
  861. #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
  862. #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
  863. #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
  864. #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
  865. #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
  866. #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
  867. #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
  868. #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
  869. #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
  870. #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
  871. #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
  872. #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
  873. #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
  874. #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
  875. #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
  876. #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
  877. #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
  878. #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
  879. #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
  880. #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
  881. #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
  882. #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
  883. #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
  884. #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
  885. #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
  886. #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
  887. #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
  888. #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
  889. #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
  890. #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
  891. #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
  892. #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
  893. #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
  894. #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
  895. /*
  896. * Portable Data Types
  897. *
  898. * Any instance where a 32-bit long or pointer type is assumed
  899. * for precision or HW defined structures, the following define
  900. * types must be used. In Linux the char, short, and int types
  901. * are all consistent at 8, 16, and 32 bits respectively. Pointers
  902. * and long types are 64 bits on Alpha and UltraSPARC.
  903. */
  904. #define ADV_PADDR __u32 /* Physical address data type. */
  905. #define ADV_VADDR __u32 /* Virtual address data type. */
  906. #define ADV_DCNT __u32 /* Unsigned Data count type. */
  907. #define ADV_SDCNT __s32 /* Signed Data count type. */
  908. /*
  909. * These macros are used to convert a virtual address to a
  910. * 32-bit value. This currently can be used on Linux Alpha
  911. * which uses 64-bit virtual address but a 32-bit bus address.
  912. * This is likely to break in the future, but doing this now
  913. * will give us time to change the HW and FW to handle 64-bit
  914. * addresses.
  915. */
  916. #define ADV_VADDR_TO_U32 virt_to_bus
  917. #define ADV_U32_TO_VADDR bus_to_virt
  918. #define AdvPortAddr void __iomem * /* Virtual memory address size */
  919. /*
  920. * Define Adv Library required memory access macros.
  921. */
  922. #define ADV_MEM_READB(addr) readb(addr)
  923. #define ADV_MEM_READW(addr) readw(addr)
  924. #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
  925. #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
  926. #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
  927. #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
  928. /*
  929. * Define total number of simultaneous maximum element scatter-gather
  930. * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
  931. * maximum number of outstanding commands per wide host adapter. Each
  932. * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
  933. * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
  934. * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
  935. * structures or 255 scatter-gather elements.
  936. *
  937. */
  938. #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
  939. /*
  940. * Define Adv Library required maximum number of scatter-gather
  941. * elements per request.
  942. */
  943. #define ADV_MAX_SG_LIST 255
  944. /* Number of SG blocks needed. */
  945. #define ADV_NUM_SG_BLOCK \
  946. ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
  947. /* Total contiguous memory needed for SG blocks. */
  948. #define ADV_SG_TOTAL_MEM_SIZE \
  949. (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
  950. #define ADV_PAGE_SIZE PAGE_SIZE
  951. #define ADV_NUM_PAGE_CROSSING \
  952. ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
  953. #define ADV_EEP_DVC_CFG_BEGIN (0x00)
  954. #define ADV_EEP_DVC_CFG_END (0x15)
  955. #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
  956. #define ADV_EEP_MAX_WORD_ADDR (0x1E)
  957. #define ADV_EEP_DELAY_MS 100
  958. #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
  959. #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
  960. /*
  961. * For the ASC3550 Bit 13 is Termination Polarity control bit.
  962. * For later ICs Bit 13 controls whether the CIS (Card Information
  963. * Service Section) is loaded from EEPROM.
  964. */
  965. #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
  966. #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
  967. /*
  968. * ASC38C1600 Bit 11
  969. *
  970. * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
  971. * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
  972. * Function 0 will specify INT B.
  973. *
  974. * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
  975. * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
  976. * Function 1 will specify INT A.
  977. */
  978. #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
  979. typedef struct adveep_3550_config {
  980. /* Word Offset, Description */
  981. ushort cfg_lsw; /* 00 power up initialization */
  982. /* bit 13 set - Term Polarity Control */
  983. /* bit 14 set - BIOS Enable */
  984. /* bit 15 set - Big Endian Mode */
  985. ushort cfg_msw; /* 01 unused */
  986. ushort disc_enable; /* 02 disconnect enable */
  987. ushort wdtr_able; /* 03 Wide DTR able */
  988. ushort sdtr_able; /* 04 Synchronous DTR able */
  989. ushort start_motor; /* 05 send start up motor */
  990. ushort tagqng_able; /* 06 tag queuing able */
  991. ushort bios_scan; /* 07 BIOS device control */
  992. ushort scam_tolerant; /* 08 no scam */
  993. uchar adapter_scsi_id; /* 09 Host Adapter ID */
  994. uchar bios_boot_delay; /* power up wait */
  995. uchar scsi_reset_delay; /* 10 reset delay */
  996. uchar bios_id_lun; /* first boot device scsi id & lun */
  997. /* high nibble is lun */
  998. /* low nibble is scsi id */
  999. uchar termination; /* 11 0 - automatic */
  1000. /* 1 - low off / high off */
  1001. /* 2 - low off / high on */
  1002. /* 3 - low on / high on */
  1003. /* There is no low on / high off */
  1004. uchar reserved1; /* reserved byte (not used) */
  1005. ushort bios_ctrl; /* 12 BIOS control bits */
  1006. /* bit 0 BIOS don't act as initiator. */
  1007. /* bit 1 BIOS > 1 GB support */
  1008. /* bit 2 BIOS > 2 Disk Support */
  1009. /* bit 3 BIOS don't support removables */
  1010. /* bit 4 BIOS support bootable CD */
  1011. /* bit 5 BIOS scan enabled */
  1012. /* bit 6 BIOS support multiple LUNs */
  1013. /* bit 7 BIOS display of message */
  1014. /* bit 8 SCAM disabled */
  1015. /* bit 9 Reset SCSI bus during init. */
  1016. /* bit 10 */
  1017. /* bit 11 No verbose initialization. */
  1018. /* bit 12 SCSI parity enabled */
  1019. /* bit 13 */
  1020. /* bit 14 */
  1021. /* bit 15 */
  1022. ushort ultra_able; /* 13 ULTRA speed able */
  1023. ushort reserved2; /* 14 reserved */
  1024. uchar max_host_qng; /* 15 maximum host queuing */
  1025. uchar max_dvc_qng; /* maximum per device queuing */
  1026. ushort dvc_cntl; /* 16 control bit for driver */
  1027. ushort bug_fix; /* 17 control bit for bug fix */
  1028. ushort serial_number_word1; /* 18 Board serial number word 1 */
  1029. ushort serial_number_word2; /* 19 Board serial number word 2 */
  1030. ushort serial_number_word3; /* 20 Board serial number word 3 */
  1031. ushort check_sum; /* 21 EEP check sum */
  1032. uchar oem_name[16]; /* 22 OEM name */
  1033. ushort dvc_err_code; /* 30 last device driver error code */
  1034. ushort adv_err_code; /* 31 last uc and Adv Lib error code */
  1035. ushort adv_err_addr; /* 32 last uc error address */
  1036. ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
  1037. ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
  1038. ushort saved_adv_err_addr; /* 35 saved last uc error address */
  1039. ushort num_of_err; /* 36 number of error */
  1040. } ADVEEP_3550_CONFIG;
  1041. typedef struct adveep_38C0800_config {
  1042. /* Word Offset, Description */
  1043. ushort cfg_lsw; /* 00 power up initialization */
  1044. /* bit 13 set - Load CIS */
  1045. /* bit 14 set - BIOS Enable */
  1046. /* bit 15 set - Big Endian Mode */
  1047. ushort cfg_msw; /* 01 unused */
  1048. ushort disc_enable; /* 02 disconnect enable */
  1049. ushort wdtr_able; /* 03 Wide DTR able */
  1050. ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
  1051. ushort start_motor; /* 05 send start up motor */
  1052. ushort tagqng_able; /* 06 tag queuing able */
  1053. ushort bios_scan; /* 07 BIOS device control */
  1054. ushort scam_tolerant; /* 08 no scam */
  1055. uchar adapter_scsi_id; /* 09 Host Adapter ID */
  1056. uchar bios_boot_delay; /* power up wait */
  1057. uchar scsi_reset_delay; /* 10 reset delay */
  1058. uchar bios_id_lun; /* first boot device scsi id & lun */
  1059. /* high nibble is lun */
  1060. /* low nibble is scsi id */
  1061. uchar termination_se; /* 11 0 - automatic */
  1062. /* 1 - low off / high off */
  1063. /* 2 - low off / high on */
  1064. /* 3 - low on / high on */
  1065. /* There is no low on / high off */
  1066. uchar termination_lvd; /* 11 0 - automatic */
  1067. /* 1 - low off / high off */
  1068. /* 2 - low off / high on */
  1069. /* 3 - low on / high on */
  1070. /* There is no low on / high off */
  1071. ushort bios_ctrl; /* 12 BIOS control bits */
  1072. /* bit 0 BIOS don't act as initiator. */
  1073. /* bit 1 BIOS > 1 GB support */
  1074. /* bit 2 BIOS > 2 Disk Support */
  1075. /* bit 3 BIOS don't support removables */
  1076. /* bit 4 BIOS support bootable CD */
  1077. /* bit 5 BIOS scan enabled */
  1078. /* bit 6 BIOS support multiple LUNs */
  1079. /* bit 7 BIOS display of message */
  1080. /* bit 8 SCAM disabled */
  1081. /* bit 9 Reset SCSI bus during init. */
  1082. /* bit 10 */
  1083. /* bit 11 No verbose initialization. */
  1084. /* bit 12 SCSI parity enabled */
  1085. /* bit 13 */
  1086. /* bit 14 */
  1087. /* bit 15 */
  1088. ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
  1089. ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
  1090. uchar max_host_qng; /* 15 maximum host queueing */
  1091. uchar max_dvc_qng; /* maximum per device queuing */
  1092. ushort dvc_cntl; /* 16 control bit for driver */
  1093. ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
  1094. ushort serial_number_word1; /* 18 Board serial number word 1 */
  1095. ushort serial_number_word2; /* 19 Board serial number word 2 */
  1096. ushort serial_number_word3; /* 20 Board serial number word 3 */
  1097. ushort check_sum; /* 21 EEP check sum */
  1098. uchar oem_name[16]; /* 22 OEM name */
  1099. ushort dvc_err_code; /* 30 last device driver error code */
  1100. ushort adv_err_code; /* 31 last uc and Adv Lib error code */
  1101. ushort adv_err_addr; /* 32 last uc error address */
  1102. ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
  1103. ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
  1104. ushort saved_adv_err_addr; /* 35 saved last uc error address */
  1105. ushort reserved36; /* 36 reserved */
  1106. ushort reserved37; /* 37 reserved */
  1107. ushort reserved38; /* 38 reserved */
  1108. ushort reserved39; /* 39 reserved */
  1109. ushort reserved40; /* 40 reserved */
  1110. ushort reserved41; /* 41 reserved */
  1111. ushort reserved42; /* 42 reserved */
  1112. ushort reserved43; /* 43 reserved */
  1113. ushort reserved44; /* 44 reserved */
  1114. ushort reserved45; /* 45 reserved */
  1115. ushort reserved46; /* 46 reserved */
  1116. ushort reserved47; /* 47 reserved */
  1117. ushort reserved48; /* 48 reserved */
  1118. ushort reserved49; /* 49 reserved */
  1119. ushort reserved50; /* 50 reserved */
  1120. ushort reserved51; /* 51 reserved */
  1121. ushort reserved52; /* 52 reserved */
  1122. ushort reserved53; /* 53 reserved */
  1123. ushort reserved54; /* 54 reserved */
  1124. ushort reserved55; /* 55 reserved */
  1125. ushort cisptr_lsw; /* 56 CIS PTR LSW */
  1126. ushort cisprt_msw; /* 57 CIS PTR MSW */
  1127. ushort subsysvid; /* 58 SubSystem Vendor ID */
  1128. ushort subsysid; /* 59 SubSystem ID */
  1129. ushort reserved60; /* 60 reserved */
  1130. ushort reserved61; /* 61 reserved */
  1131. ushort reserved62; /* 62 reserved */
  1132. ushort reserved63; /* 63 reserved */
  1133. } ADVEEP_38C0800_CONFIG;
  1134. typedef struct adveep_38C1600_config {
  1135. /* Word Offset, Description */
  1136. ushort cfg_lsw; /* 00 power up initialization */
  1137. /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
  1138. /* clear - Func. 0 INTA, Func. 1 INTB */
  1139. /* bit 13 set - Load CIS */
  1140. /* bit 14 set - BIOS Enable */
  1141. /* bit 15 set - Big Endian Mode */
  1142. ushort cfg_msw; /* 01 unused */
  1143. ushort disc_enable; /* 02 disconnect enable */
  1144. ushort wdtr_able; /* 03 Wide DTR able */
  1145. ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
  1146. ushort start_motor; /* 05 send start up motor */
  1147. ushort tagqng_able; /* 06 tag queuing able */
  1148. ushort bios_scan; /* 07 BIOS device control */
  1149. ushort scam_tolerant; /* 08 no scam */
  1150. uchar adapter_scsi_id; /* 09 Host Adapter ID */
  1151. uchar bios_boot_delay; /* power up wait */
  1152. uchar scsi_reset_delay; /* 10 reset delay */
  1153. uchar bios_id_lun; /* first boot device scsi id & lun */
  1154. /* high nibble is lun */
  1155. /* low nibble is scsi id */
  1156. uchar termination_se; /* 11 0 - automatic */
  1157. /* 1 - low off / high off */
  1158. /* 2 - low off / high on */
  1159. /* 3 - low on / high on */
  1160. /* There is no low on / high off */
  1161. uchar termination_lvd; /* 11 0 - automatic */
  1162. /* 1 - low off / high off */
  1163. /* 2 - low off / high on */
  1164. /* 3 - low on / high on */
  1165. /* There is no low on / high off */
  1166. ushort bios_ctrl; /* 12 BIOS control bits */
  1167. /* bit 0 BIOS don't act as initiator. */
  1168. /* bit 1 BIOS > 1 GB support */
  1169. /* bit 2 BIOS > 2 Disk Support */
  1170. /* bit 3 BIOS don't support removables */
  1171. /* bit 4 BIOS support bootable CD */
  1172. /* bit 5 BIOS scan enabled */
  1173. /* bit 6 BIOS support multiple LUNs */
  1174. /* bit 7 BIOS display of message */
  1175. /* bit 8 SCAM disabled */
  1176. /* bit 9 Reset SCSI bus during init. */
  1177. /* bit 10 Basic Integrity Checking disabled */
  1178. /* bit 11 No verbose initialization. */
  1179. /* bit 12 SCSI parity enabled */
  1180. /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
  1181. /* bit 14 */
  1182. /* bit 15 */
  1183. ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
  1184. ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
  1185. uchar max_host_qng; /* 15 maximum host queueing */
  1186. uchar max_dvc_qng; /* maximum per device queuing */
  1187. ushort dvc_cntl; /* 16 control bit for driver */
  1188. ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
  1189. ushort serial_number_word1; /* 18 Board serial number word 1 */
  1190. ushort serial_number_word2; /* 19 Board serial number word 2 */
  1191. ushort serial_number_word3; /* 20 Board serial number word 3 */
  1192. ushort check_sum; /* 21 EEP check sum */
  1193. uchar oem_name[16]; /* 22 OEM name */
  1194. ushort dvc_err_code; /* 30 last device driver error code */
  1195. ushort adv_err_code; /* 31 last uc and Adv Lib error code */
  1196. ushort adv_err_addr; /* 32 last uc error address */
  1197. ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
  1198. ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
  1199. ushort saved_adv_err_addr; /* 35 saved last uc error address */
  1200. ushort reserved36; /* 36 reserved */
  1201. ushort reserved37; /* 37 reserved */
  1202. ushort reserved38; /* 38 reserved */
  1203. ushort reserved39; /* 39 reserved */
  1204. ushort reserved40; /* 40 reserved */
  1205. ushort reserved41; /* 41 reserved */
  1206. ushort reserved42; /* 42 reserved */
  1207. ushort reserved43; /* 43 reserved */
  1208. ushort reserved44; /* 44 reserved */
  1209. ushort reserved45; /* 45 reserved */
  1210. ushort reserved46; /* 46 reserved */
  1211. ushort reserved47; /* 47 reserved */
  1212. ushort reserved48; /* 48 reserved */
  1213. ushort reserved49; /* 49 reserved */
  1214. ushort reserved50; /* 50 reserved */
  1215. ushort reserved51; /* 51 reserved */
  1216. ushort reserved52; /* 52 reserved */
  1217. ushort reserved53; /* 53 reserved */
  1218. ushort reserved54; /* 54 reserved */
  1219. ushort reserved55; /* 55 reserved */
  1220. ushort cisptr_lsw; /* 56 CIS PTR LSW */
  1221. ushort cisprt_msw; /* 57 CIS PTR MSW */
  1222. ushort subsysvid; /* 58 SubSystem Vendor ID */
  1223. ushort subsysid; /* 59 SubSystem ID */
  1224. ushort reserved60; /* 60 reserved */
  1225. ushort reserved61; /* 61 reserved */
  1226. ushort reserved62; /* 62 reserved */
  1227. ushort reserved63; /* 63 reserved */
  1228. } ADVEEP_38C1600_CONFIG;
  1229. /*
  1230. * EEPROM Commands
  1231. */
  1232. #define ASC_EEP_CMD_DONE 0x0200
  1233. /* bios_ctrl */
  1234. #define BIOS_CTRL_BIOS 0x0001
  1235. #define BIOS_CTRL_EXTENDED_XLAT 0x0002
  1236. #define BIOS_CTRL_GT_2_DISK 0x0004
  1237. #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
  1238. #define BIOS_CTRL_BOOTABLE_CD 0x0010
  1239. #define BIOS_CTRL_MULTIPLE_LUN 0x0040
  1240. #define BIOS_CTRL_DISPLAY_MSG 0x0080
  1241. #define BIOS_CTRL_NO_SCAM 0x0100
  1242. #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
  1243. #define BIOS_CTRL_INIT_VERBOSE 0x0800
  1244. #define BIOS_CTRL_SCSI_PARITY 0x1000
  1245. #define BIOS_CTRL_AIPP_DIS 0x2000
  1246. #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
  1247. #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
  1248. /*
  1249. * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
  1250. * a special 16K Adv Library and Microcode version. After the issue is
  1251. * resolved, should restore 32K support.
  1252. *
  1253. * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
  1254. */
  1255. #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
  1256. /*
  1257. * Byte I/O register address from base of 'iop_base'.
  1258. */
  1259. #define IOPB_INTR_STATUS_REG 0x00
  1260. #define IOPB_CHIP_ID_1 0x01
  1261. #define IOPB_INTR_ENABLES 0x02
  1262. #define IOPB_CHIP_TYPE_REV 0x03
  1263. #define IOPB_RES_ADDR_4 0x04
  1264. #define IOPB_RES_ADDR_5 0x05
  1265. #define IOPB_RAM_DATA 0x06
  1266. #define IOPB_RES_ADDR_7 0x07
  1267. #define IOPB_FLAG_REG 0x08
  1268. #define IOPB_RES_ADDR_9 0x09
  1269. #define IOPB_RISC_CSR 0x0A
  1270. #define IOPB_RES_ADDR_B 0x0B
  1271. #define IOPB_RES_ADDR_C 0x0C
  1272. #define IOPB_RES_ADDR_D 0x0D
  1273. #define IOPB_SOFT_OVER_WR 0x0E
  1274. #define IOPB_RES_ADDR_F 0x0F
  1275. #define IOPB_MEM_CFG 0x10
  1276. #define IOPB_RES_ADDR_11 0x11
  1277. #define IOPB_GPIO_DATA 0x12
  1278. #define IOPB_RES_ADDR_13 0x13
  1279. #define IOPB_FLASH_PAGE 0x14
  1280. #define IOPB_RES_ADDR_15 0x15
  1281. #define IOPB_GPIO_CNTL 0x16
  1282. #define IOPB_RES_ADDR_17 0x17
  1283. #define IOPB_FLASH_DATA 0x18
  1284. #define IOPB_RES_ADDR_19 0x19
  1285. #define IOPB_RES_ADDR_1A 0x1A
  1286. #define IOPB_RES_ADDR_1B 0x1B
  1287. #define IOPB_RES_ADDR_1C 0x1C
  1288. #define IOPB_RES_ADDR_1D 0x1D
  1289. #define IOPB_RES_ADDR_1E 0x1E
  1290. #define IOPB_RES_ADDR_1F 0x1F
  1291. #define IOPB_DMA_CFG0 0x20
  1292. #define IOPB_DMA_CFG1 0x21
  1293. #define IOPB_TICKLE 0x22
  1294. #define IOPB_DMA_REG_WR 0x23
  1295. #define IOPB_SDMA_STATUS 0x24
  1296. #define IOPB_SCSI_BYTE_CNT 0x25
  1297. #define IOPB_HOST_BYTE_CNT 0x26
  1298. #define IOPB_BYTE_LEFT_TO_XFER 0x27
  1299. #define IOPB_BYTE_TO_XFER_0 0x28
  1300. #define IOPB_BYTE_TO_XFER_1 0x29
  1301. #define IOPB_BYTE_TO_XFER_2 0x2A
  1302. #define IOPB_BYTE_TO_XFER_3 0x2B
  1303. #define IOPB_ACC_GRP 0x2C
  1304. #define IOPB_RES_ADDR_2D 0x2D
  1305. #define IOPB_DEV_ID 0x2E
  1306. #define IOPB_RES_ADDR_2F 0x2F
  1307. #define IOPB_SCSI_DATA 0x30
  1308. #define IOPB_RES_ADDR_31 0x31
  1309. #define IOPB_RES_ADDR_32 0x32
  1310. #define IOPB_SCSI_DATA_HSHK 0x33
  1311. #define IOPB_SCSI_CTRL 0x34
  1312. #define IOPB_RES_ADDR_35 0x35
  1313. #define IOPB_RES_ADDR_36 0x36
  1314. #define IOPB_RES_ADDR_37 0x37
  1315. #define IOPB_RAM_BIST 0x38
  1316. #define IOPB_PLL_TEST 0x39
  1317. #define IOPB_PCI_INT_CFG 0x3A
  1318. #define IOPB_RES_ADDR_3B 0x3B
  1319. #define IOPB_RFIFO_CNT 0x3C
  1320. #define IOPB_RES_ADDR_3D 0x3D
  1321. #define IOPB_RES_ADDR_3E 0x3E
  1322. #define IOPB_RES_ADDR_3F 0x3F
  1323. /*
  1324. * Word I/O register address from base of 'iop_base'.
  1325. */
  1326. #define IOPW_CHIP_ID_0 0x00 /* CID0 */
  1327. #define IOPW_CTRL_REG 0x02 /* CC */
  1328. #define IOPW_RAM_ADDR 0x04 /* LA */
  1329. #define IOPW_RAM_DATA 0x06 /* LD */
  1330. #define IOPW_RES_ADDR_08 0x08
  1331. #define IOPW_RISC_CSR 0x0A /* CSR */
  1332. #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
  1333. #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
  1334. #define IOPW_RES_ADDR_10 0x10
  1335. #define IOPW_SEL_MASK 0x12 /* SM */
  1336. #define IOPW_RES_ADDR_14 0x14
  1337. #define IOPW_FLASH_ADDR 0x16 /* FA */
  1338. #define IOPW_RES_ADDR_18 0x18
  1339. #define IOPW_EE_CMD 0x1A /* EC */
  1340. #define IOPW_EE_DATA 0x1C /* ED */
  1341. #define IOPW_SFIFO_CNT 0x1E /* SFC */
  1342. #define IOPW_RES_ADDR_20 0x20
  1343. #define IOPW_Q_BASE 0x22 /* QB */
  1344. #define IOPW_QP 0x24 /* QP */
  1345. #define IOPW_IX 0x26 /* IX */
  1346. #define IOPW_SP 0x28 /* SP */
  1347. #define IOPW_PC 0x2A /* PC */
  1348. #define IOPW_RES_ADDR_2C 0x2C
  1349. #define IOPW_RES_ADDR_2E 0x2E
  1350. #define IOPW_SCSI_DATA 0x30 /* SD */
  1351. #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
  1352. #define IOPW_SCSI_CTRL 0x34 /* SC */
  1353. #define IOPW_HSHK_CFG 0x36 /* HCFG */
  1354. #define IOPW_SXFR_STATUS 0x36 /* SXS */
  1355. #define IOPW_SXFR_CNTL 0x38 /* SXL */
  1356. #define IOPW_SXFR_CNTH 0x3A /* SXH */
  1357. #define IOPW_RES_ADDR_3C 0x3C
  1358. #define IOPW_RFIFO_DATA 0x3E /* RFD */
  1359. /*
  1360. * Doubleword I/O register address from base of 'iop_base'.
  1361. */
  1362. #define IOPDW_RES_ADDR_0 0x00
  1363. #define IOPDW_RAM_DATA 0x04
  1364. #define IOPDW_RES_ADDR_8 0x08
  1365. #define IOPDW_RES_ADDR_C 0x0C
  1366. #define IOPDW_RES_ADDR_10 0x10
  1367. #define IOPDW_COMMA 0x14
  1368. #define IOPDW_COMMB 0x18
  1369. #define IOPDW_RES_ADDR_1C 0x1C
  1370. #define IOPDW_SDMA_ADDR0 0x20
  1371. #define IOPDW_SDMA_ADDR1 0x24
  1372. #define IOPDW_SDMA_COUNT 0x28
  1373. #define IOPDW_SDMA_ERROR 0x2C
  1374. #define IOPDW_RDMA_ADDR0 0x30
  1375. #define IOPDW_RDMA_ADDR1 0x34
  1376. #define IOPDW_RDMA_COUNT 0x38
  1377. #define IOPDW_RDMA_ERROR 0x3C
  1378. #define ADV_CHIP_ID_BYTE 0x25
  1379. #define ADV_CHIP_ID_WORD 0x04C1
  1380. #define ADV_INTR_ENABLE_HOST_INTR 0x01
  1381. #define ADV_INTR_ENABLE_SEL_INTR 0x02
  1382. #define ADV_INTR_ENABLE_DPR_INTR 0x04
  1383. #define ADV_INTR_ENABLE_RTA_INTR 0x08
  1384. #define ADV_INTR_ENABLE_RMA_INTR 0x10
  1385. #define ADV_INTR_ENABLE_RST_INTR 0x20
  1386. #define ADV_INTR_ENABLE_DPE_INTR 0x40
  1387. #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
  1388. #define ADV_INTR_STATUS_INTRA 0x01
  1389. #define ADV_INTR_STATUS_INTRB 0x02
  1390. #define ADV_INTR_STATUS_INTRC 0x04
  1391. #define ADV_RISC_CSR_STOP (0x0000)
  1392. #define ADV_RISC_TEST_COND (0x2000)
  1393. #define ADV_RISC_CSR_RUN (0x4000)
  1394. #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
  1395. #define ADV_CTRL_REG_HOST_INTR 0x0100
  1396. #define ADV_CTRL_REG_SEL_INTR 0x0200
  1397. #define ADV_CTRL_REG_DPR_INTR 0x0400
  1398. #define ADV_CTRL_REG_RTA_INTR 0x0800
  1399. #define ADV_CTRL_REG_RMA_INTR 0x1000
  1400. #define ADV_CTRL_REG_RES_BIT14 0x2000
  1401. #define ADV_CTRL_REG_DPE_INTR 0x4000
  1402. #define ADV_CTRL_REG_POWER_DONE 0x8000
  1403. #define ADV_CTRL_REG_ANY_INTR 0xFF00
  1404. #define ADV_CTRL_REG_CMD_RESET 0x00C6
  1405. #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
  1406. #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
  1407. #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
  1408. #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
  1409. #define ADV_TICKLE_NOP 0x00
  1410. #define ADV_TICKLE_A 0x01
  1411. #define ADV_TICKLE_B 0x02
  1412. #define ADV_TICKLE_C 0x03
  1413. #define AdvIsIntPending(port) \
  1414. (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
  1415. /*
  1416. * SCSI_CFG0 Register bit definitions
  1417. */
  1418. #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
  1419. #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
  1420. #define EVEN_PARITY 0x1000 /* Select Even Parity */
  1421. #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
  1422. #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
  1423. #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
  1424. #define SCAM_EN 0x0080 /* Enable SCAM selection */
  1425. #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
  1426. #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
  1427. #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
  1428. #define OUR_ID 0x000F /* SCSI ID */
  1429. /*
  1430. * SCSI_CFG1 Register bit definitions
  1431. */
  1432. #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
  1433. #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
  1434. #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
  1435. #define FILTER_SEL 0x0C00 /* Filter Period Selection */
  1436. #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
  1437. #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
  1438. #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
  1439. #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
  1440. #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
  1441. #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
  1442. #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
  1443. #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
  1444. #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
  1445. #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
  1446. #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
  1447. /*
  1448. * Addendum for ASC-38C0800 Chip
  1449. *
  1450. * The ASC-38C1600 Chip uses the same definitions except that the
  1451. * bus mode override bits [12:10] have been moved to byte register
  1452. * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
  1453. * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
  1454. * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
  1455. * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
  1456. * and [1:0]. Bits [14], [7:6], [3:2] are unused.
  1457. */
  1458. #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
  1459. #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
  1460. #define HVD 0x1000 /* HVD Device Detect */
  1461. #define LVD 0x0800 /* LVD Device Detect */
  1462. #define SE 0x0400 /* SE Device Detect */
  1463. #define TERM_LVD 0x00C0 /* LVD Termination Bits */
  1464. #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
  1465. #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
  1466. #define TERM_SE 0x0030 /* SE Termination Bits */
  1467. #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
  1468. #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
  1469. #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
  1470. #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
  1471. #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
  1472. #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
  1473. #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
  1474. #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
  1475. #define CABLE_ILLEGAL_A 0x7
  1476. /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
  1477. #define CABLE_ILLEGAL_B 0xB
  1478. /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
  1479. /*
  1480. * MEM_CFG Register bit definitions
  1481. */
  1482. #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
  1483. #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
  1484. #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
  1485. #define RAM_SZ_2KB 0x00 /* 2 KB */
  1486. #define RAM_SZ_4KB 0x04 /* 4 KB */
  1487. #define RAM_SZ_8KB 0x08 /* 8 KB */
  1488. #define RAM_SZ_16KB 0x0C /* 16 KB */
  1489. #define RAM_SZ_32KB 0x10 /* 32 KB */
  1490. #define RAM_SZ_64KB 0x14 /* 64 KB */
  1491. /*
  1492. * DMA_CFG0 Register bit definitions
  1493. *
  1494. * This register is only accessible to the host.
  1495. */
  1496. #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
  1497. #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
  1498. #define FIFO_THRESH_16B 0x00 /* 16 bytes */
  1499. #define FIFO_THRESH_32B 0x20 /* 32 bytes */
  1500. #define FIFO_THRESH_48B 0x30 /* 48 bytes */
  1501. #define FIFO_THRESH_64B 0x40 /* 64 bytes */
  1502. #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
  1503. #define FIFO_THRESH_96B 0x60 /* 96 bytes */
  1504. #define FIFO_THRESH_112B 0x70 /* 112 bytes */
  1505. #define START_CTL 0x0C /* DMA start conditions */
  1506. #define START_CTL_TH 0x00 /* Wait threshold level (default) */
  1507. #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
  1508. #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
  1509. #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
  1510. #define READ_CMD 0x03 /* Memory Read Method */
  1511. #define READ_CMD_MR 0x00 /* Memory Read */
  1512. #define READ_CMD_MRL 0x02 /* Memory Read Long */
  1513. #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
  1514. /*
  1515. * ASC-38C0800 RAM BIST Register bit definitions
  1516. */
  1517. #define RAM_TEST_MODE 0x80
  1518. #define PRE_TEST_MODE 0x40
  1519. #define NORMAL_MODE 0x00
  1520. #define RAM_TEST_DONE 0x10
  1521. #define RAM_TEST_STATUS 0x0F
  1522. #define RAM_TEST_HOST_ERROR 0x08
  1523. #define RAM_TEST_INTRAM_ERROR 0x04
  1524. #define RAM_TEST_RISC_ERROR 0x02
  1525. #define RAM_TEST_SCSI_ERROR 0x01
  1526. #define RAM_TEST_SUCCESS 0x00
  1527. #define PRE_TEST_VALUE 0x05
  1528. #define NORMAL_VALUE 0x00
  1529. /*
  1530. * ASC38C1600 Definitions
  1531. *
  1532. * IOPB_PCI_INT_CFG Bit Field Definitions
  1533. */
  1534. #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
  1535. /*
  1536. * Bit 1 can be set to change the interrupt for the Function to operate in
  1537. * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
  1538. * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
  1539. * mode, otherwise the operating mode is undefined.
  1540. */
  1541. #define TOTEMPOLE 0x02
  1542. /*
  1543. * Bit 0 can be used to change the Int Pin for the Function. The value is
  1544. * 0 by default for both Functions with Function 0 using INT A and Function
  1545. * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
  1546. * INT A is used.
  1547. *
  1548. * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
  1549. * value specified in the PCI Configuration Space.
  1550. */
  1551. #define INTAB 0x01
  1552. /*
  1553. * Adv Library Status Definitions
  1554. */
  1555. #define ADV_TRUE 1
  1556. #define ADV_FALSE 0
  1557. #define ADV_SUCCESS 1
  1558. #define ADV_BUSY 0
  1559. #define ADV_ERROR (-1)
  1560. /*
  1561. * ADV_DVC_VAR 'warn_code' values
  1562. */
  1563. #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
  1564. #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
  1565. #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
  1566. #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
  1567. #define ADV_MAX_TID 15 /* max. target identifier */
  1568. #define ADV_MAX_LUN 7 /* max. logical unit number */
  1569. /*
  1570. * Fixed locations of microcode operating variables.
  1571. */
  1572. #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
  1573. #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
  1574. #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
  1575. #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
  1576. #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
  1577. #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
  1578. #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
  1579. #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
  1580. #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
  1581. #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
  1582. #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
  1583. #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
  1584. #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
  1585. #define ASC_MC_CHIP_TYPE 0x009A
  1586. #define ASC_MC_INTRB_CODE 0x009B
  1587. #define ASC_MC_WDTR_ABLE 0x009C
  1588. #define ASC_MC_SDTR_ABLE 0x009E
  1589. #define ASC_MC_TAGQNG_ABLE 0x00A0
  1590. #define ASC_MC_DISC_ENABLE 0x00A2
  1591. #define ASC_MC_IDLE_CMD_STATUS 0x00A4
  1592. #define ASC_MC_IDLE_CMD 0x00A6
  1593. #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
  1594. #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
  1595. #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
  1596. #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
  1597. #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
  1598. #define ASC_MC_SDTR_DONE 0x00B6
  1599. #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
  1600. #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
  1601. #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
  1602. #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
  1603. #define ASC_MC_WDTR_DONE 0x0124
  1604. #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
  1605. #define ASC_MC_ICQ 0x0160
  1606. #define ASC_MC_IRQ 0x0164
  1607. #define ASC_MC_PPR_ABLE 0x017A
  1608. /*
  1609. * BIOS LRAM variable absolute offsets.
  1610. */
  1611. #define BIOS_CODESEG 0x54
  1612. #define BIOS_CODELEN 0x56
  1613. #define BIOS_SIGNATURE 0x58
  1614. #define BIOS_VERSION 0x5A
  1615. /*
  1616. * Microcode Control Flags
  1617. *
  1618. * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
  1619. * and handled by the microcode.
  1620. */
  1621. #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
  1622. #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
  1623. /*
  1624. * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
  1625. */
  1626. #define HSHK_CFG_WIDE_XFR 0x8000
  1627. #define HSHK_CFG_RATE 0x0F00
  1628. #define HSHK_CFG_OFFSET 0x001F
  1629. #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
  1630. #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
  1631. #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
  1632. #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
  1633. #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
  1634. #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
  1635. #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
  1636. #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
  1637. #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
  1638. #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
  1639. #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
  1640. #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
  1641. #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
  1642. #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
  1643. /*
  1644. * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
  1645. * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
  1646. */
  1647. #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
  1648. #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
  1649. /*
  1650. * All fields here are accessed by the board microcode and need to be
  1651. * little-endian.
  1652. */
  1653. typedef struct adv_carr_t {
  1654. ADV_VADDR carr_va; /* Carrier Virtual Address */
  1655. ADV_PADDR carr_pa; /* Carrier Physical Address */
  1656. ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
  1657. /*
  1658. * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
  1659. *
  1660. * next_vpa [3:1] Reserved Bits
  1661. * next_vpa [0] Done Flag set in Response Queue.
  1662. */
  1663. ADV_VADDR next_vpa;
  1664. } ADV_CARR_T;
  1665. /*
  1666. * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
  1667. */
  1668. #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
  1669. #define ASC_RQ_DONE 0x00000001
  1670. #define ASC_RQ_GOOD 0x00000002
  1671. #define ASC_CQ_STOPPER 0x00000000
  1672. #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
  1673. #define ADV_CARRIER_NUM_PAGE_CROSSING \
  1674. (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
  1675. (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
  1676. #define ADV_CARRIER_BUFSIZE \
  1677. ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
  1678. /*
  1679. * ASC_SCSI_REQ_Q 'a_flag' definitions
  1680. *
  1681. * The Adv Library should limit use to the lower nibble (4 bits) of
  1682. * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
  1683. */
  1684. #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
  1685. #define ADV_SCSIQ_DONE 0x02 /* request done */
  1686. #define ADV_DONT_RETRY 0x08 /* don't do retry */
  1687. #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
  1688. #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
  1689. #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
  1690. /*
  1691. * Adapter temporary configuration structure
  1692. *
  1693. * This structure can be discarded after initialization. Don't add
  1694. * fields here needed after initialization.
  1695. *
  1696. * Field naming convention:
  1697. *
  1698. * *_enable indicates the field enables or disables a feature. The
  1699. * value of the field is never reset.
  1700. */
  1701. typedef struct adv_dvc_cfg {
  1702. ushort disc_enable; /* enable disconnection */
  1703. uchar chip_version; /* chip version */
  1704. uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
  1705. ushort control_flag; /* Microcode Control Flag */
  1706. ushort mcode_date; /* Microcode date */
  1707. ushort mcode_version; /* Microcode version */
  1708. ushort serial1; /* EEPROM serial number word 1 */
  1709. ushort serial2; /* EEPROM serial number word 2 */
  1710. ushort serial3; /* EEPROM serial number word 3 */
  1711. } ADV_DVC_CFG;
  1712. struct adv_dvc_var;
  1713. struct adv_scsi_req_q;
  1714. /*
  1715. * Adapter operation variable structure.
  1716. *
  1717. * One structure is required per host adapter.
  1718. *
  1719. * Field naming convention:
  1720. *
  1721. * *_able indicates both whether a feature should be enabled or disabled
  1722. * and whether a device isi capable of the feature. At initialization
  1723. * this field may be set, but later if a device is found to be incapable
  1724. * of the feature, the field is cleared.
  1725. */
  1726. typedef struct adv_dvc_var {
  1727. AdvPortAddr iop_base; /* I/O port address */
  1728. ushort err_code; /* fatal error code */
  1729. ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
  1730. ushort wdtr_able; /* try WDTR for a device */
  1731. ushort sdtr_able; /* try SDTR for a device */
  1732. ushort ultra_able; /* try SDTR Ultra speed for a device */
  1733. ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
  1734. ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
  1735. ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
  1736. ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
  1737. ushort tagqng_able; /* try tagged queuing with a device */
  1738. ushort ppr_able; /* PPR message capable per TID bitmask. */
  1739. uchar max_dvc_qng; /* maximum number of tagged commands per device */
  1740. ushort start_motor; /* start motor command allowed */
  1741. uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
  1742. uchar chip_no; /* should be assigned by caller */
  1743. uchar max_host_qng; /* maximum number of Q'ed command allowed */
  1744. ushort no_scam; /* scam_tolerant of EEPROM */
  1745. struct asc_board *drv_ptr; /* driver pointer to private structure */
  1746. uchar chip_scsi_id; /* chip SCSI target ID */
  1747. uchar chip_type;
  1748. uchar bist_err_code;
  1749. ADV_CARR_T *carrier_buf;
  1750. ADV_CARR_T *carr_freelist; /* Carrier free list. */
  1751. ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
  1752. ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
  1753. ushort carr_pending_cnt; /* Count of pending carriers. */
  1754. /*
  1755. * Note: The following fields will not be used after initialization. The
  1756. * driver may discard the buffer after initialization is done.
  1757. */
  1758. ADV_DVC_CFG *cfg; /* temporary configuration structure */
  1759. } ADV_DVC_VAR;
  1760. #define NO_OF_SG_PER_BLOCK 15
  1761. typedef struct asc_sg_block {
  1762. uchar reserved1;
  1763. uchar reserved2;
  1764. uchar reserved3;
  1765. uchar sg_cnt; /* Valid entries in block. */
  1766. ADV_PADDR sg_ptr; /* Pointer to next sg block. */
  1767. struct {
  1768. ADV_PADDR sg_addr; /* SG element address. */
  1769. ADV_DCNT sg_count; /* SG element count. */
  1770. } sg_list[NO_OF_SG_PER_BLOCK];
  1771. } ADV_SG_BLOCK;
  1772. /*
  1773. * ADV_SCSI_REQ_Q - microcode request structure
  1774. *
  1775. * All fields in this structure up to byte 60 are used by the microcode.
  1776. * The microcode makes assumptions about the size and ordering of fields
  1777. * in this structure. Do not change the structure definition here without
  1778. * coordinating the change with the microcode.
  1779. *
  1780. * All fields accessed by microcode must be maintained in little_endian
  1781. * order.
  1782. */
  1783. typedef struct adv_scsi_req_q {
  1784. uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
  1785. uchar target_cmd;
  1786. uchar target_id; /* Device target identifier. */
  1787. uchar target_lun; /* Device target logical unit number. */
  1788. ADV_PADDR data_addr; /* Data buffer physical address. */
  1789. ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
  1790. ADV_PADDR sense_addr;
  1791. ADV_PADDR carr_pa;
  1792. uchar mflag;
  1793. uchar sense_len;
  1794. uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
  1795. uchar scsi_cntl;
  1796. uchar done_status; /* Completion status. */
  1797. uchar scsi_status; /* SCSI status byte. */
  1798. uchar host_status; /* Ucode host status. */
  1799. uchar sg_working_ix;
  1800. uchar cdb[12]; /* SCSI CDB bytes 0-11. */
  1801. ADV_PADDR sg_real_addr; /* SG list physical address. */
  1802. ADV_PADDR scsiq_rptr;
  1803. uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
  1804. ADV_VADDR scsiq_ptr;
  1805. ADV_VADDR carr_va;
  1806. /*
  1807. * End of microcode structure - 60 bytes. The rest of the structure
  1808. * is used by the Adv Library and ignored by the microcode.
  1809. */
  1810. ADV_VADDR srb_ptr;
  1811. ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
  1812. char *vdata_addr; /* Data buffer virtual address. */
  1813. uchar a_flag;
  1814. uchar pad[2]; /* Pad out to a word boundary. */
  1815. } ADV_SCSI_REQ_Q;
  1816. /*
  1817. * Microcode idle loop commands
  1818. */
  1819. #define IDLE_CMD_COMPLETED 0
  1820. #define IDLE_CMD_STOP_CHIP 0x0001
  1821. #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
  1822. #define IDLE_CMD_SEND_INT 0x0004
  1823. #define IDLE_CMD_ABORT 0x0008
  1824. #define IDLE_CMD_DEVICE_RESET 0x0010
  1825. #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
  1826. #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
  1827. #define IDLE_CMD_SCSIREQ 0x0080
  1828. #define IDLE_CMD_STATUS_SUCCESS 0x0001
  1829. #define IDLE_CMD_STATUS_FAILURE 0x0002
  1830. /*
  1831. * AdvSendIdleCmd() flag definitions.
  1832. */
  1833. #define ADV_NOWAIT 0x01
  1834. /*
  1835. * Wait loop time out values.
  1836. */
  1837. #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
  1838. #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
  1839. #define SCSI_MAX_RETRY 10 /* retry count */
  1840. #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
  1841. #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
  1842. #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
  1843. #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
  1844. #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
  1845. /* Read byte from a register. */
  1846. #define AdvReadByteRegister(iop_base, reg_off) \
  1847. (ADV_MEM_READB((iop_base) + (reg_off)))
  1848. /* Write byte to a register. */
  1849. #define AdvWriteByteRegister(iop_base, reg_off, byte) \
  1850. (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
  1851. /* Read word (2 bytes) from a register. */
  1852. #define AdvReadWordRegister(iop_base, reg_off) \
  1853. (ADV_MEM_READW((iop_base) + (reg_off)))
  1854. /* Write word (2 bytes) to a register. */
  1855. #define AdvWriteWordRegister(iop_base, reg_off, word) \
  1856. (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
  1857. /* Write dword (4 bytes) to a register. */
  1858. #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
  1859. (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
  1860. /* Read byte from LRAM. */
  1861. #define AdvReadByteLram(iop_base, addr, byte) \
  1862. do { \
  1863. ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
  1864. (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
  1865. } while (0)
  1866. /* Write byte to LRAM. */
  1867. #define AdvWriteByteLram(iop_base, addr, byte) \
  1868. (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
  1869. ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
  1870. /* Read word (2 bytes) from LRAM. */
  1871. #define AdvReadWordLram(iop_base, addr, word) \
  1872. do { \
  1873. ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
  1874. (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
  1875. } while (0)
  1876. /* Write word (2 bytes) to LRAM. */
  1877. #define AdvWriteWordLram(iop_base, addr, word) \
  1878. (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
  1879. ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
  1880. /* Write little-endian double word (4 bytes) to LRAM */
  1881. /* Because of unspecified C language ordering don't use auto-increment. */
  1882. #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
  1883. ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
  1884. ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
  1885. cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
  1886. (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
  1887. ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
  1888. cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
  1889. /* Read word (2 bytes) from LRAM assuming that the address is already set. */
  1890. #define AdvReadWordAutoIncLram(iop_base) \
  1891. (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
  1892. /* Write word (2 bytes) to LRAM assuming that the address is already set. */
  1893. #define AdvWriteWordAutoIncLram(iop_base, word) \
  1894. (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
  1895. /*
  1896. * Define macro to check for Condor signature.
  1897. *
  1898. * Evaluate to ADV_TRUE if a Condor chip is found the specified port
  1899. * address 'iop_base'. Otherwise evalue to ADV_FALSE.
  1900. */
  1901. #define AdvFindSignature(iop_base) \
  1902. (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
  1903. ADV_CHIP_ID_BYTE) && \
  1904. (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
  1905. ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
  1906. /*
  1907. * Define macro to Return the version number of the chip at 'iop_base'.
  1908. *
  1909. * The second parameter 'bus_type' is currently unused.
  1910. */
  1911. #define AdvGetChipVersion(iop_base, bus_type) \
  1912. AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
  1913. /*
  1914. * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
  1915. * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
  1916. *
  1917. * If the request has not yet been sent to the device it will simply be
  1918. * aborted from RISC memory. If the request is disconnected it will be
  1919. * aborted on reselection by sending an Abort Message to the target ID.
  1920. *
  1921. * Return value:
  1922. * ADV_TRUE(1) - Queue was successfully aborted.
  1923. * ADV_FALSE(0) - Queue was not found on the active queue list.
  1924. */
  1925. #define AdvAbortQueue(asc_dvc, scsiq) \
  1926. AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
  1927. (ADV_DCNT) (scsiq))
  1928. /*
  1929. * Send a Bus Device Reset Message to the specified target ID.
  1930. *
  1931. * All outstanding commands will be purged if sending the
  1932. * Bus Device Reset Message is successful.
  1933. *
  1934. * Return Value:
  1935. * ADV_TRUE(1) - All requests on the target are purged.
  1936. * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
  1937. * are not purged.
  1938. */
  1939. #define AdvResetDevice(asc_dvc, target_id) \
  1940. AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
  1941. (ADV_DCNT) (target_id))
  1942. /*
  1943. * SCSI Wide Type definition.
  1944. */
  1945. #define ADV_SCSI_BIT_ID_TYPE ushort
  1946. /*
  1947. * AdvInitScsiTarget() 'cntl_flag' options.
  1948. */
  1949. #define ADV_SCAN_LUN 0x01
  1950. #define ADV_CAPINFO_NOLUN 0x02
  1951. /*
  1952. * Convert target id to target id bit mask.
  1953. */
  1954. #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
  1955. /*
  1956. * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
  1957. */
  1958. #define QD_NO_STATUS 0x00 /* Request not completed yet. */
  1959. #define QD_NO_ERROR 0x01
  1960. #define QD_ABORTED_BY_HOST 0x02
  1961. #define QD_WITH_ERROR 0x04
  1962. #define QHSTA_NO_ERROR 0x00
  1963. #define QHSTA_M_SEL_TIMEOUT 0x11
  1964. #define QHSTA_M_DATA_OVER_RUN 0x12
  1965. #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
  1966. #define QHSTA_M_QUEUE_ABORTED 0x15
  1967. #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
  1968. #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
  1969. #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
  1970. #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
  1971. #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
  1972. #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
  1973. #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
  1974. /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
  1975. #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
  1976. #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
  1977. #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
  1978. #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
  1979. #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
  1980. #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
  1981. #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
  1982. #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
  1983. #define QHSTA_M_WTM_TIMEOUT 0x41
  1984. #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
  1985. #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
  1986. #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
  1987. #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
  1988. #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
  1989. #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
  1990. /*
  1991. * DvcGetPhyAddr() flag arguments
  1992. */
  1993. #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
  1994. #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
  1995. #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
  1996. #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
  1997. #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
  1998. #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
  1999. /* Return the address that is aligned at the next doubleword >= to 'addr'. */
  2000. #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
  2001. #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
  2002. #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
  2003. /*
  2004. * Total contiguous memory needed for driver SG blocks.
  2005. *
  2006. * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
  2007. * number of scatter-gather elements the driver supports in a
  2008. * single request.
  2009. */
  2010. #define ADV_SG_LIST_MAX_BYTE_SIZE \
  2011. (sizeof(ADV_SG_BLOCK) * \
  2012. ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
  2013. /* struct asc_board flags */
  2014. #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
  2015. #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
  2016. #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
  2017. #define ASC_INFO_SIZE 128 /* advansys_info() line size */
  2018. #ifdef CONFIG_PROC_FS
  2019. /* /proc/scsi/advansys/[0...] related definitions */
  2020. #define ASC_PRTBUF_SIZE 2048
  2021. #define ASC_PRTLINE_SIZE 160
  2022. #define ASC_PRT_NEXT() \
  2023. if (cp) { \
  2024. totlen += len; \
  2025. leftlen -= len; \
  2026. if (leftlen == 0) { \
  2027. return totlen; \
  2028. } \
  2029. cp += len; \
  2030. }
  2031. #endif /* CONFIG_PROC_FS */
  2032. /* Asc Library return codes */
  2033. #define ASC_TRUE 1
  2034. #define ASC_FALSE 0
  2035. #define ASC_NOERROR 1
  2036. #define ASC_BUSY 0
  2037. #define ASC_ERROR (-1)
  2038. /* struct scsi_cmnd function return codes */
  2039. #define STATUS_BYTE(byte) (byte)
  2040. #define MSG_BYTE(byte) ((byte) << 8)
  2041. #define HOST_BYTE(byte) ((byte) << 16)
  2042. #define DRIVER_BYTE(byte) ((byte) << 24)
  2043. #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
  2044. #ifndef ADVANSYS_STATS
  2045. #define ASC_STATS_ADD(shost, counter, count)
  2046. #else /* ADVANSYS_STATS */
  2047. #define ASC_STATS_ADD(shost, counter, count) \
  2048. (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
  2049. #endif /* ADVANSYS_STATS */
  2050. #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
  2051. /* If the result wraps when calculating tenths, return 0. */
  2052. #define ASC_TENTHS(num, den) \
  2053. (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
  2054. 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
  2055. /*
  2056. * Display a message to the console.
  2057. */
  2058. #define ASC_PRINT(s) \
  2059. { \
  2060. printk("advansys: "); \
  2061. printk(s); \
  2062. }
  2063. #define ASC_PRINT1(s, a1) \
  2064. { \
  2065. printk("advansys: "); \
  2066. printk((s), (a1)); \
  2067. }
  2068. #define ASC_PRINT2(s, a1, a2) \
  2069. { \
  2070. printk("advansys: "); \
  2071. printk((s), (a1), (a2)); \
  2072. }
  2073. #define ASC_PRINT3(s, a1, a2, a3) \
  2074. { \
  2075. printk("advansys: "); \
  2076. printk((s), (a1), (a2), (a3)); \
  2077. }
  2078. #define ASC_PRINT4(s, a1, a2, a3, a4) \
  2079. { \
  2080. printk("advansys: "); \
  2081. printk((s), (a1), (a2), (a3), (a4)); \
  2082. }
  2083. #ifndef ADVANSYS_DEBUG
  2084. #define ASC_DBG(lvl, s)
  2085. #define ASC_DBG1(lvl, s, a1)
  2086. #define ASC_DBG2(lvl, s, a1, a2)
  2087. #define ASC_DBG3(lvl, s, a1, a2, a3)
  2088. #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
  2089. #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
  2090. #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
  2091. #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
  2092. #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
  2093. #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
  2094. #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
  2095. #define ASC_DBG_PRT_HEX(lvl, name, start, length)
  2096. #define ASC_DBG_PRT_CDB(lvl, cdb, len)
  2097. #define ASC_DBG_PRT_SENSE(lvl, sense, len)
  2098. #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
  2099. #else /* ADVANSYS_DEBUG */
  2100. /*
  2101. * Debugging Message Levels:
  2102. * 0: Errors Only
  2103. * 1: High-Level Tracing
  2104. * 2-N: Verbose Tracing
  2105. */
  2106. #define ASC_DBG(lvl, s) \
  2107. { \
  2108. if (asc_dbglvl >= (lvl)) { \
  2109. printk(s); \
  2110. } \
  2111. }
  2112. #define ASC_DBG1(lvl, s, a1) \
  2113. { \
  2114. if (asc_dbglvl >= (lvl)) { \
  2115. printk((s), (a1)); \
  2116. } \
  2117. }
  2118. #define ASC_DBG2(lvl, s, a1, a2) \
  2119. { \
  2120. if (asc_dbglvl >= (lvl)) { \
  2121. printk((s), (a1), (a2)); \
  2122. } \
  2123. }
  2124. #define ASC_DBG3(lvl, s, a1, a2, a3) \
  2125. { \
  2126. if (asc_dbglvl >= (lvl)) { \
  2127. printk((s), (a1), (a2), (a3)); \
  2128. } \
  2129. }
  2130. #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
  2131. { \
  2132. if (asc_dbglvl >= (lvl)) { \
  2133. printk((s), (a1), (a2), (a3), (a4)); \
  2134. } \
  2135. }
  2136. #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
  2137. { \
  2138. if (asc_dbglvl >= (lvl)) { \
  2139. asc_prt_scsi_host(s); \
  2140. } \
  2141. }
  2142. #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
  2143. { \
  2144. if (asc_dbglvl >= (lvl)) { \
  2145. asc_prt_scsi_cmnd(s); \
  2146. } \
  2147. }
  2148. #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
  2149. { \
  2150. if (asc_dbglvl >= (lvl)) { \
  2151. asc_prt_asc_scsi_q(scsiqp); \
  2152. } \
  2153. }
  2154. #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
  2155. { \
  2156. if (asc_dbglvl >= (lvl)) { \
  2157. asc_prt_asc_qdone_info(qdone); \
  2158. } \
  2159. }
  2160. #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
  2161. { \
  2162. if (asc_dbglvl >= (lvl)) { \
  2163. asc_prt_adv_scsi_req_q(scsiqp); \
  2164. } \
  2165. }
  2166. #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
  2167. { \
  2168. if (asc_dbglvl >= (lvl)) { \
  2169. asc_prt_hex((name), (start), (length)); \
  2170. } \
  2171. }
  2172. #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
  2173. ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
  2174. #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
  2175. ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
  2176. #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
  2177. ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
  2178. #endif /* ADVANSYS_DEBUG */
  2179. #ifdef ADVANSYS_STATS
  2180. /* Per board statistics structure */
  2181. struct asc_stats {
  2182. /* Driver Entrypoint Statistics */
  2183. ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
  2184. ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
  2185. ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
  2186. ADV_DCNT interrupt; /* # advansys_interrupt() calls */
  2187. ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
  2188. ADV_DCNT done; /* # calls to request's scsi_done function */
  2189. ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
  2190. ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
  2191. ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
  2192. /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
  2193. ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
  2194. ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
  2195. ADV_DCNT exe_error; /* # ASC_ERROR returns. */
  2196. ADV_DCNT exe_unknown; /* # unknown returns. */
  2197. /* Data Transfer Statistics */
  2198. ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
  2199. ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
  2200. ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
  2201. ADV_DCNT sg_elem; /* # scatter-gather elements */
  2202. ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
  2203. };
  2204. #endif /* ADVANSYS_STATS */
  2205. /*
  2206. * Adv Library Request Structures
  2207. *
  2208. * The following two structures are used to process Wide Board requests.
  2209. *
  2210. * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
  2211. * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
  2212. * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
  2213. * Mid-Level SCSI request structure.
  2214. *
  2215. * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
  2216. * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
  2217. * up to 255 scatter-gather elements may be used per request or
  2218. * ADV_SCSI_REQ_Q.
  2219. *
  2220. * Both structures must be 32 byte aligned.
  2221. */
  2222. typedef struct adv_sgblk {
  2223. ADV_SG_BLOCK sg_block; /* Sgblock structure. */
  2224. uchar align[32]; /* Sgblock structure padding. */
  2225. struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
  2226. } adv_sgblk_t;
  2227. typedef struct adv_req {
  2228. ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
  2229. uchar align[32]; /* Request structure padding. */
  2230. struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
  2231. adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
  2232. struct adv_req *next_reqp; /* Next Request Structure. */
  2233. } adv_req_t;
  2234. /*
  2235. * Structure allocated for each board.
  2236. *
  2237. * This structure is allocated by scsi_host_alloc() at the end
  2238. * of the 'Scsi_Host' structure starting at the 'hostdata'
  2239. * field. It is guaranteed to be allocated from DMA-able memory.
  2240. */
  2241. struct asc_board {
  2242. struct device *dev;
  2243. int id; /* Board Id */
  2244. uint flags; /* Board flags */
  2245. unsigned int irq;
  2246. union {
  2247. ASC_DVC_VAR asc_dvc_var; /* Narrow board */
  2248. ADV_DVC_VAR adv_dvc_var; /* Wide board */
  2249. } dvc_var;
  2250. union {
  2251. ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
  2252. ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
  2253. } dvc_cfg;
  2254. ushort asc_n_io_port; /* Number I/O ports. */
  2255. ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
  2256. ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
  2257. ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
  2258. ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
  2259. union {
  2260. ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
  2261. ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
  2262. ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
  2263. ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
  2264. } eep_config;
  2265. ulong last_reset; /* Saved last reset time */
  2266. spinlock_t lock; /* Board spinlock */
  2267. /* /proc/scsi/advansys/[0...] */
  2268. char *prtbuf; /* /proc print buffer */
  2269. #ifdef ADVANSYS_STATS
  2270. struct asc_stats asc_stats; /* Board statistics */
  2271. #endif /* ADVANSYS_STATS */
  2272. /*
  2273. * The following fields are used only for Narrow Boards.
  2274. */
  2275. uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
  2276. /*
  2277. * The following fields are used only for Wide Boards.
  2278. */
  2279. void __iomem *ioremap_addr; /* I/O Memory remap address. */
  2280. ushort ioport; /* I/O Port address. */
  2281. ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */
  2282. adv_req_t *orig_reqp; /* adv_req_t memory block. */
  2283. adv_req_t *adv_reqp; /* Request structures. */
  2284. adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
  2285. ushort bios_signature; /* BIOS Signature. */
  2286. ushort bios_version; /* BIOS Version. */
  2287. ushort bios_codeseg; /* BIOS Code Segment. */
  2288. ushort bios_codelen; /* BIOS Code Segment Length. */
  2289. };
  2290. #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
  2291. dvc_var.adv_dvc_var)
  2292. #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
  2293. /* Number of boards detected in system. */
  2294. static int asc_board_count;
  2295. /* Overrun buffer used by all narrow boards. */
  2296. static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
  2297. #ifdef ADVANSYS_DEBUG
  2298. static int asc_dbglvl = 3;
  2299. /*
  2300. * asc_prt_scsi_host()
  2301. */
  2302. static void asc_prt_scsi_host(struct Scsi_Host *s)
  2303. {
  2304. struct asc_board *boardp = shost_priv(s);
  2305. printk("Scsi_Host at addr 0x%lx\n", (ulong)s);
  2306. printk(" host_busy %u, host_no %d, last_reset %d,\n",
  2307. s->host_busy, s->host_no, (unsigned)s->last_reset);
  2308. printk(" base 0x%lx, io_port 0x%lx, irq 0x%x,\n",
  2309. (ulong)s->base, (ulong)s->io_port, boardp->irq);
  2310. printk(" dma_channel %d, this_id %d, can_queue %d,\n",
  2311. s->dma_channel, s->this_id, s->can_queue);
  2312. printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
  2313. s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
  2314. if (ASC_NARROW_BOARD(boardp)) {
  2315. asc_prt_asc_dvc_var(boardp->dvc_var.asc_dvc_var);
  2316. asc_prt_asc_dvc_cfg(boardp->dvc_cfg.asc_dvc_cfg);
  2317. } else {
  2318. asc_prt_adv_dvc_var(boardp->dvc_var.adv_dvc_var);
  2319. asc_prt_adv_dvc_cfg(boardp->dvc_cfg.adv_dvc_cfg);
  2320. }
  2321. }
  2322. /*
  2323. * asc_prt_scsi_cmnd()
  2324. */
  2325. static void asc_prt_scsi_cmnd(struct scsi_cmnd *s)
  2326. {
  2327. printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s);
  2328. printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
  2329. (ulong)s->device->host, (ulong)s->device, s->device->id,
  2330. s->device->lun, s->device->channel);
  2331. asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
  2332. printk("sc_data_direction %u, resid %d\n",
  2333. s->sc_data_direction, s->resid);
  2334. printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len);
  2335. printk(" serial_number 0x%x, retries %d, allowed %d\n",
  2336. (unsigned)s->serial_number, s->retries, s->allowed);
  2337. printk(" timeout_per_command %d\n", s->timeout_per_command);
  2338. printk(" scsi_done 0x%p, done 0x%p, host_scribble 0x%p, result 0x%x\n",
  2339. s->scsi_done, s->done, s->host_scribble, s->result);
  2340. printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid);
  2341. }
  2342. /*
  2343. * asc_prt_asc_dvc_var()
  2344. */
  2345. static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
  2346. {
  2347. printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
  2348. printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
  2349. "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
  2350. printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
  2351. (unsigned)h->init_sdtr);
  2352. printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
  2353. "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
  2354. (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
  2355. (unsigned)h->chip_no);
  2356. printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
  2357. "%u,\n", (unsigned)h->queue_full_or_busy,
  2358. (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
  2359. printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
  2360. "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
  2361. (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
  2362. (unsigned)h->in_critical_cnt);
  2363. printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
  2364. "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
  2365. (unsigned)h->init_state, (unsigned)h->no_scam,
  2366. (unsigned)h->pci_fix_asyn_xfer);
  2367. printk(" cfg 0x%lx\n", (ulong)h->cfg);
  2368. }
  2369. /*
  2370. * asc_prt_asc_dvc_cfg()
  2371. */
  2372. static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
  2373. {
  2374. printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
  2375. printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
  2376. h->can_tagged_qng, h->cmd_qng_enabled);
  2377. printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
  2378. h->disc_enable, h->sdtr_enable);
  2379. printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
  2380. "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
  2381. h->isa_dma_channel, h->chip_version);
  2382. printk(" pci_device_id %d, mcode_date 0x%x, mcode_version %d, "
  2383. "overrun_buf 0x%p\n", to_pci_dev(h->dev)->device,
  2384. h->mcode_date, h->mcode_version, h->overrun_buf);
  2385. }
  2386. /*
  2387. * asc_prt_asc_scsi_q()
  2388. */
  2389. static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
  2390. {
  2391. ASC_SG_HEAD *sgp;
  2392. int i;
  2393. printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
  2394. printk
  2395. (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
  2396. q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
  2397. q->q2.tag_code);
  2398. printk
  2399. (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
  2400. (ulong)le32_to_cpu(q->q1.data_addr),
  2401. (ulong)le32_to_cpu(q->q1.data_cnt),
  2402. (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
  2403. printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
  2404. (ulong)q->cdbptr, q->q2.cdb_len,
  2405. (ulong)q->sg_head, q->q1.sg_queue_cnt);
  2406. if (q->sg_head) {
  2407. sgp = q->sg_head;
  2408. printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
  2409. printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
  2410. sgp->queue_cnt);
  2411. for (i = 0; i < sgp->entry_cnt; i++) {
  2412. printk(" [%u]: addr 0x%lx, bytes %lu\n",
  2413. i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
  2414. (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
  2415. }
  2416. }
  2417. }
  2418. /*
  2419. * asc_prt_asc_qdone_info()
  2420. */
  2421. static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
  2422. {
  2423. printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
  2424. printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
  2425. (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
  2426. q->d2.tag_code);
  2427. printk
  2428. (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
  2429. q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
  2430. }
  2431. /*
  2432. * asc_prt_adv_dvc_var()
  2433. *
  2434. * Display an ADV_DVC_VAR structure.
  2435. */
  2436. static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
  2437. {
  2438. printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
  2439. printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
  2440. (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
  2441. printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
  2442. (ulong)h->isr_callback, (unsigned)h->sdtr_able,
  2443. (unsigned)h->wdtr_able);
  2444. printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
  2445. (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
  2446. printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
  2447. (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
  2448. (ulong)h->carr_freelist);
  2449. printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
  2450. (ulong)h->icq_sp, (ulong)h->irq_sp);
  2451. printk(" no_scam 0x%x, tagqng_able 0x%x\n",
  2452. (unsigned)h->no_scam, (unsigned)h->tagqng_able);
  2453. printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
  2454. (unsigned)h->chip_scsi_id, (ulong)h->cfg);
  2455. }
  2456. /*
  2457. * asc_prt_adv_dvc_cfg()
  2458. *
  2459. * Display an ADV_DVC_CFG structure.
  2460. */
  2461. static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
  2462. {
  2463. printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
  2464. printk(" disc_enable 0x%x, termination 0x%x\n",
  2465. h->disc_enable, h->termination);
  2466. printk(" chip_version 0x%x, mcode_date 0x%x\n",
  2467. h->chip_version, h->mcode_date);
  2468. printk(" mcode_version 0x%x, pci_device_id 0x%x\n",
  2469. h->mcode_version, to_pci_dev(h->dev)->device);
  2470. printk(" control_flag 0x%x\n", h->control_flag);
  2471. }
  2472. /*
  2473. * asc_prt_adv_scsi_req_q()
  2474. *
  2475. * Display an ADV_SCSI_REQ_Q structure.
  2476. */
  2477. static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
  2478. {
  2479. int sg_blk_cnt;
  2480. struct asc_sg_block *sg_ptr;
  2481. printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
  2482. printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
  2483. q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
  2484. printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
  2485. q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
  2486. printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
  2487. (ulong)le32_to_cpu(q->data_cnt),
  2488. (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
  2489. printk
  2490. (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
  2491. q->cdb_len, q->done_status, q->host_status, q->scsi_status);
  2492. printk(" sg_working_ix 0x%x, target_cmd %u\n",
  2493. q->sg_working_ix, q->target_cmd);
  2494. printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
  2495. (ulong)le32_to_cpu(q->scsiq_rptr),
  2496. (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
  2497. /* Display the request's ADV_SG_BLOCK structures. */
  2498. if (q->sg_list_ptr != NULL) {
  2499. sg_blk_cnt = 0;
  2500. while (1) {
  2501. /*
  2502. * 'sg_ptr' is a physical address. Convert it to a virtual
  2503. * address by indexing 'sg_blk_cnt' into the virtual address
  2504. * array 'sg_list_ptr'.
  2505. *
  2506. * XXX - Assumes all SG physical blocks are virtually contiguous.
  2507. */
  2508. sg_ptr =
  2509. &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
  2510. asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
  2511. if (sg_ptr->sg_ptr == 0) {
  2512. break;
  2513. }
  2514. sg_blk_cnt++;
  2515. }
  2516. }
  2517. }
  2518. /*
  2519. * asc_prt_adv_sgblock()
  2520. *
  2521. * Display an ADV_SG_BLOCK structure.
  2522. */
  2523. static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
  2524. {
  2525. int i;
  2526. printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
  2527. (ulong)b, sgblockno);
  2528. printk(" sg_cnt %u, sg_ptr 0x%lx\n",
  2529. b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
  2530. BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
  2531. if (b->sg_ptr != 0)
  2532. BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
  2533. for (i = 0; i < b->sg_cnt; i++) {
  2534. printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
  2535. i, (ulong)b->sg_list[i].sg_addr,
  2536. (ulong)b->sg_list[i].sg_count);
  2537. }
  2538. }
  2539. /*
  2540. * asc_prt_hex()
  2541. *
  2542. * Print hexadecimal output in 4 byte groupings 32 bytes
  2543. * or 8 double-words per line.
  2544. */
  2545. static void asc_prt_hex(char *f, uchar *s, int l)
  2546. {
  2547. int i;
  2548. int j;
  2549. int k;
  2550. int m;
  2551. printk("%s: (%d bytes)\n", f, l);
  2552. for (i = 0; i < l; i += 32) {
  2553. /* Display a maximum of 8 double-words per line. */
  2554. if ((k = (l - i) / 4) >= 8) {
  2555. k = 8;
  2556. m = 0;
  2557. } else {
  2558. m = (l - i) % 4;
  2559. }
  2560. for (j = 0; j < k; j++) {
  2561. printk(" %2.2X%2.2X%2.2X%2.2X",
  2562. (unsigned)s[i + (j * 4)],
  2563. (unsigned)s[i + (j * 4) + 1],
  2564. (unsigned)s[i + (j * 4) + 2],
  2565. (unsigned)s[i + (j * 4) + 3]);
  2566. }
  2567. switch (m) {
  2568. case 0:
  2569. default:
  2570. break;
  2571. case 1:
  2572. printk(" %2.2X", (unsigned)s[i + (j * 4)]);
  2573. break;
  2574. case 2:
  2575. printk(" %2.2X%2.2X",
  2576. (unsigned)s[i + (j * 4)],
  2577. (unsigned)s[i + (j * 4) + 1]);
  2578. break;
  2579. case 3:
  2580. printk(" %2.2X%2.2X%2.2X",
  2581. (unsigned)s[i + (j * 4) + 1],
  2582. (unsigned)s[i + (j * 4) + 2],
  2583. (unsigned)s[i + (j * 4) + 3]);
  2584. break;
  2585. }
  2586. printk("\n");
  2587. }
  2588. }
  2589. #endif /* ADVANSYS_DEBUG */
  2590. /*
  2591. * advansys_info()
  2592. *
  2593. * Return suitable for printing on the console with the argument
  2594. * adapter's configuration information.
  2595. *
  2596. * Note: The information line should not exceed ASC_INFO_SIZE bytes,
  2597. * otherwise the static 'info' array will be overrun.
  2598. */
  2599. static const char *advansys_info(struct Scsi_Host *shost)
  2600. {
  2601. static char info[ASC_INFO_SIZE];
  2602. struct asc_board *boardp = shost_priv(shost);
  2603. ASC_DVC_VAR *asc_dvc_varp;
  2604. ADV_DVC_VAR *adv_dvc_varp;
  2605. char *busname;
  2606. char *widename = NULL;
  2607. if (ASC_NARROW_BOARD(boardp)) {
  2608. asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
  2609. ASC_DBG(1, "advansys_info: begin\n");
  2610. if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
  2611. if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
  2612. ASC_IS_ISAPNP) {
  2613. busname = "ISA PnP";
  2614. } else {
  2615. busname = "ISA";
  2616. }
  2617. sprintf(info,
  2618. "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
  2619. ASC_VERSION, busname,
  2620. (ulong)shost->io_port,
  2621. (ulong)shost->io_port + ASC_IOADR_GAP - 1,
  2622. boardp->irq, shost->dma_channel);
  2623. } else {
  2624. if (asc_dvc_varp->bus_type & ASC_IS_VL) {
  2625. busname = "VL";
  2626. } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
  2627. busname = "EISA";
  2628. } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
  2629. if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
  2630. == ASC_IS_PCI_ULTRA) {
  2631. busname = "PCI Ultra";
  2632. } else {
  2633. busname = "PCI";
  2634. }
  2635. } else {
  2636. busname = "?";
  2637. ASC_PRINT2("advansys_info: board %d: unknown "
  2638. "bus type %d\n", boardp->id,
  2639. asc_dvc_varp->bus_type);
  2640. }
  2641. sprintf(info,
  2642. "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
  2643. ASC_VERSION, busname, (ulong)shost->io_port,
  2644. (ulong)shost->io_port + ASC_IOADR_GAP - 1,
  2645. boardp->irq);
  2646. }
  2647. } else {
  2648. /*
  2649. * Wide Adapter Information
  2650. *
  2651. * Memory-mapped I/O is used instead of I/O space to access
  2652. * the adapter, but display the I/O Port range. The Memory
  2653. * I/O address is displayed through the driver /proc file.
  2654. */
  2655. adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
  2656. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  2657. widename = "Ultra-Wide";
  2658. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  2659. widename = "Ultra2-Wide";
  2660. } else {
  2661. widename = "Ultra3-Wide";
  2662. }
  2663. sprintf(info,
  2664. "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
  2665. ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
  2666. (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
  2667. }
  2668. BUG_ON(strlen(info) >= ASC_INFO_SIZE);
  2669. ASC_DBG(1, "advansys_info: end\n");
  2670. return info;
  2671. }
  2672. #ifdef CONFIG_PROC_FS
  2673. /*
  2674. * asc_prt_line()
  2675. *
  2676. * If 'cp' is NULL print to the console, otherwise print to a buffer.
  2677. *
  2678. * Return 0 if printing to the console, otherwise return the number of
  2679. * bytes written to the buffer.
  2680. *
  2681. * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
  2682. * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
  2683. */
  2684. static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
  2685. {
  2686. va_list args;
  2687. int ret;
  2688. char s[ASC_PRTLINE_SIZE];
  2689. va_start(args, fmt);
  2690. ret = vsprintf(s, fmt, args);
  2691. BUG_ON(ret >= ASC_PRTLINE_SIZE);
  2692. if (buf == NULL) {
  2693. (void)printk(s);
  2694. ret = 0;
  2695. } else {
  2696. ret = min(buflen, ret);
  2697. memcpy(buf, s, ret);
  2698. }
  2699. va_end(args);
  2700. return ret;
  2701. }
  2702. /*
  2703. * asc_prt_board_devices()
  2704. *
  2705. * Print driver information for devices attached to the board.
  2706. *
  2707. * Note: no single line should be greater than ASC_PRTLINE_SIZE,
  2708. * cf. asc_prt_line().
  2709. *
  2710. * Return the number of characters copied into 'cp'. No more than
  2711. * 'cplen' characters will be copied to 'cp'.
  2712. */
  2713. static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
  2714. {
  2715. struct asc_board *boardp = shost_priv(shost);
  2716. int leftlen;
  2717. int totlen;
  2718. int len;
  2719. int chip_scsi_id;
  2720. int i;
  2721. leftlen = cplen;
  2722. totlen = len = 0;
  2723. len = asc_prt_line(cp, leftlen,
  2724. "\nDevice Information for AdvanSys SCSI Host %d:\n",
  2725. shost->host_no);
  2726. ASC_PRT_NEXT();
  2727. if (ASC_NARROW_BOARD(boardp)) {
  2728. chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
  2729. } else {
  2730. chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
  2731. }
  2732. len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
  2733. ASC_PRT_NEXT();
  2734. for (i = 0; i <= ADV_MAX_TID; i++) {
  2735. if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
  2736. len = asc_prt_line(cp, leftlen, " %X,", i);
  2737. ASC_PRT_NEXT();
  2738. }
  2739. }
  2740. len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
  2741. ASC_PRT_NEXT();
  2742. return totlen;
  2743. }
  2744. /*
  2745. * Display Wide Board BIOS Information.
  2746. */
  2747. static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
  2748. {
  2749. struct asc_board *boardp = shost_priv(shost);
  2750. int leftlen;
  2751. int totlen;
  2752. int len;
  2753. ushort major, minor, letter;
  2754. leftlen = cplen;
  2755. totlen = len = 0;
  2756. len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
  2757. ASC_PRT_NEXT();
  2758. /*
  2759. * If the BIOS saved a valid signature, then fill in
  2760. * the BIOS code segment base address.
  2761. */
  2762. if (boardp->bios_signature != 0x55AA) {
  2763. len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
  2764. ASC_PRT_NEXT();
  2765. len = asc_prt_line(cp, leftlen,
  2766. "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
  2767. ASC_PRT_NEXT();
  2768. len = asc_prt_line(cp, leftlen,
  2769. "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
  2770. ASC_PRT_NEXT();
  2771. } else {
  2772. major = (boardp->bios_version >> 12) & 0xF;
  2773. minor = (boardp->bios_version >> 8) & 0xF;
  2774. letter = (boardp->bios_version & 0xFF);
  2775. len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
  2776. major, minor,
  2777. letter >= 26 ? '?' : letter + 'A');
  2778. ASC_PRT_NEXT();
  2779. /*
  2780. * Current available ROM BIOS release is 3.1I for UW
  2781. * and 3.2I for U2W. This code doesn't differentiate
  2782. * UW and U2W boards.
  2783. */
  2784. if (major < 3 || (major <= 3 && minor < 1) ||
  2785. (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
  2786. len = asc_prt_line(cp, leftlen,
  2787. "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
  2788. ASC_PRT_NEXT();
  2789. len = asc_prt_line(cp, leftlen,
  2790. "ftp://ftp.connectcom.net/pub\n");
  2791. ASC_PRT_NEXT();
  2792. }
  2793. }
  2794. return totlen;
  2795. }
  2796. /*
  2797. * Add serial number to information bar if signature AAh
  2798. * is found in at bit 15-9 (7 bits) of word 1.
  2799. *
  2800. * Serial Number consists fo 12 alpha-numeric digits.
  2801. *
  2802. * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
  2803. * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
  2804. * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
  2805. * 5 - Product revision (A-J) Word0: " "
  2806. *
  2807. * Signature Word1: 15-9 (7 bits)
  2808. * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
  2809. * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
  2810. *
  2811. * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
  2812. *
  2813. * Note 1: Only production cards will have a serial number.
  2814. *
  2815. * Note 2: Signature is most significant 7 bits (0xFE).
  2816. *
  2817. * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
  2818. */
  2819. static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
  2820. {
  2821. ushort w, num;
  2822. if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
  2823. return ASC_FALSE;
  2824. } else {
  2825. /*
  2826. * First word - 6 digits.
  2827. */
  2828. w = serialnum[0];
  2829. /* Product type - 1st digit. */
  2830. if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
  2831. /* Product type is P=Prototype */
  2832. *cp += 0x8;
  2833. }
  2834. cp++;
  2835. /* Manufacturing location - 2nd digit. */
  2836. *cp++ = 'A' + ((w & 0x1C00) >> 10);
  2837. /* Product ID - 3rd, 4th digits. */
  2838. num = w & 0x3FF;
  2839. *cp++ = '0' + (num / 100);
  2840. num %= 100;
  2841. *cp++ = '0' + (num / 10);
  2842. /* Product revision - 5th digit. */
  2843. *cp++ = 'A' + (num % 10);
  2844. /*
  2845. * Second word
  2846. */
  2847. w = serialnum[1];
  2848. /*
  2849. * Year - 6th digit.
  2850. *
  2851. * If bit 15 of third word is set, then the
  2852. * last digit of the year is greater than 7.
  2853. */
  2854. if (serialnum[2] & 0x8000) {
  2855. *cp++ = '8' + ((w & 0x1C0) >> 6);
  2856. } else {
  2857. *cp++ = '0' + ((w & 0x1C0) >> 6);
  2858. }
  2859. /* Week of year - 7th, 8th digits. */
  2860. num = w & 0x003F;
  2861. *cp++ = '0' + num / 10;
  2862. num %= 10;
  2863. *cp++ = '0' + num;
  2864. /*
  2865. * Third word
  2866. */
  2867. w = serialnum[2] & 0x7FFF;
  2868. /* Serial number - 9th digit. */
  2869. *cp++ = 'A' + (w / 1000);
  2870. /* 10th, 11th, 12th digits. */
  2871. num = w % 1000;
  2872. *cp++ = '0' + num / 100;
  2873. num %= 100;
  2874. *cp++ = '0' + num / 10;
  2875. num %= 10;
  2876. *cp++ = '0' + num;
  2877. *cp = '\0'; /* Null Terminate the string. */
  2878. return ASC_TRUE;
  2879. }
  2880. }
  2881. /*
  2882. * asc_prt_asc_board_eeprom()
  2883. *
  2884. * Print board EEPROM configuration.
  2885. *
  2886. * Note: no single line should be greater than ASC_PRTLINE_SIZE,
  2887. * cf. asc_prt_line().
  2888. *
  2889. * Return the number of characters copied into 'cp'. No more than
  2890. * 'cplen' characters will be copied to 'cp'.
  2891. */
  2892. static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
  2893. {
  2894. struct asc_board *boardp = shost_priv(shost);
  2895. ASC_DVC_VAR *asc_dvc_varp;
  2896. int leftlen;
  2897. int totlen;
  2898. int len;
  2899. ASCEEP_CONFIG *ep;
  2900. int i;
  2901. #ifdef CONFIG_ISA
  2902. int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
  2903. #endif /* CONFIG_ISA */
  2904. uchar serialstr[13];
  2905. asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
  2906. ep = &boardp->eep_config.asc_eep;
  2907. leftlen = cplen;
  2908. totlen = len = 0;
  2909. len = asc_prt_line(cp, leftlen,
  2910. "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
  2911. shost->host_no);
  2912. ASC_PRT_NEXT();
  2913. if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
  2914. == ASC_TRUE) {
  2915. len =
  2916. asc_prt_line(cp, leftlen, " Serial Number: %s\n",
  2917. serialstr);
  2918. ASC_PRT_NEXT();
  2919. } else {
  2920. if (ep->adapter_info[5] == 0xBB) {
  2921. len = asc_prt_line(cp, leftlen,
  2922. " Default Settings Used for EEPROM-less Adapter.\n");
  2923. ASC_PRT_NEXT();
  2924. } else {
  2925. len = asc_prt_line(cp, leftlen,
  2926. " Serial Number Signature Not Present.\n");
  2927. ASC_PRT_NEXT();
  2928. }
  2929. }
  2930. len = asc_prt_line(cp, leftlen,
  2931. " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
  2932. ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
  2933. ep->max_tag_qng);
  2934. ASC_PRT_NEXT();
  2935. len = asc_prt_line(cp, leftlen,
  2936. " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
  2937. ASC_PRT_NEXT();
  2938. len = asc_prt_line(cp, leftlen, " Target ID: ");
  2939. ASC_PRT_NEXT();
  2940. for (i = 0; i <= ASC_MAX_TID; i++) {
  2941. len = asc_prt_line(cp, leftlen, " %d", i);
  2942. ASC_PRT_NEXT();
  2943. }
  2944. len = asc_prt_line(cp, leftlen, "\n");
  2945. ASC_PRT_NEXT();
  2946. len = asc_prt_line(cp, leftlen, " Disconnects: ");
  2947. ASC_PRT_NEXT();
  2948. for (i = 0; i <= ASC_MAX_TID; i++) {
  2949. len = asc_prt_line(cp, leftlen, " %c",
  2950. (ep->
  2951. disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  2952. 'N');
  2953. ASC_PRT_NEXT();
  2954. }
  2955. len = asc_prt_line(cp, leftlen, "\n");
  2956. ASC_PRT_NEXT();
  2957. len = asc_prt_line(cp, leftlen, " Command Queuing: ");
  2958. ASC_PRT_NEXT();
  2959. for (i = 0; i <= ASC_MAX_TID; i++) {
  2960. len = asc_prt_line(cp, leftlen, " %c",
  2961. (ep->
  2962. use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  2963. 'N');
  2964. ASC_PRT_NEXT();
  2965. }
  2966. len = asc_prt_line(cp, leftlen, "\n");
  2967. ASC_PRT_NEXT();
  2968. len = asc_prt_line(cp, leftlen, " Start Motor: ");
  2969. ASC_PRT_NEXT();
  2970. for (i = 0; i <= ASC_MAX_TID; i++) {
  2971. len = asc_prt_line(cp, leftlen, " %c",
  2972. (ep->
  2973. start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  2974. 'N');
  2975. ASC_PRT_NEXT();
  2976. }
  2977. len = asc_prt_line(cp, leftlen, "\n");
  2978. ASC_PRT_NEXT();
  2979. len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
  2980. ASC_PRT_NEXT();
  2981. for (i = 0; i <= ASC_MAX_TID; i++) {
  2982. len = asc_prt_line(cp, leftlen, " %c",
  2983. (ep->
  2984. init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  2985. 'N');
  2986. ASC_PRT_NEXT();
  2987. }
  2988. len = asc_prt_line(cp, leftlen, "\n");
  2989. ASC_PRT_NEXT();
  2990. #ifdef CONFIG_ISA
  2991. if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
  2992. len = asc_prt_line(cp, leftlen,
  2993. " Host ISA DMA speed: %d MB/S\n",
  2994. isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
  2995. ASC_PRT_NEXT();
  2996. }
  2997. #endif /* CONFIG_ISA */
  2998. return totlen;
  2999. }
  3000. /*
  3001. * asc_prt_adv_board_eeprom()
  3002. *
  3003. * Print board EEPROM configuration.
  3004. *
  3005. * Note: no single line should be greater than ASC_PRTLINE_SIZE,
  3006. * cf. asc_prt_line().
  3007. *
  3008. * Return the number of characters copied into 'cp'. No more than
  3009. * 'cplen' characters will be copied to 'cp'.
  3010. */
  3011. static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
  3012. {
  3013. struct asc_board *boardp = shost_priv(shost);
  3014. ADV_DVC_VAR *adv_dvc_varp;
  3015. int leftlen;
  3016. int totlen;
  3017. int len;
  3018. int i;
  3019. char *termstr;
  3020. uchar serialstr[13];
  3021. ADVEEP_3550_CONFIG *ep_3550 = NULL;
  3022. ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
  3023. ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
  3024. ushort word;
  3025. ushort *wordp;
  3026. ushort sdtr_speed = 0;
  3027. adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
  3028. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3029. ep_3550 = &boardp->eep_config.adv_3550_eep;
  3030. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3031. ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
  3032. } else {
  3033. ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
  3034. }
  3035. leftlen = cplen;
  3036. totlen = len = 0;
  3037. len = asc_prt_line(cp, leftlen,
  3038. "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
  3039. shost->host_no);
  3040. ASC_PRT_NEXT();
  3041. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3042. wordp = &ep_3550->serial_number_word1;
  3043. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3044. wordp = &ep_38C0800->serial_number_word1;
  3045. } else {
  3046. wordp = &ep_38C1600->serial_number_word1;
  3047. }
  3048. if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
  3049. len =
  3050. asc_prt_line(cp, leftlen, " Serial Number: %s\n",
  3051. serialstr);
  3052. ASC_PRT_NEXT();
  3053. } else {
  3054. len = asc_prt_line(cp, leftlen,
  3055. " Serial Number Signature Not Present.\n");
  3056. ASC_PRT_NEXT();
  3057. }
  3058. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3059. len = asc_prt_line(cp, leftlen,
  3060. " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
  3061. ep_3550->adapter_scsi_id,
  3062. ep_3550->max_host_qng, ep_3550->max_dvc_qng);
  3063. ASC_PRT_NEXT();
  3064. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3065. len = asc_prt_line(cp, leftlen,
  3066. " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
  3067. ep_38C0800->adapter_scsi_id,
  3068. ep_38C0800->max_host_qng,
  3069. ep_38C0800->max_dvc_qng);
  3070. ASC_PRT_NEXT();
  3071. } else {
  3072. len = asc_prt_line(cp, leftlen,
  3073. " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
  3074. ep_38C1600->adapter_scsi_id,
  3075. ep_38C1600->max_host_qng,
  3076. ep_38C1600->max_dvc_qng);
  3077. ASC_PRT_NEXT();
  3078. }
  3079. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3080. word = ep_3550->termination;
  3081. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3082. word = ep_38C0800->termination_lvd;
  3083. } else {
  3084. word = ep_38C1600->termination_lvd;
  3085. }
  3086. switch (word) {
  3087. case 1:
  3088. termstr = "Low Off/High Off";
  3089. break;
  3090. case 2:
  3091. termstr = "Low Off/High On";
  3092. break;
  3093. case 3:
  3094. termstr = "Low On/High On";
  3095. break;
  3096. default:
  3097. case 0:
  3098. termstr = "Automatic";
  3099. break;
  3100. }
  3101. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3102. len = asc_prt_line(cp, leftlen,
  3103. " termination: %u (%s), bios_ctrl: 0x%x\n",
  3104. ep_3550->termination, termstr,
  3105. ep_3550->bios_ctrl);
  3106. ASC_PRT_NEXT();
  3107. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3108. len = asc_prt_line(cp, leftlen,
  3109. " termination: %u (%s), bios_ctrl: 0x%x\n",
  3110. ep_38C0800->termination_lvd, termstr,
  3111. ep_38C0800->bios_ctrl);
  3112. ASC_PRT_NEXT();
  3113. } else {
  3114. len = asc_prt_line(cp, leftlen,
  3115. " termination: %u (%s), bios_ctrl: 0x%x\n",
  3116. ep_38C1600->termination_lvd, termstr,
  3117. ep_38C1600->bios_ctrl);
  3118. ASC_PRT_NEXT();
  3119. }
  3120. len = asc_prt_line(cp, leftlen, " Target ID: ");
  3121. ASC_PRT_NEXT();
  3122. for (i = 0; i <= ADV_MAX_TID; i++) {
  3123. len = asc_prt_line(cp, leftlen, " %X", i);
  3124. ASC_PRT_NEXT();
  3125. }
  3126. len = asc_prt_line(cp, leftlen, "\n");
  3127. ASC_PRT_NEXT();
  3128. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3129. word = ep_3550->disc_enable;
  3130. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3131. word = ep_38C0800->disc_enable;
  3132. } else {
  3133. word = ep_38C1600->disc_enable;
  3134. }
  3135. len = asc_prt_line(cp, leftlen, " Disconnects: ");
  3136. ASC_PRT_NEXT();
  3137. for (i = 0; i <= ADV_MAX_TID; i++) {
  3138. len = asc_prt_line(cp, leftlen, " %c",
  3139. (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
  3140. ASC_PRT_NEXT();
  3141. }
  3142. len = asc_prt_line(cp, leftlen, "\n");
  3143. ASC_PRT_NEXT();
  3144. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3145. word = ep_3550->tagqng_able;
  3146. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3147. word = ep_38C0800->tagqng_able;
  3148. } else {
  3149. word = ep_38C1600->tagqng_able;
  3150. }
  3151. len = asc_prt_line(cp, leftlen, " Command Queuing: ");
  3152. ASC_PRT_NEXT();
  3153. for (i = 0; i <= ADV_MAX_TID; i++) {
  3154. len = asc_prt_line(cp, leftlen, " %c",
  3155. (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
  3156. ASC_PRT_NEXT();
  3157. }
  3158. len = asc_prt_line(cp, leftlen, "\n");
  3159. ASC_PRT_NEXT();
  3160. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3161. word = ep_3550->start_motor;
  3162. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3163. word = ep_38C0800->start_motor;
  3164. } else {
  3165. word = ep_38C1600->start_motor;
  3166. }
  3167. len = asc_prt_line(cp, leftlen, " Start Motor: ");
  3168. ASC_PRT_NEXT();
  3169. for (i = 0; i <= ADV_MAX_TID; i++) {
  3170. len = asc_prt_line(cp, leftlen, " %c",
  3171. (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
  3172. ASC_PRT_NEXT();
  3173. }
  3174. len = asc_prt_line(cp, leftlen, "\n");
  3175. ASC_PRT_NEXT();
  3176. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3177. len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
  3178. ASC_PRT_NEXT();
  3179. for (i = 0; i <= ADV_MAX_TID; i++) {
  3180. len = asc_prt_line(cp, leftlen, " %c",
  3181. (ep_3550->
  3182. sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
  3183. 'Y' : 'N');
  3184. ASC_PRT_NEXT();
  3185. }
  3186. len = asc_prt_line(cp, leftlen, "\n");
  3187. ASC_PRT_NEXT();
  3188. }
  3189. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3190. len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
  3191. ASC_PRT_NEXT();
  3192. for (i = 0; i <= ADV_MAX_TID; i++) {
  3193. len = asc_prt_line(cp, leftlen, " %c",
  3194. (ep_3550->
  3195. ultra_able & ADV_TID_TO_TIDMASK(i))
  3196. ? 'Y' : 'N');
  3197. ASC_PRT_NEXT();
  3198. }
  3199. len = asc_prt_line(cp, leftlen, "\n");
  3200. ASC_PRT_NEXT();
  3201. }
  3202. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  3203. word = ep_3550->wdtr_able;
  3204. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  3205. word = ep_38C0800->wdtr_able;
  3206. } else {
  3207. word = ep_38C1600->wdtr_able;
  3208. }
  3209. len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
  3210. ASC_PRT_NEXT();
  3211. for (i = 0; i <= ADV_MAX_TID; i++) {
  3212. len = asc_prt_line(cp, leftlen, " %c",
  3213. (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
  3214. ASC_PRT_NEXT();
  3215. }
  3216. len = asc_prt_line(cp, leftlen, "\n");
  3217. ASC_PRT_NEXT();
  3218. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
  3219. adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
  3220. len = asc_prt_line(cp, leftlen,
  3221. " Synchronous Transfer Speed (Mhz):\n ");
  3222. ASC_PRT_NEXT();
  3223. for (i = 0; i <= ADV_MAX_TID; i++) {
  3224. char *speed_str;
  3225. if (i == 0) {
  3226. sdtr_speed = adv_dvc_varp->sdtr_speed1;
  3227. } else if (i == 4) {
  3228. sdtr_speed = adv_dvc_varp->sdtr_speed2;
  3229. } else if (i == 8) {
  3230. sdtr_speed = adv_dvc_varp->sdtr_speed3;
  3231. } else if (i == 12) {
  3232. sdtr_speed = adv_dvc_varp->sdtr_speed4;
  3233. }
  3234. switch (sdtr_speed & ADV_MAX_TID) {
  3235. case 0:
  3236. speed_str = "Off";
  3237. break;
  3238. case 1:
  3239. speed_str = " 5";
  3240. break;
  3241. case 2:
  3242. speed_str = " 10";
  3243. break;
  3244. case 3:
  3245. speed_str = " 20";
  3246. break;
  3247. case 4:
  3248. speed_str = " 40";
  3249. break;
  3250. case 5:
  3251. speed_str = " 80";
  3252. break;
  3253. default:
  3254. speed_str = "Unk";
  3255. break;
  3256. }
  3257. len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
  3258. ASC_PRT_NEXT();
  3259. if (i == 7) {
  3260. len = asc_prt_line(cp, leftlen, "\n ");
  3261. ASC_PRT_NEXT();
  3262. }
  3263. sdtr_speed >>= 4;
  3264. }
  3265. len = asc_prt_line(cp, leftlen, "\n");
  3266. ASC_PRT_NEXT();
  3267. }
  3268. return totlen;
  3269. }
  3270. /*
  3271. * asc_prt_driver_conf()
  3272. *
  3273. * Note: no single line should be greater than ASC_PRTLINE_SIZE,
  3274. * cf. asc_prt_line().
  3275. *
  3276. * Return the number of characters copied into 'cp'. No more than
  3277. * 'cplen' characters will be copied to 'cp'.
  3278. */
  3279. static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
  3280. {
  3281. struct asc_board *boardp = shost_priv(shost);
  3282. int leftlen;
  3283. int totlen;
  3284. int len;
  3285. int chip_scsi_id;
  3286. leftlen = cplen;
  3287. totlen = len = 0;
  3288. len = asc_prt_line(cp, leftlen,
  3289. "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
  3290. shost->host_no);
  3291. ASC_PRT_NEXT();
  3292. len = asc_prt_line(cp, leftlen,
  3293. " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
  3294. shost->host_busy, shost->last_reset, shost->max_id,
  3295. shost->max_lun, shost->max_channel);
  3296. ASC_PRT_NEXT();
  3297. len = asc_prt_line(cp, leftlen,
  3298. " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
  3299. shost->unique_id, shost->can_queue, shost->this_id,
  3300. shost->sg_tablesize, shost->cmd_per_lun);
  3301. ASC_PRT_NEXT();
  3302. len = asc_prt_line(cp, leftlen,
  3303. " unchecked_isa_dma %d, use_clustering %d\n",
  3304. shost->unchecked_isa_dma, shost->use_clustering);
  3305. ASC_PRT_NEXT();
  3306. len = asc_prt_line(cp, leftlen,
  3307. " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
  3308. boardp->flags, boardp->last_reset, jiffies,
  3309. boardp->asc_n_io_port);
  3310. ASC_PRT_NEXT();
  3311. len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
  3312. ASC_PRT_NEXT();
  3313. if (ASC_NARROW_BOARD(boardp)) {
  3314. chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
  3315. } else {
  3316. chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
  3317. }
  3318. return totlen;
  3319. }
  3320. /*
  3321. * asc_prt_asc_board_info()
  3322. *
  3323. * Print dynamic board configuration information.
  3324. *
  3325. * Note: no single line should be greater than ASC_PRTLINE_SIZE,
  3326. * cf. asc_prt_line().
  3327. *
  3328. * Return the number of characters copied into 'cp'. No more than
  3329. * 'cplen' characters will be copied to 'cp'.
  3330. */
  3331. static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
  3332. {
  3333. struct asc_board *boardp = shost_priv(shost);
  3334. int chip_scsi_id;
  3335. int leftlen;
  3336. int totlen;
  3337. int len;
  3338. ASC_DVC_VAR *v;
  3339. ASC_DVC_CFG *c;
  3340. int i;
  3341. int renegotiate = 0;
  3342. v = &boardp->dvc_var.asc_dvc_var;
  3343. c = &boardp->dvc_cfg.asc_dvc_cfg;
  3344. chip_scsi_id = c->chip_scsi_id;
  3345. leftlen = cplen;
  3346. totlen = len = 0;
  3347. len = asc_prt_line(cp, leftlen,
  3348. "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
  3349. shost->host_no);
  3350. ASC_PRT_NEXT();
  3351. len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
  3352. "mcode_version 0x%x, err_code %u\n",
  3353. c->chip_version, c->mcode_date, c->mcode_version,
  3354. v->err_code);
  3355. ASC_PRT_NEXT();
  3356. /* Current number of commands waiting for the host. */
  3357. len = asc_prt_line(cp, leftlen,
  3358. " Total Command Pending: %d\n", v->cur_total_qng);
  3359. ASC_PRT_NEXT();
  3360. len = asc_prt_line(cp, leftlen, " Command Queuing:");
  3361. ASC_PRT_NEXT();
  3362. for (i = 0; i <= ASC_MAX_TID; i++) {
  3363. if ((chip_scsi_id == i) ||
  3364. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3365. continue;
  3366. }
  3367. len = asc_prt_line(cp, leftlen, " %X:%c",
  3368. i,
  3369. (v->
  3370. use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
  3371. 'Y' : 'N');
  3372. ASC_PRT_NEXT();
  3373. }
  3374. len = asc_prt_line(cp, leftlen, "\n");
  3375. ASC_PRT_NEXT();
  3376. /* Current number of commands waiting for a device. */
  3377. len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
  3378. ASC_PRT_NEXT();
  3379. for (i = 0; i <= ASC_MAX_TID; i++) {
  3380. if ((chip_scsi_id == i) ||
  3381. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3382. continue;
  3383. }
  3384. len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
  3385. ASC_PRT_NEXT();
  3386. }
  3387. len = asc_prt_line(cp, leftlen, "\n");
  3388. ASC_PRT_NEXT();
  3389. /* Current limit on number of commands that can be sent to a device. */
  3390. len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
  3391. ASC_PRT_NEXT();
  3392. for (i = 0; i <= ASC_MAX_TID; i++) {
  3393. if ((chip_scsi_id == i) ||
  3394. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3395. continue;
  3396. }
  3397. len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
  3398. ASC_PRT_NEXT();
  3399. }
  3400. len = asc_prt_line(cp, leftlen, "\n");
  3401. ASC_PRT_NEXT();
  3402. /* Indicate whether the device has returned queue full status. */
  3403. len = asc_prt_line(cp, leftlen, " Command Queue Full:");
  3404. ASC_PRT_NEXT();
  3405. for (i = 0; i <= ASC_MAX_TID; i++) {
  3406. if ((chip_scsi_id == i) ||
  3407. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3408. continue;
  3409. }
  3410. if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
  3411. len = asc_prt_line(cp, leftlen, " %X:Y-%d",
  3412. i, boardp->queue_full_cnt[i]);
  3413. } else {
  3414. len = asc_prt_line(cp, leftlen, " %X:N", i);
  3415. }
  3416. ASC_PRT_NEXT();
  3417. }
  3418. len = asc_prt_line(cp, leftlen, "\n");
  3419. ASC_PRT_NEXT();
  3420. len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
  3421. ASC_PRT_NEXT();
  3422. for (i = 0; i <= ASC_MAX_TID; i++) {
  3423. if ((chip_scsi_id == i) ||
  3424. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3425. continue;
  3426. }
  3427. len = asc_prt_line(cp, leftlen, " %X:%c",
  3428. i,
  3429. (v->
  3430. sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  3431. 'N');
  3432. ASC_PRT_NEXT();
  3433. }
  3434. len = asc_prt_line(cp, leftlen, "\n");
  3435. ASC_PRT_NEXT();
  3436. for (i = 0; i <= ASC_MAX_TID; i++) {
  3437. uchar syn_period_ix;
  3438. if ((chip_scsi_id == i) ||
  3439. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
  3440. ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3441. continue;
  3442. }
  3443. len = asc_prt_line(cp, leftlen, " %X:", i);
  3444. ASC_PRT_NEXT();
  3445. if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
  3446. len = asc_prt_line(cp, leftlen, " Asynchronous");
  3447. ASC_PRT_NEXT();
  3448. } else {
  3449. syn_period_ix =
  3450. (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
  3451. 1);
  3452. len = asc_prt_line(cp, leftlen,
  3453. " Transfer Period Factor: %d (%d.%d Mhz),",
  3454. v->sdtr_period_tbl[syn_period_ix],
  3455. 250 /
  3456. v->sdtr_period_tbl[syn_period_ix],
  3457. ASC_TENTHS(250,
  3458. v->
  3459. sdtr_period_tbl
  3460. [syn_period_ix]));
  3461. ASC_PRT_NEXT();
  3462. len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
  3463. boardp->
  3464. sdtr_data[i] & ASC_SYN_MAX_OFFSET);
  3465. ASC_PRT_NEXT();
  3466. }
  3467. if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
  3468. len = asc_prt_line(cp, leftlen, "*\n");
  3469. renegotiate = 1;
  3470. } else {
  3471. len = asc_prt_line(cp, leftlen, "\n");
  3472. }
  3473. ASC_PRT_NEXT();
  3474. }
  3475. if (renegotiate) {
  3476. len = asc_prt_line(cp, leftlen,
  3477. " * = Re-negotiation pending before next command.\n");
  3478. ASC_PRT_NEXT();
  3479. }
  3480. return totlen;
  3481. }
  3482. /*
  3483. * asc_prt_adv_board_info()
  3484. *
  3485. * Print dynamic board configuration information.
  3486. *
  3487. * Note: no single line should be greater than ASC_PRTLINE_SIZE,
  3488. * cf. asc_prt_line().
  3489. *
  3490. * Return the number of characters copied into 'cp'. No more than
  3491. * 'cplen' characters will be copied to 'cp'.
  3492. */
  3493. static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
  3494. {
  3495. struct asc_board *boardp = shost_priv(shost);
  3496. int leftlen;
  3497. int totlen;
  3498. int len;
  3499. int i;
  3500. ADV_DVC_VAR *v;
  3501. ADV_DVC_CFG *c;
  3502. AdvPortAddr iop_base;
  3503. ushort chip_scsi_id;
  3504. ushort lramword;
  3505. uchar lrambyte;
  3506. ushort tagqng_able;
  3507. ushort sdtr_able, wdtr_able;
  3508. ushort wdtr_done, sdtr_done;
  3509. ushort period = 0;
  3510. int renegotiate = 0;
  3511. v = &boardp->dvc_var.adv_dvc_var;
  3512. c = &boardp->dvc_cfg.adv_dvc_cfg;
  3513. iop_base = v->iop_base;
  3514. chip_scsi_id = v->chip_scsi_id;
  3515. leftlen = cplen;
  3516. totlen = len = 0;
  3517. len = asc_prt_line(cp, leftlen,
  3518. "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
  3519. shost->host_no);
  3520. ASC_PRT_NEXT();
  3521. len = asc_prt_line(cp, leftlen,
  3522. " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
  3523. v->iop_base,
  3524. AdvReadWordRegister(iop_base,
  3525. IOPW_SCSI_CFG1) & CABLE_DETECT,
  3526. v->err_code);
  3527. ASC_PRT_NEXT();
  3528. len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
  3529. "mcode_version 0x%x\n", c->chip_version,
  3530. c->mcode_date, c->mcode_version);
  3531. ASC_PRT_NEXT();
  3532. AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
  3533. len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
  3534. ASC_PRT_NEXT();
  3535. for (i = 0; i <= ADV_MAX_TID; i++) {
  3536. if ((chip_scsi_id == i) ||
  3537. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3538. continue;
  3539. }
  3540. len = asc_prt_line(cp, leftlen, " %X:%c",
  3541. i,
  3542. (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  3543. 'N');
  3544. ASC_PRT_NEXT();
  3545. }
  3546. len = asc_prt_line(cp, leftlen, "\n");
  3547. ASC_PRT_NEXT();
  3548. len = asc_prt_line(cp, leftlen, " Queue Limit:");
  3549. ASC_PRT_NEXT();
  3550. for (i = 0; i <= ADV_MAX_TID; i++) {
  3551. if ((chip_scsi_id == i) ||
  3552. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3553. continue;
  3554. }
  3555. AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
  3556. lrambyte);
  3557. len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
  3558. ASC_PRT_NEXT();
  3559. }
  3560. len = asc_prt_line(cp, leftlen, "\n");
  3561. ASC_PRT_NEXT();
  3562. len = asc_prt_line(cp, leftlen, " Command Pending:");
  3563. ASC_PRT_NEXT();
  3564. for (i = 0; i <= ADV_MAX_TID; i++) {
  3565. if ((chip_scsi_id == i) ||
  3566. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3567. continue;
  3568. }
  3569. AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
  3570. lrambyte);
  3571. len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
  3572. ASC_PRT_NEXT();
  3573. }
  3574. len = asc_prt_line(cp, leftlen, "\n");
  3575. ASC_PRT_NEXT();
  3576. AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  3577. len = asc_prt_line(cp, leftlen, " Wide Enabled:");
  3578. ASC_PRT_NEXT();
  3579. for (i = 0; i <= ADV_MAX_TID; i++) {
  3580. if ((chip_scsi_id == i) ||
  3581. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3582. continue;
  3583. }
  3584. len = asc_prt_line(cp, leftlen, " %X:%c",
  3585. i,
  3586. (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  3587. 'N');
  3588. ASC_PRT_NEXT();
  3589. }
  3590. len = asc_prt_line(cp, leftlen, "\n");
  3591. ASC_PRT_NEXT();
  3592. AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
  3593. len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
  3594. ASC_PRT_NEXT();
  3595. for (i = 0; i <= ADV_MAX_TID; i++) {
  3596. if ((chip_scsi_id == i) ||
  3597. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3598. continue;
  3599. }
  3600. AdvReadWordLram(iop_base,
  3601. ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
  3602. lramword);
  3603. len = asc_prt_line(cp, leftlen, " %X:%d",
  3604. i, (lramword & 0x8000) ? 16 : 8);
  3605. ASC_PRT_NEXT();
  3606. if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
  3607. (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
  3608. len = asc_prt_line(cp, leftlen, "*");
  3609. ASC_PRT_NEXT();
  3610. renegotiate = 1;
  3611. }
  3612. }
  3613. len = asc_prt_line(cp, leftlen, "\n");
  3614. ASC_PRT_NEXT();
  3615. AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  3616. len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
  3617. ASC_PRT_NEXT();
  3618. for (i = 0; i <= ADV_MAX_TID; i++) {
  3619. if ((chip_scsi_id == i) ||
  3620. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3621. continue;
  3622. }
  3623. len = asc_prt_line(cp, leftlen, " %X:%c",
  3624. i,
  3625. (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
  3626. 'N');
  3627. ASC_PRT_NEXT();
  3628. }
  3629. len = asc_prt_line(cp, leftlen, "\n");
  3630. ASC_PRT_NEXT();
  3631. AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
  3632. for (i = 0; i <= ADV_MAX_TID; i++) {
  3633. AdvReadWordLram(iop_base,
  3634. ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
  3635. lramword);
  3636. lramword &= ~0x8000;
  3637. if ((chip_scsi_id == i) ||
  3638. ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
  3639. ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
  3640. continue;
  3641. }
  3642. len = asc_prt_line(cp, leftlen, " %X:", i);
  3643. ASC_PRT_NEXT();
  3644. if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
  3645. len = asc_prt_line(cp, leftlen, " Asynchronous");
  3646. ASC_PRT_NEXT();
  3647. } else {
  3648. len =
  3649. asc_prt_line(cp, leftlen,
  3650. " Transfer Period Factor: ");
  3651. ASC_PRT_NEXT();
  3652. if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
  3653. len =
  3654. asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
  3655. ASC_PRT_NEXT();
  3656. } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
  3657. len =
  3658. asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
  3659. ASC_PRT_NEXT();
  3660. } else { /* 20 Mhz or below. */
  3661. period = (((lramword >> 8) * 25) + 50) / 4;
  3662. if (period == 0) { /* Should never happen. */
  3663. len =
  3664. asc_prt_line(cp, leftlen,
  3665. "%d (? Mhz), ");
  3666. ASC_PRT_NEXT();
  3667. } else {
  3668. len = asc_prt_line(cp, leftlen,
  3669. "%d (%d.%d Mhz),",
  3670. period, 250 / period,
  3671. ASC_TENTHS(250,
  3672. period));
  3673. ASC_PRT_NEXT();
  3674. }
  3675. }
  3676. len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
  3677. lramword & 0x1F);
  3678. ASC_PRT_NEXT();
  3679. }
  3680. if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
  3681. len = asc_prt_line(cp, leftlen, "*\n");
  3682. renegotiate = 1;
  3683. } else {
  3684. len = asc_prt_line(cp, leftlen, "\n");
  3685. }
  3686. ASC_PRT_NEXT();
  3687. }
  3688. if (renegotiate) {
  3689. len = asc_prt_line(cp, leftlen,
  3690. " * = Re-negotiation pending before next command.\n");
  3691. ASC_PRT_NEXT();
  3692. }
  3693. return totlen;
  3694. }
  3695. /*
  3696. * asc_proc_copy()
  3697. *
  3698. * Copy proc information to a read buffer taking into account the current
  3699. * read offset in the file and the remaining space in the read buffer.
  3700. */
  3701. static int
  3702. asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
  3703. char *cp, int cplen)
  3704. {
  3705. int cnt = 0;
  3706. ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
  3707. (unsigned)offset, (unsigned)advoffset, cplen);
  3708. if (offset <= advoffset) {
  3709. /* Read offset below current offset, copy everything. */
  3710. cnt = min(cplen, leftlen);
  3711. ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
  3712. (ulong)curbuf, (ulong)cp, cnt);
  3713. memcpy(curbuf, cp, cnt);
  3714. } else if (offset < advoffset + cplen) {
  3715. /* Read offset within current range, partial copy. */
  3716. cnt = (advoffset + cplen) - offset;
  3717. cp = (cp + cplen) - cnt;
  3718. cnt = min(cnt, leftlen);
  3719. ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
  3720. (ulong)curbuf, (ulong)cp, cnt);
  3721. memcpy(curbuf, cp, cnt);
  3722. }
  3723. return cnt;
  3724. }
  3725. #ifdef ADVANSYS_STATS
  3726. /*
  3727. * asc_prt_board_stats()
  3728. *
  3729. * Note: no single line should be greater than ASC_PRTLINE_SIZE,
  3730. * cf. asc_prt_line().
  3731. *
  3732. * Return the number of characters copied into 'cp'. No more than
  3733. * 'cplen' characters will be copied to 'cp'.
  3734. */
  3735. static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
  3736. {
  3737. struct asc_board *boardp = shost_priv(shost);
  3738. struct asc_stats *s = &boardp->asc_stats;
  3739. int leftlen = cplen;
  3740. int len, totlen = 0;
  3741. len = asc_prt_line(cp, leftlen,
  3742. "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
  3743. shost->host_no);
  3744. ASC_PRT_NEXT();
  3745. len = asc_prt_line(cp, leftlen,
  3746. " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
  3747. s->queuecommand, s->reset, s->biosparam,
  3748. s->interrupt);
  3749. ASC_PRT_NEXT();
  3750. len = asc_prt_line(cp, leftlen,
  3751. " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
  3752. s->callback, s->done, s->build_error,
  3753. s->adv_build_noreq, s->adv_build_nosg);
  3754. ASC_PRT_NEXT();
  3755. len = asc_prt_line(cp, leftlen,
  3756. " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
  3757. s->exe_noerror, s->exe_busy, s->exe_error,
  3758. s->exe_unknown);
  3759. ASC_PRT_NEXT();
  3760. /*
  3761. * Display data transfer statistics.
  3762. */
  3763. if (s->cont_cnt > 0) {
  3764. len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
  3765. ASC_PRT_NEXT();
  3766. len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
  3767. s->cont_xfer / 2,
  3768. ASC_TENTHS(s->cont_xfer, 2));
  3769. ASC_PRT_NEXT();
  3770. /* Contiguous transfer average size */
  3771. len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
  3772. (s->cont_xfer / 2) / s->cont_cnt,
  3773. ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
  3774. ASC_PRT_NEXT();
  3775. }
  3776. if (s->sg_cnt > 0) {
  3777. len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
  3778. s->sg_cnt, s->sg_elem);
  3779. ASC_PRT_NEXT();
  3780. len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
  3781. s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
  3782. ASC_PRT_NEXT();
  3783. /* Scatter gather transfer statistics */
  3784. len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
  3785. s->sg_elem / s->sg_cnt,
  3786. ASC_TENTHS(s->sg_elem, s->sg_cnt));
  3787. ASC_PRT_NEXT();
  3788. len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
  3789. (s->sg_xfer / 2) / s->sg_elem,
  3790. ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
  3791. ASC_PRT_NEXT();
  3792. len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
  3793. (s->sg_xfer / 2) / s->sg_cnt,
  3794. ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
  3795. ASC_PRT_NEXT();
  3796. }
  3797. /*
  3798. * Display request queuing statistics.
  3799. */
  3800. len = asc_prt_line(cp, leftlen,
  3801. " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
  3802. HZ);
  3803. ASC_PRT_NEXT();
  3804. return totlen;
  3805. }
  3806. #endif /* ADVANSYS_STATS */
  3807. /*
  3808. * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
  3809. *
  3810. * *buffer: I/O buffer
  3811. * **start: if inout == FALSE pointer into buffer where user read should start
  3812. * offset: current offset into a /proc/scsi/advansys/[0...] file
  3813. * length: length of buffer
  3814. * hostno: Scsi_Host host_no
  3815. * inout: TRUE - user is writing; FALSE - user is reading
  3816. *
  3817. * Return the number of bytes read from or written to a
  3818. * /proc/scsi/advansys/[0...] file.
  3819. *
  3820. * Note: This function uses the per board buffer 'prtbuf' which is
  3821. * allocated when the board is initialized in advansys_detect(). The
  3822. * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
  3823. * used to write to the buffer. The way asc_proc_copy() is written
  3824. * if 'prtbuf' is too small it will not be overwritten. Instead the
  3825. * user just won't get all the available statistics.
  3826. */
  3827. static int
  3828. advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
  3829. off_t offset, int length, int inout)
  3830. {
  3831. struct asc_board *boardp = shost_priv(shost);
  3832. char *cp;
  3833. int cplen;
  3834. int cnt;
  3835. int totcnt;
  3836. int leftlen;
  3837. char *curbuf;
  3838. off_t advoffset;
  3839. ASC_DBG(1, "advansys_proc_info: begin\n");
  3840. /*
  3841. * User write not supported.
  3842. */
  3843. if (inout == TRUE)
  3844. return -ENOSYS;
  3845. /*
  3846. * User read of /proc/scsi/advansys/[0...] file.
  3847. */
  3848. /* Copy read data starting at the beginning of the buffer. */
  3849. *start = buffer;
  3850. curbuf = buffer;
  3851. advoffset = 0;
  3852. totcnt = 0;
  3853. leftlen = length;
  3854. /*
  3855. * Get board configuration information.
  3856. *
  3857. * advansys_info() returns the board string from its own static buffer.
  3858. */
  3859. cp = (char *)advansys_info(shost);
  3860. strcat(cp, "\n");
  3861. cplen = strlen(cp);
  3862. /* Copy board information. */
  3863. cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
  3864. totcnt += cnt;
  3865. leftlen -= cnt;
  3866. if (leftlen == 0) {
  3867. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3868. return totcnt;
  3869. }
  3870. advoffset += cplen;
  3871. curbuf += cnt;
  3872. /*
  3873. * Display Wide Board BIOS Information.
  3874. */
  3875. if (!ASC_NARROW_BOARD(boardp)) {
  3876. cp = boardp->prtbuf;
  3877. cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
  3878. BUG_ON(cplen >= ASC_PRTBUF_SIZE);
  3879. cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
  3880. cplen);
  3881. totcnt += cnt;
  3882. leftlen -= cnt;
  3883. if (leftlen == 0) {
  3884. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3885. return totcnt;
  3886. }
  3887. advoffset += cplen;
  3888. curbuf += cnt;
  3889. }
  3890. /*
  3891. * Display driver information for each device attached to the board.
  3892. */
  3893. cp = boardp->prtbuf;
  3894. cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
  3895. BUG_ON(cplen >= ASC_PRTBUF_SIZE);
  3896. cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
  3897. totcnt += cnt;
  3898. leftlen -= cnt;
  3899. if (leftlen == 0) {
  3900. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3901. return totcnt;
  3902. }
  3903. advoffset += cplen;
  3904. curbuf += cnt;
  3905. /*
  3906. * Display EEPROM configuration for the board.
  3907. */
  3908. cp = boardp->prtbuf;
  3909. if (ASC_NARROW_BOARD(boardp)) {
  3910. cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
  3911. } else {
  3912. cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
  3913. }
  3914. BUG_ON(cplen >= ASC_PRTBUF_SIZE);
  3915. cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
  3916. totcnt += cnt;
  3917. leftlen -= cnt;
  3918. if (leftlen == 0) {
  3919. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3920. return totcnt;
  3921. }
  3922. advoffset += cplen;
  3923. curbuf += cnt;
  3924. /*
  3925. * Display driver configuration and information for the board.
  3926. */
  3927. cp = boardp->prtbuf;
  3928. cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
  3929. BUG_ON(cplen >= ASC_PRTBUF_SIZE);
  3930. cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
  3931. totcnt += cnt;
  3932. leftlen -= cnt;
  3933. if (leftlen == 0) {
  3934. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3935. return totcnt;
  3936. }
  3937. advoffset += cplen;
  3938. curbuf += cnt;
  3939. #ifdef ADVANSYS_STATS
  3940. /*
  3941. * Display driver statistics for the board.
  3942. */
  3943. cp = boardp->prtbuf;
  3944. cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
  3945. BUG_ON(cplen >= ASC_PRTBUF_SIZE);
  3946. cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
  3947. totcnt += cnt;
  3948. leftlen -= cnt;
  3949. if (leftlen == 0) {
  3950. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3951. return totcnt;
  3952. }
  3953. advoffset += cplen;
  3954. curbuf += cnt;
  3955. #endif /* ADVANSYS_STATS */
  3956. /*
  3957. * Display Asc Library dynamic configuration information
  3958. * for the board.
  3959. */
  3960. cp = boardp->prtbuf;
  3961. if (ASC_NARROW_BOARD(boardp)) {
  3962. cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
  3963. } else {
  3964. cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
  3965. }
  3966. BUG_ON(cplen >= ASC_PRTBUF_SIZE);
  3967. cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
  3968. totcnt += cnt;
  3969. leftlen -= cnt;
  3970. if (leftlen == 0) {
  3971. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3972. return totcnt;
  3973. }
  3974. advoffset += cplen;
  3975. curbuf += cnt;
  3976. ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
  3977. return totcnt;
  3978. }
  3979. #endif /* CONFIG_PROC_FS */
  3980. static void asc_scsi_done(struct scsi_cmnd *scp)
  3981. {
  3982. struct asc_board *boardp = shost_priv(scp->device->host);
  3983. if (scp->use_sg)
  3984. dma_unmap_sg(boardp->dev,
  3985. (struct scatterlist *)scp->request_buffer,
  3986. scp->use_sg, scp->sc_data_direction);
  3987. else if (scp->request_bufflen)
  3988. dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
  3989. scp->request_bufflen, scp->sc_data_direction);
  3990. ASC_STATS(scp->device->host, done);
  3991. scp->scsi_done(scp);
  3992. }
  3993. static void AscSetBank(PortAddr iop_base, uchar bank)
  3994. {
  3995. uchar val;
  3996. val = AscGetChipControl(iop_base) &
  3997. (~
  3998. (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
  3999. CC_CHIP_RESET));
  4000. if (bank == 1) {
  4001. val |= CC_BANK_ONE;
  4002. } else if (bank == 2) {
  4003. val |= CC_DIAG | CC_BANK_ONE;
  4004. } else {
  4005. val &= ~CC_BANK_ONE;
  4006. }
  4007. AscSetChipControl(iop_base, val);
  4008. return;
  4009. }
  4010. static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
  4011. {
  4012. AscSetBank(iop_base, 1);
  4013. AscWriteChipIH(iop_base, ins_code);
  4014. AscSetBank(iop_base, 0);
  4015. return;
  4016. }
  4017. static int AscStartChip(PortAddr iop_base)
  4018. {
  4019. AscSetChipControl(iop_base, 0);
  4020. if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
  4021. return (0);
  4022. }
  4023. return (1);
  4024. }
  4025. static int AscStopChip(PortAddr iop_base)
  4026. {
  4027. uchar cc_val;
  4028. cc_val =
  4029. AscGetChipControl(iop_base) &
  4030. (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
  4031. AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
  4032. AscSetChipIH(iop_base, INS_HALT);
  4033. AscSetChipIH(iop_base, INS_RFLAG_WTM);
  4034. if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
  4035. return (0);
  4036. }
  4037. return (1);
  4038. }
  4039. static int AscIsChipHalted(PortAddr iop_base)
  4040. {
  4041. if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
  4042. if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
  4043. return (1);
  4044. }
  4045. }
  4046. return (0);
  4047. }
  4048. static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
  4049. {
  4050. PortAddr iop_base;
  4051. int i = 10;
  4052. iop_base = asc_dvc->iop_base;
  4053. while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
  4054. && (i-- > 0)) {
  4055. mdelay(100);
  4056. }
  4057. AscStopChip(iop_base);
  4058. AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
  4059. udelay(60);
  4060. AscSetChipIH(iop_base, INS_RFLAG_WTM);
  4061. AscSetChipIH(iop_base, INS_HALT);
  4062. AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
  4063. AscSetChipControl(iop_base, CC_HALT);
  4064. mdelay(200);
  4065. AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
  4066. AscSetChipStatus(iop_base, 0);
  4067. return (AscIsChipHalted(iop_base));
  4068. }
  4069. static int AscFindSignature(PortAddr iop_base)
  4070. {
  4071. ushort sig_word;
  4072. ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
  4073. iop_base, AscGetChipSignatureByte(iop_base));
  4074. if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
  4075. ASC_DBG2(1,
  4076. "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
  4077. iop_base, AscGetChipSignatureWord(iop_base));
  4078. sig_word = AscGetChipSignatureWord(iop_base);
  4079. if ((sig_word == (ushort)ASC_1000_ID0W) ||
  4080. (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
  4081. return (1);
  4082. }
  4083. }
  4084. return (0);
  4085. }
  4086. static void AscEnableInterrupt(PortAddr iop_base)
  4087. {
  4088. ushort cfg;
  4089. cfg = AscGetChipCfgLsw(iop_base);
  4090. AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
  4091. return;
  4092. }
  4093. static void AscDisableInterrupt(PortAddr iop_base)
  4094. {
  4095. ushort cfg;
  4096. cfg = AscGetChipCfgLsw(iop_base);
  4097. AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
  4098. return;
  4099. }
  4100. static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
  4101. {
  4102. unsigned char byte_data;
  4103. unsigned short word_data;
  4104. if (isodd_word(addr)) {
  4105. AscSetChipLramAddr(iop_base, addr - 1);
  4106. word_data = AscGetChipLramData(iop_base);
  4107. byte_data = (word_data >> 8) & 0xFF;
  4108. } else {
  4109. AscSetChipLramAddr(iop_base, addr);
  4110. word_data = AscGetChipLramData(iop_base);
  4111. byte_data = word_data & 0xFF;
  4112. }
  4113. return byte_data;
  4114. }
  4115. static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
  4116. {
  4117. ushort word_data;
  4118. AscSetChipLramAddr(iop_base, addr);
  4119. word_data = AscGetChipLramData(iop_base);
  4120. return (word_data);
  4121. }
  4122. #if CC_VERY_LONG_SG_LIST
  4123. static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
  4124. {
  4125. ushort val_low, val_high;
  4126. ASC_DCNT dword_data;
  4127. AscSetChipLramAddr(iop_base, addr);
  4128. val_low = AscGetChipLramData(iop_base);
  4129. val_high = AscGetChipLramData(iop_base);
  4130. dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
  4131. return (dword_data);
  4132. }
  4133. #endif /* CC_VERY_LONG_SG_LIST */
  4134. static void
  4135. AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
  4136. {
  4137. int i;
  4138. AscSetChipLramAddr(iop_base, s_addr);
  4139. for (i = 0; i < words; i++) {
  4140. AscSetChipLramData(iop_base, set_wval);
  4141. }
  4142. }
  4143. static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
  4144. {
  4145. AscSetChipLramAddr(iop_base, addr);
  4146. AscSetChipLramData(iop_base, word_val);
  4147. return;
  4148. }
  4149. static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
  4150. {
  4151. ushort word_data;
  4152. if (isodd_word(addr)) {
  4153. addr--;
  4154. word_data = AscReadLramWord(iop_base, addr);
  4155. word_data &= 0x00FF;
  4156. word_data |= (((ushort)byte_val << 8) & 0xFF00);
  4157. } else {
  4158. word_data = AscReadLramWord(iop_base, addr);
  4159. word_data &= 0xFF00;
  4160. word_data |= ((ushort)byte_val & 0x00FF);
  4161. }
  4162. AscWriteLramWord(iop_base, addr, word_data);
  4163. return;
  4164. }
  4165. /*
  4166. * Copy 2 bytes to LRAM.
  4167. *
  4168. * The source data is assumed to be in little-endian order in memory
  4169. * and is maintained in little-endian order when written to LRAM.
  4170. */
  4171. static void
  4172. AscMemWordCopyPtrToLram(PortAddr iop_base,
  4173. ushort s_addr, uchar *s_buffer, int words)
  4174. {
  4175. int i;
  4176. AscSetChipLramAddr(iop_base, s_addr);
  4177. for (i = 0; i < 2 * words; i += 2) {
  4178. /*
  4179. * On a little-endian system the second argument below
  4180. * produces a little-endian ushort which is written to
  4181. * LRAM in little-endian order. On a big-endian system
  4182. * the second argument produces a big-endian ushort which
  4183. * is "transparently" byte-swapped by outpw() and written
  4184. * in little-endian order to LRAM.
  4185. */
  4186. outpw(iop_base + IOP_RAM_DATA,
  4187. ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
  4188. }
  4189. return;
  4190. }
  4191. /*
  4192. * Copy 4 bytes to LRAM.
  4193. *
  4194. * The source data is assumed to be in little-endian order in memory
  4195. * and is maintained in little-endian order when writen to LRAM.
  4196. */
  4197. static void
  4198. AscMemDWordCopyPtrToLram(PortAddr iop_base,
  4199. ushort s_addr, uchar *s_buffer, int dwords)
  4200. {
  4201. int i;
  4202. AscSetChipLramAddr(iop_base, s_addr);
  4203. for (i = 0; i < 4 * dwords; i += 4) {
  4204. outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
  4205. outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
  4206. }
  4207. return;
  4208. }
  4209. /*
  4210. * Copy 2 bytes from LRAM.
  4211. *
  4212. * The source data is assumed to be in little-endian order in LRAM
  4213. * and is maintained in little-endian order when written to memory.
  4214. */
  4215. static void
  4216. AscMemWordCopyPtrFromLram(PortAddr iop_base,
  4217. ushort s_addr, uchar *d_buffer, int words)
  4218. {
  4219. int i;
  4220. ushort word;
  4221. AscSetChipLramAddr(iop_base, s_addr);
  4222. for (i = 0; i < 2 * words; i += 2) {
  4223. word = inpw(iop_base + IOP_RAM_DATA);
  4224. d_buffer[i] = word & 0xff;
  4225. d_buffer[i + 1] = (word >> 8) & 0xff;
  4226. }
  4227. return;
  4228. }
  4229. static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
  4230. {
  4231. ASC_DCNT sum;
  4232. int i;
  4233. sum = 0L;
  4234. for (i = 0; i < words; i++, s_addr += 2) {
  4235. sum += AscReadLramWord(iop_base, s_addr);
  4236. }
  4237. return (sum);
  4238. }
  4239. static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
  4240. {
  4241. uchar i;
  4242. ushort s_addr;
  4243. PortAddr iop_base;
  4244. ushort warn_code;
  4245. iop_base = asc_dvc->iop_base;
  4246. warn_code = 0;
  4247. AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
  4248. (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
  4249. 64) >> 1));
  4250. i = ASC_MIN_ACTIVE_QNO;
  4251. s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
  4252. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
  4253. (uchar)(i + 1));
  4254. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
  4255. (uchar)(asc_dvc->max_total_qng));
  4256. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
  4257. (uchar)i);
  4258. i++;
  4259. s_addr += ASC_QBLK_SIZE;
  4260. for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
  4261. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
  4262. (uchar)(i + 1));
  4263. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
  4264. (uchar)(i - 1));
  4265. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
  4266. (uchar)i);
  4267. }
  4268. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
  4269. (uchar)ASC_QLINK_END);
  4270. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
  4271. (uchar)(asc_dvc->max_total_qng - 1));
  4272. AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
  4273. (uchar)asc_dvc->max_total_qng);
  4274. i++;
  4275. s_addr += ASC_QBLK_SIZE;
  4276. for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
  4277. i++, s_addr += ASC_QBLK_SIZE) {
  4278. AscWriteLramByte(iop_base,
  4279. (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
  4280. AscWriteLramByte(iop_base,
  4281. (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
  4282. AscWriteLramByte(iop_base,
  4283. (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
  4284. }
  4285. return warn_code;
  4286. }
  4287. static ASC_DCNT
  4288. AscLoadMicroCode(PortAddr iop_base,
  4289. ushort s_addr, uchar *mcode_buf, ushort mcode_size)
  4290. {
  4291. ASC_DCNT chksum;
  4292. ushort mcode_word_size;
  4293. ushort mcode_chksum;
  4294. /* Write the microcode buffer starting at LRAM address 0. */
  4295. mcode_word_size = (ushort)(mcode_size >> 1);
  4296. AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
  4297. AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
  4298. chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
  4299. ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum);
  4300. mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
  4301. (ushort)ASC_CODE_SEC_BEG,
  4302. (ushort)((mcode_size -
  4303. s_addr - (ushort)
  4304. ASC_CODE_SEC_BEG) /
  4305. 2));
  4306. ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
  4307. (ulong)mcode_chksum);
  4308. AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
  4309. AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
  4310. return (chksum);
  4311. }
  4312. /* Microcode buffer is kept after initialization for error recovery. */
  4313. static uchar _asc_mcode_buf[] = {
  4314. 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4315. 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
  4316. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4317. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4318. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4319. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
  4320. 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4321. 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  4322. 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
  4323. 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
  4324. 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
  4325. 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
  4326. 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
  4327. 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
  4328. 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
  4329. 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
  4330. 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
  4331. 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
  4332. 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
  4333. 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
  4334. 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
  4335. 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
  4336. 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
  4337. 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
  4338. 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
  4339. 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
  4340. 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
  4341. 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
  4342. 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
  4343. 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
  4344. 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
  4345. 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
  4346. 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
  4347. 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
  4348. 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
  4349. 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
  4350. 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
  4351. 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
  4352. 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
  4353. 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
  4354. 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
  4355. 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
  4356. 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
  4357. 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
  4358. 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
  4359. 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
  4360. 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
  4361. 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
  4362. 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
  4363. 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
  4364. 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
  4365. 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
  4366. 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
  4367. 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
  4368. 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
  4369. 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
  4370. 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
  4371. 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
  4372. 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
  4373. 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
  4374. 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
  4375. 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
  4376. 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
  4377. 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
  4378. 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
  4379. 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
  4380. 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
  4381. 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
  4382. 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
  4383. 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
  4384. 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
  4385. 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
  4386. 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
  4387. 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
  4388. 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
  4389. 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
  4390. 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
  4391. 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
  4392. 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
  4393. 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
  4394. 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
  4395. 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
  4396. 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
  4397. 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
  4398. 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
  4399. 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
  4400. 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
  4401. 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
  4402. 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
  4403. 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
  4404. 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
  4405. 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
  4406. 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
  4407. 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
  4408. 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
  4409. 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
  4410. 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
  4411. 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
  4412. 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
  4413. 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
  4414. 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
  4415. 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
  4416. 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
  4417. 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
  4418. 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
  4419. 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
  4420. 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
  4421. 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
  4422. 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
  4423. 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
  4424. 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
  4425. 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
  4426. 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
  4427. 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
  4428. 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
  4429. 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
  4430. 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
  4431. 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
  4432. 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
  4433. 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
  4434. 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
  4435. 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
  4436. 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
  4437. 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
  4438. 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
  4439. 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
  4440. 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
  4441. 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
  4442. 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
  4443. 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
  4444. 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
  4445. 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
  4446. 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
  4447. 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
  4448. 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
  4449. 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
  4450. 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
  4451. 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
  4452. 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
  4453. 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
  4454. 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
  4455. 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
  4456. 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
  4457. 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
  4458. 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
  4459. 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
  4460. 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
  4461. 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
  4462. 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
  4463. 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
  4464. 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
  4465. 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
  4466. 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
  4467. 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
  4468. 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
  4469. 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
  4470. 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
  4471. 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
  4472. 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
  4473. 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
  4474. 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
  4475. 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
  4476. 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
  4477. 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
  4478. 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
  4479. 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
  4480. 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
  4481. 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
  4482. 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
  4483. 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
  4484. 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
  4485. 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
  4486. 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
  4487. 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
  4488. 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
  4489. 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
  4490. 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
  4491. 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
  4492. 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
  4493. 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
  4494. 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
  4495. 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
  4496. 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
  4497. 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
  4498. 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
  4499. 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
  4500. 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
  4501. 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
  4502. 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
  4503. 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
  4504. 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
  4505. 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
  4506. };
  4507. static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
  4508. static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
  4509. /* Microcode buffer is kept after initialization for error recovery. */
  4510. static unsigned char _adv_asc3550_buf[] = {
  4511. 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
  4512. 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
  4513. 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
  4514. 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
  4515. 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
  4516. 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
  4517. 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
  4518. 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
  4519. 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
  4520. 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
  4521. 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
  4522. 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
  4523. 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
  4524. 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
  4525. 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
  4526. 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
  4527. 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
  4528. 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
  4529. 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
  4530. 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
  4531. 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
  4532. 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
  4533. 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
  4534. 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
  4535. 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
  4536. 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
  4537. 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
  4538. 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
  4539. 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
  4540. 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
  4541. 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
  4542. 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
  4543. 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
  4544. 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
  4545. 0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02,
  4546. 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
  4547. 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
  4548. 0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13,
  4549. 0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18,
  4550. 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
  4551. 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
  4552. 0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90,
  4553. 0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10,
  4554. 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
  4555. 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
  4556. 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00,
  4557. 0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
  4558. 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
  4559. 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
  4560. 0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe,
  4561. 0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02,
  4562. 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
  4563. 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
  4564. 0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe,
  4565. 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
  4566. 0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02,
  4567. 0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02,
  4568. 0xfe, 0x46, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02,
  4569. 0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x48, 0x02,
  4570. 0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18,
  4571. 0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe,
  4572. 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10,
  4573. 0xfe, 0x06, 0xfc, 0xc7, 0x0a, 0x6b, 0x01, 0x9e, 0x02, 0x29, 0x14, 0x4d,
  4574. 0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xbd,
  4575. 0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
  4576. 0x58, 0x1c, 0x17, 0x06, 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0,
  4577. 0xfe, 0x02, 0x02, 0x21, 0xfe, 0x94, 0x02, 0xfe, 0x5a, 0x1c, 0xea, 0xfe,
  4578. 0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97, 0x01, 0xfe, 0x54, 0x0f,
  4579. 0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe,
  4580. 0x69, 0x10, 0x17, 0x06, 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d,
  4581. 0x12, 0x20, 0xfe, 0x05, 0xf6, 0xc7, 0x01, 0xfe, 0x52, 0x16, 0x09, 0x4a,
  4582. 0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6, 0x02, 0x29, 0x0a, 0x40,
  4583. 0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41,
  4584. 0x58, 0x0a, 0x99, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03,
  4585. 0x01, 0xe6, 0x02, 0x29, 0x2a, 0x46, 0xfe, 0x02, 0xe8, 0x27, 0xf8, 0xfe,
  4586. 0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc, 0x01, 0xfe, 0x07, 0x4b,
  4587. 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0,
  4588. 0xfe, 0x56, 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0,
  4589. 0x9c, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe, 0x64, 0x03, 0xeb, 0x0f,
  4590. 0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48, 0x1c, 0xeb, 0x09, 0x04,
  4591. 0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40,
  4592. 0x01, 0x0e, 0xac, 0x75, 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2,
  4593. 0xfe, 0x01, 0xf0, 0xd2, 0xfe, 0x82, 0xf0, 0xfe, 0x92, 0x03, 0xec, 0x11,
  4594. 0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25, 0x32, 0x1f, 0xfe, 0xb4,
  4595. 0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe,
  4596. 0x0a, 0xf0, 0xfe, 0x7a, 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe,
  4597. 0xf6, 0x04, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02, 0xd1,
  4598. 0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8, 0xf7, 0xfe, 0x48, 0x1c,
  4599. 0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3,
  4600. 0x0a, 0xca, 0x01, 0x0e, 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28,
  4601. 0xfe, 0x10, 0x12, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02,
  4602. 0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65, 0xfe, 0x3c, 0x04, 0x1f,
  4603. 0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
  4604. 0x12, 0x2b, 0xff, 0x02, 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04,
  4605. 0x2b, 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd5, 0xfe, 0x4c, 0x44, 0xfe,
  4606. 0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64,
  4607. 0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d,
  4608. 0xfe, 0x2a, 0x13, 0x2f, 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c,
  4609. 0xfe, 0x4c, 0x54, 0x64, 0xd3, 0xfa, 0xef, 0x86, 0x09, 0x04, 0x1d, 0xfe,
  4610. 0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04, 0x1d, 0xfe, 0x1c, 0x12,
  4611. 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe,
  4612. 0x70, 0x0c, 0x02, 0x22, 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90,
  4613. 0xf9, 0x03, 0x14, 0x92, 0x01, 0x33, 0x02, 0x29, 0xfe, 0x42, 0x5b, 0x67,
  4614. 0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4,
  4615. 0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a,
  4616. 0xfe, 0x70, 0x12, 0x49, 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2,
  4617. 0x00, 0x28, 0x16, 0xfe, 0x80, 0x05, 0xfe, 0x31, 0xe4, 0x6a, 0x49, 0x04,
  4618. 0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x42, 0x12,
  4619. 0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05,
  4620. 0x11, 0xfe, 0xe3, 0x00, 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05,
  4621. 0xfe, 0x49, 0xf0, 0xfe, 0x64, 0x05, 0x83, 0x24, 0xfe, 0x21, 0x00, 0xa1,
  4622. 0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe, 0x09, 0x48, 0x01, 0x08,
  4623. 0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01,
  4624. 0x86, 0x24, 0x06, 0x12, 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d,
  4625. 0xfe, 0x22, 0x12, 0x47, 0x01, 0xa7, 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b,
  4626. 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22, 0x05, 0xfe,
  4627. 0x9c, 0x00, 0x28, 0xfe, 0x3e, 0x12, 0x05, 0x50, 0x28, 0xfe, 0x36, 0x13,
  4628. 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x08, 0x06, 0x0a, 0x06, 0x49, 0x04, 0x19,
  4629. 0xfe, 0x02, 0x12, 0x5f, 0x01, 0xfe, 0xaa, 0x14, 0x1f, 0xfe, 0xfe, 0x05,
  4630. 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x50, 0xb4, 0x0c,
  4631. 0x50, 0x05, 0xc6, 0x28, 0xfe, 0x62, 0x12, 0x05, 0x3f, 0x28, 0xfe, 0x5a,
  4632. 0x13, 0x01, 0xfe, 0x14, 0x18, 0x01, 0xfe, 0x66, 0x18, 0xfe, 0x43, 0x48,
  4633. 0xb7, 0x19, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d,
  4634. 0x85, 0xb7, 0x69, 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x72, 0x06, 0x49, 0x04,
  4635. 0x1b, 0xdf, 0x89, 0x0a, 0x4d, 0x01, 0xfe, 0xd8, 0x14, 0x1f, 0xfe, 0x68,
  4636. 0x06, 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x3f, 0xb4,
  4637. 0x0c, 0x3f, 0x17, 0x06, 0x01, 0xa7, 0xec, 0x72, 0x70, 0x01, 0x6e, 0x87,
  4638. 0x11, 0xfe, 0xe2, 0x00, 0x01, 0x08, 0x25, 0x32, 0xfe, 0x0a, 0xf0, 0xfe,
  4639. 0xa6, 0x06, 0x8c, 0xfe, 0x5c, 0x07, 0xfe, 0x06, 0xf0, 0xfe, 0x64, 0x07,
  4640. 0x8d, 0x81, 0x02, 0x22, 0x09, 0x04, 0x0b, 0xfe, 0x2e, 0x12, 0x15, 0x1a,
  4641. 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00,
  4642. 0x01, 0x08, 0xfe, 0x99, 0xa4, 0x01, 0x08, 0x15, 0x00, 0x02, 0xfe, 0x32,
  4643. 0x08, 0x61, 0x04, 0x1b, 0xfe, 0x38, 0x12, 0x09, 0x04, 0x1b, 0x6e, 0x15,
  4644. 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01,
  4645. 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x06, 0x01, 0x08, 0x15, 0x00, 0x02,
  4646. 0xd9, 0x66, 0x4c, 0xfe, 0x3a, 0x55, 0x5f, 0xfe, 0x9a, 0x81, 0x4b, 0x1d,
  4647. 0xba, 0xfe, 0x32, 0x07, 0x0a, 0x1d, 0xfe, 0x09, 0x6f, 0xaf, 0xfe, 0xca,
  4648. 0x45, 0xfe, 0x32, 0x12, 0x62, 0x2c, 0x85, 0x66, 0x7b, 0x01, 0x08, 0x25,
  4649. 0x32, 0xfe, 0x0a, 0xf0, 0xfe, 0x32, 0x07, 0x8d, 0x81, 0x8c, 0xfe, 0x5c,
  4650. 0x07, 0x02, 0x22, 0x01, 0x43, 0x02, 0xfe, 0x8a, 0x06, 0x15, 0x19, 0x02,
  4651. 0xfe, 0x8a, 0x06, 0xfe, 0x9c, 0xf7, 0xd4, 0xfe, 0x2c, 0x90, 0xfe, 0xae,
  4652. 0x90, 0x77, 0xfe, 0xca, 0x07, 0x0c, 0x54, 0x18, 0x55, 0x09, 0x4a, 0x6a,
  4653. 0x35, 0x1e, 0x20, 0x07, 0x10, 0xfe, 0x0e, 0x12, 0x74, 0xfe, 0x80, 0x80,
  4654. 0x37, 0x20, 0x63, 0x27, 0xfe, 0x06, 0x10, 0xfe, 0x83, 0xe7, 0xc4, 0xa1,
  4655. 0xfe, 0x03, 0x40, 0x09, 0x4a, 0x4f, 0x35, 0x01, 0xa8, 0xad, 0xfe, 0x1f,
  4656. 0x40, 0x12, 0x58, 0x01, 0xa5, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe,
  4657. 0x44, 0x51, 0xfe, 0xc6, 0x51, 0x83, 0xfb, 0xfe, 0x8a, 0x90, 0x0c, 0x52,
  4658. 0x18, 0x53, 0xfe, 0x0c, 0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe,
  4659. 0xc2, 0x50, 0x0c, 0x39, 0x18, 0x3a, 0xfe, 0x4a, 0x10, 0x09, 0x04, 0x6a,
  4660. 0xfe, 0x2a, 0x12, 0xfe, 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x54, 0x18,
  4661. 0x55, 0x09, 0x04, 0x4f, 0x85, 0x01, 0xa8, 0xfe, 0x1f, 0x80, 0x12, 0x58,
  4662. 0xfe, 0x44, 0x90, 0xfe, 0xc6, 0x90, 0x0c, 0x56, 0x18, 0x57, 0xfb, 0xfe,
  4663. 0x8a, 0x90, 0x0c, 0x52, 0x18, 0x53, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90,
  4664. 0x0c, 0x39, 0x18, 0x3a, 0x0c, 0x38, 0x18, 0x4e, 0x09, 0x4a, 0x19, 0x35,
  4665. 0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x48, 0x08, 0xfe, 0x9e, 0xf0,
  4666. 0xfe, 0x5c, 0x08, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0xfe, 0x80,
  4667. 0x08, 0xb9, 0xfe, 0x9e, 0x08, 0x8c, 0xfe, 0x74, 0x08, 0xfe, 0x06, 0xf0,
  4668. 0xfe, 0x7a, 0x08, 0x8d, 0x81, 0x02, 0x22, 0x01, 0x43, 0xfe, 0xc9, 0x10,
  4669. 0x15, 0x19, 0xfe, 0xc9, 0x10, 0x61, 0x04, 0x06, 0xfe, 0x10, 0x12, 0x61,
  4670. 0x04, 0x0b, 0x45, 0x09, 0x04, 0x0b, 0xfe, 0x68, 0x12, 0xfe, 0x2e, 0x1c,
  4671. 0x02, 0xfe, 0x24, 0x0a, 0x61, 0x04, 0x06, 0x45, 0x61, 0x04, 0x0b, 0xfe,
  4672. 0x52, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0x1e, 0x09, 0xfe,
  4673. 0xac, 0xf0, 0xfe, 0xbe, 0x08, 0xfe, 0x8a, 0x10, 0xaa, 0xfe, 0xf3, 0x10,
  4674. 0xfe, 0xad, 0xf0, 0xfe, 0xca, 0x08, 0x02, 0xfe, 0x24, 0x0a, 0xab, 0xfe,
  4675. 0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0x9d, 0xe9, 0x1c, 0xfe, 0x00, 0xfe, 0xfe,
  4676. 0x1c, 0x12, 0xb5, 0xfe, 0xd2, 0xf0, 0x9d, 0xfe, 0x76, 0x18, 0x1c, 0x1a,
  4677. 0x16, 0x9d, 0x05, 0xcb, 0x1c, 0x06, 0x16, 0x9d, 0xb8, 0x6d, 0xb9, 0x6d,
  4678. 0xaa, 0xab, 0xfe, 0xb1, 0x10, 0x70, 0x5e, 0x2b, 0x14, 0x92, 0x01, 0x33,
  4679. 0x0f, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x5a, 0x0f, 0x7c, 0x02, 0x5a,
  4680. 0xfe, 0x74, 0x18, 0x1c, 0xfe, 0x00, 0xf8, 0x16, 0x6d, 0x67, 0x1b, 0x01,
  4681. 0xfe, 0x44, 0x0d, 0x3b, 0x01, 0xe6, 0x1e, 0x27, 0x74, 0x67, 0x1a, 0x02,
  4682. 0x6d, 0x09, 0x04, 0x0b, 0x21, 0xfe, 0x06, 0x0a, 0x09, 0x04, 0x6a, 0xfe,
  4683. 0x82, 0x12, 0x09, 0x04, 0x19, 0xfe, 0x66, 0x13, 0x1e, 0x58, 0xac, 0xfc,
  4684. 0xfe, 0x83, 0x80, 0xfe, 0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91,
  4685. 0xfe, 0x86, 0x91, 0x63, 0x27, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x77,
  4686. 0xd7, 0x05, 0x54, 0x31, 0x55, 0x0c, 0x7b, 0x18, 0x7c, 0xbe, 0x54, 0xbf,
  4687. 0x55, 0x01, 0xa8, 0xad, 0x63, 0x27, 0x12, 0x58, 0xc0, 0x38, 0xc1, 0x4e,
  4688. 0x79, 0x56, 0x68, 0x57, 0xf4, 0xf5, 0xfe, 0x04, 0xfa, 0x38, 0xfe, 0x05,
  4689. 0xfa, 0x4e, 0x01, 0xa5, 0xa2, 0x23, 0x0c, 0x7b, 0x0c, 0x7c, 0x79, 0x56,
  4690. 0x68, 0x57, 0xfe, 0x12, 0x10, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x79, 0x39,
  4691. 0x68, 0x3a, 0x09, 0x04, 0xfe, 0xf7, 0x00, 0x35, 0x05, 0x52, 0x31, 0x53,
  4692. 0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59,
  4693. 0x02, 0x6d, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x09, 0x04, 0xfe, 0xf7, 0x00,
  4694. 0x35, 0xfe, 0x3a, 0x55, 0xfe, 0x19, 0x81, 0x5f, 0xfe, 0x10, 0x90, 0xfe,
  4695. 0x92, 0x90, 0xfe, 0xd7, 0x10, 0x2f, 0x07, 0x9b, 0x16, 0xfe, 0xc6, 0x08,
  4696. 0x11, 0x9b, 0x09, 0x04, 0x0b, 0xfe, 0x14, 0x13, 0x05, 0x39, 0x31, 0x3a,
  4697. 0x77, 0xfe, 0xc6, 0x08, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x02, 0x6d,
  4698. 0x23, 0x47, 0xfe, 0x19, 0x80, 0xde, 0x09, 0x04, 0x0b, 0xfe, 0x1a, 0x12,
  4699. 0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41, 0xe9, 0xb5, 0xfe, 0xd1, 0xf0, 0xd9,
  4700. 0x14, 0x7a, 0x01, 0x33, 0x0f, 0xfe, 0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe,
  4701. 0x6c, 0x19, 0xbe, 0x39, 0xfe, 0xed, 0x19, 0xbf, 0x3a, 0xfe, 0x0c, 0x51,
  4702. 0xfe, 0x8e, 0x51, 0xe9, 0x1c, 0xfe, 0x00, 0xff, 0x34, 0xfe, 0x74, 0x10,
  4703. 0xb5, 0xfe, 0xd2, 0xf0, 0xfe, 0xb2, 0x0a, 0xfe, 0x76, 0x18, 0x1c, 0x1a,
  4704. 0x84, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0x08, 0x13, 0x0f, 0xfe, 0x16, 0x00,
  4705. 0x02, 0x5a, 0xfe, 0xd1, 0xf0, 0xfe, 0xc4, 0x0a, 0x14, 0x7a, 0x01, 0x33,
  4706. 0x0f, 0xfe, 0x17, 0x00, 0xfe, 0x42, 0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xca,
  4707. 0x0a, 0xfe, 0x3c, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xd6, 0x0a, 0x0f, 0xfe,
  4708. 0x22, 0x00, 0x02, 0x5a, 0xfe, 0xcb, 0xf0, 0xfe, 0xe2, 0x0a, 0x0f, 0xfe,
  4709. 0x24, 0x00, 0x02, 0x5a, 0xfe, 0xd0, 0xf0, 0xfe, 0xec, 0x0a, 0x0f, 0x93,
  4710. 0xdc, 0xfe, 0xcf, 0xf0, 0xfe, 0xf6, 0x0a, 0x0f, 0x4c, 0xfe, 0x10, 0x10,
  4711. 0xfe, 0xcc, 0xf0, 0xd9, 0x61, 0x04, 0x19, 0x3b, 0x0f, 0xfe, 0x12, 0x00,
  4712. 0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x0c, 0x0b, 0xfe, 0x9e, 0xf0,
  4713. 0xfe, 0x20, 0x0b, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0x22, 0xb9,
  4714. 0x22, 0x2a, 0xec, 0x65, 0xfe, 0x2c, 0x0b, 0x25, 0x32, 0x8c, 0xfe, 0x48,
  4715. 0x0b, 0x8d, 0x81, 0xb8, 0xd4, 0xb9, 0xd4, 0x02, 0x22, 0x01, 0x43, 0xfe,
  4716. 0xdb, 0x10, 0x11, 0xfe, 0xe8, 0x00, 0xaa, 0xab, 0x70, 0xbc, 0x7d, 0xbd,
  4717. 0x7f, 0xfe, 0x89, 0xf0, 0x22, 0x30, 0x2e, 0xd8, 0xbc, 0x7d, 0xbd, 0x7f,
  4718. 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd6, 0xb1, 0x45, 0x0f, 0xfe, 0x42,
  4719. 0x00, 0x02, 0x5a, 0x78, 0x06, 0xfe, 0x81, 0x49, 0x16, 0xfe, 0x38, 0x0c,
  4720. 0x09, 0x04, 0x0b, 0xfe, 0x44, 0x13, 0x0f, 0x00, 0x4b, 0x0b, 0xfe, 0x54,
  4721. 0x12, 0x4b, 0xfe, 0x28, 0x00, 0x21, 0xfe, 0xa6, 0x0c, 0x0a, 0x40, 0x01,
  4722. 0x0e, 0x07, 0x00, 0x5d, 0x3e, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01,
  4723. 0xe7, 0x01, 0xe8, 0x0a, 0x99, 0x01, 0xfe, 0x32, 0x0e, 0x59, 0x11, 0x2d,
  4724. 0x01, 0x6f, 0x02, 0x29, 0x0f, 0xfe, 0x44, 0x00, 0x4b, 0x0b, 0xdf, 0x3e,
  4725. 0x0b, 0xfe, 0xb4, 0x10, 0x01, 0x86, 0x3e, 0x0b, 0xfe, 0xaa, 0x10, 0x01,
  4726. 0x86, 0xfe, 0x19, 0x82, 0xfe, 0x34, 0x46, 0xa3, 0x3e, 0x0b, 0x0f, 0xfe,
  4727. 0x43, 0x00, 0xfe, 0x96, 0x10, 0x09, 0x4a, 0x0b, 0x35, 0x01, 0xe7, 0x01,
  4728. 0xe8, 0x59, 0x11, 0x2d, 0x01, 0x6f, 0x67, 0x0b, 0x59, 0x3c, 0x8a, 0x02,
  4729. 0xfe, 0x2a, 0x03, 0x09, 0x04, 0x0b, 0x84, 0x3e, 0x0b, 0x0f, 0x00, 0xfe,
  4730. 0x5c, 0x10, 0x61, 0x04, 0x1b, 0xfe, 0x58, 0x12, 0x09, 0x04, 0x1b, 0xfe,
  4731. 0x50, 0x13, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x5c, 0x0c, 0xfe,
  4732. 0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x62, 0x0c, 0x09, 0x4a, 0x1b, 0x35,
  4733. 0xfe, 0xa9, 0x10, 0x0f, 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0b, 0x5f,
  4734. 0x5c, 0x0f, 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x0f, 0xfe, 0x47, 0x00,
  4735. 0xa1, 0x0f, 0xfe, 0x41, 0x00, 0xa0, 0x0f, 0xfe, 0x24, 0x00, 0x87, 0xaa,
  4736. 0xab, 0x70, 0x05, 0x6b, 0x28, 0x21, 0xd1, 0x5f, 0xfe, 0x04, 0xe6, 0x1b,
  4737. 0xfe, 0x9d, 0x41, 0xfe, 0x1c, 0x42, 0x59, 0x01, 0xda, 0x02, 0x29, 0xea,
  4738. 0x14, 0x0b, 0x37, 0x95, 0xa9, 0x14, 0xfe, 0x31, 0x00, 0x37, 0x97, 0x01,
  4739. 0xfe, 0x54, 0x0f, 0x02, 0xd0, 0x3c, 0xfe, 0x06, 0xec, 0xc9, 0xee, 0x3e,
  4740. 0x1d, 0xfe, 0xce, 0x45, 0x34, 0x3c, 0xfe, 0x06, 0xea, 0xc9, 0xfe, 0x47,
  4741. 0x4b, 0x89, 0xfe, 0x75, 0x57, 0x05, 0x51, 0xfe, 0x98, 0x56, 0xfe, 0x38,
  4742. 0x12, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x44, 0x48, 0x46, 0x09, 0x04, 0x1d,
  4743. 0xfe, 0x1a, 0x13, 0x0a, 0x40, 0x01, 0x0e, 0x47, 0xfe, 0x41, 0x58, 0x0a,
  4744. 0x99, 0x01, 0x0e, 0xfe, 0x49, 0x54, 0x8e, 0xfe, 0x2a, 0x0d, 0x02, 0xfe,
  4745. 0x2a, 0x03, 0x0a, 0x51, 0xfe, 0xee, 0x14, 0xee, 0x3e, 0x1d, 0xfe, 0xce,
  4746. 0x45, 0x34, 0x3c, 0xfe, 0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x29, 0x1e,
  4747. 0x20, 0x07, 0x10, 0xfe, 0x9e, 0x12, 0x23, 0x12, 0x4d, 0x12, 0x94, 0x12,
  4748. 0xce, 0x1e, 0x2d, 0x47, 0x37, 0x2d, 0xb1, 0xe0, 0xfe, 0xbc, 0xf0, 0xfe,
  4749. 0xec, 0x0d, 0x13, 0x06, 0x12, 0x4d, 0x01, 0xfe, 0xe2, 0x15, 0x05, 0xfe,
  4750. 0x38, 0x01, 0x31, 0xfe, 0x3a, 0x01, 0x77, 0xfe, 0xf0, 0x0d, 0xfe, 0x02,
  4751. 0xec, 0xce, 0x62, 0x00, 0x5d, 0xfe, 0x04, 0xec, 0x20, 0x46, 0xfe, 0x05,
  4752. 0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x52, 0x16, 0xfb, 0xfe, 0x48, 0xf4,
  4753. 0x0d, 0xfe, 0x18, 0x13, 0xaf, 0xfe, 0x02, 0xea, 0xce, 0x62, 0x7a, 0xfe,
  4754. 0xc5, 0x13, 0x14, 0x1b, 0x37, 0x95, 0xa9, 0x5c, 0x05, 0xfe, 0x38, 0x01,
  4755. 0x1c, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x05, 0xfe, 0x3a, 0x01,
  4756. 0x0c, 0xfe, 0x62, 0x01, 0x3d, 0x12, 0x20, 0x24, 0x06, 0x12, 0x2d, 0x11,
  4757. 0x2d, 0x8a, 0x13, 0x06, 0x03, 0x23, 0x03, 0x1e, 0x4d, 0xfe, 0xf7, 0x12,
  4758. 0x1e, 0x94, 0xac, 0x12, 0x94, 0x07, 0x7a, 0xfe, 0x71, 0x13, 0xfe, 0x24,
  4759. 0x1c, 0x14, 0x1a, 0x37, 0x95, 0xa9, 0xfe, 0xd9, 0x10, 0xb6, 0xfe, 0x03,
  4760. 0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xb6, 0xfe, 0x03, 0xdc,
  4761. 0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x23,
  4762. 0xfe, 0x00, 0xcc, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x75, 0x03, 0x09, 0x04,
  4763. 0x4c, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13,
  4764. 0xfe, 0x1e, 0x80, 0xe1, 0xfe, 0x1d, 0x80, 0xa4, 0xfe, 0x0c, 0x90, 0xfe,
  4765. 0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xa3, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4,
  4766. 0x0b, 0xfe, 0x3c, 0x50, 0xa0, 0x01, 0xfe, 0x82, 0x16, 0x2f, 0x07, 0x2d,
  4767. 0xe0, 0x01, 0xfe, 0xbc, 0x15, 0x09, 0x04, 0x1d, 0x45, 0x01, 0xe7, 0x01,
  4768. 0xe8, 0x11, 0xfe, 0xe9, 0x00, 0x09, 0x04, 0x4c, 0xfe, 0x2c, 0x13, 0x01,
  4769. 0xfe, 0x14, 0x16, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90,
  4770. 0x0c, 0xfe, 0x64, 0x01, 0x18, 0xfe, 0x66, 0x01, 0x09, 0x04, 0x4f, 0xfe,
  4771. 0x12, 0x12, 0xfe, 0x03, 0x80, 0x74, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80,
  4772. 0x40, 0x12, 0x20, 0x63, 0x27, 0x11, 0xc8, 0x59, 0x1e, 0x20, 0xed, 0x76,
  4773. 0x20, 0x03, 0xfe, 0x08, 0x1c, 0x05, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58,
  4774. 0x05, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x05, 0xfe, 0xb0, 0x00, 0xfe,
  4775. 0x08, 0x58, 0x05, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c,
  4776. 0x24, 0x69, 0x12, 0xc9, 0x23, 0x0c, 0x50, 0x0c, 0x3f, 0x13, 0x40, 0x48,
  4777. 0x5f, 0x17, 0x1d, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x21, 0xfe, 0x08,
  4778. 0x0f, 0x3e, 0x10, 0x13, 0x42, 0x48, 0x17, 0x4c, 0xfe, 0x90, 0x4d, 0xfe,
  4779. 0x91, 0x54, 0x21, 0xfe, 0x1e, 0x0f, 0x24, 0x10, 0x12, 0x20, 0x78, 0x2c,
  4780. 0x46, 0x1e, 0x20, 0xed, 0x76, 0x20, 0x11, 0xc8, 0xf6, 0xfe, 0xd6, 0xf0,
  4781. 0xfe, 0x32, 0x0f, 0xea, 0x70, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe,
  4782. 0x18, 0x1c, 0x03, 0x3c, 0xfe, 0x0c, 0x14, 0xee, 0xfe, 0x07, 0xe6, 0x1d,
  4783. 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x03, 0x01, 0x86, 0x78, 0x2c, 0x46,
  4784. 0xfa, 0xef, 0xfe, 0x42, 0x13, 0x2f, 0x07, 0x2d, 0xfe, 0x34, 0x13, 0x0a,
  4785. 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x36, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01,
  4786. 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10,
  4787. 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xfe, 0x80, 0x5c, 0x01, 0x6f, 0xfe, 0x0e,
  4788. 0x10, 0x07, 0x7e, 0x45, 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x6c, 0x0f, 0x03,
  4789. 0xfe, 0x44, 0x58, 0x74, 0xfe, 0x01, 0xec, 0x97, 0xfe, 0x9e, 0x40, 0xfe,
  4790. 0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x1b, 0x76, 0x27, 0x01, 0xda, 0xfe,
  4791. 0xdd, 0x10, 0x2a, 0xbc, 0x7d, 0xbd, 0x7f, 0x30, 0x2e, 0xd5, 0x07, 0x1b,
  4792. 0xfe, 0x48, 0x12, 0x07, 0x0b, 0xfe, 0x56, 0x12, 0x07, 0x1a, 0xfe, 0x30,
  4793. 0x12, 0x07, 0xc2, 0x16, 0xfe, 0x3e, 0x11, 0x07, 0xfe, 0x23, 0x00, 0x16,
  4794. 0xfe, 0x4a, 0x11, 0x07, 0x06, 0x16, 0xfe, 0xa8, 0x11, 0x07, 0x19, 0xfe,
  4795. 0x12, 0x12, 0x07, 0x00, 0x16, 0x22, 0x14, 0xc2, 0x01, 0x33, 0x9f, 0x2b,
  4796. 0x01, 0x08, 0x8c, 0x43, 0x03, 0x2b, 0xfe, 0x62, 0x08, 0x0a, 0xca, 0x01,
  4797. 0xfe, 0x32, 0x0e, 0x11, 0x7e, 0x02, 0x29, 0x2b, 0x2f, 0x07, 0x9b, 0xfe,
  4798. 0xd9, 0x13, 0x79, 0x39, 0x68, 0x3a, 0x77, 0xfe, 0xfc, 0x10, 0x09, 0x04,
  4799. 0x6a, 0xfe, 0x72, 0x12, 0xc0, 0x38, 0xc1, 0x4e, 0xf4, 0xf5, 0x8e, 0xfe,
  4800. 0xc6, 0x10, 0x1e, 0x58, 0xfe, 0x26, 0x13, 0x05, 0x7b, 0x31, 0x7c, 0x77,
  4801. 0xfe, 0x82, 0x0c, 0x0c, 0x54, 0x18, 0x55, 0x23, 0x0c, 0x7b, 0x0c, 0x7c,
  4802. 0x01, 0xa8, 0x24, 0x69, 0x73, 0x12, 0x58, 0x01, 0xa5, 0xc0, 0x38, 0xc1,
  4803. 0x4e, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x38, 0xfe,
  4804. 0x05, 0xfa, 0x4e, 0xfe, 0x91, 0x10, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x40,
  4805. 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x56, 0x18, 0x57, 0x83, 0xc0, 0x38, 0xc1,
  4806. 0x4e, 0xf4, 0xf5, 0x05, 0x52, 0x31, 0x53, 0xfe, 0x00, 0x56, 0xfe, 0xa1,
  4807. 0x56, 0x0c, 0x52, 0x18, 0x53, 0x09, 0x04, 0x6a, 0xfe, 0x1e, 0x12, 0x1e,
  4808. 0x58, 0xfe, 0x1f, 0x40, 0x05, 0x54, 0x31, 0x55, 0xfe, 0x2c, 0x50, 0xfe,
  4809. 0xae, 0x50, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x44, 0x50, 0xfe, 0xc6, 0x50,
  4810. 0x05, 0x52, 0x31, 0x53, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x05, 0x39,
  4811. 0x31, 0x3a, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x02, 0x5c, 0x24, 0x06,
  4812. 0x12, 0xcd, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x1f, 0x44, 0x30, 0x2e, 0xd5,
  4813. 0x07, 0x06, 0x21, 0x44, 0x2f, 0x07, 0x9b, 0x21, 0x5b, 0x01, 0x6e, 0x1c,
  4814. 0x3d, 0x16, 0x44, 0x09, 0x04, 0x0b, 0xe2, 0x79, 0x39, 0x68, 0x3a, 0xfe,
  4815. 0x0a, 0x55, 0x34, 0xfe, 0x8b, 0x55, 0xbe, 0x39, 0xbf, 0x3a, 0xfe, 0x0c,
  4816. 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x5b, 0xfe, 0x19, 0x81, 0xaf, 0xfe, 0x19,
  4817. 0x41, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e,
  4818. 0xd8, 0x4b, 0x1a, 0xfe, 0xa6, 0x12, 0x4b, 0x0b, 0x3b, 0x02, 0x44, 0x01,
  4819. 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e, 0xd6, 0x07, 0x1a, 0x21, 0x44,
  4820. 0x01, 0x08, 0x1f, 0xa2, 0x30, 0x2e, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49,
  4821. 0x60, 0x05, 0xfe, 0x9c, 0x00, 0x28, 0x84, 0x49, 0x04, 0x19, 0x34, 0x9f,
  4822. 0xfe, 0xbb, 0x45, 0x4b, 0x00, 0x45, 0x3e, 0x06, 0x78, 0x3d, 0xfe, 0xda,
  4823. 0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1,
  4824. 0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe,
  4825. 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c,
  4826. 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
  4827. 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06,
  4828. 0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14,
  4829. 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a,
  4830. 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
  4831. 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe,
  4832. 0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe,
  4833. 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc,
  4834. 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
  4835. 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
  4836. 0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13,
  4837. 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56,
  4838. 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
  4839. 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58,
  4840. 0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
  4841. 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
  4842. 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
  4843. 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
  4844. 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
  4845. 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
  4846. 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
  4847. 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
  4848. 0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
  4849. 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
  4850. 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
  4851. 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
  4852. 0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
  4853. 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
  4854. 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
  4855. 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
  4856. 0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
  4857. 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
  4858. 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
  4859. 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
  4860. 0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
  4861. 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
  4862. 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
  4863. 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
  4864. 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
  4865. 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
  4866. 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
  4867. 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
  4868. 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
  4869. 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
  4870. 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
  4871. 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
  4872. 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
  4873. 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
  4874. 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
  4875. 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
  4876. 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
  4877. 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
  4878. 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
  4879. 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
  4880. 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
  4881. 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
  4882. 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
  4883. 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
  4884. 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
  4885. 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
  4886. 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
  4887. 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
  4888. 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
  4889. 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
  4890. 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
  4891. 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
  4892. 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
  4893. 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
  4894. 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
  4895. 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
  4896. 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
  4897. 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
  4898. 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
  4899. 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
  4900. 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
  4901. 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
  4902. 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
  4903. 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
  4904. 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
  4905. 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
  4906. 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
  4907. 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
  4908. 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
  4909. 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
  4910. 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
  4911. 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
  4912. 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
  4913. 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
  4914. 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
  4915. 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
  4916. 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
  4917. 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
  4918. 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
  4919. 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
  4920. 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
  4921. 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
  4922. 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
  4923. 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
  4924. 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
  4925. 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
  4926. 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
  4927. 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
  4928. 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
  4929. 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
  4930. };
  4931. static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
  4932. static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
  4933. /* Microcode buffer is kept after initialization for error recovery. */
  4934. static unsigned char _adv_asc38C0800_buf[] = {
  4935. 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
  4936. 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
  4937. 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
  4938. 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
  4939. 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
  4940. 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
  4941. 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
  4942. 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
  4943. 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
  4944. 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
  4945. 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
  4946. 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
  4947. 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
  4948. 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
  4949. 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
  4950. 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
  4951. 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
  4952. 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
  4953. 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
  4954. 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
  4955. 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
  4956. 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
  4957. 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
  4958. 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
  4959. 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
  4960. 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
  4961. 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
  4962. 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
  4963. 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
  4964. 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
  4965. 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
  4966. 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
  4967. 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
  4968. 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
  4969. 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
  4970. 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
  4971. 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
  4972. 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
  4973. 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
  4974. 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
  4975. 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
  4976. 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
  4977. 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
  4978. 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
  4979. 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
  4980. 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00,
  4981. 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
  4982. 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
  4983. 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
  4984. 0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe,
  4985. 0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06,
  4986. 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
  4987. 0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
  4988. 0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe,
  4989. 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
  4990. 0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02,
  4991. 0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
  4992. 0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02,
  4993. 0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02,
  4994. 0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14,
  4995. 0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
  4996. 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10,
  4997. 0xfe, 0x06, 0xfc, 0xce, 0x09, 0x70, 0x01, 0xa8, 0x02, 0x2b, 0x15, 0x59,
  4998. 0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xbd,
  4999. 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
  5000. 0x58, 0x1c, 0x18, 0x06, 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0,
  5001. 0xfe, 0x06, 0x02, 0x23, 0xfe, 0x98, 0x02, 0xfe, 0x5a, 0x1c, 0xf8, 0xfe,
  5002. 0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10,
  5003. 0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe,
  5004. 0x69, 0x10, 0x18, 0x06, 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43,
  5005. 0x13, 0x20, 0xfe, 0x05, 0xf6, 0xce, 0x01, 0xfe, 0x4a, 0x17, 0x08, 0x54,
  5006. 0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b,
  5007. 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10,
  5008. 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe,
  5009. 0x10, 0x03, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, 0x2c, 0x4f, 0xfe, 0x02,
  5010. 0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe,
  5011. 0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7,
  5012. 0xfe, 0x40, 0x1c, 0x1c, 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe,
  5013. 0xa0, 0xf0, 0xfe, 0x48, 0x03, 0xfe, 0x11, 0xf0, 0xa7, 0xfe, 0xef, 0x10,
  5014. 0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10, 0xfe, 0x11, 0x00, 0x02,
  5015. 0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13,
  5016. 0x21, 0x22, 0xa3, 0xb7, 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78,
  5017. 0x01, 0xfe, 0xb4, 0x16, 0x12, 0xd1, 0x1c, 0xd9, 0xfe, 0x01, 0xf0, 0xd9,
  5018. 0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12, 0xfe, 0xe4, 0x00, 0x27,
  5019. 0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe,
  5020. 0x06, 0xf0, 0xfe, 0xc8, 0x03, 0x95, 0x86, 0xfe, 0x0a, 0xf0, 0xfe, 0x8a,
  5021. 0x06, 0x02, 0x24, 0x03, 0x70, 0x28, 0x17, 0xfe, 0xfa, 0x04, 0x15, 0x6d,
  5022. 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, 0xd8, 0xf9, 0x2c, 0x99, 0x19,
  5023. 0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c,
  5024. 0x74, 0x01, 0xaf, 0x8c, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x17, 0xda,
  5025. 0x09, 0xd1, 0x01, 0x0e, 0x8d, 0x51, 0x64, 0x79, 0x2a, 0x03, 0x70, 0x28,
  5026. 0xfe, 0x10, 0x12, 0x15, 0x6d, 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02,
  5027. 0xd8, 0xc7, 0x81, 0xc8, 0x83, 0x1c, 0x24, 0x27, 0xfe, 0x40, 0x04, 0x1d,
  5028. 0xfe, 0x3c, 0x04, 0x3b, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e,
  5029. 0x12, 0x2d, 0xff, 0x02, 0x00, 0x10, 0x01, 0x0b, 0x1d, 0xfe, 0xe4, 0x04,
  5030. 0x2d, 0x01, 0x0b, 0x1d, 0x24, 0x33, 0x31, 0xde, 0xfe, 0x4c, 0x44, 0xfe,
  5031. 0x4c, 0x12, 0x51, 0xfe, 0x44, 0x48, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b,
  5032. 0xda, 0x4f, 0x79, 0x2a, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x62,
  5033. 0x13, 0x08, 0x05, 0x1b, 0xfe, 0x2a, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x52,
  5034. 0x13, 0xfe, 0x20, 0x10, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b, 0xda, 0xfe,
  5035. 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x40, 0x13, 0x08, 0x05, 0x1b, 0xfe,
  5036. 0x08, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x30, 0x13, 0x08, 0x05, 0x1b, 0xfe,
  5037. 0x1c, 0x12, 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00,
  5038. 0x01, 0x36, 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x2d, 0x12, 0xfe, 0xe6,
  5039. 0x00, 0xfe, 0x1c, 0x90, 0xfe, 0x40, 0x5c, 0x04, 0x15, 0x9d, 0x01, 0x36,
  5040. 0x02, 0x2b, 0xfe, 0x42, 0x5b, 0x99, 0x19, 0xfe, 0x46, 0x59, 0xfe, 0xbf,
  5041. 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4, 0x5b, 0x08,
  5042. 0x05, 0x0a, 0xfe, 0x84, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x19, 0xfe, 0x7c,
  5043. 0x12, 0x53, 0x05, 0x06, 0xfe, 0x6c, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x28,
  5044. 0x17, 0xfe, 0x90, 0x05, 0xfe, 0x31, 0xe4, 0x5a, 0x53, 0x05, 0x0a, 0xfe,
  5045. 0x56, 0x13, 0x03, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x4e, 0x12, 0x67, 0xff,
  5046. 0x02, 0x00, 0x10, 0x27, 0xfe, 0x48, 0x05, 0x1c, 0x34, 0xfe, 0x89, 0x48,
  5047. 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x56, 0x05, 0x26, 0xfe, 0xa8, 0x05,
  5048. 0x12, 0xfe, 0xe3, 0x00, 0x21, 0x53, 0xfe, 0x4a, 0xf0, 0xfe, 0x76, 0x05,
  5049. 0xfe, 0x49, 0xf0, 0xfe, 0x70, 0x05, 0x88, 0x25, 0xfe, 0x21, 0x00, 0xab,
  5050. 0x25, 0xfe, 0x22, 0x00, 0xaa, 0x25, 0x58, 0xfe, 0x09, 0x48, 0xff, 0x02,
  5051. 0x00, 0x10, 0x27, 0xfe, 0x86, 0x05, 0x26, 0xfe, 0xa8, 0x05, 0xfe, 0xe2,
  5052. 0x08, 0x53, 0x05, 0xcb, 0x4d, 0x01, 0xb0, 0x25, 0x06, 0x13, 0xd3, 0x39,
  5053. 0xfe, 0x27, 0x01, 0x08, 0x05, 0x1b, 0xfe, 0x22, 0x12, 0x41, 0x01, 0xb2,
  5054. 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00, 0x01, 0x36,
  5055. 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0xeb,
  5056. 0x03, 0x5c, 0x28, 0xfe, 0x36, 0x13, 0x41, 0x01, 0xb2, 0x26, 0xfe, 0x18,
  5057. 0x06, 0x09, 0x06, 0x53, 0x05, 0x1f, 0xfe, 0x02, 0x12, 0x50, 0x01, 0xfe,
  5058. 0x9e, 0x15, 0x1d, 0xfe, 0x0e, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, 0xfe,
  5059. 0xe5, 0x00, 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x03, 0xcd, 0x28, 0xfe, 0x62,
  5060. 0x12, 0x03, 0x45, 0x28, 0xfe, 0x5a, 0x13, 0x01, 0xfe, 0x0c, 0x19, 0x01,
  5061. 0xfe, 0x76, 0x19, 0xfe, 0x43, 0x48, 0xc4, 0xcc, 0x0f, 0x71, 0xff, 0x02,
  5062. 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0x8b, 0xc4, 0x6e, 0x41, 0x01, 0xb2,
  5063. 0x26, 0xfe, 0x82, 0x06, 0x53, 0x05, 0x1a, 0xe9, 0x91, 0x09, 0x59, 0x01,
  5064. 0xfe, 0xcc, 0x15, 0x1d, 0xfe, 0x78, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12,
  5065. 0xfe, 0xe5, 0x00, 0x03, 0x45, 0xc1, 0x0c, 0x45, 0x18, 0x06, 0x01, 0xb2,
  5066. 0xfa, 0x76, 0x74, 0x01, 0xaf, 0x8c, 0x12, 0xfe, 0xe2, 0x00, 0x27, 0xdb,
  5067. 0x1c, 0x34, 0xfe, 0x0a, 0xf0, 0xfe, 0xb6, 0x06, 0x94, 0xfe, 0x6c, 0x07,
  5068. 0xfe, 0x06, 0xf0, 0xfe, 0x74, 0x07, 0x95, 0x86, 0x02, 0x24, 0x08, 0x05,
  5069. 0x0a, 0xfe, 0x2e, 0x12, 0x16, 0x19, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b,
  5070. 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0xfe, 0x99, 0xa4, 0x01,
  5071. 0x0b, 0x16, 0x00, 0x02, 0xfe, 0x42, 0x08, 0x68, 0x05, 0x1a, 0xfe, 0x38,
  5072. 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x30, 0x13, 0x16, 0xfe, 0x1b, 0x00, 0x01,
  5073. 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01,
  5074. 0x0b, 0x16, 0x06, 0x01, 0x0b, 0x16, 0x00, 0x02, 0xe2, 0x6c, 0x58, 0xbe,
  5075. 0x50, 0xfe, 0x9a, 0x81, 0x55, 0x1b, 0x7a, 0xfe, 0x42, 0x07, 0x09, 0x1b,
  5076. 0xfe, 0x09, 0x6f, 0xba, 0xfe, 0xca, 0x45, 0xfe, 0x32, 0x12, 0x69, 0x6d,
  5077. 0x8b, 0x6c, 0x7f, 0x27, 0xfe, 0x54, 0x07, 0x1c, 0x34, 0xfe, 0x0a, 0xf0,
  5078. 0xfe, 0x42, 0x07, 0x95, 0x86, 0x94, 0xfe, 0x6c, 0x07, 0x02, 0x24, 0x01,
  5079. 0x4b, 0x02, 0xdb, 0x16, 0x1f, 0x02, 0xdb, 0xfe, 0x9c, 0xf7, 0xdc, 0xfe,
  5080. 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x56, 0xfe, 0xda, 0x07, 0x0c, 0x60, 0x14,
  5081. 0x61, 0x08, 0x54, 0x5a, 0x37, 0x22, 0x20, 0x07, 0x11, 0xfe, 0x0e, 0x12,
  5082. 0x8d, 0xfe, 0x80, 0x80, 0x39, 0x20, 0x6a, 0x2a, 0xfe, 0x06, 0x10, 0xfe,
  5083. 0x83, 0xe7, 0xfe, 0x48, 0x00, 0xab, 0xfe, 0x03, 0x40, 0x08, 0x54, 0x5b,
  5084. 0x37, 0x01, 0xb3, 0xb8, 0xfe, 0x1f, 0x40, 0x13, 0x62, 0x01, 0xef, 0xfe,
  5085. 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe, 0x44, 0x51, 0xfe, 0xc6, 0x51, 0x88,
  5086. 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90, 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x0c,
  5087. 0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x0c, 0x3d,
  5088. 0x14, 0x3e, 0xfe, 0x4a, 0x10, 0x08, 0x05, 0x5a, 0xfe, 0x2a, 0x12, 0xfe,
  5089. 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x60, 0x14, 0x61, 0x08, 0x05, 0x5b,
  5090. 0x8b, 0x01, 0xb3, 0xfe, 0x1f, 0x80, 0x13, 0x62, 0xfe, 0x44, 0x90, 0xfe,
  5091. 0xc6, 0x90, 0x0c, 0x3f, 0x14, 0x40, 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90,
  5092. 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90, 0x0c, 0x3d,
  5093. 0x14, 0x3e, 0x0c, 0x2e, 0x14, 0x3c, 0x21, 0x0c, 0x49, 0x0c, 0x63, 0x08,
  5094. 0x54, 0x1f, 0x37, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27, 0xdd, 0xfe, 0x9e,
  5095. 0xf0, 0xfe, 0x76, 0x08, 0xbc, 0x17, 0x34, 0x2c, 0x77, 0xe6, 0xc5, 0xfe,
  5096. 0x9a, 0x08, 0xc6, 0xfe, 0xb8, 0x08, 0x94, 0xfe, 0x8e, 0x08, 0xfe, 0x06,
  5097. 0xf0, 0xfe, 0x94, 0x08, 0x95, 0x86, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xc9,
  5098. 0x10, 0x16, 0x1f, 0xfe, 0xc9, 0x10, 0x68, 0x05, 0x06, 0xfe, 0x10, 0x12,
  5099. 0x68, 0x05, 0x0a, 0x4e, 0x08, 0x05, 0x0a, 0xfe, 0x90, 0x12, 0xfe, 0x2e,
  5100. 0x1c, 0x02, 0xfe, 0x18, 0x0b, 0x68, 0x05, 0x06, 0x4e, 0x68, 0x05, 0x0a,
  5101. 0xfe, 0x7a, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0xd2, 0x09,
  5102. 0xfe, 0xac, 0xf0, 0xfe, 0x00, 0x09, 0x02, 0xfe, 0xde, 0x09, 0xfe, 0xb7,
  5103. 0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0x02, 0xf6, 0x1a, 0x50, 0xfe, 0x70, 0x18,
  5104. 0xfe, 0xf1, 0x18, 0xfe, 0x40, 0x55, 0xfe, 0xe1, 0x55, 0xfe, 0x10, 0x58,
  5105. 0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x1c, 0x85, 0xfe,
  5106. 0x8c, 0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0xac, 0xf0, 0xfe, 0xf0, 0x08, 0xb5,
  5107. 0xfe, 0xcb, 0x10, 0xfe, 0xad, 0xf0, 0xfe, 0x0c, 0x09, 0x02, 0xfe, 0x18,
  5108. 0x0b, 0xb6, 0xfe, 0xbf, 0x10, 0xfe, 0x2b, 0xf0, 0x85, 0xf4, 0x1e, 0xfe,
  5109. 0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xc2, 0xfe, 0xd2, 0xf0, 0x85, 0xfe, 0x76,
  5110. 0x18, 0x1e, 0x19, 0x17, 0x85, 0x03, 0xd2, 0x1e, 0x06, 0x17, 0x85, 0xc5,
  5111. 0x4a, 0xc6, 0x4a, 0xb5, 0xb6, 0xfe, 0x89, 0x10, 0x74, 0x67, 0x2d, 0x15,
  5112. 0x9d, 0x01, 0x36, 0x10, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x65, 0x10,
  5113. 0x80, 0x02, 0x65, 0xfe, 0x98, 0x80, 0xfe, 0x19, 0xe4, 0x0a, 0xfe, 0x1a,
  5114. 0x12, 0x51, 0xfe, 0x19, 0x82, 0xfe, 0x6c, 0x18, 0xfe, 0x44, 0x54, 0xbe,
  5115. 0xfe, 0x19, 0x81, 0xfe, 0x74, 0x18, 0x8f, 0x90, 0x17, 0xfe, 0xce, 0x08,
  5116. 0x02, 0x4a, 0x08, 0x05, 0x5a, 0xec, 0x03, 0x2e, 0x29, 0x3c, 0x0c, 0x3f,
  5117. 0x14, 0x40, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x6c, 0x18, 0xfe, 0xed, 0x18,
  5118. 0xfe, 0x44, 0x54, 0xfe, 0xe5, 0x54, 0x3a, 0x3f, 0x3b, 0x40, 0x03, 0x49,
  5119. 0x29, 0x63, 0x8f, 0xfe, 0xe3, 0x54, 0xfe, 0x74, 0x18, 0xfe, 0xf5, 0x18,
  5120. 0x8f, 0xfe, 0xe3, 0x54, 0x90, 0xc0, 0x56, 0xfe, 0xce, 0x08, 0x02, 0x4a,
  5121. 0xfe, 0x37, 0xf0, 0xfe, 0xda, 0x09, 0xfe, 0x8b, 0xf0, 0xfe, 0x60, 0x09,
  5122. 0x02, 0x4a, 0x08, 0x05, 0x0a, 0x23, 0xfe, 0xfa, 0x0a, 0x3a, 0x49, 0x3b,
  5123. 0x63, 0x56, 0xfe, 0x3e, 0x0a, 0x0f, 0xfe, 0xc0, 0x07, 0x41, 0x98, 0x00,
  5124. 0xad, 0xfe, 0x01, 0x59, 0xfe, 0x52, 0xf0, 0xfe, 0x0c, 0x0a, 0x8f, 0x7a,
  5125. 0xfe, 0x24, 0x0a, 0x3a, 0x49, 0x8f, 0xfe, 0xe3, 0x54, 0x57, 0x49, 0x7d,
  5126. 0x63, 0xfe, 0x14, 0x58, 0xfe, 0x95, 0x58, 0x02, 0x4a, 0x3a, 0x49, 0x3b,
  5127. 0x63, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0xbe, 0x57, 0x49, 0x57, 0x63,
  5128. 0x02, 0x4a, 0x08, 0x05, 0x5a, 0xfe, 0x82, 0x12, 0x08, 0x05, 0x1f, 0xfe,
  5129. 0x66, 0x13, 0x22, 0x62, 0xb7, 0xfe, 0x03, 0xa1, 0xfe, 0x83, 0x80, 0xfe,
  5130. 0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91, 0xfe, 0x86, 0x91, 0x6a,
  5131. 0x2a, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x56, 0xe0, 0x03, 0x60, 0x29,
  5132. 0x61, 0x0c, 0x7f, 0x14, 0x80, 0x57, 0x60, 0x7d, 0x61, 0x01, 0xb3, 0xb8,
  5133. 0x6a, 0x2a, 0x13, 0x62, 0x9b, 0x2e, 0x9c, 0x3c, 0x3a, 0x3f, 0x3b, 0x40,
  5134. 0x90, 0xc0, 0xfe, 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0x01, 0xef,
  5135. 0xfe, 0x36, 0x10, 0x21, 0x0c, 0x7f, 0x0c, 0x80, 0x3a, 0x3f, 0x3b, 0x40,
  5136. 0xe4, 0x08, 0x05, 0x1f, 0x17, 0xe0, 0x3a, 0x3d, 0x3b, 0x3e, 0x08, 0x05,
  5137. 0xfe, 0xf7, 0x00, 0x37, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x10, 0x58, 0xfe,
  5138. 0x91, 0x58, 0x57, 0x49, 0x7d, 0x63, 0x02, 0xfe, 0xf4, 0x09, 0x08, 0x05,
  5139. 0x1f, 0x17, 0xe0, 0x08, 0x05, 0xfe, 0xf7, 0x00, 0x37, 0xbe, 0xfe, 0x19,
  5140. 0x81, 0x50, 0xfe, 0x10, 0x90, 0xfe, 0x92, 0x90, 0xfe, 0xd3, 0x10, 0x32,
  5141. 0x07, 0xa6, 0x17, 0xfe, 0x08, 0x09, 0x12, 0xa6, 0x08, 0x05, 0x0a, 0xfe,
  5142. 0x14, 0x13, 0x03, 0x3d, 0x29, 0x3e, 0x56, 0xfe, 0x08, 0x09, 0xfe, 0x0c,
  5143. 0x58, 0xfe, 0x8d, 0x58, 0x02, 0x4a, 0x21, 0x41, 0xfe, 0x19, 0x80, 0xe7,
  5144. 0x08, 0x05, 0x0a, 0xfe, 0x1a, 0x12, 0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41,
  5145. 0xf4, 0xc2, 0xfe, 0xd1, 0xf0, 0xe2, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe,
  5146. 0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe, 0x6c, 0x19, 0x57, 0x3d, 0xfe, 0xed,
  5147. 0x19, 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0xf4, 0x1e, 0xfe,
  5148. 0x00, 0xff, 0x35, 0xfe, 0x74, 0x10, 0xc2, 0xfe, 0xd2, 0xf0, 0xfe, 0xa6,
  5149. 0x0b, 0xfe, 0x76, 0x18, 0x1e, 0x19, 0x8a, 0x03, 0xd2, 0x1e, 0x06, 0xfe,
  5150. 0x08, 0x13, 0x10, 0xfe, 0x16, 0x00, 0x02, 0x65, 0xfe, 0xd1, 0xf0, 0xfe,
  5151. 0xb8, 0x0b, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe, 0x17, 0x00, 0xfe, 0x42,
  5152. 0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xbe, 0x0b, 0xfe, 0x3c, 0x10, 0xfe, 0xcd,
  5153. 0xf0, 0xfe, 0xca, 0x0b, 0x10, 0xfe, 0x22, 0x00, 0x02, 0x65, 0xfe, 0xcb,
  5154. 0xf0, 0xfe, 0xd6, 0x0b, 0x10, 0xfe, 0x24, 0x00, 0x02, 0x65, 0xfe, 0xd0,
  5155. 0xf0, 0xfe, 0xe0, 0x0b, 0x10, 0x9e, 0xe5, 0xfe, 0xcf, 0xf0, 0xfe, 0xea,
  5156. 0x0b, 0x10, 0x58, 0xfe, 0x10, 0x10, 0xfe, 0xcc, 0xf0, 0xe2, 0x68, 0x05,
  5157. 0x1f, 0x4d, 0x10, 0xfe, 0x12, 0x00, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27,
  5158. 0xfe, 0x00, 0x0c, 0xfe, 0x9e, 0xf0, 0xfe, 0x14, 0x0c, 0xbc, 0x17, 0x34,
  5159. 0x2c, 0x77, 0xe6, 0xc5, 0x24, 0xc6, 0x24, 0x2c, 0xfa, 0x27, 0xfe, 0x20,
  5160. 0x0c, 0x1c, 0x34, 0x94, 0xfe, 0x3c, 0x0c, 0x95, 0x86, 0xc5, 0xdc, 0xc6,
  5161. 0xdc, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xdb, 0x10, 0x12, 0xfe, 0xe8, 0x00,
  5162. 0xb5, 0xb6, 0x74, 0xc7, 0x81, 0xc8, 0x83, 0xfe, 0x89, 0xf0, 0x24, 0x33,
  5163. 0x31, 0xe1, 0xc7, 0x81, 0xc8, 0x83, 0x27, 0xfe, 0x66, 0x0c, 0x1d, 0x24,
  5164. 0x33, 0x31, 0xdf, 0xbc, 0x4e, 0x10, 0xfe, 0x42, 0x00, 0x02, 0x65, 0x7c,
  5165. 0x06, 0xfe, 0x81, 0x49, 0x17, 0xfe, 0x2c, 0x0d, 0x08, 0x05, 0x0a, 0xfe,
  5166. 0x44, 0x13, 0x10, 0x00, 0x55, 0x0a, 0xfe, 0x54, 0x12, 0x55, 0xfe, 0x28,
  5167. 0x00, 0x23, 0xfe, 0x9a, 0x0d, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66,
  5168. 0x44, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01, 0xf5, 0x01, 0xf6, 0x09,
  5169. 0xa4, 0x01, 0xfe, 0x26, 0x0f, 0x64, 0x12, 0x2f, 0x01, 0x73, 0x02, 0x2b,
  5170. 0x10, 0xfe, 0x44, 0x00, 0x55, 0x0a, 0xe9, 0x44, 0x0a, 0xfe, 0xb4, 0x10,
  5171. 0x01, 0xb0, 0x44, 0x0a, 0xfe, 0xaa, 0x10, 0x01, 0xb0, 0xfe, 0x19, 0x82,
  5172. 0xfe, 0x34, 0x46, 0xac, 0x44, 0x0a, 0x10, 0xfe, 0x43, 0x00, 0xfe, 0x96,
  5173. 0x10, 0x08, 0x54, 0x0a, 0x37, 0x01, 0xf5, 0x01, 0xf6, 0x64, 0x12, 0x2f,
  5174. 0x01, 0x73, 0x99, 0x0a, 0x64, 0x42, 0x92, 0x02, 0xfe, 0x2e, 0x03, 0x08,
  5175. 0x05, 0x0a, 0x8a, 0x44, 0x0a, 0x10, 0x00, 0xfe, 0x5c, 0x10, 0x68, 0x05,
  5176. 0x1a, 0xfe, 0x58, 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x50, 0x13, 0xfe, 0x1c,
  5177. 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x50, 0x0d, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d,
  5178. 0xf0, 0xfe, 0x56, 0x0d, 0x08, 0x54, 0x1a, 0x37, 0xfe, 0xa9, 0x10, 0x10,
  5179. 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0a, 0x50, 0xfe, 0x2e, 0x10, 0x10,
  5180. 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x10, 0x6f, 0xab, 0x10, 0xfe, 0x41,
  5181. 0x00, 0xaa, 0x10, 0xfe, 0x24, 0x00, 0x8c, 0xb5, 0xb6, 0x74, 0x03, 0x70,
  5182. 0x28, 0x23, 0xd8, 0x50, 0xfe, 0x04, 0xe6, 0x1a, 0xfe, 0x9d, 0x41, 0xfe,
  5183. 0x1c, 0x42, 0x64, 0x01, 0xe3, 0x02, 0x2b, 0xf8, 0x15, 0x0a, 0x39, 0xa0,
  5184. 0xb4, 0x15, 0xfe, 0x31, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10, 0x02,
  5185. 0xd7, 0x42, 0xfe, 0x06, 0xec, 0xd0, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45,
  5186. 0x35, 0x42, 0xfe, 0x06, 0xea, 0xd0, 0xfe, 0x47, 0x4b, 0x91, 0xfe, 0x75,
  5187. 0x57, 0x03, 0x5d, 0xfe, 0x98, 0x56, 0xfe, 0x38, 0x12, 0x09, 0x48, 0x01,
  5188. 0x0e, 0xfe, 0x44, 0x48, 0x4f, 0x08, 0x05, 0x1b, 0xfe, 0x1a, 0x13, 0x09,
  5189. 0x46, 0x01, 0x0e, 0x41, 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe,
  5190. 0x49, 0x54, 0x96, 0xfe, 0x1e, 0x0e, 0x02, 0xfe, 0x2e, 0x03, 0x09, 0x5d,
  5191. 0xfe, 0xee, 0x14, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45, 0x35, 0x42, 0xfe,
  5192. 0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x2b, 0x22, 0x20, 0x07, 0x11, 0xfe,
  5193. 0x9e, 0x12, 0x21, 0x13, 0x59, 0x13, 0x9f, 0x13, 0xd5, 0x22, 0x2f, 0x41,
  5194. 0x39, 0x2f, 0xbc, 0xad, 0xfe, 0xbc, 0xf0, 0xfe, 0xe0, 0x0e, 0x0f, 0x06,
  5195. 0x13, 0x59, 0x01, 0xfe, 0xda, 0x16, 0x03, 0xfe, 0x38, 0x01, 0x29, 0xfe,
  5196. 0x3a, 0x01, 0x56, 0xfe, 0xe4, 0x0e, 0xfe, 0x02, 0xec, 0xd5, 0x69, 0x00,
  5197. 0x66, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01,
  5198. 0x01, 0xfe, 0x4a, 0x17, 0xfe, 0x08, 0x90, 0xfe, 0x48, 0xf4, 0x0d, 0xfe,
  5199. 0x18, 0x13, 0xba, 0xfe, 0x02, 0xea, 0xd5, 0x69, 0x7e, 0xfe, 0xc5, 0x13,
  5200. 0x15, 0x1a, 0x39, 0xa0, 0xb4, 0xfe, 0x2e, 0x10, 0x03, 0xfe, 0x38, 0x01,
  5201. 0x1e, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x03, 0xfe, 0x3a, 0x01,
  5202. 0x0c, 0xfe, 0x62, 0x01, 0x43, 0x13, 0x20, 0x25, 0x06, 0x13, 0x2f, 0x12,
  5203. 0x2f, 0x92, 0x0f, 0x06, 0x04, 0x21, 0x04, 0x22, 0x59, 0xfe, 0xf7, 0x12,
  5204. 0x22, 0x9f, 0xb7, 0x13, 0x9f, 0x07, 0x7e, 0xfe, 0x71, 0x13, 0xfe, 0x24,
  5205. 0x1c, 0x15, 0x19, 0x39, 0xa0, 0xb4, 0xfe, 0xd9, 0x10, 0xc3, 0xfe, 0x03,
  5206. 0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xc3, 0xfe, 0x03, 0xdc,
  5207. 0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x21,
  5208. 0xfe, 0x00, 0xcc, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x78, 0x04, 0x08, 0x05,
  5209. 0x58, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13,
  5210. 0xfe, 0x1e, 0x80, 0xed, 0xfe, 0x1d, 0x80, 0xae, 0xfe, 0x0c, 0x90, 0xfe,
  5211. 0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xac, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4,
  5212. 0x0a, 0xfe, 0x3c, 0x50, 0xaa, 0x01, 0xfe, 0x7a, 0x17, 0x32, 0x07, 0x2f,
  5213. 0xad, 0x01, 0xfe, 0xb4, 0x16, 0x08, 0x05, 0x1b, 0x4e, 0x01, 0xf5, 0x01,
  5214. 0xf6, 0x12, 0xfe, 0xe9, 0x00, 0x08, 0x05, 0x58, 0xfe, 0x2c, 0x13, 0x01,
  5215. 0xfe, 0x0c, 0x17, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90,
  5216. 0x0c, 0xfe, 0x64, 0x01, 0x14, 0xfe, 0x66, 0x01, 0x08, 0x05, 0x5b, 0xfe,
  5217. 0x12, 0x12, 0xfe, 0x03, 0x80, 0x8d, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80,
  5218. 0x40, 0x13, 0x20, 0x6a, 0x2a, 0x12, 0xcf, 0x64, 0x22, 0x20, 0xfb, 0x79,
  5219. 0x20, 0x04, 0xfe, 0x08, 0x1c, 0x03, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58,
  5220. 0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe,
  5221. 0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c,
  5222. 0x25, 0x6e, 0x13, 0xd0, 0x21, 0x0c, 0x5c, 0x0c, 0x45, 0x0f, 0x46, 0x52,
  5223. 0x50, 0x18, 0x1b, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x23, 0xfe, 0xfc,
  5224. 0x0f, 0x44, 0x11, 0x0f, 0x48, 0x52, 0x18, 0x58, 0xfe, 0x90, 0x4d, 0xfe,
  5225. 0x91, 0x54, 0x23, 0xe4, 0x25, 0x11, 0x13, 0x20, 0x7c, 0x6f, 0x4f, 0x22,
  5226. 0x20, 0xfb, 0x79, 0x20, 0x12, 0xcf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0,
  5227. 0xfe, 0x26, 0x10, 0xf8, 0x74, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe,
  5228. 0x18, 0x1c, 0x04, 0x42, 0xfe, 0x0c, 0x14, 0xfc, 0xfe, 0x07, 0xe6, 0x1b,
  5229. 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x04, 0x01, 0xb0, 0x7c, 0x6f, 0x4f,
  5230. 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42, 0x13, 0x32, 0x07, 0x2f,
  5231. 0xfe, 0x34, 0x13, 0x09, 0x48, 0x01, 0x0e, 0xbb, 0xfe, 0x36, 0x12, 0xfe,
  5232. 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe,
  5233. 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe,
  5234. 0x80, 0x5c, 0x01, 0x73, 0xfe, 0x0e, 0x10, 0x07, 0x82, 0x4e, 0xfe, 0x14,
  5235. 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x60, 0x10, 0x04, 0xfe, 0x44, 0x58, 0x8d,
  5236. 0xfe, 0x01, 0xec, 0xa2, 0xfe, 0x9e, 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe,
  5237. 0x9c, 0xe7, 0x1a, 0x79, 0x2a, 0x01, 0xe3, 0xfe, 0xdd, 0x10, 0x2c, 0xc7,
  5238. 0x81, 0xc8, 0x83, 0x33, 0x31, 0xde, 0x07, 0x1a, 0xfe, 0x48, 0x12, 0x07,
  5239. 0x0a, 0xfe, 0x56, 0x12, 0x07, 0x19, 0xfe, 0x30, 0x12, 0x07, 0xc9, 0x17,
  5240. 0xfe, 0x32, 0x12, 0x07, 0xfe, 0x23, 0x00, 0x17, 0xeb, 0x07, 0x06, 0x17,
  5241. 0xfe, 0x9c, 0x12, 0x07, 0x1f, 0xfe, 0x12, 0x12, 0x07, 0x00, 0x17, 0x24,
  5242. 0x15, 0xc9, 0x01, 0x36, 0xa9, 0x2d, 0x01, 0x0b, 0x94, 0x4b, 0x04, 0x2d,
  5243. 0xdd, 0x09, 0xd1, 0x01, 0xfe, 0x26, 0x0f, 0x12, 0x82, 0x02, 0x2b, 0x2d,
  5244. 0x32, 0x07, 0xa6, 0xfe, 0xd9, 0x13, 0x3a, 0x3d, 0x3b, 0x3e, 0x56, 0xfe,
  5245. 0xf0, 0x11, 0x08, 0x05, 0x5a, 0xfe, 0x72, 0x12, 0x9b, 0x2e, 0x9c, 0x3c,
  5246. 0x90, 0xc0, 0x96, 0xfe, 0xba, 0x11, 0x22, 0x62, 0xfe, 0x26, 0x13, 0x03,
  5247. 0x7f, 0x29, 0x80, 0x56, 0xfe, 0x76, 0x0d, 0x0c, 0x60, 0x14, 0x61, 0x21,
  5248. 0x0c, 0x7f, 0x0c, 0x80, 0x01, 0xb3, 0x25, 0x6e, 0x77, 0x13, 0x62, 0x01,
  5249. 0xef, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe,
  5250. 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0xfe, 0x91, 0x10, 0x03, 0x3f,
  5251. 0x29, 0x40, 0xfe, 0x40, 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x3f, 0x14, 0x40,
  5252. 0x88, 0x9b, 0x2e, 0x9c, 0x3c, 0x90, 0xc0, 0x03, 0x5e, 0x29, 0x5f, 0xfe,
  5253. 0x00, 0x56, 0xfe, 0xa1, 0x56, 0x0c, 0x5e, 0x14, 0x5f, 0x08, 0x05, 0x5a,
  5254. 0xfe, 0x1e, 0x12, 0x22, 0x62, 0xfe, 0x1f, 0x40, 0x03, 0x60, 0x29, 0x61,
  5255. 0xfe, 0x2c, 0x50, 0xfe, 0xae, 0x50, 0x03, 0x3f, 0x29, 0x40, 0xfe, 0x44,
  5256. 0x50, 0xfe, 0xc6, 0x50, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x08, 0x50, 0xfe,
  5257. 0x8a, 0x50, 0x03, 0x3d, 0x29, 0x3e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50,
  5258. 0x02, 0x89, 0x25, 0x06, 0x13, 0xd4, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1d,
  5259. 0x4c, 0x33, 0x31, 0xde, 0x07, 0x06, 0x23, 0x4c, 0x32, 0x07, 0xa6, 0x23,
  5260. 0x72, 0x01, 0xaf, 0x1e, 0x43, 0x17, 0x4c, 0x08, 0x05, 0x0a, 0xee, 0x3a,
  5261. 0x3d, 0x3b, 0x3e, 0xfe, 0x0a, 0x55, 0x35, 0xfe, 0x8b, 0x55, 0x57, 0x3d,
  5262. 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x72, 0xfe, 0x19,
  5263. 0x81, 0xba, 0xfe, 0x19, 0x41, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1c, 0x34,
  5264. 0x1d, 0xe8, 0x33, 0x31, 0xe1, 0x55, 0x19, 0xfe, 0xa6, 0x12, 0x55, 0x0a,
  5265. 0x4d, 0x02, 0x4c, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0xe8, 0x33, 0x31, 0xdf,
  5266. 0x07, 0x19, 0x23, 0x4c, 0x01, 0x0b, 0x1d, 0xe8, 0x33, 0x31, 0xfe, 0xe8,
  5267. 0x09, 0xfe, 0xc2, 0x49, 0x51, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0x8a, 0x53,
  5268. 0x05, 0x1f, 0x35, 0xa9, 0xfe, 0xbb, 0x45, 0x55, 0x00, 0x4e, 0x44, 0x06,
  5269. 0x7c, 0x43, 0xfe, 0xda, 0x14, 0x01, 0xaf, 0x8c, 0xfe, 0x4b, 0x45, 0xee,
  5270. 0x32, 0x07, 0xa5, 0xed, 0x03, 0xcd, 0x28, 0x8a, 0x03, 0x45, 0x28, 0x35,
  5271. 0x67, 0x02, 0x72, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17,
  5272. 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01,
  5273. 0xfe, 0x9e, 0x15, 0x02, 0x89, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0x4c, 0x33,
  5274. 0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
  5275. 0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a,
  5276. 0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1,
  5277. 0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15,
  5278. 0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
  5279. 0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0,
  5280. 0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01,
  5281. 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
  5282. 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
  5283. 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56,
  5284. 0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
  5285. 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58,
  5286. 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
  5287. 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52,
  5288. 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c,
  5289. 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd,
  5290. 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
  5291. 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
  5292. 0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
  5293. 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
  5294. 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
  5295. 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
  5296. 0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
  5297. 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
  5298. 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
  5299. 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
  5300. 0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
  5301. 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
  5302. 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
  5303. 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
  5304. 0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
  5305. 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
  5306. 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
  5307. 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
  5308. 0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
  5309. 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
  5310. 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
  5311. 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
  5312. 0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
  5313. 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
  5314. 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
  5315. 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
  5316. 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
  5317. 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
  5318. 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
  5319. 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
  5320. 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
  5321. 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
  5322. 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
  5323. 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
  5324. 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
  5325. 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
  5326. 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
  5327. 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
  5328. 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
  5329. 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
  5330. 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
  5331. 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
  5332. 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
  5333. 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
  5334. 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
  5335. 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
  5336. 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
  5337. 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
  5338. 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
  5339. 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
  5340. 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
  5341. 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
  5342. 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
  5343. 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
  5344. 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
  5345. 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
  5346. 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
  5347. 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
  5348. 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
  5349. 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
  5350. 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
  5351. 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
  5352. 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
  5353. 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
  5354. 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
  5355. 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
  5356. 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
  5357. 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
  5358. 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
  5359. 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
  5360. 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
  5361. 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
  5362. 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
  5363. 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
  5364. 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
  5365. 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
  5366. 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
  5367. 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
  5368. 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
  5369. 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
  5370. 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
  5371. 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
  5372. 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
  5373. 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
  5374. 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
  5375. 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
  5376. 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
  5377. 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
  5378. 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
  5379. 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
  5380. };
  5381. static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
  5382. static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
  5383. /* Microcode buffer is kept after initialization for error recovery. */
  5384. static unsigned char _adv_asc38C1600_buf[] = {
  5385. 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
  5386. 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
  5387. 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
  5388. 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
  5389. 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
  5390. 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
  5391. 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
  5392. 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
  5393. 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
  5394. 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
  5395. 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
  5396. 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
  5397. 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
  5398. 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
  5399. 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
  5400. 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
  5401. 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
  5402. 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
  5403. 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
  5404. 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
  5405. 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
  5406. 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
  5407. 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
  5408. 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
  5409. 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
  5410. 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
  5411. 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
  5412. 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
  5413. 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
  5414. 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
  5415. 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
  5416. 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
  5417. 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
  5418. 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
  5419. 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
  5420. 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
  5421. 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
  5422. 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
  5423. 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
  5424. 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
  5425. 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
  5426. 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
  5427. 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
  5428. 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
  5429. 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
  5430. 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
  5431. 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
  5432. 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
  5433. 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
  5434. 0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
  5435. 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
  5436. 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
  5437. 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
  5438. 0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
  5439. 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
  5440. 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
  5441. 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
  5442. 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
  5443. 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
  5444. 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
  5445. 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
  5446. 0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7,
  5447. 0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f,
  5448. 0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe,
  5449. 0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
  5450. 0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d,
  5451. 0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe,
  5452. 0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01,
  5453. 0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
  5454. 0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec,
  5455. 0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde,
  5456. 0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51,
  5457. 0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
  5458. 0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41,
  5459. 0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03,
  5460. 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30,
  5461. 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
  5462. 0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40,
  5463. 0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0,
  5464. 0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f,
  5465. 0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
  5466. 0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28,
  5467. 0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01,
  5468. 0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15, 0xe1, 0x2a, 0xeb, 0xfe,
  5469. 0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32,
  5470. 0x15, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe,
  5471. 0xc6, 0x03, 0x01, 0x41, 0xfe, 0x06, 0xf0, 0xfe, 0xd6, 0x03, 0xaf, 0xa0,
  5472. 0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29, 0x03, 0x81, 0x1e, 0x1b,
  5473. 0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05,
  5474. 0xea, 0xfe, 0x46, 0x1c, 0x37, 0x7d, 0x1d, 0xfe, 0x67, 0x1b, 0xfe, 0xbf,
  5475. 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c, 0x75, 0x01, 0xa6, 0x86, 0x0a,
  5476. 0x57, 0x01, 0x18, 0x09, 0x00, 0x1b, 0xec, 0x0a, 0xe1, 0x01, 0x18, 0x77,
  5477. 0x50, 0x40, 0x8d, 0x30, 0x03, 0x81, 0x1e, 0xf8, 0x1f, 0x63, 0x01, 0x42,
  5478. 0x8f, 0xfe, 0x70, 0x02, 0x05, 0xea, 0xd7, 0x99, 0xd8, 0x9c, 0x2a, 0x29,
  5479. 0x2f, 0xfe, 0x4e, 0x04, 0x16, 0xfe, 0x4a, 0x04, 0x7e, 0xfe, 0xa0, 0x00,
  5480. 0xfe, 0x9b, 0x57, 0xfe, 0x54, 0x12, 0x32, 0xff, 0x02, 0x00, 0x10, 0x01,
  5481. 0x08, 0x16, 0xfe, 0x02, 0x05, 0x32, 0x01, 0x08, 0x16, 0x29, 0x27, 0x25,
  5482. 0xee, 0xfe, 0x4c, 0x44, 0xfe, 0x58, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x13,
  5483. 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x60, 0x8d, 0x30, 0x01, 0xfe, 0x4e,
  5484. 0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x7c, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xfe,
  5485. 0x32, 0x13, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x68, 0x13, 0xfe, 0x26, 0x10,
  5486. 0x13, 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x01, 0xfe, 0x4e, 0x1e, 0xfe,
  5487. 0x48, 0x47, 0xfe, 0x54, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xa5, 0x01, 0x43,
  5488. 0x09, 0x9b, 0xfe, 0x40, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xf9, 0x1f, 0x7f,
  5489. 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, 0x8f,
  5490. 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x32, 0x15, 0xfe, 0xe6, 0x00, 0x0f, 0xfe,
  5491. 0x1c, 0x90, 0x04, 0xfe, 0x9c, 0x93, 0x3a, 0x0b, 0x0e, 0x8b, 0x02, 0x1f,
  5492. 0x7f, 0x01, 0x42, 0x05, 0x35, 0xfe, 0x42, 0x5b, 0x7d, 0x1d, 0xfe, 0x46,
  5493. 0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0x0f, 0xfe, 0x87, 0x80, 0x04,
  5494. 0xfe, 0x87, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xd0, 0x65, 0x01, 0x0c,
  5495. 0x06, 0x0d, 0xfe, 0x98, 0x13, 0x0f, 0xfe, 0x20, 0x80, 0x04, 0xfe, 0xa0,
  5496. 0x83, 0x33, 0x0b, 0x0e, 0x09, 0x1d, 0xfe, 0x84, 0x12, 0x01, 0x38, 0x06,
  5497. 0x07, 0xfe, 0x70, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x1e, 0x1b, 0xfe, 0xda,
  5498. 0x05, 0xd0, 0x54, 0x01, 0x38, 0x06, 0x0d, 0xfe, 0x58, 0x13, 0x03, 0xfe,
  5499. 0xa0, 0x00, 0x1e, 0xfe, 0x50, 0x12, 0x5e, 0xff, 0x02, 0x00, 0x10, 0x2f,
  5500. 0xfe, 0x90, 0x05, 0x2a, 0x3c, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe,
  5501. 0x9e, 0x05, 0x17, 0xfe, 0xf4, 0x05, 0x15, 0xfe, 0xe3, 0x00, 0x26, 0x01,
  5502. 0x38, 0xfe, 0x4a, 0xf0, 0xfe, 0xc0, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0xba,
  5503. 0x05, 0x71, 0x2e, 0xfe, 0x21, 0x00, 0xf1, 0x2e, 0xfe, 0x22, 0x00, 0xa2,
  5504. 0x2e, 0x4a, 0xfe, 0x09, 0x48, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe, 0xd0,
  5505. 0x05, 0x17, 0xfe, 0xf4, 0x05, 0xfe, 0xe2, 0x08, 0x01, 0x38, 0x06, 0xfe,
  5506. 0x1c, 0x00, 0x4d, 0x01, 0xa7, 0x2e, 0x07, 0x20, 0xe4, 0x47, 0xfe, 0x27,
  5507. 0x01, 0x01, 0x0c, 0x06, 0x28, 0xfe, 0x24, 0x12, 0x3e, 0x01, 0x84, 0x1f,
  5508. 0x7f, 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42,
  5509. 0x8f, 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x03, 0xe6, 0x1e, 0xfe, 0xca, 0x13,
  5510. 0x03, 0xb6, 0x1e, 0xfe, 0x40, 0x12, 0x03, 0x66, 0x1e, 0xfe, 0x38, 0x13,
  5511. 0x3e, 0x01, 0x84, 0x17, 0xfe, 0x72, 0x06, 0x0a, 0x07, 0x01, 0x38, 0x06,
  5512. 0x24, 0xfe, 0x02, 0x12, 0x4f, 0x01, 0xfe, 0x56, 0x19, 0x16, 0xfe, 0x68,
  5513. 0x06, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x03, 0x66, 0x8a, 0x10, 0x66,
  5514. 0x03, 0x9a, 0x1e, 0xfe, 0x70, 0x12, 0x03, 0x55, 0x1e, 0xfe, 0x68, 0x13,
  5515. 0x01, 0xc6, 0x09, 0x12, 0x48, 0xfe, 0x92, 0x06, 0x2e, 0x12, 0x01, 0xfe,
  5516. 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0x13, 0x58, 0xff, 0x02, 0x00,
  5517. 0x57, 0x52, 0xad, 0x23, 0x3f, 0x4e, 0x62, 0x49, 0x3e, 0x01, 0x84, 0x17,
  5518. 0xfe, 0xea, 0x06, 0x01, 0x38, 0x06, 0x12, 0xf7, 0x45, 0x0a, 0x95, 0x01,
  5519. 0xfe, 0x84, 0x19, 0x16, 0xfe, 0xe0, 0x06, 0x15, 0x82, 0x01, 0x41, 0x15,
  5520. 0xe2, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x1c, 0x07, 0x01, 0x84, 0xfe, 0xae,
  5521. 0x10, 0x03, 0x6f, 0x1e, 0xfe, 0x9e, 0x13, 0x3e, 0x01, 0x84, 0x03, 0x9a,
  5522. 0x1e, 0xfe, 0x1a, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfc, 0x01, 0xc6, 0x01,
  5523. 0xfe, 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0xf0, 0x45, 0x0a, 0x95,
  5524. 0x03, 0xb6, 0x1e, 0xf8, 0x01, 0x38, 0x06, 0x24, 0x36, 0xfe, 0x02, 0xf6,
  5525. 0x07, 0x71, 0x78, 0x8c, 0x00, 0x4d, 0x62, 0x49, 0x3e, 0x2d, 0x93, 0x4e,
  5526. 0xd0, 0x0d, 0x17, 0xfe, 0x9a, 0x07, 0x01, 0xfe, 0xc0, 0x19, 0x16, 0xfe,
  5527. 0x90, 0x07, 0x26, 0x20, 0x9e, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x21,
  5528. 0x9e, 0x09, 0x07, 0xfb, 0x03, 0xe6, 0xfe, 0x58, 0x57, 0x10, 0xe6, 0x05,
  5529. 0xfe, 0x2a, 0x06, 0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x1c, 0x07, 0x01, 0x84,
  5530. 0xfe, 0x9c, 0x32, 0x5f, 0x75, 0x01, 0xa6, 0x86, 0x15, 0xfe, 0xe2, 0x00,
  5531. 0x2f, 0xed, 0x2a, 0x3c, 0xfe, 0x0a, 0xf0, 0xfe, 0xce, 0x07, 0xae, 0xfe,
  5532. 0x96, 0x08, 0xfe, 0x06, 0xf0, 0xfe, 0x9e, 0x08, 0xaf, 0xa0, 0x05, 0x29,
  5533. 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x2e, 0x12, 0x14, 0x1d, 0x01, 0x08, 0x14,
  5534. 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0xfe,
  5535. 0x99, 0xa4, 0x01, 0x08, 0x14, 0x00, 0x05, 0xfe, 0xc6, 0x09, 0x01, 0x76,
  5536. 0x06, 0x12, 0xfe, 0x3a, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x30, 0x13,
  5537. 0x14, 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00,
  5538. 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x07, 0x01, 0x08, 0x14, 0x00,
  5539. 0x05, 0xef, 0x7c, 0x4a, 0x78, 0x4f, 0x0f, 0xfe, 0x9a, 0x81, 0x04, 0xfe,
  5540. 0x9a, 0x83, 0xfe, 0xcb, 0x47, 0x0b, 0x0e, 0x2d, 0x28, 0x48, 0xfe, 0x6c,
  5541. 0x08, 0x0a, 0x28, 0xfe, 0x09, 0x6f, 0xca, 0xfe, 0xca, 0x45, 0xfe, 0x32,
  5542. 0x12, 0x53, 0x63, 0x4e, 0x7c, 0x97, 0x2f, 0xfe, 0x7e, 0x08, 0x2a, 0x3c,
  5543. 0xfe, 0x0a, 0xf0, 0xfe, 0x6c, 0x08, 0xaf, 0xa0, 0xae, 0xfe, 0x96, 0x08,
  5544. 0x05, 0x29, 0x01, 0x41, 0x05, 0xed, 0x14, 0x24, 0x05, 0xed, 0xfe, 0x9c,
  5545. 0xf7, 0x9f, 0x01, 0xfe, 0xae, 0x1e, 0xfe, 0x18, 0x58, 0x01, 0xfe, 0xbe,
  5546. 0x1e, 0xfe, 0x99, 0x58, 0xfe, 0x78, 0x18, 0xfe, 0xf9, 0x18, 0x8e, 0xfe,
  5547. 0x16, 0x09, 0x10, 0x6a, 0x22, 0x6b, 0x01, 0x0c, 0x61, 0x54, 0x44, 0x21,
  5548. 0x2c, 0x09, 0x1a, 0xf8, 0x77, 0x01, 0xfe, 0x7e, 0x1e, 0x47, 0x2c, 0x7a,
  5549. 0x30, 0xf0, 0xfe, 0x83, 0xe7, 0xfe, 0x3f, 0x00, 0x71, 0xfe, 0x03, 0x40,
  5550. 0x01, 0x0c, 0x61, 0x65, 0x44, 0x01, 0xc2, 0xc8, 0xfe, 0x1f, 0x40, 0x20,
  5551. 0x6e, 0x01, 0xfe, 0x6a, 0x16, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe,
  5552. 0x44, 0x51, 0xfe, 0xc6, 0x51, 0xfe, 0x10, 0x10, 0x01, 0xfe, 0xce, 0x1e,
  5553. 0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x01, 0xfe, 0xee, 0x1e,
  5554. 0x01, 0xfe, 0xfe, 0x1e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x10, 0x4b,
  5555. 0x22, 0x4c, 0xfe, 0x8a, 0x10, 0x01, 0x0c, 0x06, 0x54, 0xfe, 0x50, 0x12,
  5556. 0x01, 0xfe, 0xae, 0x1e, 0x01, 0xfe, 0xbe, 0x1e, 0x10, 0x6a, 0x22, 0x6b,
  5557. 0x01, 0x0c, 0x06, 0x65, 0x4e, 0x01, 0xc2, 0x0f, 0xfe, 0x1f, 0x80, 0x04,
  5558. 0xfe, 0x9f, 0x83, 0x33, 0x0b, 0x0e, 0x20, 0x6e, 0x0f, 0xfe, 0x44, 0x90,
  5559. 0x04, 0xfe, 0xc4, 0x93, 0x3a, 0x0b, 0xfe, 0xc6, 0x90, 0x04, 0xfe, 0xc6,
  5560. 0x93, 0x79, 0x0b, 0x0e, 0x10, 0x6c, 0x22, 0x6d, 0x01, 0xfe, 0xce, 0x1e,
  5561. 0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x0f, 0xfe, 0x40, 0x90,
  5562. 0x04, 0xfe, 0xc0, 0x93, 0x3a, 0x0b, 0xfe, 0xc2, 0x90, 0x04, 0xfe, 0xc2,
  5563. 0x93, 0x79, 0x0b, 0x0e, 0x10, 0x4b, 0x22, 0x4c, 0x10, 0x64, 0x22, 0x34,
  5564. 0x01, 0x0c, 0x61, 0x24, 0x44, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe,
  5565. 0xde, 0x09, 0xfe, 0x9e, 0xf0, 0xfe, 0xf2, 0x09, 0xfe, 0x01, 0x48, 0x1b,
  5566. 0x3c, 0x37, 0x88, 0xf5, 0xd4, 0xfe, 0x1e, 0x0a, 0xd5, 0xfe, 0x42, 0x0a,
  5567. 0xd2, 0xfe, 0x1e, 0x0a, 0xd3, 0xfe, 0x42, 0x0a, 0xae, 0xfe, 0x12, 0x0a,
  5568. 0xfe, 0x06, 0xf0, 0xfe, 0x18, 0x0a, 0xaf, 0xa0, 0x05, 0x29, 0x01, 0x41,
  5569. 0xfe, 0xc1, 0x10, 0x14, 0x24, 0xfe, 0xc1, 0x10, 0x01, 0x76, 0x06, 0x07,
  5570. 0xfe, 0x14, 0x12, 0x01, 0x76, 0x06, 0x0d, 0x5d, 0x01, 0x0c, 0x06, 0x0d,
  5571. 0xfe, 0x74, 0x12, 0xfe, 0x2e, 0x1c, 0x05, 0xfe, 0x1a, 0x0c, 0x01, 0x76,
  5572. 0x06, 0x07, 0x5d, 0x01, 0x76, 0x06, 0x0d, 0x41, 0xfe, 0x2c, 0x1c, 0xfe,
  5573. 0xaa, 0xf0, 0xfe, 0xce, 0x0a, 0xfe, 0xac, 0xf0, 0xfe, 0x66, 0x0a, 0xfe,
  5574. 0x92, 0x10, 0xc4, 0xf6, 0xfe, 0xad, 0xf0, 0xfe, 0x72, 0x0a, 0x05, 0xfe,
  5575. 0x1a, 0x0c, 0xc5, 0xfe, 0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0xbf, 0xfe, 0x6b,
  5576. 0x18, 0x23, 0xfe, 0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xac, 0xfe, 0xd2, 0xf0,
  5577. 0xbf, 0xfe, 0x76, 0x18, 0x23, 0x1d, 0x1b, 0xbf, 0x03, 0xe3, 0x23, 0x07,
  5578. 0x1b, 0xbf, 0xd4, 0x5b, 0xd5, 0x5b, 0xd2, 0x5b, 0xd3, 0x5b, 0xc4, 0xc5,
  5579. 0xfe, 0xa9, 0x10, 0x75, 0x5e, 0x32, 0x1f, 0x7f, 0x01, 0x42, 0x19, 0xfe,
  5580. 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x70, 0x19, 0x98, 0x05, 0x70, 0xfe, 0x74,
  5581. 0x18, 0x23, 0xfe, 0x00, 0xf8, 0x1b, 0x5b, 0x7d, 0x12, 0x01, 0xfe, 0x78,
  5582. 0x0f, 0x4d, 0x01, 0xfe, 0x96, 0x1a, 0x21, 0x30, 0x77, 0x7d, 0x1d, 0x05,
  5583. 0x5b, 0x01, 0x0c, 0x06, 0x0d, 0x2b, 0xfe, 0xe2, 0x0b, 0x01, 0x0c, 0x06,
  5584. 0x54, 0xfe, 0xa6, 0x12, 0x01, 0x0c, 0x06, 0x24, 0xfe, 0x88, 0x13, 0x21,
  5585. 0x6e, 0xc7, 0x01, 0xfe, 0x1e, 0x1f, 0x0f, 0xfe, 0x83, 0x80, 0x04, 0xfe,
  5586. 0x83, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xfe, 0xc8, 0x44, 0xfe, 0x42,
  5587. 0x13, 0x0f, 0xfe, 0x04, 0x91, 0x04, 0xfe, 0x84, 0x93, 0xfe, 0xca, 0x57,
  5588. 0x0b, 0xfe, 0x86, 0x91, 0x04, 0xfe, 0x86, 0x93, 0xfe, 0xcb, 0x57, 0x0b,
  5589. 0x0e, 0x7a, 0x30, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x8e, 0x40, 0x03,
  5590. 0x6a, 0x3b, 0x6b, 0x10, 0x97, 0x22, 0x98, 0xd9, 0x6a, 0xda, 0x6b, 0x01,
  5591. 0xc2, 0xc8, 0x7a, 0x30, 0x20, 0x6e, 0xdb, 0x64, 0xdc, 0x34, 0x91, 0x6c,
  5592. 0x7e, 0x6d, 0xfe, 0x44, 0x55, 0xfe, 0xe5, 0x55, 0xfe, 0x04, 0xfa, 0x64,
  5593. 0xfe, 0x05, 0xfa, 0x34, 0x01, 0xfe, 0x6a, 0x16, 0xa3, 0x26, 0x10, 0x97,
  5594. 0x10, 0x98, 0x91, 0x6c, 0x7e, 0x6d, 0xfe, 0x14, 0x10, 0x01, 0x0c, 0x06,
  5595. 0x24, 0x1b, 0x40, 0x91, 0x4b, 0x7e, 0x4c, 0x01, 0x0c, 0x06, 0xfe, 0xf7,
  5596. 0x00, 0x44, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58,
  5597. 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x05, 0x5b, 0x01, 0x0c, 0x06, 0x24,
  5598. 0x1b, 0x40, 0x01, 0x0c, 0x06, 0xfe, 0xf7, 0x00, 0x44, 0x78, 0x01, 0xfe,
  5599. 0x8e, 0x1e, 0x4f, 0x0f, 0xfe, 0x10, 0x90, 0x04, 0xfe, 0x90, 0x93, 0x3a,
  5600. 0x0b, 0xfe, 0x92, 0x90, 0x04, 0xfe, 0x92, 0x93, 0x79, 0x0b, 0x0e, 0xfe,
  5601. 0xbd, 0x10, 0x01, 0x43, 0x09, 0xbb, 0x1b, 0xfe, 0x6e, 0x0a, 0x15, 0xbb,
  5602. 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x14, 0x13, 0x03, 0x4b, 0x3b, 0x4c, 0x8e,
  5603. 0xfe, 0x6e, 0x0a, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x05, 0x5b, 0x26,
  5604. 0x3e, 0x0f, 0xfe, 0x19, 0x80, 0x04, 0xfe, 0x99, 0x83, 0x33, 0x0b, 0x0e,
  5605. 0xfe, 0xe5, 0x10, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x1a, 0x12, 0xfe, 0x6c,
  5606. 0x19, 0xfe, 0x19, 0x41, 0xfe, 0x6b, 0x18, 0xac, 0xfe, 0xd1, 0xf0, 0xef,
  5607. 0x1f, 0x92, 0x01, 0x42, 0x19, 0xfe, 0x44, 0x00, 0xfe, 0x90, 0x10, 0xfe,
  5608. 0x6c, 0x19, 0xd9, 0x4b, 0xfe, 0xed, 0x19, 0xda, 0x4c, 0xfe, 0x0c, 0x51,
  5609. 0xfe, 0x8e, 0x51, 0xfe, 0x6b, 0x18, 0x23, 0xfe, 0x00, 0xff, 0x31, 0xfe,
  5610. 0x76, 0x10, 0xac, 0xfe, 0xd2, 0xf0, 0xfe, 0xba, 0x0c, 0xfe, 0x76, 0x18,
  5611. 0x23, 0x1d, 0x5d, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0x08, 0x13, 0x19, 0xfe,
  5612. 0x16, 0x00, 0x05, 0x70, 0xfe, 0xd1, 0xf0, 0xfe, 0xcc, 0x0c, 0x1f, 0x92,
  5613. 0x01, 0x42, 0x19, 0xfe, 0x17, 0x00, 0x5c, 0xfe, 0xce, 0xf0, 0xfe, 0xd2,
  5614. 0x0c, 0xfe, 0x3e, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xde, 0x0c, 0x19, 0xfe,
  5615. 0x22, 0x00, 0x05, 0x70, 0xfe, 0xcb, 0xf0, 0xfe, 0xea, 0x0c, 0x19, 0xfe,
  5616. 0x24, 0x00, 0x05, 0x70, 0xfe, 0xd0, 0xf0, 0xfe, 0xf4, 0x0c, 0x19, 0x94,
  5617. 0xfe, 0x1c, 0x10, 0xfe, 0xcf, 0xf0, 0xfe, 0xfe, 0x0c, 0x19, 0x4a, 0xf3,
  5618. 0xfe, 0xcc, 0xf0, 0xef, 0x01, 0x76, 0x06, 0x24, 0x4d, 0x19, 0xfe, 0x12,
  5619. 0x00, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe, 0x16, 0x0d, 0xfe, 0x9e,
  5620. 0xf0, 0xfe, 0x2a, 0x0d, 0xfe, 0x01, 0x48, 0x1b, 0x3c, 0x37, 0x88, 0xf5,
  5621. 0xd4, 0x29, 0xd5, 0x29, 0xd2, 0x29, 0xd3, 0x29, 0x37, 0xfe, 0x9c, 0x32,
  5622. 0x2f, 0xfe, 0x3e, 0x0d, 0x2a, 0x3c, 0xae, 0xfe, 0x62, 0x0d, 0xaf, 0xa0,
  5623. 0xd4, 0x9f, 0xd5, 0x9f, 0xd2, 0x9f, 0xd3, 0x9f, 0x05, 0x29, 0x01, 0x41,
  5624. 0xfe, 0xd3, 0x10, 0x15, 0xfe, 0xe8, 0x00, 0xc4, 0xc5, 0x75, 0xd7, 0x99,
  5625. 0xd8, 0x9c, 0xfe, 0x89, 0xf0, 0x29, 0x27, 0x25, 0xbe, 0xd7, 0x99, 0xd8,
  5626. 0x9c, 0x2f, 0xfe, 0x8c, 0x0d, 0x16, 0x29, 0x27, 0x25, 0xbd, 0xfe, 0x01,
  5627. 0x48, 0xa4, 0x19, 0xfe, 0x42, 0x00, 0x05, 0x70, 0x90, 0x07, 0xfe, 0x81,
  5628. 0x49, 0x1b, 0xfe, 0x64, 0x0e, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x44, 0x13,
  5629. 0x19, 0x00, 0x2d, 0x0d, 0xfe, 0x54, 0x12, 0x2d, 0xfe, 0x28, 0x00, 0x2b,
  5630. 0xfe, 0xda, 0x0e, 0x0a, 0x57, 0x01, 0x18, 0x09, 0x00, 0x36, 0x46, 0xfe,
  5631. 0x28, 0x00, 0xfe, 0xfa, 0x10, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00,
  5632. 0x1d, 0x0a, 0xba, 0x01, 0xfe, 0x58, 0x10, 0x40, 0x15, 0x56, 0x01, 0x85,
  5633. 0x05, 0x35, 0x19, 0xfe, 0x44, 0x00, 0x2d, 0x0d, 0xf7, 0x46, 0x0d, 0xfe,
  5634. 0xcc, 0x10, 0x01, 0xa7, 0x46, 0x0d, 0xfe, 0xc2, 0x10, 0x01, 0xa7, 0x0f,
  5635. 0xfe, 0x19, 0x82, 0x04, 0xfe, 0x99, 0x83, 0xfe, 0xcc, 0x47, 0x0b, 0x0e,
  5636. 0xfe, 0x34, 0x46, 0xa5, 0x46, 0x0d, 0x19, 0xfe, 0x43, 0x00, 0xfe, 0xa2,
  5637. 0x10, 0x01, 0x0c, 0x61, 0x0d, 0x44, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe,
  5638. 0x00, 0x1d, 0x40, 0x15, 0x56, 0x01, 0x85, 0x7d, 0x0d, 0x40, 0x51, 0x01,
  5639. 0xfe, 0x9e, 0x1e, 0x05, 0xfe, 0x3a, 0x03, 0x01, 0x0c, 0x06, 0x0d, 0x5d,
  5640. 0x46, 0x0d, 0x19, 0x00, 0xfe, 0x62, 0x10, 0x01, 0x76, 0x06, 0x12, 0xfe,
  5641. 0x5c, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x52, 0x13, 0xfe, 0x1c, 0x1c,
  5642. 0xfe, 0x9d, 0xf0, 0xfe, 0x8e, 0x0e, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0,
  5643. 0xfe, 0x94, 0x0e, 0x01, 0x0c, 0x61, 0x12, 0x44, 0xfe, 0x9f, 0x10, 0x19,
  5644. 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0d, 0x4f, 0xfe, 0x2e, 0x10, 0x19,
  5645. 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x19, 0xfe, 0x47, 0x00, 0xf1, 0x19,
  5646. 0xfe, 0x41, 0x00, 0xa2, 0x19, 0xfe, 0x24, 0x00, 0x86, 0xc4, 0xc5, 0x75,
  5647. 0x03, 0x81, 0x1e, 0x2b, 0xea, 0x4f, 0xfe, 0x04, 0xe6, 0x12, 0xfe, 0x9d,
  5648. 0x41, 0xfe, 0x1c, 0x42, 0x40, 0x01, 0xf4, 0x05, 0x35, 0xfe, 0x12, 0x1c,
  5649. 0x1f, 0x0d, 0x47, 0xb5, 0xc3, 0x1f, 0xfe, 0x31, 0x00, 0x47, 0xb8, 0x01,
  5650. 0xfe, 0xd4, 0x11, 0x05, 0xe9, 0x51, 0xfe, 0x06, 0xec, 0xe0, 0xfe, 0x0e,
  5651. 0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0x06, 0xea, 0xe0,
  5652. 0xfe, 0x47, 0x4b, 0x45, 0xfe, 0x75, 0x57, 0x03, 0x67, 0xfe, 0x98, 0x56,
  5653. 0xfe, 0x38, 0x12, 0x0a, 0x5a, 0x01, 0x18, 0xfe, 0x44, 0x48, 0x60, 0x01,
  5654. 0x0c, 0x06, 0x28, 0xfe, 0x18, 0x13, 0x0a, 0x57, 0x01, 0x18, 0x3e, 0xfe,
  5655. 0x41, 0x58, 0x0a, 0xba, 0xfe, 0xfa, 0x14, 0xfe, 0x49, 0x54, 0xb0, 0xfe,
  5656. 0x5e, 0x0f, 0x05, 0xfe, 0x3a, 0x03, 0x0a, 0x67, 0xfe, 0xe0, 0x14, 0xfe,
  5657. 0x0e, 0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0xce, 0x47,
  5658. 0xfe, 0xad, 0x13, 0x05, 0x35, 0x21, 0x2c, 0x09, 0x1a, 0xfe, 0x98, 0x12,
  5659. 0x26, 0x20, 0x96, 0x20, 0xe7, 0xfe, 0x08, 0x1c, 0xfe, 0x7c, 0x19, 0xfe,
  5660. 0xfd, 0x19, 0xfe, 0x0a, 0x1c, 0x03, 0xe5, 0xfe, 0x48, 0x55, 0xa5, 0x3b,
  5661. 0xfe, 0x62, 0x01, 0xfe, 0xc9, 0x55, 0x31, 0xfe, 0x74, 0x10, 0x01, 0xfe,
  5662. 0xf0, 0x1a, 0x03, 0xfe, 0x38, 0x01, 0x3b, 0xfe, 0x3a, 0x01, 0x8e, 0xfe,
  5663. 0x1e, 0x10, 0xfe, 0x02, 0xec, 0xe7, 0x53, 0x00, 0x36, 0xfe, 0x04, 0xec,
  5664. 0x2c, 0x60, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x62, 0x1b,
  5665. 0x01, 0xfe, 0xce, 0x1e, 0xb2, 0x11, 0xfe, 0x18, 0x13, 0xca, 0xfe, 0x02,
  5666. 0xea, 0xe7, 0x53, 0x92, 0xfe, 0xc3, 0x13, 0x1f, 0x12, 0x47, 0xb5, 0xc3,
  5667. 0xfe, 0x2a, 0x10, 0x03, 0xfe, 0x38, 0x01, 0x23, 0xfe, 0xf0, 0xff, 0x10,
  5668. 0xe5, 0x03, 0xfe, 0x3a, 0x01, 0x10, 0xfe, 0x62, 0x01, 0x01, 0xfe, 0x1e,
  5669. 0x1e, 0x20, 0x2c, 0x15, 0x56, 0x01, 0xfe, 0x9e, 0x1e, 0x13, 0x07, 0x02,
  5670. 0x26, 0x02, 0x21, 0x96, 0xc7, 0x20, 0x96, 0x09, 0x92, 0xfe, 0x79, 0x13,
  5671. 0x1f, 0x1d, 0x47, 0xb5, 0xc3, 0xfe, 0xe1, 0x10, 0xcf, 0xfe, 0x03, 0xdc,
  5672. 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xcf, 0xfe, 0x03, 0xdc, 0xfe,
  5673. 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x26, 0xfe,
  5674. 0x00, 0xcc, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x89, 0x02, 0x01, 0x0c, 0x06,
  5675. 0x4a, 0xfe, 0x4e, 0x13, 0x0f, 0xfe, 0x1c, 0x80, 0x04, 0xfe, 0x9c, 0x83,
  5676. 0x33, 0x0b, 0x0e, 0x09, 0x07, 0xfe, 0x3a, 0x13, 0x0f, 0xfe, 0x1e, 0x80,
  5677. 0x04, 0xfe, 0x9e, 0x83, 0x33, 0x0b, 0x0e, 0xfe, 0x2a, 0x13, 0x0f, 0xfe,
  5678. 0x1d, 0x80, 0x04, 0xfe, 0x9d, 0x83, 0xfe, 0xf9, 0x13, 0x0e, 0xfe, 0x1c,
  5679. 0x13, 0x01, 0xfe, 0xee, 0x1e, 0xac, 0xfe, 0x14, 0x13, 0x01, 0xfe, 0xfe,
  5680. 0x1e, 0xfe, 0x81, 0x58, 0xfa, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4,
  5681. 0x0d, 0xfe, 0x3c, 0x50, 0xa2, 0x01, 0xfe, 0x92, 0x1b, 0x01, 0x43, 0x09,
  5682. 0x56, 0xfb, 0x01, 0xfe, 0xc8, 0x1a, 0x01, 0x0c, 0x06, 0x28, 0xa4, 0x01,
  5683. 0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00, 0x1d, 0x15, 0xfe, 0xe9, 0x00, 0x01,
  5684. 0x0c, 0x06, 0x4a, 0xfe, 0x4e, 0x13, 0x01, 0xfe, 0x22, 0x1b, 0xfe, 0x1e,
  5685. 0x1c, 0x0f, 0xfe, 0x14, 0x90, 0x04, 0xfe, 0x94, 0x93, 0x3a, 0x0b, 0xfe,
  5686. 0x96, 0x90, 0x04, 0xfe, 0x96, 0x93, 0x79, 0x0b, 0x0e, 0x10, 0xfe, 0x64,
  5687. 0x01, 0x22, 0xfe, 0x66, 0x01, 0x01, 0x0c, 0x06, 0x65, 0xf9, 0x0f, 0xfe,
  5688. 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x0e, 0x77, 0xfe, 0x01,
  5689. 0xec, 0x2c, 0xfe, 0x80, 0x40, 0x20, 0x2c, 0x7a, 0x30, 0x15, 0xdf, 0x40,
  5690. 0x21, 0x2c, 0xfe, 0x00, 0x40, 0x8d, 0x2c, 0x02, 0xfe, 0x08, 0x1c, 0x03,
  5691. 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58, 0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07,
  5692. 0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe, 0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00,
  5693. 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c, 0x2e, 0x49, 0x20, 0xe0, 0x26, 0x10,
  5694. 0x66, 0x10, 0x55, 0x10, 0x6f, 0x13, 0x57, 0x52, 0x4f, 0x1c, 0x28, 0xfe,
  5695. 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe, 0x88, 0x11, 0x46, 0x1a, 0x13,
  5696. 0x5a, 0x52, 0x1c, 0x4a, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe,
  5697. 0x9e, 0x11, 0x2e, 0x1a, 0x20, 0x2c, 0x90, 0x34, 0x60, 0x21, 0x2c, 0xfe,
  5698. 0x00, 0x40, 0x8d, 0x2c, 0x15, 0xdf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0,
  5699. 0xfe, 0xb2, 0x11, 0xfe, 0x12, 0x1c, 0x75, 0xfe, 0x14, 0x1c, 0xfe, 0x10,
  5700. 0x1c, 0xfe, 0x18, 0x1c, 0x02, 0x51, 0xfe, 0x0c, 0x14, 0xfe, 0x0e, 0x47,
  5701. 0xfe, 0x07, 0xe6, 0x28, 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x02, 0x01,
  5702. 0xa7, 0x90, 0x34, 0x60, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42,
  5703. 0x13, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x34, 0x13, 0x0a, 0x5a, 0x01,
  5704. 0x18, 0xcb, 0xfe, 0x36, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
  5705. 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f, 0x89,
  5706. 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x5c, 0x01, 0x85,
  5707. 0xf2, 0x09, 0x9b, 0xa4, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0xec,
  5708. 0x11, 0x02, 0xfe, 0x44, 0x58, 0x77, 0xfe, 0x01, 0xec, 0xb8, 0xfe, 0x9e,
  5709. 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x12, 0x8d, 0x30, 0x01,
  5710. 0xf4, 0xfe, 0xdd, 0x10, 0x37, 0xd7, 0x99, 0xd8, 0x9c, 0x27, 0x25, 0xee,
  5711. 0x09, 0x12, 0xfe, 0x48, 0x12, 0x09, 0x0d, 0xfe, 0x56, 0x12, 0x09, 0x1d,
  5712. 0xfe, 0x30, 0x12, 0x09, 0xdd, 0x1b, 0xfe, 0xc4, 0x13, 0x09, 0xfe, 0x23,
  5713. 0x00, 0x1b, 0xfe, 0xd0, 0x13, 0x09, 0x07, 0x1b, 0xfe, 0x34, 0x14, 0x09,
  5714. 0x24, 0xfe, 0x12, 0x12, 0x09, 0x00, 0x1b, 0x29, 0x1f, 0xdd, 0x01, 0x42,
  5715. 0xa1, 0x32, 0x01, 0x08, 0xae, 0x41, 0x02, 0x32, 0xfe, 0x62, 0x08, 0x0a,
  5716. 0xe1, 0x01, 0xfe, 0x58, 0x10, 0x15, 0x9b, 0x05, 0x35, 0x32, 0x01, 0x43,
  5717. 0x09, 0xbb, 0xfe, 0xd7, 0x13, 0x91, 0x4b, 0x7e, 0x4c, 0x8e, 0xfe, 0x80,
  5718. 0x13, 0x01, 0x0c, 0x06, 0x54, 0xfe, 0x72, 0x12, 0xdb, 0x64, 0xdc, 0x34,
  5719. 0xfe, 0x44, 0x55, 0xfe, 0xe5, 0x55, 0xb0, 0xfe, 0x4a, 0x13, 0x21, 0x6e,
  5720. 0xfe, 0x26, 0x13, 0x03, 0x97, 0x3b, 0x98, 0x8e, 0xfe, 0xb6, 0x0e, 0x10,
  5721. 0x6a, 0x22, 0x6b, 0x26, 0x10, 0x97, 0x10, 0x98, 0x01, 0xc2, 0x2e, 0x49,
  5722. 0x88, 0x20, 0x6e, 0x01, 0xfe, 0x6a, 0x16, 0xdb, 0x64, 0xdc, 0x34, 0xfe,
  5723. 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x64, 0xfe, 0x05, 0xfa,
  5724. 0x34, 0xfe, 0x8f, 0x10, 0x03, 0x6c, 0x3b, 0x6d, 0xfe, 0x40, 0x56, 0xfe,
  5725. 0xe1, 0x56, 0x10, 0x6c, 0x22, 0x6d, 0x71, 0xdb, 0x64, 0xdc, 0x34, 0xfe,
  5726. 0x44, 0x55, 0xfe, 0xe5, 0x55, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x00, 0x56,
  5727. 0xfe, 0xa1, 0x56, 0x10, 0x68, 0x22, 0x69, 0x01, 0x0c, 0x06, 0x54, 0xf9,
  5728. 0x21, 0x6e, 0xfe, 0x1f, 0x40, 0x03, 0x6a, 0x3b, 0x6b, 0xfe, 0x2c, 0x50,
  5729. 0xfe, 0xae, 0x50, 0x03, 0x6c, 0x3b, 0x6d, 0xfe, 0x44, 0x50, 0xfe, 0xc6,
  5730. 0x50, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x03,
  5731. 0x4b, 0x3b, 0x4c, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x05, 0x73, 0x2e,
  5732. 0x07, 0x20, 0x9e, 0x05, 0x72, 0x32, 0x01, 0x08, 0x16, 0x3d, 0x27, 0x25,
  5733. 0xee, 0x09, 0x07, 0x2b, 0x3d, 0x01, 0x43, 0x09, 0xbb, 0x2b, 0x72, 0x01,
  5734. 0xa6, 0x23, 0x3f, 0x1b, 0x3d, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x1e, 0x13,
  5735. 0x91, 0x4b, 0x7e, 0x4c, 0xfe, 0x0a, 0x55, 0x31, 0xfe, 0x8b, 0x55, 0xd9,
  5736. 0x4b, 0xda, 0x4c, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x05, 0x72, 0x01,
  5737. 0xfe, 0x8e, 0x1e, 0xca, 0xfe, 0x19, 0x41, 0x05, 0x72, 0x32, 0x01, 0x08,
  5738. 0x2a, 0x3c, 0x16, 0xc0, 0x27, 0x25, 0xbe, 0x2d, 0x1d, 0xc0, 0x2d, 0x0d,
  5739. 0x83, 0x2d, 0x7f, 0x1b, 0xfe, 0x66, 0x15, 0x05, 0x3d, 0x01, 0x08, 0x2a,
  5740. 0x3c, 0x16, 0xc0, 0x27, 0x25, 0xbd, 0x09, 0x1d, 0x2b, 0x3d, 0x01, 0x08,
  5741. 0x16, 0xc0, 0x27, 0x25, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49, 0x50, 0x03,
  5742. 0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa1, 0xfe, 0xbb, 0x45,
  5743. 0x2d, 0x00, 0xa4, 0x46, 0x07, 0x90, 0x3f, 0x01, 0xfe, 0xf8, 0x15, 0x01,
  5744. 0xa6, 0x86, 0xfe, 0x4b, 0x45, 0xfe, 0x20, 0x13, 0x01, 0x43, 0x09, 0x82,
  5745. 0xfe, 0x16, 0x13, 0x03, 0x9a, 0x1e, 0x5d, 0x03, 0x55, 0x1e, 0x31, 0x5e,
  5746. 0x05, 0x72, 0xfe, 0xc0, 0x5d, 0x01, 0xa7, 0xfe, 0x03, 0x17, 0x03, 0x66,
  5747. 0x8a, 0x10, 0x66, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73, 0x01, 0xfe, 0x56,
  5748. 0x19, 0x05, 0x73, 0x01, 0x08, 0x2a, 0x3c, 0x16, 0x3d, 0x27, 0x25, 0xbd,
  5749. 0x09, 0x07, 0x2b, 0x3d, 0x01, 0xfe, 0xbe, 0x16, 0xfe, 0x42, 0x58, 0xfe,
  5750. 0xe8, 0x14, 0x01, 0xa6, 0x86, 0xfe, 0x4a, 0xf4, 0x0d, 0x1b, 0x3d, 0xfe,
  5751. 0x4a, 0xf4, 0x07, 0xfe, 0x0e, 0x12, 0x01, 0x43, 0x09, 0x82, 0x4e, 0x05,
  5752. 0x72, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73,
  5753. 0x01, 0xfe, 0x84, 0x19, 0x05, 0x73, 0x01, 0x08, 0x2a, 0x3c, 0x16, 0x3d,
  5754. 0x27, 0x25, 0xbd, 0x09, 0x12, 0x2b, 0x3d, 0x01, 0xfe, 0xe8, 0x17, 0x8b,
  5755. 0xfe, 0xaa, 0x14, 0xfe, 0xb6, 0x14, 0x86, 0xa8, 0xb2, 0x0d, 0x1b, 0x3d,
  5756. 0xb2, 0x07, 0xfe, 0x0e, 0x12, 0x01, 0x43, 0x09, 0x82, 0x4e, 0x05, 0x72,
  5757. 0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73, 0x01,
  5758. 0xfe, 0xc0, 0x19, 0x05, 0x73, 0x13, 0x07, 0x2f, 0xfe, 0xcc, 0x15, 0x17,
  5759. 0xfe, 0xe2, 0x15, 0x5f, 0xcc, 0x01, 0x08, 0x26, 0x5f, 0x02, 0x8f, 0xfe,
  5760. 0xde, 0x15, 0x2a, 0xfe, 0xde, 0x15, 0x16, 0xfe, 0xcc, 0x15, 0x5e, 0x32,
  5761. 0x01, 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52,
  5762. 0xad, 0x23, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x02,
  5763. 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xad, 0x23, 0x3f, 0xfe, 0x30,
  5764. 0x56, 0xfe, 0x00, 0x5c, 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52,
  5765. 0xad, 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xfe, 0x00, 0x5e,
  5766. 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xad, 0xfe, 0x0b, 0x58,
  5767. 0x02, 0x0a, 0x66, 0x01, 0x5c, 0x0a, 0x55, 0x01, 0x5c, 0x0a, 0x6f, 0x01,
  5768. 0x5c, 0x02, 0x01, 0xfe, 0x1e, 0x1f, 0x23, 0x1a, 0xff, 0x03, 0x00, 0x54,
  5769. 0xfe, 0x00, 0xf4, 0x24, 0x52, 0x0f, 0xfe, 0x00, 0x7c, 0x04, 0xfe, 0x07,
  5770. 0x7c, 0x3a, 0x0b, 0x0e, 0xfe, 0x00, 0x71, 0xfe, 0xf9, 0x18, 0xfe, 0x7a,
  5771. 0x19, 0xfe, 0xfb, 0x19, 0xfe, 0x1a, 0xf7, 0x00, 0xfe, 0x1b, 0xf7, 0x00,
  5772. 0x7a, 0x30, 0x10, 0x68, 0x22, 0x69, 0xd9, 0x6c, 0xda, 0x6d, 0x02, 0xfe,
  5773. 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x77,
  5774. 0x02, 0x01, 0xc6, 0xfe, 0x42, 0x48, 0x4f, 0x50, 0x45, 0x01, 0x08, 0x16,
  5775. 0xfe, 0xe0, 0x17, 0x27, 0x25, 0xbe, 0x01, 0x08, 0x16, 0xfe, 0xe0, 0x17,
  5776. 0x27, 0x25, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0x9a, 0x1e, 0xfe,
  5777. 0xda, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfe, 0xd0, 0x13, 0x26, 0x53, 0x12,
  5778. 0x48, 0xfe, 0x08, 0x17, 0xd1, 0x12, 0x53, 0x12, 0xfe, 0x1e, 0x13, 0x2d,
  5779. 0xb4, 0x7b, 0xfe, 0x26, 0x17, 0x4d, 0x13, 0x07, 0x1c, 0xb4, 0x90, 0x04,
  5780. 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xf1, 0xff, 0x02, 0x83, 0x55,
  5781. 0x53, 0x1d, 0xfe, 0x12, 0x13, 0xd6, 0xfe, 0x30, 0x00, 0xb0, 0xfe, 0x80,
  5782. 0x17, 0x1c, 0x63, 0x13, 0x07, 0xfe, 0x56, 0x10, 0x53, 0x0d, 0xfe, 0x16,
  5783. 0x13, 0xd6, 0xfe, 0x64, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0x64,
  5784. 0x00, 0x1c, 0x94, 0x13, 0x07, 0xfe, 0x28, 0x10, 0x53, 0x07, 0xfe, 0x60,
  5785. 0x13, 0xd6, 0xfe, 0xc8, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0xc8,
  5786. 0x00, 0x1c, 0x95, 0x13, 0x07, 0x71, 0xd6, 0xfe, 0x90, 0x01, 0x48, 0xfe,
  5787. 0x8c, 0x17, 0x45, 0xf3, 0xfe, 0x43, 0xf4, 0x96, 0xfe, 0x56, 0xf0, 0xfe,
  5788. 0x9e, 0x17, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x43, 0xf4, 0x94, 0xf6, 0x8b,
  5789. 0x01, 0xfe, 0x24, 0x16, 0x23, 0x3f, 0xfc, 0xa8, 0x8c, 0x49, 0x48, 0xfe,
  5790. 0xda, 0x17, 0x62, 0x49, 0xfe, 0x1c, 0x10, 0xa8, 0x8c, 0x80, 0x48, 0xfe,
  5791. 0xda, 0x17, 0x62, 0x80, 0x71, 0x50, 0x26, 0xfe, 0x4d, 0xf4, 0x00, 0xf7,
  5792. 0x45, 0x13, 0x07, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x02, 0x50, 0x13,
  5793. 0x0d, 0x02, 0x50, 0x3e, 0x78, 0x4f, 0x45, 0x01, 0x08, 0x16, 0xa9, 0x27,
  5794. 0x25, 0xbe, 0xfe, 0x03, 0xea, 0xfe, 0x7e, 0x01, 0x01, 0x08, 0x16, 0xa9,
  5795. 0x27, 0x25, 0xfe, 0xe9, 0x0a, 0x01, 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe,
  5796. 0xe9, 0x0a, 0xfe, 0x05, 0xea, 0xfe, 0x7f, 0x01, 0x01, 0x08, 0x16, 0xa9,
  5797. 0x27, 0x25, 0xfe, 0x69, 0x09, 0xfe, 0x02, 0xea, 0xfe, 0x80, 0x01, 0x01,
  5798. 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe, 0xe8, 0x08, 0x47, 0xfe, 0x81, 0x01,
  5799. 0x03, 0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa2, 0x78, 0xf2,
  5800. 0x53, 0x07, 0x36, 0xfe, 0x34, 0xf4, 0x3f, 0xa1, 0x78, 0x03, 0x9a, 0x1e,
  5801. 0x83, 0x01, 0x38, 0x06, 0x12, 0x31, 0xf0, 0x4f, 0x45, 0xfe, 0x90, 0x10,
  5802. 0xfe, 0x40, 0x5a, 0x23, 0x3f, 0xfb, 0x8c, 0x49, 0x48, 0xfe, 0xaa, 0x18,
  5803. 0x62, 0x49, 0x71, 0x8c, 0x80, 0x48, 0xfe, 0xaa, 0x18, 0x62, 0x80, 0xfe,
  5804. 0xb4, 0x56, 0xfe, 0x40, 0x5d, 0x01, 0xc6, 0x01, 0xfe, 0xac, 0x1d, 0xfe,
  5805. 0x02, 0x17, 0xfe, 0xc8, 0x45, 0xfe, 0x5a, 0xf0, 0xfe, 0xc0, 0x18, 0xfe,
  5806. 0x43, 0x48, 0x2d, 0x93, 0x36, 0xfe, 0x34, 0xf4, 0xfe, 0x00, 0x11, 0xfe,
  5807. 0x40, 0x10, 0x2d, 0xb4, 0x36, 0xfe, 0x34, 0xf4, 0x04, 0xfe, 0x34, 0x10,
  5808. 0x2d, 0xfe, 0x0b, 0x00, 0x36, 0x46, 0x63, 0xfe, 0x28, 0x10, 0xfe, 0xc0,
  5809. 0x49, 0xff, 0x02, 0x00, 0x54, 0xb2, 0xfe, 0x90, 0x01, 0x48, 0xfe, 0xfa,
  5810. 0x18, 0x45, 0xfe, 0x1c, 0xf4, 0x3f, 0xf3, 0xfe, 0x40, 0xf4, 0x96, 0xfe,
  5811. 0x56, 0xf0, 0xfe, 0x0c, 0x19, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x40, 0xf4,
  5812. 0x94, 0xf6, 0x3e, 0x2d, 0x93, 0x4e, 0xd0, 0x0d, 0x21, 0xfe, 0x7f, 0x01,
  5813. 0xfe, 0xc8, 0x46, 0xfe, 0x24, 0x13, 0x8c, 0x00, 0x5d, 0x26, 0x21, 0xfe,
  5814. 0x7e, 0x01, 0xfe, 0xc8, 0x45, 0xfe, 0x14, 0x13, 0x21, 0xfe, 0x80, 0x01,
  5815. 0xfe, 0x48, 0x45, 0xfa, 0x21, 0xfe, 0x81, 0x01, 0xfe, 0xc8, 0x44, 0x4e,
  5816. 0x26, 0x02, 0x13, 0x07, 0x02, 0x78, 0x45, 0x50, 0x13, 0x0d, 0x02, 0x14,
  5817. 0x07, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x14, 0x0d, 0x01, 0x08, 0x17,
  5818. 0xfe, 0x82, 0x19, 0x14, 0x1d, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x5f,
  5819. 0xfe, 0x89, 0x49, 0x01, 0x08, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
  5820. 0x14, 0x1d, 0x01, 0x08, 0x17, 0xc1, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1,
  5821. 0xfe, 0x89, 0x49, 0x01, 0x08, 0x17, 0xc1, 0x5f, 0xfe, 0x89, 0x4a, 0x01,
  5822. 0x08, 0x02, 0x50, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0x74, 0x14, 0x7f,
  5823. 0x01, 0x08, 0x17, 0x74, 0x14, 0x12, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x89,
  5824. 0x49, 0x01, 0x08, 0x17, 0x74, 0x14, 0x00, 0x01, 0x08, 0x17, 0x74, 0xfe,
  5825. 0x89, 0x4a, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x09, 0x49, 0x01, 0x08, 0x17,
  5826. 0x74, 0x5f, 0xcc, 0x01, 0x08, 0x02, 0x21, 0xe4, 0x09, 0x07, 0xfe, 0x4c,
  5827. 0x13, 0xc8, 0x20, 0xe4, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x5f, 0xa1, 0x5e,
  5828. 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f,
  5829. 0xfe, 0x3e, 0x1a, 0x01, 0x43, 0x09, 0xfe, 0xe3, 0x00, 0xfe, 0x22, 0x13,
  5830. 0x16, 0xfe, 0x64, 0x1a, 0x26, 0x20, 0x9e, 0x01, 0x41, 0x21, 0x9e, 0x09,
  5831. 0x07, 0x5d, 0x01, 0x0c, 0x61, 0x07, 0x44, 0x02, 0x0a, 0x5a, 0x01, 0x18,
  5832. 0xfe, 0x00, 0x40, 0xaa, 0x09, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01,
  5833. 0x18, 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x9d, 0x01, 0x18, 0xaa,
  5834. 0xfe, 0x80, 0xe7, 0x1a, 0x09, 0x1a, 0x5d, 0xfe, 0x45, 0x58, 0x01, 0xfe,
  5835. 0xb2, 0x16, 0xaa, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0xaa, 0x0a, 0x67, 0x01,
  5836. 0xa3, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x01, 0xfe, 0x7e, 0x1e, 0xfe, 0x80,
  5837. 0x4c, 0xfe, 0x49, 0xe4, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, 0x18,
  5838. 0xfe, 0x80, 0x4c, 0x0a, 0x67, 0x01, 0x5c, 0x02, 0x1c, 0x1a, 0x87, 0x7c,
  5839. 0xe5, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe, 0x1d,
  5840. 0xf7, 0x28, 0xb1, 0xfe, 0x04, 0x1b, 0x01, 0xfe, 0x2a, 0x1c, 0xfa, 0xb3,
  5841. 0x28, 0x7c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x02, 0xc9, 0x2b, 0xfe,
  5842. 0xf4, 0x1a, 0xfe, 0xfa, 0x10, 0x1c, 0x1a, 0x87, 0x03, 0xfe, 0x64, 0x01,
  5843. 0xfe, 0x00, 0xf4, 0x24, 0xfe, 0x18, 0x58, 0x03, 0xfe, 0x66, 0x01, 0xfe,
  5844. 0x19, 0x58, 0xb3, 0x24, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4, 0x07,
  5845. 0xfe, 0x3c, 0x50, 0x7c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c,
  5846. 0xf7, 0x24, 0xb1, 0xfe, 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9,
  5847. 0x2b, 0xfe, 0x26, 0x1b, 0xfe, 0xba, 0x10, 0x1c, 0x1a, 0x87, 0xfe, 0x83,
  5848. 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1,
  5849. 0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe,
  5850. 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b,
  5851. 0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f, 0xfe, 0x30, 0x90, 0x04,
  5852. 0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04,
  5853. 0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a,
  5854. 0x7c, 0x12, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6,
  5855. 0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x96, 0x1b, 0x5c,
  5856. 0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe,
  5857. 0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee,
  5858. 0x1b, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83,
  5859. 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a, 0xfe, 0x81, 0xe7, 0x1a,
  5860. 0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45,
  5861. 0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe,
  5862. 0x39, 0xf0, 0x75, 0x26, 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13,
  5863. 0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0xef, 0x12, 0xfe, 0xe1,
  5864. 0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13,
  5865. 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a,
  5866. 0x01, 0x18, 0xcb, 0xfe, 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48,
  5867. 0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f,
  5868. 0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01,
  5869. 0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24,
  5870. 0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d,
  5871. 0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30,
  5872. 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
  5873. 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
  5874. 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
  5875. 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
  5876. 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
  5877. 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
  5878. 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
  5879. 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
  5880. 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
  5881. 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
  5882. 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
  5883. 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
  5884. 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
  5885. 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
  5886. 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
  5887. 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
  5888. 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
  5889. 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
  5890. 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
  5891. 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
  5892. 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
  5893. 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
  5894. 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
  5895. 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
  5896. 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
  5897. 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
  5898. 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
  5899. 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
  5900. 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
  5901. 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
  5902. 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
  5903. 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
  5904. 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
  5905. 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
  5906. 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
  5907. 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
  5908. 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
  5909. 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
  5910. 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
  5911. 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
  5912. 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
  5913. };
  5914. static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
  5915. static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
  5916. static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
  5917. {
  5918. PortAddr iop_base;
  5919. int i;
  5920. ushort lram_addr;
  5921. iop_base = asc_dvc->iop_base;
  5922. AscPutRiscVarFreeQHead(iop_base, 1);
  5923. AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
  5924. AscPutVarFreeQHead(iop_base, 1);
  5925. AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
  5926. AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
  5927. (uchar)((int)asc_dvc->max_total_qng + 1));
  5928. AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
  5929. (uchar)((int)asc_dvc->max_total_qng + 2));
  5930. AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
  5931. asc_dvc->max_total_qng);
  5932. AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
  5933. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  5934. AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
  5935. AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
  5936. AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
  5937. AscPutQDoneInProgress(iop_base, 0);
  5938. lram_addr = ASC_QADR_BEG;
  5939. for (i = 0; i < 32; i++, lram_addr += 2) {
  5940. AscWriteLramWord(iop_base, lram_addr, 0);
  5941. }
  5942. }
  5943. static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
  5944. {
  5945. int i;
  5946. ushort warn_code;
  5947. PortAddr iop_base;
  5948. ASC_PADDR phy_addr;
  5949. ASC_DCNT phy_size;
  5950. iop_base = asc_dvc->iop_base;
  5951. warn_code = 0;
  5952. for (i = 0; i <= ASC_MAX_TID; i++) {
  5953. AscPutMCodeInitSDTRAtID(iop_base, i,
  5954. asc_dvc->cfg->sdtr_period_offset[i]);
  5955. }
  5956. AscInitQLinkVar(asc_dvc);
  5957. AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
  5958. asc_dvc->cfg->disc_enable);
  5959. AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
  5960. ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
  5961. /* Align overrun buffer on an 8 byte boundary. */
  5962. phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
  5963. phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
  5964. AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
  5965. (uchar *)&phy_addr, 1);
  5966. phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
  5967. AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
  5968. (uchar *)&phy_size, 1);
  5969. asc_dvc->cfg->mcode_date =
  5970. AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
  5971. asc_dvc->cfg->mcode_version =
  5972. AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
  5973. AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
  5974. if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
  5975. asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
  5976. return warn_code;
  5977. }
  5978. if (AscStartChip(iop_base) != 1) {
  5979. asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
  5980. return warn_code;
  5981. }
  5982. return warn_code;
  5983. }
  5984. static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
  5985. {
  5986. ushort warn_code;
  5987. PortAddr iop_base;
  5988. iop_base = asc_dvc->iop_base;
  5989. warn_code = 0;
  5990. if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
  5991. !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
  5992. AscResetChipAndScsiBus(asc_dvc);
  5993. mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
  5994. }
  5995. asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
  5996. if (asc_dvc->err_code != 0)
  5997. return UW_ERR;
  5998. if (!AscFindSignature(asc_dvc->iop_base)) {
  5999. asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
  6000. return warn_code;
  6001. }
  6002. AscDisableInterrupt(iop_base);
  6003. warn_code |= AscInitLram(asc_dvc);
  6004. if (asc_dvc->err_code != 0)
  6005. return UW_ERR;
  6006. ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
  6007. (ulong)_asc_mcode_chksum);
  6008. if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
  6009. _asc_mcode_size) != _asc_mcode_chksum) {
  6010. asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
  6011. return warn_code;
  6012. }
  6013. warn_code |= AscInitMicroCodeVar(asc_dvc);
  6014. asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
  6015. AscEnableInterrupt(iop_base);
  6016. return warn_code;
  6017. }
  6018. /*
  6019. * Load the Microcode
  6020. *
  6021. * Write the microcode image to RISC memory starting at address 0.
  6022. *
  6023. * The microcode is stored compressed in the following format:
  6024. *
  6025. * 254 word (508 byte) table indexed by byte code followed
  6026. * by the following byte codes:
  6027. *
  6028. * 1-Byte Code:
  6029. * 00: Emit word 0 in table.
  6030. * 01: Emit word 1 in table.
  6031. * .
  6032. * FD: Emit word 253 in table.
  6033. *
  6034. * Multi-Byte Code:
  6035. * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
  6036. * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
  6037. *
  6038. * Returns 0 or an error if the checksum doesn't match
  6039. */
  6040. static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
  6041. int memsize, int chksum)
  6042. {
  6043. int i, j, end, len = 0;
  6044. ADV_DCNT sum;
  6045. AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
  6046. for (i = 253 * 2; i < size; i++) {
  6047. if (buf[i] == 0xff) {
  6048. unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
  6049. for (j = 0; j < buf[i + 1]; j++) {
  6050. AdvWriteWordAutoIncLram(iop_base, word);
  6051. len += 2;
  6052. }
  6053. i += 3;
  6054. } else if (buf[i] == 0xfe) {
  6055. unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
  6056. AdvWriteWordAutoIncLram(iop_base, word);
  6057. i += 2;
  6058. len += 2;
  6059. } else {
  6060. unsigned char off = buf[i] * 2;
  6061. unsigned short word = (buf[off + 1] << 8) | buf[off];
  6062. AdvWriteWordAutoIncLram(iop_base, word);
  6063. len += 2;
  6064. }
  6065. }
  6066. end = len;
  6067. while (len < memsize) {
  6068. AdvWriteWordAutoIncLram(iop_base, 0);
  6069. len += 2;
  6070. }
  6071. /* Verify the microcode checksum. */
  6072. sum = 0;
  6073. AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
  6074. for (len = 0; len < end; len += 2) {
  6075. sum += AdvReadWordAutoIncLram(iop_base);
  6076. }
  6077. if (sum != chksum)
  6078. return ASC_IERR_MCODE_CHKSUM;
  6079. return 0;
  6080. }
  6081. /*
  6082. * DvcGetPhyAddr()
  6083. *
  6084. * Return the physical address of 'vaddr' and set '*lenp' to the
  6085. * number of physically contiguous bytes that follow 'vaddr'.
  6086. * 'flag' indicates the type of structure whose physical address
  6087. * is being translated.
  6088. *
  6089. * Note: Because Linux currently doesn't page the kernel and all
  6090. * kernel buffers are physically contiguous, leave '*lenp' unchanged.
  6091. */
  6092. ADV_PADDR
  6093. DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
  6094. uchar *vaddr, ADV_SDCNT *lenp, int flag)
  6095. {
  6096. ADV_PADDR paddr = virt_to_bus(vaddr);
  6097. ASC_DBG4(4, "DvcGetPhyAddr: vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n",
  6098. vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr);
  6099. return paddr;
  6100. }
  6101. static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
  6102. {
  6103. ADV_CARR_T *carrp;
  6104. ADV_SDCNT buf_size;
  6105. ADV_PADDR carr_paddr;
  6106. BUG_ON(!asc_dvc->carrier_buf);
  6107. carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
  6108. asc_dvc->carr_freelist = NULL;
  6109. if (carrp == asc_dvc->carrier_buf) {
  6110. buf_size = ADV_CARRIER_BUFSIZE;
  6111. } else {
  6112. buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
  6113. }
  6114. do {
  6115. /* Get physical address of the carrier 'carrp'. */
  6116. ADV_DCNT contig_len = sizeof(ADV_CARR_T);
  6117. carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
  6118. (uchar *)carrp,
  6119. (ADV_SDCNT *)&contig_len,
  6120. ADV_IS_CARRIER_FLAG));
  6121. buf_size -= sizeof(ADV_CARR_T);
  6122. /*
  6123. * If the current carrier is not physically contiguous, then
  6124. * maybe there was a page crossing. Try the next carrier
  6125. * aligned start address.
  6126. */
  6127. if (contig_len < sizeof(ADV_CARR_T)) {
  6128. carrp++;
  6129. continue;
  6130. }
  6131. carrp->carr_pa = carr_paddr;
  6132. carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
  6133. /*
  6134. * Insert the carrier at the beginning of the freelist.
  6135. */
  6136. carrp->next_vpa =
  6137. cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
  6138. asc_dvc->carr_freelist = carrp;
  6139. carrp++;
  6140. } while (buf_size > 0);
  6141. }
  6142. /*
  6143. * Send an idle command to the chip and wait for completion.
  6144. *
  6145. * Command completion is polled for once per microsecond.
  6146. *
  6147. * The function can be called from anywhere including an interrupt handler.
  6148. * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
  6149. * functions to prevent reentrancy.
  6150. *
  6151. * Return Values:
  6152. * ADV_TRUE - command completed successfully
  6153. * ADV_FALSE - command failed
  6154. * ADV_ERROR - command timed out
  6155. */
  6156. static int
  6157. AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
  6158. ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
  6159. {
  6160. int result;
  6161. ADV_DCNT i, j;
  6162. AdvPortAddr iop_base;
  6163. iop_base = asc_dvc->iop_base;
  6164. /*
  6165. * Clear the idle command status which is set by the microcode
  6166. * to a non-zero value to indicate when the command is completed.
  6167. * The non-zero result is one of the IDLE_CMD_STATUS_* values
  6168. */
  6169. AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
  6170. /*
  6171. * Write the idle command value after the idle command parameter
  6172. * has been written to avoid a race condition. If the order is not
  6173. * followed, the microcode may process the idle command before the
  6174. * parameters have been written to LRAM.
  6175. */
  6176. AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
  6177. cpu_to_le32(idle_cmd_parameter));
  6178. AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
  6179. /*
  6180. * Tickle the RISC to tell it to process the idle command.
  6181. */
  6182. AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
  6183. if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
  6184. /*
  6185. * Clear the tickle value. In the ASC-3550 the RISC flag
  6186. * command 'clr_tickle_b' does not work unless the host
  6187. * value is cleared.
  6188. */
  6189. AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
  6190. }
  6191. /* Wait for up to 100 millisecond for the idle command to timeout. */
  6192. for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
  6193. /* Poll once each microsecond for command completion. */
  6194. for (j = 0; j < SCSI_US_PER_MSEC; j++) {
  6195. AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
  6196. result);
  6197. if (result != 0)
  6198. return result;
  6199. udelay(1);
  6200. }
  6201. }
  6202. BUG(); /* The idle command should never timeout. */
  6203. return ADV_ERROR;
  6204. }
  6205. /*
  6206. * Reset SCSI Bus and purge all outstanding requests.
  6207. *
  6208. * Return Value:
  6209. * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
  6210. * ADV_FALSE(0) - Microcode command failed.
  6211. * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
  6212. * may be hung which requires driver recovery.
  6213. */
  6214. static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
  6215. {
  6216. int status;
  6217. /*
  6218. * Send the SCSI Bus Reset idle start idle command which asserts
  6219. * the SCSI Bus Reset signal.
  6220. */
  6221. status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
  6222. if (status != ADV_TRUE) {
  6223. return status;
  6224. }
  6225. /*
  6226. * Delay for the specified SCSI Bus Reset hold time.
  6227. *
  6228. * The hold time delay is done on the host because the RISC has no
  6229. * microsecond accurate timer.
  6230. */
  6231. udelay(ASC_SCSI_RESET_HOLD_TIME_US);
  6232. /*
  6233. * Send the SCSI Bus Reset end idle command which de-asserts
  6234. * the SCSI Bus Reset signal and purges any pending requests.
  6235. */
  6236. status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
  6237. if (status != ADV_TRUE) {
  6238. return status;
  6239. }
  6240. mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
  6241. return status;
  6242. }
  6243. /*
  6244. * Initialize the ASC-3550.
  6245. *
  6246. * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
  6247. *
  6248. * For a non-fatal error return a warning code. If there are no warnings
  6249. * then 0 is returned.
  6250. *
  6251. * Needed after initialization for error recovery.
  6252. */
  6253. static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
  6254. {
  6255. AdvPortAddr iop_base;
  6256. ushort warn_code;
  6257. int begin_addr;
  6258. int end_addr;
  6259. ushort code_sum;
  6260. int word;
  6261. int i;
  6262. ushort scsi_cfg1;
  6263. uchar tid;
  6264. ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
  6265. ushort wdtr_able = 0, sdtr_able, tagqng_able;
  6266. uchar max_cmd[ADV_MAX_TID + 1];
  6267. /* If there is already an error, don't continue. */
  6268. if (asc_dvc->err_code != 0)
  6269. return ADV_ERROR;
  6270. /*
  6271. * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
  6272. */
  6273. if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
  6274. asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
  6275. return ADV_ERROR;
  6276. }
  6277. warn_code = 0;
  6278. iop_base = asc_dvc->iop_base;
  6279. /*
  6280. * Save the RISC memory BIOS region before writing the microcode.
  6281. * The BIOS may already be loaded and using its RISC LRAM region
  6282. * so its region must be saved and restored.
  6283. *
  6284. * Note: This code makes the assumption, which is currently true,
  6285. * that a chip reset does not clear RISC LRAM.
  6286. */
  6287. for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
  6288. AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
  6289. bios_mem[i]);
  6290. }
  6291. /*
  6292. * Save current per TID negotiated values.
  6293. */
  6294. if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
  6295. ushort bios_version, major, minor;
  6296. bios_version =
  6297. bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
  6298. major = (bios_version >> 12) & 0xF;
  6299. minor = (bios_version >> 8) & 0xF;
  6300. if (major < 3 || (major == 3 && minor == 1)) {
  6301. /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
  6302. AdvReadWordLram(iop_base, 0x120, wdtr_able);
  6303. } else {
  6304. AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  6305. }
  6306. }
  6307. AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  6308. AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
  6309. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  6310. AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
  6311. max_cmd[tid]);
  6312. }
  6313. asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
  6314. _adv_asc3550_size, ADV_3550_MEMSIZE,
  6315. _adv_asc3550_chksum);
  6316. if (asc_dvc->err_code)
  6317. return ADV_ERROR;
  6318. /*
  6319. * Restore the RISC memory BIOS region.
  6320. */
  6321. for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
  6322. AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
  6323. bios_mem[i]);
  6324. }
  6325. /*
  6326. * Calculate and write the microcode code checksum to the microcode
  6327. * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
  6328. */
  6329. AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
  6330. AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
  6331. code_sum = 0;
  6332. AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
  6333. for (word = begin_addr; word < end_addr; word += 2) {
  6334. code_sum += AdvReadWordAutoIncLram(iop_base);
  6335. }
  6336. AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
  6337. /*
  6338. * Read and save microcode version and date.
  6339. */
  6340. AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
  6341. asc_dvc->cfg->mcode_date);
  6342. AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
  6343. asc_dvc->cfg->mcode_version);
  6344. /*
  6345. * Set the chip type to indicate the ASC3550.
  6346. */
  6347. AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
  6348. /*
  6349. * If the PCI Configuration Command Register "Parity Error Response
  6350. * Control" Bit was clear (0), then set the microcode variable
  6351. * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
  6352. * to ignore DMA parity errors.
  6353. */
  6354. if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
  6355. AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  6356. word |= CONTROL_FLAG_IGNORE_PERR;
  6357. AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  6358. }
  6359. /*
  6360. * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
  6361. * threshold of 128 bytes. This register is only accessible to the host.
  6362. */
  6363. AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
  6364. START_CTL_EMFU | READ_CMD_MRM);
  6365. /*
  6366. * Microcode operating variables for WDTR, SDTR, and command tag
  6367. * queuing will be set in slave_configure() based on what a
  6368. * device reports it is capable of in Inquiry byte 7.
  6369. *
  6370. * If SCSI Bus Resets have been disabled, then directly set
  6371. * SDTR and WDTR from the EEPROM configuration. This will allow
  6372. * the BIOS and warm boot to work without a SCSI bus hang on
  6373. * the Inquiry caused by host and target mismatched DTR values.
  6374. * Without the SCSI Bus Reset, before an Inquiry a device can't
  6375. * be assumed to be in Asynchronous, Narrow mode.
  6376. */
  6377. if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
  6378. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
  6379. asc_dvc->wdtr_able);
  6380. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
  6381. asc_dvc->sdtr_able);
  6382. }
  6383. /*
  6384. * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
  6385. * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
  6386. * bitmask. These values determine the maximum SDTR speed negotiated
  6387. * with a device.
  6388. *
  6389. * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
  6390. * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
  6391. * without determining here whether the device supports SDTR.
  6392. *
  6393. * 4-bit speed SDTR speed name
  6394. * =========== ===============
  6395. * 0000b (0x0) SDTR disabled
  6396. * 0001b (0x1) 5 Mhz
  6397. * 0010b (0x2) 10 Mhz
  6398. * 0011b (0x3) 20 Mhz (Ultra)
  6399. * 0100b (0x4) 40 Mhz (LVD/Ultra2)
  6400. * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
  6401. * 0110b (0x6) Undefined
  6402. * .
  6403. * 1111b (0xF) Undefined
  6404. */
  6405. word = 0;
  6406. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  6407. if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
  6408. /* Set Ultra speed for TID 'tid'. */
  6409. word |= (0x3 << (4 * (tid % 4)));
  6410. } else {
  6411. /* Set Fast speed for TID 'tid'. */
  6412. word |= (0x2 << (4 * (tid % 4)));
  6413. }
  6414. if (tid == 3) { /* Check if done with sdtr_speed1. */
  6415. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
  6416. word = 0;
  6417. } else if (tid == 7) { /* Check if done with sdtr_speed2. */
  6418. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
  6419. word = 0;
  6420. } else if (tid == 11) { /* Check if done with sdtr_speed3. */
  6421. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
  6422. word = 0;
  6423. } else if (tid == 15) { /* Check if done with sdtr_speed4. */
  6424. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
  6425. /* End of loop. */
  6426. }
  6427. }
  6428. /*
  6429. * Set microcode operating variable for the disconnect per TID bitmask.
  6430. */
  6431. AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
  6432. asc_dvc->cfg->disc_enable);
  6433. /*
  6434. * Set SCSI_CFG0 Microcode Default Value.
  6435. *
  6436. * The microcode will set the SCSI_CFG0 register using this value
  6437. * after it is started below.
  6438. */
  6439. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
  6440. PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
  6441. asc_dvc->chip_scsi_id);
  6442. /*
  6443. * Determine SCSI_CFG1 Microcode Default Value.
  6444. *
  6445. * The microcode will set the SCSI_CFG1 register using this value
  6446. * after it is started below.
  6447. */
  6448. /* Read current SCSI_CFG1 Register value. */
  6449. scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
  6450. /*
  6451. * If all three connectors are in use, return an error.
  6452. */
  6453. if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
  6454. (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
  6455. asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
  6456. return ADV_ERROR;
  6457. }
  6458. /*
  6459. * If the internal narrow cable is reversed all of the SCSI_CTRL
  6460. * register signals will be set. Check for and return an error if
  6461. * this condition is found.
  6462. */
  6463. if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
  6464. asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
  6465. return ADV_ERROR;
  6466. }
  6467. /*
  6468. * If this is a differential board and a single-ended device
  6469. * is attached to one of the connectors, return an error.
  6470. */
  6471. if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
  6472. asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
  6473. return ADV_ERROR;
  6474. }
  6475. /*
  6476. * If automatic termination control is enabled, then set the
  6477. * termination value based on a table listed in a_condor.h.
  6478. *
  6479. * If manual termination was specified with an EEPROM setting
  6480. * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
  6481. * is ready to be 'ored' into SCSI_CFG1.
  6482. */
  6483. if (asc_dvc->cfg->termination == 0) {
  6484. /*
  6485. * The software always controls termination by setting TERM_CTL_SEL.
  6486. * If TERM_CTL_SEL were set to 0, the hardware would set termination.
  6487. */
  6488. asc_dvc->cfg->termination |= TERM_CTL_SEL;
  6489. switch (scsi_cfg1 & CABLE_DETECT) {
  6490. /* TERM_CTL_H: on, TERM_CTL_L: on */
  6491. case 0x3:
  6492. case 0x7:
  6493. case 0xB:
  6494. case 0xD:
  6495. case 0xE:
  6496. case 0xF:
  6497. asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
  6498. break;
  6499. /* TERM_CTL_H: on, TERM_CTL_L: off */
  6500. case 0x1:
  6501. case 0x5:
  6502. case 0x9:
  6503. case 0xA:
  6504. case 0xC:
  6505. asc_dvc->cfg->termination |= TERM_CTL_H;
  6506. break;
  6507. /* TERM_CTL_H: off, TERM_CTL_L: off */
  6508. case 0x2:
  6509. case 0x6:
  6510. break;
  6511. }
  6512. }
  6513. /*
  6514. * Clear any set TERM_CTL_H and TERM_CTL_L bits.
  6515. */
  6516. scsi_cfg1 &= ~TERM_CTL;
  6517. /*
  6518. * Invert the TERM_CTL_H and TERM_CTL_L bits and then
  6519. * set 'scsi_cfg1'. The TERM_POL bit does not need to be
  6520. * referenced, because the hardware internally inverts
  6521. * the Termination High and Low bits if TERM_POL is set.
  6522. */
  6523. scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
  6524. /*
  6525. * Set SCSI_CFG1 Microcode Default Value
  6526. *
  6527. * Set filter value and possibly modified termination control
  6528. * bits in the Microcode SCSI_CFG1 Register Value.
  6529. *
  6530. * The microcode will set the SCSI_CFG1 register using this value
  6531. * after it is started below.
  6532. */
  6533. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
  6534. FLTR_DISABLE | scsi_cfg1);
  6535. /*
  6536. * Set MEM_CFG Microcode Default Value
  6537. *
  6538. * The microcode will set the MEM_CFG register using this value
  6539. * after it is started below.
  6540. *
  6541. * MEM_CFG may be accessed as a word or byte, but only bits 0-7
  6542. * are defined.
  6543. *
  6544. * ASC-3550 has 8KB internal memory.
  6545. */
  6546. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
  6547. BIOS_EN | RAM_SZ_8KB);
  6548. /*
  6549. * Set SEL_MASK Microcode Default Value
  6550. *
  6551. * The microcode will set the SEL_MASK register using this value
  6552. * after it is started below.
  6553. */
  6554. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
  6555. ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
  6556. AdvBuildCarrierFreelist(asc_dvc);
  6557. /*
  6558. * Set-up the Host->RISC Initiator Command Queue (ICQ).
  6559. */
  6560. if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
  6561. asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
  6562. return ADV_ERROR;
  6563. }
  6564. asc_dvc->carr_freelist = (ADV_CARR_T *)
  6565. ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
  6566. /*
  6567. * The first command issued will be placed in the stopper carrier.
  6568. */
  6569. asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
  6570. /*
  6571. * Set RISC ICQ physical address start value.
  6572. */
  6573. AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
  6574. /*
  6575. * Set-up the RISC->Host Initiator Response Queue (IRQ).
  6576. */
  6577. if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
  6578. asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
  6579. return ADV_ERROR;
  6580. }
  6581. asc_dvc->carr_freelist = (ADV_CARR_T *)
  6582. ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
  6583. /*
  6584. * The first command completed by the RISC will be placed in
  6585. * the stopper.
  6586. *
  6587. * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
  6588. * completed the RISC will set the ASC_RQ_STOPPER bit.
  6589. */
  6590. asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
  6591. /*
  6592. * Set RISC IRQ physical address start value.
  6593. */
  6594. AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
  6595. asc_dvc->carr_pending_cnt = 0;
  6596. AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
  6597. (ADV_INTR_ENABLE_HOST_INTR |
  6598. ADV_INTR_ENABLE_GLOBAL_INTR));
  6599. AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
  6600. AdvWriteWordRegister(iop_base, IOPW_PC, word);
  6601. /* finally, finally, gentlemen, start your engine */
  6602. AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
  6603. /*
  6604. * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
  6605. * Resets should be performed. The RISC has to be running
  6606. * to issue a SCSI Bus Reset.
  6607. */
  6608. if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
  6609. /*
  6610. * If the BIOS Signature is present in memory, restore the
  6611. * BIOS Handshake Configuration Table and do not perform
  6612. * a SCSI Bus Reset.
  6613. */
  6614. if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
  6615. 0x55AA) {
  6616. /*
  6617. * Restore per TID negotiated values.
  6618. */
  6619. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  6620. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  6621. AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
  6622. tagqng_able);
  6623. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  6624. AdvWriteByteLram(iop_base,
  6625. ASC_MC_NUMBER_OF_MAX_CMD + tid,
  6626. max_cmd[tid]);
  6627. }
  6628. } else {
  6629. if (AdvResetSB(asc_dvc) != ADV_TRUE) {
  6630. warn_code = ASC_WARN_BUSRESET_ERROR;
  6631. }
  6632. }
  6633. }
  6634. return warn_code;
  6635. }
  6636. /*
  6637. * Initialize the ASC-38C0800.
  6638. *
  6639. * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
  6640. *
  6641. * For a non-fatal error return a warning code. If there are no warnings
  6642. * then 0 is returned.
  6643. *
  6644. * Needed after initialization for error recovery.
  6645. */
  6646. static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
  6647. {
  6648. AdvPortAddr iop_base;
  6649. ushort warn_code;
  6650. int begin_addr;
  6651. int end_addr;
  6652. ushort code_sum;
  6653. int word;
  6654. int i;
  6655. ushort scsi_cfg1;
  6656. uchar byte;
  6657. uchar tid;
  6658. ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
  6659. ushort wdtr_able, sdtr_able, tagqng_able;
  6660. uchar max_cmd[ADV_MAX_TID + 1];
  6661. /* If there is already an error, don't continue. */
  6662. if (asc_dvc->err_code != 0)
  6663. return ADV_ERROR;
  6664. /*
  6665. * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
  6666. */
  6667. if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
  6668. asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
  6669. return ADV_ERROR;
  6670. }
  6671. warn_code = 0;
  6672. iop_base = asc_dvc->iop_base;
  6673. /*
  6674. * Save the RISC memory BIOS region before writing the microcode.
  6675. * The BIOS may already be loaded and using its RISC LRAM region
  6676. * so its region must be saved and restored.
  6677. *
  6678. * Note: This code makes the assumption, which is currently true,
  6679. * that a chip reset does not clear RISC LRAM.
  6680. */
  6681. for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
  6682. AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
  6683. bios_mem[i]);
  6684. }
  6685. /*
  6686. * Save current per TID negotiated values.
  6687. */
  6688. AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  6689. AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  6690. AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
  6691. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  6692. AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
  6693. max_cmd[tid]);
  6694. }
  6695. /*
  6696. * RAM BIST (RAM Built-In Self Test)
  6697. *
  6698. * Address : I/O base + offset 0x38h register (byte).
  6699. * Function: Bit 7-6(RW) : RAM mode
  6700. * Normal Mode : 0x00
  6701. * Pre-test Mode : 0x40
  6702. * RAM Test Mode : 0x80
  6703. * Bit 5 : unused
  6704. * Bit 4(RO) : Done bit
  6705. * Bit 3-0(RO) : Status
  6706. * Host Error : 0x08
  6707. * Int_RAM Error : 0x04
  6708. * RISC Error : 0x02
  6709. * SCSI Error : 0x01
  6710. * No Error : 0x00
  6711. *
  6712. * Note: RAM BIST code should be put right here, before loading the
  6713. * microcode and after saving the RISC memory BIOS region.
  6714. */
  6715. /*
  6716. * LRAM Pre-test
  6717. *
  6718. * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
  6719. * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
  6720. * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
  6721. * to NORMAL_MODE, return an error too.
  6722. */
  6723. for (i = 0; i < 2; i++) {
  6724. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
  6725. mdelay(10); /* Wait for 10ms before reading back. */
  6726. byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
  6727. if ((byte & RAM_TEST_DONE) == 0
  6728. || (byte & 0x0F) != PRE_TEST_VALUE) {
  6729. asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
  6730. return ADV_ERROR;
  6731. }
  6732. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
  6733. mdelay(10); /* Wait for 10ms before reading back. */
  6734. if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
  6735. != NORMAL_VALUE) {
  6736. asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
  6737. return ADV_ERROR;
  6738. }
  6739. }
  6740. /*
  6741. * LRAM Test - It takes about 1.5 ms to run through the test.
  6742. *
  6743. * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
  6744. * If Done bit not set or Status not 0, save register byte, set the
  6745. * err_code, and return an error.
  6746. */
  6747. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
  6748. mdelay(10); /* Wait for 10ms before checking status. */
  6749. byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
  6750. if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
  6751. /* Get here if Done bit not set or Status not 0. */
  6752. asc_dvc->bist_err_code = byte; /* for BIOS display message */
  6753. asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
  6754. return ADV_ERROR;
  6755. }
  6756. /* We need to reset back to normal mode after LRAM test passes. */
  6757. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
  6758. asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
  6759. _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
  6760. _adv_asc38C0800_chksum);
  6761. if (asc_dvc->err_code)
  6762. return ADV_ERROR;
  6763. /*
  6764. * Restore the RISC memory BIOS region.
  6765. */
  6766. for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
  6767. AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
  6768. bios_mem[i]);
  6769. }
  6770. /*
  6771. * Calculate and write the microcode code checksum to the microcode
  6772. * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
  6773. */
  6774. AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
  6775. AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
  6776. code_sum = 0;
  6777. AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
  6778. for (word = begin_addr; word < end_addr; word += 2) {
  6779. code_sum += AdvReadWordAutoIncLram(iop_base);
  6780. }
  6781. AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
  6782. /*
  6783. * Read microcode version and date.
  6784. */
  6785. AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
  6786. asc_dvc->cfg->mcode_date);
  6787. AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
  6788. asc_dvc->cfg->mcode_version);
  6789. /*
  6790. * Set the chip type to indicate the ASC38C0800.
  6791. */
  6792. AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
  6793. /*
  6794. * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
  6795. * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
  6796. * cable detection and then we are able to read C_DET[3:0].
  6797. *
  6798. * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
  6799. * Microcode Default Value' section below.
  6800. */
  6801. scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
  6802. AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
  6803. scsi_cfg1 | DIS_TERM_DRV);
  6804. /*
  6805. * If the PCI Configuration Command Register "Parity Error Response
  6806. * Control" Bit was clear (0), then set the microcode variable
  6807. * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
  6808. * to ignore DMA parity errors.
  6809. */
  6810. if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
  6811. AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  6812. word |= CONTROL_FLAG_IGNORE_PERR;
  6813. AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  6814. }
  6815. /*
  6816. * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
  6817. * bits for the default FIFO threshold.
  6818. *
  6819. * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
  6820. *
  6821. * For DMA Errata #4 set the BC_THRESH_ENB bit.
  6822. */
  6823. AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
  6824. BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
  6825. READ_CMD_MRM);
  6826. /*
  6827. * Microcode operating variables for WDTR, SDTR, and command tag
  6828. * queuing will be set in slave_configure() based on what a
  6829. * device reports it is capable of in Inquiry byte 7.
  6830. *
  6831. * If SCSI Bus Resets have been disabled, then directly set
  6832. * SDTR and WDTR from the EEPROM configuration. This will allow
  6833. * the BIOS and warm boot to work without a SCSI bus hang on
  6834. * the Inquiry caused by host and target mismatched DTR values.
  6835. * Without the SCSI Bus Reset, before an Inquiry a device can't
  6836. * be assumed to be in Asynchronous, Narrow mode.
  6837. */
  6838. if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
  6839. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
  6840. asc_dvc->wdtr_able);
  6841. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
  6842. asc_dvc->sdtr_able);
  6843. }
  6844. /*
  6845. * Set microcode operating variables for DISC and SDTR_SPEED1,
  6846. * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
  6847. * configuration values.
  6848. *
  6849. * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
  6850. * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
  6851. * without determining here whether the device supports SDTR.
  6852. */
  6853. AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
  6854. asc_dvc->cfg->disc_enable);
  6855. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
  6856. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
  6857. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
  6858. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
  6859. /*
  6860. * Set SCSI_CFG0 Microcode Default Value.
  6861. *
  6862. * The microcode will set the SCSI_CFG0 register using this value
  6863. * after it is started below.
  6864. */
  6865. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
  6866. PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
  6867. asc_dvc->chip_scsi_id);
  6868. /*
  6869. * Determine SCSI_CFG1 Microcode Default Value.
  6870. *
  6871. * The microcode will set the SCSI_CFG1 register using this value
  6872. * after it is started below.
  6873. */
  6874. /* Read current SCSI_CFG1 Register value. */
  6875. scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
  6876. /*
  6877. * If the internal narrow cable is reversed all of the SCSI_CTRL
  6878. * register signals will be set. Check for and return an error if
  6879. * this condition is found.
  6880. */
  6881. if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
  6882. asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
  6883. return ADV_ERROR;
  6884. }
  6885. /*
  6886. * All kind of combinations of devices attached to one of four
  6887. * connectors are acceptable except HVD device attached. For example,
  6888. * LVD device can be attached to SE connector while SE device attached
  6889. * to LVD connector. If LVD device attached to SE connector, it only
  6890. * runs up to Ultra speed.
  6891. *
  6892. * If an HVD device is attached to one of LVD connectors, return an
  6893. * error. However, there is no way to detect HVD device attached to
  6894. * SE connectors.
  6895. */
  6896. if (scsi_cfg1 & HVD) {
  6897. asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
  6898. return ADV_ERROR;
  6899. }
  6900. /*
  6901. * If either SE or LVD automatic termination control is enabled, then
  6902. * set the termination value based on a table listed in a_condor.h.
  6903. *
  6904. * If manual termination was specified with an EEPROM setting then
  6905. * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
  6906. * to be 'ored' into SCSI_CFG1.
  6907. */
  6908. if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
  6909. /* SE automatic termination control is enabled. */
  6910. switch (scsi_cfg1 & C_DET_SE) {
  6911. /* TERM_SE_HI: on, TERM_SE_LO: on */
  6912. case 0x1:
  6913. case 0x2:
  6914. case 0x3:
  6915. asc_dvc->cfg->termination |= TERM_SE;
  6916. break;
  6917. /* TERM_SE_HI: on, TERM_SE_LO: off */
  6918. case 0x0:
  6919. asc_dvc->cfg->termination |= TERM_SE_HI;
  6920. break;
  6921. }
  6922. }
  6923. if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
  6924. /* LVD automatic termination control is enabled. */
  6925. switch (scsi_cfg1 & C_DET_LVD) {
  6926. /* TERM_LVD_HI: on, TERM_LVD_LO: on */
  6927. case 0x4:
  6928. case 0x8:
  6929. case 0xC:
  6930. asc_dvc->cfg->termination |= TERM_LVD;
  6931. break;
  6932. /* TERM_LVD_HI: off, TERM_LVD_LO: off */
  6933. case 0x0:
  6934. break;
  6935. }
  6936. }
  6937. /*
  6938. * Clear any set TERM_SE and TERM_LVD bits.
  6939. */
  6940. scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
  6941. /*
  6942. * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
  6943. */
  6944. scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
  6945. /*
  6946. * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
  6947. * bits and set possibly modified termination control bits in the
  6948. * Microcode SCSI_CFG1 Register Value.
  6949. */
  6950. scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
  6951. /*
  6952. * Set SCSI_CFG1 Microcode Default Value
  6953. *
  6954. * Set possibly modified termination control and reset DIS_TERM_DRV
  6955. * bits in the Microcode SCSI_CFG1 Register Value.
  6956. *
  6957. * The microcode will set the SCSI_CFG1 register using this value
  6958. * after it is started below.
  6959. */
  6960. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
  6961. /*
  6962. * Set MEM_CFG Microcode Default Value
  6963. *
  6964. * The microcode will set the MEM_CFG register using this value
  6965. * after it is started below.
  6966. *
  6967. * MEM_CFG may be accessed as a word or byte, but only bits 0-7
  6968. * are defined.
  6969. *
  6970. * ASC-38C0800 has 16KB internal memory.
  6971. */
  6972. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
  6973. BIOS_EN | RAM_SZ_16KB);
  6974. /*
  6975. * Set SEL_MASK Microcode Default Value
  6976. *
  6977. * The microcode will set the SEL_MASK register using this value
  6978. * after it is started below.
  6979. */
  6980. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
  6981. ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
  6982. AdvBuildCarrierFreelist(asc_dvc);
  6983. /*
  6984. * Set-up the Host->RISC Initiator Command Queue (ICQ).
  6985. */
  6986. if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
  6987. asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
  6988. return ADV_ERROR;
  6989. }
  6990. asc_dvc->carr_freelist = (ADV_CARR_T *)
  6991. ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
  6992. /*
  6993. * The first command issued will be placed in the stopper carrier.
  6994. */
  6995. asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
  6996. /*
  6997. * Set RISC ICQ physical address start value.
  6998. * carr_pa is LE, must be native before write
  6999. */
  7000. AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
  7001. /*
  7002. * Set-up the RISC->Host Initiator Response Queue (IRQ).
  7003. */
  7004. if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
  7005. asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
  7006. return ADV_ERROR;
  7007. }
  7008. asc_dvc->carr_freelist = (ADV_CARR_T *)
  7009. ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
  7010. /*
  7011. * The first command completed by the RISC will be placed in
  7012. * the stopper.
  7013. *
  7014. * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
  7015. * completed the RISC will set the ASC_RQ_STOPPER bit.
  7016. */
  7017. asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
  7018. /*
  7019. * Set RISC IRQ physical address start value.
  7020. *
  7021. * carr_pa is LE, must be native before write *
  7022. */
  7023. AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
  7024. asc_dvc->carr_pending_cnt = 0;
  7025. AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
  7026. (ADV_INTR_ENABLE_HOST_INTR |
  7027. ADV_INTR_ENABLE_GLOBAL_INTR));
  7028. AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
  7029. AdvWriteWordRegister(iop_base, IOPW_PC, word);
  7030. /* finally, finally, gentlemen, start your engine */
  7031. AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
  7032. /*
  7033. * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
  7034. * Resets should be performed. The RISC has to be running
  7035. * to issue a SCSI Bus Reset.
  7036. */
  7037. if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
  7038. /*
  7039. * If the BIOS Signature is present in memory, restore the
  7040. * BIOS Handshake Configuration Table and do not perform
  7041. * a SCSI Bus Reset.
  7042. */
  7043. if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
  7044. 0x55AA) {
  7045. /*
  7046. * Restore per TID negotiated values.
  7047. */
  7048. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  7049. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  7050. AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
  7051. tagqng_able);
  7052. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  7053. AdvWriteByteLram(iop_base,
  7054. ASC_MC_NUMBER_OF_MAX_CMD + tid,
  7055. max_cmd[tid]);
  7056. }
  7057. } else {
  7058. if (AdvResetSB(asc_dvc) != ADV_TRUE) {
  7059. warn_code = ASC_WARN_BUSRESET_ERROR;
  7060. }
  7061. }
  7062. }
  7063. return warn_code;
  7064. }
  7065. /*
  7066. * Initialize the ASC-38C1600.
  7067. *
  7068. * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
  7069. *
  7070. * For a non-fatal error return a warning code. If there are no warnings
  7071. * then 0 is returned.
  7072. *
  7073. * Needed after initialization for error recovery.
  7074. */
  7075. static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
  7076. {
  7077. AdvPortAddr iop_base;
  7078. ushort warn_code;
  7079. int begin_addr;
  7080. int end_addr;
  7081. ushort code_sum;
  7082. long word;
  7083. int i;
  7084. ushort scsi_cfg1;
  7085. uchar byte;
  7086. uchar tid;
  7087. ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
  7088. ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
  7089. uchar max_cmd[ASC_MAX_TID + 1];
  7090. /* If there is already an error, don't continue. */
  7091. if (asc_dvc->err_code != 0) {
  7092. return ADV_ERROR;
  7093. }
  7094. /*
  7095. * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
  7096. */
  7097. if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
  7098. asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
  7099. return ADV_ERROR;
  7100. }
  7101. warn_code = 0;
  7102. iop_base = asc_dvc->iop_base;
  7103. /*
  7104. * Save the RISC memory BIOS region before writing the microcode.
  7105. * The BIOS may already be loaded and using its RISC LRAM region
  7106. * so its region must be saved and restored.
  7107. *
  7108. * Note: This code makes the assumption, which is currently true,
  7109. * that a chip reset does not clear RISC LRAM.
  7110. */
  7111. for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
  7112. AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
  7113. bios_mem[i]);
  7114. }
  7115. /*
  7116. * Save current per TID negotiated values.
  7117. */
  7118. AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  7119. AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  7120. AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
  7121. AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
  7122. for (tid = 0; tid <= ASC_MAX_TID; tid++) {
  7123. AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
  7124. max_cmd[tid]);
  7125. }
  7126. /*
  7127. * RAM BIST (Built-In Self Test)
  7128. *
  7129. * Address : I/O base + offset 0x38h register (byte).
  7130. * Function: Bit 7-6(RW) : RAM mode
  7131. * Normal Mode : 0x00
  7132. * Pre-test Mode : 0x40
  7133. * RAM Test Mode : 0x80
  7134. * Bit 5 : unused
  7135. * Bit 4(RO) : Done bit
  7136. * Bit 3-0(RO) : Status
  7137. * Host Error : 0x08
  7138. * Int_RAM Error : 0x04
  7139. * RISC Error : 0x02
  7140. * SCSI Error : 0x01
  7141. * No Error : 0x00
  7142. *
  7143. * Note: RAM BIST code should be put right here, before loading the
  7144. * microcode and after saving the RISC memory BIOS region.
  7145. */
  7146. /*
  7147. * LRAM Pre-test
  7148. *
  7149. * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
  7150. * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
  7151. * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
  7152. * to NORMAL_MODE, return an error too.
  7153. */
  7154. for (i = 0; i < 2; i++) {
  7155. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
  7156. mdelay(10); /* Wait for 10ms before reading back. */
  7157. byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
  7158. if ((byte & RAM_TEST_DONE) == 0
  7159. || (byte & 0x0F) != PRE_TEST_VALUE) {
  7160. asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
  7161. return ADV_ERROR;
  7162. }
  7163. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
  7164. mdelay(10); /* Wait for 10ms before reading back. */
  7165. if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
  7166. != NORMAL_VALUE) {
  7167. asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
  7168. return ADV_ERROR;
  7169. }
  7170. }
  7171. /*
  7172. * LRAM Test - It takes about 1.5 ms to run through the test.
  7173. *
  7174. * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
  7175. * If Done bit not set or Status not 0, save register byte, set the
  7176. * err_code, and return an error.
  7177. */
  7178. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
  7179. mdelay(10); /* Wait for 10ms before checking status. */
  7180. byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
  7181. if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
  7182. /* Get here if Done bit not set or Status not 0. */
  7183. asc_dvc->bist_err_code = byte; /* for BIOS display message */
  7184. asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
  7185. return ADV_ERROR;
  7186. }
  7187. /* We need to reset back to normal mode after LRAM test passes. */
  7188. AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
  7189. asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
  7190. _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
  7191. _adv_asc38C1600_chksum);
  7192. if (asc_dvc->err_code)
  7193. return ADV_ERROR;
  7194. /*
  7195. * Restore the RISC memory BIOS region.
  7196. */
  7197. for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
  7198. AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
  7199. bios_mem[i]);
  7200. }
  7201. /*
  7202. * Calculate and write the microcode code checksum to the microcode
  7203. * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
  7204. */
  7205. AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
  7206. AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
  7207. code_sum = 0;
  7208. AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
  7209. for (word = begin_addr; word < end_addr; word += 2) {
  7210. code_sum += AdvReadWordAutoIncLram(iop_base);
  7211. }
  7212. AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
  7213. /*
  7214. * Read microcode version and date.
  7215. */
  7216. AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
  7217. asc_dvc->cfg->mcode_date);
  7218. AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
  7219. asc_dvc->cfg->mcode_version);
  7220. /*
  7221. * Set the chip type to indicate the ASC38C1600.
  7222. */
  7223. AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
  7224. /*
  7225. * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
  7226. * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
  7227. * cable detection and then we are able to read C_DET[3:0].
  7228. *
  7229. * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
  7230. * Microcode Default Value' section below.
  7231. */
  7232. scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
  7233. AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
  7234. scsi_cfg1 | DIS_TERM_DRV);
  7235. /*
  7236. * If the PCI Configuration Command Register "Parity Error Response
  7237. * Control" Bit was clear (0), then set the microcode variable
  7238. * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
  7239. * to ignore DMA parity errors.
  7240. */
  7241. if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
  7242. AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  7243. word |= CONTROL_FLAG_IGNORE_PERR;
  7244. AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  7245. }
  7246. /*
  7247. * If the BIOS control flag AIPP (Asynchronous Information
  7248. * Phase Protection) disable bit is not set, then set the firmware
  7249. * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
  7250. * AIPP checking and encoding.
  7251. */
  7252. if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
  7253. AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  7254. word |= CONTROL_FLAG_ENABLE_AIPP;
  7255. AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
  7256. }
  7257. /*
  7258. * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
  7259. * and START_CTL_TH [3:2].
  7260. */
  7261. AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
  7262. FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
  7263. /*
  7264. * Microcode operating variables for WDTR, SDTR, and command tag
  7265. * queuing will be set in slave_configure() based on what a
  7266. * device reports it is capable of in Inquiry byte 7.
  7267. *
  7268. * If SCSI Bus Resets have been disabled, then directly set
  7269. * SDTR and WDTR from the EEPROM configuration. This will allow
  7270. * the BIOS and warm boot to work without a SCSI bus hang on
  7271. * the Inquiry caused by host and target mismatched DTR values.
  7272. * Without the SCSI Bus Reset, before an Inquiry a device can't
  7273. * be assumed to be in Asynchronous, Narrow mode.
  7274. */
  7275. if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
  7276. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
  7277. asc_dvc->wdtr_able);
  7278. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
  7279. asc_dvc->sdtr_able);
  7280. }
  7281. /*
  7282. * Set microcode operating variables for DISC and SDTR_SPEED1,
  7283. * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
  7284. * configuration values.
  7285. *
  7286. * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
  7287. * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
  7288. * without determining here whether the device supports SDTR.
  7289. */
  7290. AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
  7291. asc_dvc->cfg->disc_enable);
  7292. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
  7293. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
  7294. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
  7295. AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
  7296. /*
  7297. * Set SCSI_CFG0 Microcode Default Value.
  7298. *
  7299. * The microcode will set the SCSI_CFG0 register using this value
  7300. * after it is started below.
  7301. */
  7302. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
  7303. PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
  7304. asc_dvc->chip_scsi_id);
  7305. /*
  7306. * Calculate SCSI_CFG1 Microcode Default Value.
  7307. *
  7308. * The microcode will set the SCSI_CFG1 register using this value
  7309. * after it is started below.
  7310. *
  7311. * Each ASC-38C1600 function has only two cable detect bits.
  7312. * The bus mode override bits are in IOPB_SOFT_OVER_WR.
  7313. */
  7314. scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
  7315. /*
  7316. * If the cable is reversed all of the SCSI_CTRL register signals
  7317. * will be set. Check for and return an error if this condition is
  7318. * found.
  7319. */
  7320. if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
  7321. asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
  7322. return ADV_ERROR;
  7323. }
  7324. /*
  7325. * Each ASC-38C1600 function has two connectors. Only an HVD device
  7326. * can not be connected to either connector. An LVD device or SE device
  7327. * may be connected to either connecor. If an SE device is connected,
  7328. * then at most Ultra speed (20 Mhz) can be used on both connectors.
  7329. *
  7330. * If an HVD device is attached, return an error.
  7331. */
  7332. if (scsi_cfg1 & HVD) {
  7333. asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
  7334. return ADV_ERROR;
  7335. }
  7336. /*
  7337. * Each function in the ASC-38C1600 uses only the SE cable detect and
  7338. * termination because there are two connectors for each function. Each
  7339. * function may use either LVD or SE mode. Corresponding the SE automatic
  7340. * termination control EEPROM bits are used for each function. Each
  7341. * function has its own EEPROM. If SE automatic control is enabled for
  7342. * the function, then set the termination value based on a table listed
  7343. * in a_condor.h.
  7344. *
  7345. * If manual termination is specified in the EEPROM for the function,
  7346. * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
  7347. * ready to be 'ored' into SCSI_CFG1.
  7348. */
  7349. if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
  7350. struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
  7351. /* SE automatic termination control is enabled. */
  7352. switch (scsi_cfg1 & C_DET_SE) {
  7353. /* TERM_SE_HI: on, TERM_SE_LO: on */
  7354. case 0x1:
  7355. case 0x2:
  7356. case 0x3:
  7357. asc_dvc->cfg->termination |= TERM_SE;
  7358. break;
  7359. case 0x0:
  7360. if (PCI_FUNC(pdev->devfn) == 0) {
  7361. /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
  7362. } else {
  7363. /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
  7364. asc_dvc->cfg->termination |= TERM_SE_HI;
  7365. }
  7366. break;
  7367. }
  7368. }
  7369. /*
  7370. * Clear any set TERM_SE bits.
  7371. */
  7372. scsi_cfg1 &= ~TERM_SE;
  7373. /*
  7374. * Invert the TERM_SE bits and then set 'scsi_cfg1'.
  7375. */
  7376. scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
  7377. /*
  7378. * Clear Big Endian and Terminator Polarity bits and set possibly
  7379. * modified termination control bits in the Microcode SCSI_CFG1
  7380. * Register Value.
  7381. *
  7382. * Big Endian bit is not used even on big endian machines.
  7383. */
  7384. scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
  7385. /*
  7386. * Set SCSI_CFG1 Microcode Default Value
  7387. *
  7388. * Set possibly modified termination control bits in the Microcode
  7389. * SCSI_CFG1 Register Value.
  7390. *
  7391. * The microcode will set the SCSI_CFG1 register using this value
  7392. * after it is started below.
  7393. */
  7394. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
  7395. /*
  7396. * Set MEM_CFG Microcode Default Value
  7397. *
  7398. * The microcode will set the MEM_CFG register using this value
  7399. * after it is started below.
  7400. *
  7401. * MEM_CFG may be accessed as a word or byte, but only bits 0-7
  7402. * are defined.
  7403. *
  7404. * ASC-38C1600 has 32KB internal memory.
  7405. *
  7406. * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
  7407. * out a special 16K Adv Library and Microcode version. After the issue
  7408. * resolved, we should turn back to the 32K support. Both a_condor.h and
  7409. * mcode.sas files also need to be updated.
  7410. *
  7411. * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
  7412. * BIOS_EN | RAM_SZ_32KB);
  7413. */
  7414. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
  7415. BIOS_EN | RAM_SZ_16KB);
  7416. /*
  7417. * Set SEL_MASK Microcode Default Value
  7418. *
  7419. * The microcode will set the SEL_MASK register using this value
  7420. * after it is started below.
  7421. */
  7422. AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
  7423. ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
  7424. AdvBuildCarrierFreelist(asc_dvc);
  7425. /*
  7426. * Set-up the Host->RISC Initiator Command Queue (ICQ).
  7427. */
  7428. if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
  7429. asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
  7430. return ADV_ERROR;
  7431. }
  7432. asc_dvc->carr_freelist = (ADV_CARR_T *)
  7433. ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
  7434. /*
  7435. * The first command issued will be placed in the stopper carrier.
  7436. */
  7437. asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
  7438. /*
  7439. * Set RISC ICQ physical address start value. Initialize the
  7440. * COMMA register to the same value otherwise the RISC will
  7441. * prematurely detect a command is available.
  7442. */
  7443. AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
  7444. AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
  7445. le32_to_cpu(asc_dvc->icq_sp->carr_pa));
  7446. /*
  7447. * Set-up the RISC->Host Initiator Response Queue (IRQ).
  7448. */
  7449. if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
  7450. asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
  7451. return ADV_ERROR;
  7452. }
  7453. asc_dvc->carr_freelist = (ADV_CARR_T *)
  7454. ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
  7455. /*
  7456. * The first command completed by the RISC will be placed in
  7457. * the stopper.
  7458. *
  7459. * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
  7460. * completed the RISC will set the ASC_RQ_STOPPER bit.
  7461. */
  7462. asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
  7463. /*
  7464. * Set RISC IRQ physical address start value.
  7465. */
  7466. AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
  7467. asc_dvc->carr_pending_cnt = 0;
  7468. AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
  7469. (ADV_INTR_ENABLE_HOST_INTR |
  7470. ADV_INTR_ENABLE_GLOBAL_INTR));
  7471. AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
  7472. AdvWriteWordRegister(iop_base, IOPW_PC, word);
  7473. /* finally, finally, gentlemen, start your engine */
  7474. AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
  7475. /*
  7476. * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
  7477. * Resets should be performed. The RISC has to be running
  7478. * to issue a SCSI Bus Reset.
  7479. */
  7480. if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
  7481. /*
  7482. * If the BIOS Signature is present in memory, restore the
  7483. * per TID microcode operating variables.
  7484. */
  7485. if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
  7486. 0x55AA) {
  7487. /*
  7488. * Restore per TID negotiated values.
  7489. */
  7490. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  7491. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  7492. AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
  7493. AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
  7494. tagqng_able);
  7495. for (tid = 0; tid <= ASC_MAX_TID; tid++) {
  7496. AdvWriteByteLram(iop_base,
  7497. ASC_MC_NUMBER_OF_MAX_CMD + tid,
  7498. max_cmd[tid]);
  7499. }
  7500. } else {
  7501. if (AdvResetSB(asc_dvc) != ADV_TRUE) {
  7502. warn_code = ASC_WARN_BUSRESET_ERROR;
  7503. }
  7504. }
  7505. }
  7506. return warn_code;
  7507. }
  7508. /*
  7509. * Reset chip and SCSI Bus.
  7510. *
  7511. * Return Value:
  7512. * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
  7513. * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
  7514. */
  7515. static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
  7516. {
  7517. int status;
  7518. ushort wdtr_able, sdtr_able, tagqng_able;
  7519. ushort ppr_able = 0;
  7520. uchar tid, max_cmd[ADV_MAX_TID + 1];
  7521. AdvPortAddr iop_base;
  7522. ushort bios_sig;
  7523. iop_base = asc_dvc->iop_base;
  7524. /*
  7525. * Save current per TID negotiated values.
  7526. */
  7527. AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  7528. AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  7529. if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
  7530. AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
  7531. }
  7532. AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
  7533. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  7534. AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
  7535. max_cmd[tid]);
  7536. }
  7537. /*
  7538. * Force the AdvInitAsc3550/38C0800Driver() function to
  7539. * perform a SCSI Bus Reset by clearing the BIOS signature word.
  7540. * The initialization functions assumes a SCSI Bus Reset is not
  7541. * needed if the BIOS signature word is present.
  7542. */
  7543. AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
  7544. AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
  7545. /*
  7546. * Stop chip and reset it.
  7547. */
  7548. AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
  7549. AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
  7550. mdelay(100);
  7551. AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
  7552. ADV_CTRL_REG_CMD_WR_IO_REG);
  7553. /*
  7554. * Reset Adv Library error code, if any, and try
  7555. * re-initializing the chip.
  7556. */
  7557. asc_dvc->err_code = 0;
  7558. if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
  7559. status = AdvInitAsc38C1600Driver(asc_dvc);
  7560. } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
  7561. status = AdvInitAsc38C0800Driver(asc_dvc);
  7562. } else {
  7563. status = AdvInitAsc3550Driver(asc_dvc);
  7564. }
  7565. /* Translate initialization return value to status value. */
  7566. if (status == 0) {
  7567. status = ADV_TRUE;
  7568. } else {
  7569. status = ADV_FALSE;
  7570. }
  7571. /*
  7572. * Restore the BIOS signature word.
  7573. */
  7574. AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
  7575. /*
  7576. * Restore per TID negotiated values.
  7577. */
  7578. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
  7579. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
  7580. if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
  7581. AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
  7582. }
  7583. AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
  7584. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  7585. AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
  7586. max_cmd[tid]);
  7587. }
  7588. return status;
  7589. }
  7590. /*
  7591. * adv_async_callback() - Adv Library asynchronous event callback function.
  7592. */
  7593. static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
  7594. {
  7595. switch (code) {
  7596. case ADV_ASYNC_SCSI_BUS_RESET_DET:
  7597. /*
  7598. * The firmware detected a SCSI Bus reset.
  7599. */
  7600. ASC_DBG(0,
  7601. "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
  7602. break;
  7603. case ADV_ASYNC_RDMA_FAILURE:
  7604. /*
  7605. * Handle RDMA failure by resetting the SCSI Bus and
  7606. * possibly the chip if it is unresponsive. Log the error
  7607. * with a unique code.
  7608. */
  7609. ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
  7610. AdvResetChipAndSB(adv_dvc_varp);
  7611. break;
  7612. case ADV_HOST_SCSI_BUS_RESET:
  7613. /*
  7614. * Host generated SCSI bus reset occurred.
  7615. */
  7616. ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
  7617. break;
  7618. default:
  7619. ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
  7620. break;
  7621. }
  7622. }
  7623. /*
  7624. * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
  7625. *
  7626. * Callback function for the Wide SCSI Adv Library.
  7627. */
  7628. static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
  7629. {
  7630. struct asc_board *boardp;
  7631. adv_req_t *reqp;
  7632. adv_sgblk_t *sgblkp;
  7633. struct scsi_cmnd *scp;
  7634. struct Scsi_Host *shost;
  7635. ADV_DCNT resid_cnt;
  7636. ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
  7637. (ulong)adv_dvc_varp, (ulong)scsiqp);
  7638. ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
  7639. /*
  7640. * Get the adv_req_t structure for the command that has been
  7641. * completed. The adv_req_t structure actually contains the
  7642. * completed ADV_SCSI_REQ_Q structure.
  7643. */
  7644. reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
  7645. ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp);
  7646. if (reqp == NULL) {
  7647. ASC_PRINT("adv_isr_callback: reqp is NULL\n");
  7648. return;
  7649. }
  7650. /*
  7651. * Get the struct scsi_cmnd structure and Scsi_Host structure for the
  7652. * command that has been completed.
  7653. *
  7654. * Note: The adv_req_t request structure and adv_sgblk_t structure,
  7655. * if any, are dropped, because a board structure pointer can not be
  7656. * determined.
  7657. */
  7658. scp = reqp->cmndp;
  7659. ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp);
  7660. if (scp == NULL) {
  7661. ASC_PRINT
  7662. ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
  7663. return;
  7664. }
  7665. ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
  7666. shost = scp->device->host;
  7667. ASC_STATS(shost, callback);
  7668. ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost);
  7669. boardp = shost_priv(shost);
  7670. BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
  7671. /*
  7672. * 'done_status' contains the command's ending status.
  7673. */
  7674. switch (scsiqp->done_status) {
  7675. case QD_NO_ERROR:
  7676. ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
  7677. scp->result = 0;
  7678. /*
  7679. * Check for an underrun condition.
  7680. *
  7681. * If there was no error and an underrun condition, then
  7682. * then return the number of underrun bytes.
  7683. */
  7684. resid_cnt = le32_to_cpu(scsiqp->data_cnt);
  7685. if (scp->request_bufflen != 0 && resid_cnt != 0 &&
  7686. resid_cnt <= scp->request_bufflen) {
  7687. ASC_DBG1(1,
  7688. "adv_isr_callback: underrun condition %lu bytes\n",
  7689. (ulong)resid_cnt);
  7690. scp->resid = resid_cnt;
  7691. }
  7692. break;
  7693. case QD_WITH_ERROR:
  7694. ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
  7695. switch (scsiqp->host_status) {
  7696. case QHSTA_NO_ERROR:
  7697. if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
  7698. ASC_DBG(2,
  7699. "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
  7700. ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
  7701. sizeof(scp->sense_buffer));
  7702. /*
  7703. * Note: The 'status_byte()' macro used by
  7704. * target drivers defined in scsi.h shifts the
  7705. * status byte returned by host drivers right
  7706. * by 1 bit. This is why target drivers also
  7707. * use right shifted status byte definitions.
  7708. * For instance target drivers use
  7709. * CHECK_CONDITION, defined to 0x1, instead of
  7710. * the SCSI defined check condition value of
  7711. * 0x2. Host drivers are supposed to return
  7712. * the status byte as it is defined by SCSI.
  7713. */
  7714. scp->result = DRIVER_BYTE(DRIVER_SENSE) |
  7715. STATUS_BYTE(scsiqp->scsi_status);
  7716. } else {
  7717. scp->result = STATUS_BYTE(scsiqp->scsi_status);
  7718. }
  7719. break;
  7720. default:
  7721. /* Some other QHSTA error occurred. */
  7722. ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
  7723. scsiqp->host_status);
  7724. scp->result = HOST_BYTE(DID_BAD_TARGET);
  7725. break;
  7726. }
  7727. break;
  7728. case QD_ABORTED_BY_HOST:
  7729. ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
  7730. scp->result =
  7731. HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
  7732. break;
  7733. default:
  7734. ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n",
  7735. scsiqp->done_status);
  7736. scp->result =
  7737. HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
  7738. break;
  7739. }
  7740. /*
  7741. * If the 'init_tidmask' bit isn't already set for the target and the
  7742. * current request finished normally, then set the bit for the target
  7743. * to indicate that a device is present.
  7744. */
  7745. if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
  7746. scsiqp->done_status == QD_NO_ERROR &&
  7747. scsiqp->host_status == QHSTA_NO_ERROR) {
  7748. boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
  7749. }
  7750. asc_scsi_done(scp);
  7751. /*
  7752. * Free all 'adv_sgblk_t' structures allocated for the request.
  7753. */
  7754. while ((sgblkp = reqp->sgblkp) != NULL) {
  7755. /* Remove 'sgblkp' from the request list. */
  7756. reqp->sgblkp = sgblkp->next_sgblkp;
  7757. /* Add 'sgblkp' to the board free list. */
  7758. sgblkp->next_sgblkp = boardp->adv_sgblkp;
  7759. boardp->adv_sgblkp = sgblkp;
  7760. }
  7761. /*
  7762. * Free the adv_req_t structure used with the command by adding
  7763. * it back to the board free list.
  7764. */
  7765. reqp->next_reqp = boardp->adv_reqp;
  7766. boardp->adv_reqp = reqp;
  7767. ASC_DBG(1, "adv_isr_callback: done\n");
  7768. return;
  7769. }
  7770. /*
  7771. * Adv Library Interrupt Service Routine
  7772. *
  7773. * This function is called by a driver's interrupt service routine.
  7774. * The function disables and re-enables interrupts.
  7775. *
  7776. * When a microcode idle command is completed, the ADV_DVC_VAR
  7777. * 'idle_cmd_done' field is set to ADV_TRUE.
  7778. *
  7779. * Note: AdvISR() can be called when interrupts are disabled or even
  7780. * when there is no hardware interrupt condition present. It will
  7781. * always check for completed idle commands and microcode requests.
  7782. * This is an important feature that shouldn't be changed because it
  7783. * allows commands to be completed from polling mode loops.
  7784. *
  7785. * Return:
  7786. * ADV_TRUE(1) - interrupt was pending
  7787. * ADV_FALSE(0) - no interrupt was pending
  7788. */
  7789. static int AdvISR(ADV_DVC_VAR *asc_dvc)
  7790. {
  7791. AdvPortAddr iop_base;
  7792. uchar int_stat;
  7793. ushort target_bit;
  7794. ADV_CARR_T *free_carrp;
  7795. ADV_VADDR irq_next_vpa;
  7796. ADV_SCSI_REQ_Q *scsiq;
  7797. iop_base = asc_dvc->iop_base;
  7798. /* Reading the register clears the interrupt. */
  7799. int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
  7800. if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
  7801. ADV_INTR_STATUS_INTRC)) == 0) {
  7802. return ADV_FALSE;
  7803. }
  7804. /*
  7805. * Notify the driver of an asynchronous microcode condition by
  7806. * calling the adv_async_callback function. The function
  7807. * is passed the microcode ASC_MC_INTRB_CODE byte value.
  7808. */
  7809. if (int_stat & ADV_INTR_STATUS_INTRB) {
  7810. uchar intrb_code;
  7811. AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
  7812. if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
  7813. asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
  7814. if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
  7815. asc_dvc->carr_pending_cnt != 0) {
  7816. AdvWriteByteRegister(iop_base, IOPB_TICKLE,
  7817. ADV_TICKLE_A);
  7818. if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
  7819. AdvWriteByteRegister(iop_base,
  7820. IOPB_TICKLE,
  7821. ADV_TICKLE_NOP);
  7822. }
  7823. }
  7824. }
  7825. adv_async_callback(asc_dvc, intrb_code);
  7826. }
  7827. /*
  7828. * Check if the IRQ stopper carrier contains a completed request.
  7829. */
  7830. while (((irq_next_vpa =
  7831. le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
  7832. /*
  7833. * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
  7834. * The RISC will have set 'areq_vpa' to a virtual address.
  7835. *
  7836. * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
  7837. * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
  7838. * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
  7839. * in AdvExeScsiQueue().
  7840. */
  7841. scsiq = (ADV_SCSI_REQ_Q *)
  7842. ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
  7843. /*
  7844. * Request finished with good status and the queue was not
  7845. * DMAed to host memory by the firmware. Set all status fields
  7846. * to indicate good status.
  7847. */
  7848. if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
  7849. scsiq->done_status = QD_NO_ERROR;
  7850. scsiq->host_status = scsiq->scsi_status = 0;
  7851. scsiq->data_cnt = 0L;
  7852. }
  7853. /*
  7854. * Advance the stopper pointer to the next carrier
  7855. * ignoring the lower four bits. Free the previous
  7856. * stopper carrier.
  7857. */
  7858. free_carrp = asc_dvc->irq_sp;
  7859. asc_dvc->irq_sp = (ADV_CARR_T *)
  7860. ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
  7861. free_carrp->next_vpa =
  7862. cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
  7863. asc_dvc->carr_freelist = free_carrp;
  7864. asc_dvc->carr_pending_cnt--;
  7865. target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
  7866. /*
  7867. * Clear request microcode control flag.
  7868. */
  7869. scsiq->cntl = 0;
  7870. /*
  7871. * Notify the driver of the completed request by passing
  7872. * the ADV_SCSI_REQ_Q pointer to its callback function.
  7873. */
  7874. scsiq->a_flag |= ADV_SCSIQ_DONE;
  7875. adv_isr_callback(asc_dvc, scsiq);
  7876. /*
  7877. * Note: After the driver callback function is called, 'scsiq'
  7878. * can no longer be referenced.
  7879. *
  7880. * Fall through and continue processing other completed
  7881. * requests...
  7882. */
  7883. }
  7884. return ADV_TRUE;
  7885. }
  7886. static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
  7887. {
  7888. if (asc_dvc->err_code == 0) {
  7889. asc_dvc->err_code = err_code;
  7890. AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
  7891. err_code);
  7892. }
  7893. return err_code;
  7894. }
  7895. static void AscAckInterrupt(PortAddr iop_base)
  7896. {
  7897. uchar host_flag;
  7898. uchar risc_flag;
  7899. ushort loop;
  7900. loop = 0;
  7901. do {
  7902. risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
  7903. if (loop++ > 0x7FFF) {
  7904. break;
  7905. }
  7906. } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
  7907. host_flag =
  7908. AscReadLramByte(iop_base,
  7909. ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
  7910. AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
  7911. (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
  7912. AscSetChipStatus(iop_base, CIW_INT_ACK);
  7913. loop = 0;
  7914. while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
  7915. AscSetChipStatus(iop_base, CIW_INT_ACK);
  7916. if (loop++ > 3) {
  7917. break;
  7918. }
  7919. }
  7920. AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
  7921. return;
  7922. }
  7923. static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
  7924. {
  7925. uchar *period_table;
  7926. int max_index;
  7927. int min_index;
  7928. int i;
  7929. period_table = asc_dvc->sdtr_period_tbl;
  7930. max_index = (int)asc_dvc->max_sdtr_index;
  7931. min_index = (int)asc_dvc->host_init_sdtr_index;
  7932. if ((syn_time <= period_table[max_index])) {
  7933. for (i = min_index; i < (max_index - 1); i++) {
  7934. if (syn_time <= period_table[i]) {
  7935. return (uchar)i;
  7936. }
  7937. }
  7938. return (uchar)max_index;
  7939. } else {
  7940. return (uchar)(max_index + 1);
  7941. }
  7942. }
  7943. static uchar
  7944. AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
  7945. {
  7946. EXT_MSG sdtr_buf;
  7947. uchar sdtr_period_index;
  7948. PortAddr iop_base;
  7949. iop_base = asc_dvc->iop_base;
  7950. sdtr_buf.msg_type = EXTENDED_MESSAGE;
  7951. sdtr_buf.msg_len = MS_SDTR_LEN;
  7952. sdtr_buf.msg_req = EXTENDED_SDTR;
  7953. sdtr_buf.xfer_period = sdtr_period;
  7954. sdtr_offset &= ASC_SYN_MAX_OFFSET;
  7955. sdtr_buf.req_ack_offset = sdtr_offset;
  7956. sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
  7957. if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
  7958. AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
  7959. (uchar *)&sdtr_buf,
  7960. sizeof(EXT_MSG) >> 1);
  7961. return ((sdtr_period_index << 4) | sdtr_offset);
  7962. } else {
  7963. sdtr_buf.req_ack_offset = 0;
  7964. AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
  7965. (uchar *)&sdtr_buf,
  7966. sizeof(EXT_MSG) >> 1);
  7967. return 0;
  7968. }
  7969. }
  7970. static uchar
  7971. AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
  7972. {
  7973. uchar byte;
  7974. uchar sdtr_period_ix;
  7975. sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
  7976. if (sdtr_period_ix > asc_dvc->max_sdtr_index) {
  7977. return 0xFF;
  7978. }
  7979. byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
  7980. return byte;
  7981. }
  7982. static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
  7983. {
  7984. ASC_SCSI_BIT_ID_TYPE org_id;
  7985. int i;
  7986. int sta = TRUE;
  7987. AscSetBank(iop_base, 1);
  7988. org_id = AscReadChipDvcID(iop_base);
  7989. for (i = 0; i <= ASC_MAX_TID; i++) {
  7990. if (org_id == (0x01 << i))
  7991. break;
  7992. }
  7993. org_id = (ASC_SCSI_BIT_ID_TYPE) i;
  7994. AscWriteChipDvcID(iop_base, id);
  7995. if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
  7996. AscSetBank(iop_base, 0);
  7997. AscSetChipSyn(iop_base, sdtr_data);
  7998. if (AscGetChipSyn(iop_base) != sdtr_data) {
  7999. sta = FALSE;
  8000. }
  8001. } else {
  8002. sta = FALSE;
  8003. }
  8004. AscSetBank(iop_base, 1);
  8005. AscWriteChipDvcID(iop_base, org_id);
  8006. AscSetBank(iop_base, 0);
  8007. return (sta);
  8008. }
  8009. static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
  8010. {
  8011. AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
  8012. AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
  8013. }
  8014. static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
  8015. {
  8016. EXT_MSG ext_msg;
  8017. EXT_MSG out_msg;
  8018. ushort halt_q_addr;
  8019. int sdtr_accept;
  8020. ushort int_halt_code;
  8021. ASC_SCSI_BIT_ID_TYPE scsi_busy;
  8022. ASC_SCSI_BIT_ID_TYPE target_id;
  8023. PortAddr iop_base;
  8024. uchar tag_code;
  8025. uchar q_status;
  8026. uchar halt_qp;
  8027. uchar sdtr_data;
  8028. uchar target_ix;
  8029. uchar q_cntl, tid_no;
  8030. uchar cur_dvc_qng;
  8031. uchar asyn_sdtr;
  8032. uchar scsi_status;
  8033. struct asc_board *boardp;
  8034. BUG_ON(!asc_dvc->drv_ptr);
  8035. boardp = asc_dvc->drv_ptr;
  8036. iop_base = asc_dvc->iop_base;
  8037. int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
  8038. halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
  8039. halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
  8040. target_ix = AscReadLramByte(iop_base,
  8041. (ushort)(halt_q_addr +
  8042. (ushort)ASC_SCSIQ_B_TARGET_IX));
  8043. q_cntl = AscReadLramByte(iop_base,
  8044. (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
  8045. tid_no = ASC_TIX_TO_TID(target_ix);
  8046. target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
  8047. if (asc_dvc->pci_fix_asyn_xfer & target_id) {
  8048. asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
  8049. } else {
  8050. asyn_sdtr = 0;
  8051. }
  8052. if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
  8053. if (asc_dvc->pci_fix_asyn_xfer & target_id) {
  8054. AscSetChipSDTR(iop_base, 0, tid_no);
  8055. boardp->sdtr_data[tid_no] = 0;
  8056. }
  8057. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8058. return (0);
  8059. } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
  8060. if (asc_dvc->pci_fix_asyn_xfer & target_id) {
  8061. AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
  8062. boardp->sdtr_data[tid_no] = asyn_sdtr;
  8063. }
  8064. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8065. return (0);
  8066. } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
  8067. AscMemWordCopyPtrFromLram(iop_base,
  8068. ASCV_MSGIN_BEG,
  8069. (uchar *)&ext_msg,
  8070. sizeof(EXT_MSG) >> 1);
  8071. if (ext_msg.msg_type == EXTENDED_MESSAGE &&
  8072. ext_msg.msg_req == EXTENDED_SDTR &&
  8073. ext_msg.msg_len == MS_SDTR_LEN) {
  8074. sdtr_accept = TRUE;
  8075. if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
  8076. sdtr_accept = FALSE;
  8077. ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
  8078. }
  8079. if ((ext_msg.xfer_period <
  8080. asc_dvc->sdtr_period_tbl[asc_dvc->
  8081. host_init_sdtr_index])
  8082. || (ext_msg.xfer_period >
  8083. asc_dvc->sdtr_period_tbl[asc_dvc->
  8084. max_sdtr_index])) {
  8085. sdtr_accept = FALSE;
  8086. ext_msg.xfer_period =
  8087. asc_dvc->sdtr_period_tbl[asc_dvc->
  8088. host_init_sdtr_index];
  8089. }
  8090. if (sdtr_accept) {
  8091. sdtr_data =
  8092. AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
  8093. ext_msg.req_ack_offset);
  8094. if ((sdtr_data == 0xFF)) {
  8095. q_cntl |= QC_MSG_OUT;
  8096. asc_dvc->init_sdtr &= ~target_id;
  8097. asc_dvc->sdtr_done &= ~target_id;
  8098. AscSetChipSDTR(iop_base, asyn_sdtr,
  8099. tid_no);
  8100. boardp->sdtr_data[tid_no] = asyn_sdtr;
  8101. }
  8102. }
  8103. if (ext_msg.req_ack_offset == 0) {
  8104. q_cntl &= ~QC_MSG_OUT;
  8105. asc_dvc->init_sdtr &= ~target_id;
  8106. asc_dvc->sdtr_done &= ~target_id;
  8107. AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
  8108. } else {
  8109. if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
  8110. q_cntl &= ~QC_MSG_OUT;
  8111. asc_dvc->sdtr_done |= target_id;
  8112. asc_dvc->init_sdtr |= target_id;
  8113. asc_dvc->pci_fix_asyn_xfer &=
  8114. ~target_id;
  8115. sdtr_data =
  8116. AscCalSDTRData(asc_dvc,
  8117. ext_msg.xfer_period,
  8118. ext_msg.
  8119. req_ack_offset);
  8120. AscSetChipSDTR(iop_base, sdtr_data,
  8121. tid_no);
  8122. boardp->sdtr_data[tid_no] = sdtr_data;
  8123. } else {
  8124. q_cntl |= QC_MSG_OUT;
  8125. AscMsgOutSDTR(asc_dvc,
  8126. ext_msg.xfer_period,
  8127. ext_msg.req_ack_offset);
  8128. asc_dvc->pci_fix_asyn_xfer &=
  8129. ~target_id;
  8130. sdtr_data =
  8131. AscCalSDTRData(asc_dvc,
  8132. ext_msg.xfer_period,
  8133. ext_msg.
  8134. req_ack_offset);
  8135. AscSetChipSDTR(iop_base, sdtr_data,
  8136. tid_no);
  8137. boardp->sdtr_data[tid_no] = sdtr_data;
  8138. asc_dvc->sdtr_done |= target_id;
  8139. asc_dvc->init_sdtr |= target_id;
  8140. }
  8141. }
  8142. AscWriteLramByte(iop_base,
  8143. (ushort)(halt_q_addr +
  8144. (ushort)ASC_SCSIQ_B_CNTL),
  8145. q_cntl);
  8146. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8147. return (0);
  8148. } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
  8149. ext_msg.msg_req == EXTENDED_WDTR &&
  8150. ext_msg.msg_len == MS_WDTR_LEN) {
  8151. ext_msg.wdtr_width = 0;
  8152. AscMemWordCopyPtrToLram(iop_base,
  8153. ASCV_MSGOUT_BEG,
  8154. (uchar *)&ext_msg,
  8155. sizeof(EXT_MSG) >> 1);
  8156. q_cntl |= QC_MSG_OUT;
  8157. AscWriteLramByte(iop_base,
  8158. (ushort)(halt_q_addr +
  8159. (ushort)ASC_SCSIQ_B_CNTL),
  8160. q_cntl);
  8161. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8162. return (0);
  8163. } else {
  8164. ext_msg.msg_type = MESSAGE_REJECT;
  8165. AscMemWordCopyPtrToLram(iop_base,
  8166. ASCV_MSGOUT_BEG,
  8167. (uchar *)&ext_msg,
  8168. sizeof(EXT_MSG) >> 1);
  8169. q_cntl |= QC_MSG_OUT;
  8170. AscWriteLramByte(iop_base,
  8171. (ushort)(halt_q_addr +
  8172. (ushort)ASC_SCSIQ_B_CNTL),
  8173. q_cntl);
  8174. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8175. return (0);
  8176. }
  8177. } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
  8178. q_cntl |= QC_REQ_SENSE;
  8179. if ((asc_dvc->init_sdtr & target_id) != 0) {
  8180. asc_dvc->sdtr_done &= ~target_id;
  8181. sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
  8182. q_cntl |= QC_MSG_OUT;
  8183. AscMsgOutSDTR(asc_dvc,
  8184. asc_dvc->
  8185. sdtr_period_tbl[(sdtr_data >> 4) &
  8186. (uchar)(asc_dvc->
  8187. max_sdtr_index -
  8188. 1)],
  8189. (uchar)(sdtr_data & (uchar)
  8190. ASC_SYN_MAX_OFFSET));
  8191. }
  8192. AscWriteLramByte(iop_base,
  8193. (ushort)(halt_q_addr +
  8194. (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
  8195. tag_code = AscReadLramByte(iop_base,
  8196. (ushort)(halt_q_addr + (ushort)
  8197. ASC_SCSIQ_B_TAG_CODE));
  8198. tag_code &= 0xDC;
  8199. if ((asc_dvc->pci_fix_asyn_xfer & target_id)
  8200. && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
  8201. ) {
  8202. tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
  8203. | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
  8204. }
  8205. AscWriteLramByte(iop_base,
  8206. (ushort)(halt_q_addr +
  8207. (ushort)ASC_SCSIQ_B_TAG_CODE),
  8208. tag_code);
  8209. q_status = AscReadLramByte(iop_base,
  8210. (ushort)(halt_q_addr + (ushort)
  8211. ASC_SCSIQ_B_STATUS));
  8212. q_status |= (QS_READY | QS_BUSY);
  8213. AscWriteLramByte(iop_base,
  8214. (ushort)(halt_q_addr +
  8215. (ushort)ASC_SCSIQ_B_STATUS),
  8216. q_status);
  8217. scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
  8218. scsi_busy &= ~target_id;
  8219. AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
  8220. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8221. return (0);
  8222. } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
  8223. AscMemWordCopyPtrFromLram(iop_base,
  8224. ASCV_MSGOUT_BEG,
  8225. (uchar *)&out_msg,
  8226. sizeof(EXT_MSG) >> 1);
  8227. if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
  8228. (out_msg.msg_len == MS_SDTR_LEN) &&
  8229. (out_msg.msg_req == EXTENDED_SDTR)) {
  8230. asc_dvc->init_sdtr &= ~target_id;
  8231. asc_dvc->sdtr_done &= ~target_id;
  8232. AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
  8233. boardp->sdtr_data[tid_no] = asyn_sdtr;
  8234. }
  8235. q_cntl &= ~QC_MSG_OUT;
  8236. AscWriteLramByte(iop_base,
  8237. (ushort)(halt_q_addr +
  8238. (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
  8239. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8240. return (0);
  8241. } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
  8242. scsi_status = AscReadLramByte(iop_base,
  8243. (ushort)((ushort)halt_q_addr +
  8244. (ushort)
  8245. ASC_SCSIQ_SCSI_STATUS));
  8246. cur_dvc_qng =
  8247. AscReadLramByte(iop_base,
  8248. (ushort)((ushort)ASC_QADR_BEG +
  8249. (ushort)target_ix));
  8250. if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
  8251. scsi_busy = AscReadLramByte(iop_base,
  8252. (ushort)ASCV_SCSIBUSY_B);
  8253. scsi_busy |= target_id;
  8254. AscWriteLramByte(iop_base,
  8255. (ushort)ASCV_SCSIBUSY_B, scsi_busy);
  8256. asc_dvc->queue_full_or_busy |= target_id;
  8257. if (scsi_status == SAM_STAT_TASK_SET_FULL) {
  8258. if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
  8259. cur_dvc_qng -= 1;
  8260. asc_dvc->max_dvc_qng[tid_no] =
  8261. cur_dvc_qng;
  8262. AscWriteLramByte(iop_base,
  8263. (ushort)((ushort)
  8264. ASCV_MAX_DVC_QNG_BEG
  8265. + (ushort)
  8266. tid_no),
  8267. cur_dvc_qng);
  8268. /*
  8269. * Set the device queue depth to the
  8270. * number of active requests when the
  8271. * QUEUE FULL condition was encountered.
  8272. */
  8273. boardp->queue_full |= target_id;
  8274. boardp->queue_full_cnt[tid_no] =
  8275. cur_dvc_qng;
  8276. }
  8277. }
  8278. }
  8279. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8280. return (0);
  8281. }
  8282. #if CC_VERY_LONG_SG_LIST
  8283. else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
  8284. uchar q_no;
  8285. ushort q_addr;
  8286. uchar sg_wk_q_no;
  8287. uchar first_sg_wk_q_no;
  8288. ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
  8289. ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
  8290. ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
  8291. ushort sg_list_dwords;
  8292. ushort sg_entry_cnt;
  8293. uchar next_qp;
  8294. int i;
  8295. q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
  8296. if (q_no == ASC_QLINK_END)
  8297. return 0;
  8298. q_addr = ASC_QNO_TO_QADDR(q_no);
  8299. /*
  8300. * Convert the request's SRB pointer to a host ASC_SCSI_REQ
  8301. * structure pointer using a macro provided by the driver.
  8302. * The ASC_SCSI_REQ pointer provides a pointer to the
  8303. * host ASC_SG_HEAD structure.
  8304. */
  8305. /* Read request's SRB pointer. */
  8306. scsiq = (ASC_SCSI_Q *)
  8307. ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
  8308. (ushort)
  8309. (q_addr +
  8310. ASC_SCSIQ_D_SRBPTR))));
  8311. /*
  8312. * Get request's first and working SG queue.
  8313. */
  8314. sg_wk_q_no = AscReadLramByte(iop_base,
  8315. (ushort)(q_addr +
  8316. ASC_SCSIQ_B_SG_WK_QP));
  8317. first_sg_wk_q_no = AscReadLramByte(iop_base,
  8318. (ushort)(q_addr +
  8319. ASC_SCSIQ_B_FIRST_SG_WK_QP));
  8320. /*
  8321. * Reset request's working SG queue back to the
  8322. * first SG queue.
  8323. */
  8324. AscWriteLramByte(iop_base,
  8325. (ushort)(q_addr +
  8326. (ushort)ASC_SCSIQ_B_SG_WK_QP),
  8327. first_sg_wk_q_no);
  8328. sg_head = scsiq->sg_head;
  8329. /*
  8330. * Set sg_entry_cnt to the number of SG elements
  8331. * that will be completed on this interrupt.
  8332. *
  8333. * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
  8334. * SG elements. The data_cnt and data_addr fields which
  8335. * add 1 to the SG element capacity are not used when
  8336. * restarting SG handling after a halt.
  8337. */
  8338. if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
  8339. sg_entry_cnt = ASC_MAX_SG_LIST - 1;
  8340. /*
  8341. * Keep track of remaining number of SG elements that
  8342. * will need to be handled on the next interrupt.
  8343. */
  8344. scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
  8345. } else {
  8346. sg_entry_cnt = scsiq->remain_sg_entry_cnt;
  8347. scsiq->remain_sg_entry_cnt = 0;
  8348. }
  8349. /*
  8350. * Copy SG elements into the list of allocated SG queues.
  8351. *
  8352. * Last index completed is saved in scsiq->next_sg_index.
  8353. */
  8354. next_qp = first_sg_wk_q_no;
  8355. q_addr = ASC_QNO_TO_QADDR(next_qp);
  8356. scsi_sg_q.sg_head_qp = q_no;
  8357. scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
  8358. for (i = 0; i < sg_head->queue_cnt; i++) {
  8359. scsi_sg_q.seq_no = i + 1;
  8360. if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
  8361. sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
  8362. sg_entry_cnt -= ASC_SG_LIST_PER_Q;
  8363. /*
  8364. * After very first SG queue RISC FW uses next
  8365. * SG queue first element then checks sg_list_cnt
  8366. * against zero and then decrements, so set
  8367. * sg_list_cnt 1 less than number of SG elements
  8368. * in each SG queue.
  8369. */
  8370. scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
  8371. scsi_sg_q.sg_cur_list_cnt =
  8372. ASC_SG_LIST_PER_Q - 1;
  8373. } else {
  8374. /*
  8375. * This is the last SG queue in the list of
  8376. * allocated SG queues. If there are more
  8377. * SG elements than will fit in the allocated
  8378. * queues, then set the QCSG_SG_XFER_MORE flag.
  8379. */
  8380. if (scsiq->remain_sg_entry_cnt != 0) {
  8381. scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
  8382. } else {
  8383. scsi_sg_q.cntl |= QCSG_SG_XFER_END;
  8384. }
  8385. /* equals sg_entry_cnt * 2 */
  8386. sg_list_dwords = sg_entry_cnt << 1;
  8387. scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
  8388. scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
  8389. sg_entry_cnt = 0;
  8390. }
  8391. scsi_sg_q.q_no = next_qp;
  8392. AscMemWordCopyPtrToLram(iop_base,
  8393. q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
  8394. (uchar *)&scsi_sg_q,
  8395. sizeof(ASC_SG_LIST_Q) >> 1);
  8396. AscMemDWordCopyPtrToLram(iop_base,
  8397. q_addr + ASC_SGQ_LIST_BEG,
  8398. (uchar *)&sg_head->
  8399. sg_list[scsiq->next_sg_index],
  8400. sg_list_dwords);
  8401. scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
  8402. /*
  8403. * If the just completed SG queue contained the
  8404. * last SG element, then no more SG queues need
  8405. * to be written.
  8406. */
  8407. if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
  8408. break;
  8409. }
  8410. next_qp = AscReadLramByte(iop_base,
  8411. (ushort)(q_addr +
  8412. ASC_SCSIQ_B_FWD));
  8413. q_addr = ASC_QNO_TO_QADDR(next_qp);
  8414. }
  8415. /*
  8416. * Clear the halt condition so the RISC will be restarted
  8417. * after the return.
  8418. */
  8419. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
  8420. return (0);
  8421. }
  8422. #endif /* CC_VERY_LONG_SG_LIST */
  8423. return (0);
  8424. }
  8425. /*
  8426. * void
  8427. * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
  8428. *
  8429. * Calling/Exit State:
  8430. * none
  8431. *
  8432. * Description:
  8433. * Input an ASC_QDONE_INFO structure from the chip
  8434. */
  8435. static void
  8436. DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
  8437. {
  8438. int i;
  8439. ushort word;
  8440. AscSetChipLramAddr(iop_base, s_addr);
  8441. for (i = 0; i < 2 * words; i += 2) {
  8442. if (i == 10) {
  8443. continue;
  8444. }
  8445. word = inpw(iop_base + IOP_RAM_DATA);
  8446. inbuf[i] = word & 0xff;
  8447. inbuf[i + 1] = (word >> 8) & 0xff;
  8448. }
  8449. ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
  8450. }
  8451. static uchar
  8452. _AscCopyLramScsiDoneQ(PortAddr iop_base,
  8453. ushort q_addr,
  8454. ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
  8455. {
  8456. ushort _val;
  8457. uchar sg_queue_cnt;
  8458. DvcGetQinfo(iop_base,
  8459. q_addr + ASC_SCSIQ_DONE_INFO_BEG,
  8460. (uchar *)scsiq,
  8461. (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
  8462. _val = AscReadLramWord(iop_base,
  8463. (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
  8464. scsiq->q_status = (uchar)_val;
  8465. scsiq->q_no = (uchar)(_val >> 8);
  8466. _val = AscReadLramWord(iop_base,
  8467. (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
  8468. scsiq->cntl = (uchar)_val;
  8469. sg_queue_cnt = (uchar)(_val >> 8);
  8470. _val = AscReadLramWord(iop_base,
  8471. (ushort)(q_addr +
  8472. (ushort)ASC_SCSIQ_B_SENSE_LEN));
  8473. scsiq->sense_len = (uchar)_val;
  8474. scsiq->extra_bytes = (uchar)(_val >> 8);
  8475. /*
  8476. * Read high word of remain bytes from alternate location.
  8477. */
  8478. scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
  8479. (ushort)(q_addr +
  8480. (ushort)
  8481. ASC_SCSIQ_W_ALT_DC1)))
  8482. << 16);
  8483. /*
  8484. * Read low word of remain bytes from original location.
  8485. */
  8486. scsiq->remain_bytes += AscReadLramWord(iop_base,
  8487. (ushort)(q_addr + (ushort)
  8488. ASC_SCSIQ_DW_REMAIN_XFER_CNT));
  8489. scsiq->remain_bytes &= max_dma_count;
  8490. return sg_queue_cnt;
  8491. }
  8492. /*
  8493. * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
  8494. *
  8495. * Interrupt callback function for the Narrow SCSI Asc Library.
  8496. */
  8497. static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
  8498. {
  8499. struct asc_board *boardp;
  8500. struct scsi_cmnd *scp;
  8501. struct Scsi_Host *shost;
  8502. ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
  8503. (ulong)asc_dvc_varp, (ulong)qdonep);
  8504. ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
  8505. /*
  8506. * Get the struct scsi_cmnd structure and Scsi_Host structure for the
  8507. * command that has been completed.
  8508. */
  8509. scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
  8510. ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp);
  8511. if (scp == NULL) {
  8512. ASC_PRINT("asc_isr_callback: scp is NULL\n");
  8513. return;
  8514. }
  8515. ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
  8516. shost = scp->device->host;
  8517. ASC_STATS(shost, callback);
  8518. ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost);
  8519. boardp = shost_priv(shost);
  8520. BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
  8521. /*
  8522. * 'qdonep' contains the command's ending status.
  8523. */
  8524. switch (qdonep->d3.done_stat) {
  8525. case QD_NO_ERROR:
  8526. ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
  8527. scp->result = 0;
  8528. /*
  8529. * Check for an underrun condition.
  8530. *
  8531. * If there was no error and an underrun condition, then
  8532. * return the number of underrun bytes.
  8533. */
  8534. if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
  8535. qdonep->remain_bytes <= scp->request_bufflen) {
  8536. ASC_DBG1(1,
  8537. "asc_isr_callback: underrun condition %u bytes\n",
  8538. (unsigned)qdonep->remain_bytes);
  8539. scp->resid = qdonep->remain_bytes;
  8540. }
  8541. break;
  8542. case QD_WITH_ERROR:
  8543. ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
  8544. switch (qdonep->d3.host_stat) {
  8545. case QHSTA_NO_ERROR:
  8546. if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
  8547. ASC_DBG(2,
  8548. "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
  8549. ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
  8550. sizeof(scp->sense_buffer));
  8551. /*
  8552. * Note: The 'status_byte()' macro used by
  8553. * target drivers defined in scsi.h shifts the
  8554. * status byte returned by host drivers right
  8555. * by 1 bit. This is why target drivers also
  8556. * use right shifted status byte definitions.
  8557. * For instance target drivers use
  8558. * CHECK_CONDITION, defined to 0x1, instead of
  8559. * the SCSI defined check condition value of
  8560. * 0x2. Host drivers are supposed to return
  8561. * the status byte as it is defined by SCSI.
  8562. */
  8563. scp->result = DRIVER_BYTE(DRIVER_SENSE) |
  8564. STATUS_BYTE(qdonep->d3.scsi_stat);
  8565. } else {
  8566. scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
  8567. }
  8568. break;
  8569. default:
  8570. /* QHSTA error occurred */
  8571. ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
  8572. qdonep->d3.host_stat);
  8573. scp->result = HOST_BYTE(DID_BAD_TARGET);
  8574. break;
  8575. }
  8576. break;
  8577. case QD_ABORTED_BY_HOST:
  8578. ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
  8579. scp->result =
  8580. HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
  8581. scsi_msg) |
  8582. STATUS_BYTE(qdonep->d3.scsi_stat);
  8583. break;
  8584. default:
  8585. ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n",
  8586. qdonep->d3.done_stat);
  8587. scp->result =
  8588. HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
  8589. scsi_msg) |
  8590. STATUS_BYTE(qdonep->d3.scsi_stat);
  8591. break;
  8592. }
  8593. /*
  8594. * If the 'init_tidmask' bit isn't already set for the target and the
  8595. * current request finished normally, then set the bit for the target
  8596. * to indicate that a device is present.
  8597. */
  8598. if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
  8599. qdonep->d3.done_stat == QD_NO_ERROR &&
  8600. qdonep->d3.host_stat == QHSTA_NO_ERROR) {
  8601. boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
  8602. }
  8603. asc_scsi_done(scp);
  8604. return;
  8605. }
  8606. static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
  8607. {
  8608. uchar next_qp;
  8609. uchar n_q_used;
  8610. uchar sg_list_qp;
  8611. uchar sg_queue_cnt;
  8612. uchar q_cnt;
  8613. uchar done_q_tail;
  8614. uchar tid_no;
  8615. ASC_SCSI_BIT_ID_TYPE scsi_busy;
  8616. ASC_SCSI_BIT_ID_TYPE target_id;
  8617. PortAddr iop_base;
  8618. ushort q_addr;
  8619. ushort sg_q_addr;
  8620. uchar cur_target_qng;
  8621. ASC_QDONE_INFO scsiq_buf;
  8622. ASC_QDONE_INFO *scsiq;
  8623. int false_overrun;
  8624. iop_base = asc_dvc->iop_base;
  8625. n_q_used = 1;
  8626. scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
  8627. done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
  8628. q_addr = ASC_QNO_TO_QADDR(done_q_tail);
  8629. next_qp = AscReadLramByte(iop_base,
  8630. (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
  8631. if (next_qp != ASC_QLINK_END) {
  8632. AscPutVarDoneQTail(iop_base, next_qp);
  8633. q_addr = ASC_QNO_TO_QADDR(next_qp);
  8634. sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
  8635. asc_dvc->max_dma_count);
  8636. AscWriteLramByte(iop_base,
  8637. (ushort)(q_addr +
  8638. (ushort)ASC_SCSIQ_B_STATUS),
  8639. (uchar)(scsiq->
  8640. q_status & (uchar)~(QS_READY |
  8641. QS_ABORTED)));
  8642. tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
  8643. target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
  8644. if ((scsiq->cntl & QC_SG_HEAD) != 0) {
  8645. sg_q_addr = q_addr;
  8646. sg_list_qp = next_qp;
  8647. for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
  8648. sg_list_qp = AscReadLramByte(iop_base,
  8649. (ushort)(sg_q_addr
  8650. + (ushort)
  8651. ASC_SCSIQ_B_FWD));
  8652. sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
  8653. if (sg_list_qp == ASC_QLINK_END) {
  8654. AscSetLibErrorCode(asc_dvc,
  8655. ASCQ_ERR_SG_Q_LINKS);
  8656. scsiq->d3.done_stat = QD_WITH_ERROR;
  8657. scsiq->d3.host_stat =
  8658. QHSTA_D_QDONE_SG_LIST_CORRUPTED;
  8659. goto FATAL_ERR_QDONE;
  8660. }
  8661. AscWriteLramByte(iop_base,
  8662. (ushort)(sg_q_addr + (ushort)
  8663. ASC_SCSIQ_B_STATUS),
  8664. QS_FREE);
  8665. }
  8666. n_q_used = sg_queue_cnt + 1;
  8667. AscPutVarDoneQTail(iop_base, sg_list_qp);
  8668. }
  8669. if (asc_dvc->queue_full_or_busy & target_id) {
  8670. cur_target_qng = AscReadLramByte(iop_base,
  8671. (ushort)((ushort)
  8672. ASC_QADR_BEG
  8673. + (ushort)
  8674. scsiq->d2.
  8675. target_ix));
  8676. if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
  8677. scsi_busy = AscReadLramByte(iop_base, (ushort)
  8678. ASCV_SCSIBUSY_B);
  8679. scsi_busy &= ~target_id;
  8680. AscWriteLramByte(iop_base,
  8681. (ushort)ASCV_SCSIBUSY_B,
  8682. scsi_busy);
  8683. asc_dvc->queue_full_or_busy &= ~target_id;
  8684. }
  8685. }
  8686. if (asc_dvc->cur_total_qng >= n_q_used) {
  8687. asc_dvc->cur_total_qng -= n_q_used;
  8688. if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
  8689. asc_dvc->cur_dvc_qng[tid_no]--;
  8690. }
  8691. } else {
  8692. AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
  8693. scsiq->d3.done_stat = QD_WITH_ERROR;
  8694. goto FATAL_ERR_QDONE;
  8695. }
  8696. if ((scsiq->d2.srb_ptr == 0UL) ||
  8697. ((scsiq->q_status & QS_ABORTED) != 0)) {
  8698. return (0x11);
  8699. } else if (scsiq->q_status == QS_DONE) {
  8700. false_overrun = FALSE;
  8701. if (scsiq->extra_bytes != 0) {
  8702. scsiq->remain_bytes +=
  8703. (ADV_DCNT)scsiq->extra_bytes;
  8704. }
  8705. if (scsiq->d3.done_stat == QD_WITH_ERROR) {
  8706. if (scsiq->d3.host_stat ==
  8707. QHSTA_M_DATA_OVER_RUN) {
  8708. if ((scsiq->
  8709. cntl & (QC_DATA_IN | QC_DATA_OUT))
  8710. == 0) {
  8711. scsiq->d3.done_stat =
  8712. QD_NO_ERROR;
  8713. scsiq->d3.host_stat =
  8714. QHSTA_NO_ERROR;
  8715. } else if (false_overrun) {
  8716. scsiq->d3.done_stat =
  8717. QD_NO_ERROR;
  8718. scsiq->d3.host_stat =
  8719. QHSTA_NO_ERROR;
  8720. }
  8721. } else if (scsiq->d3.host_stat ==
  8722. QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
  8723. AscStopChip(iop_base);
  8724. AscSetChipControl(iop_base,
  8725. (uchar)(CC_SCSI_RESET
  8726. | CC_HALT));
  8727. udelay(60);
  8728. AscSetChipControl(iop_base, CC_HALT);
  8729. AscSetChipStatus(iop_base,
  8730. CIW_CLR_SCSI_RESET_INT);
  8731. AscSetChipStatus(iop_base, 0);
  8732. AscSetChipControl(iop_base, 0);
  8733. }
  8734. }
  8735. if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
  8736. asc_isr_callback(asc_dvc, scsiq);
  8737. } else {
  8738. if ((AscReadLramByte(iop_base,
  8739. (ushort)(q_addr + (ushort)
  8740. ASC_SCSIQ_CDB_BEG))
  8741. == START_STOP)) {
  8742. asc_dvc->unit_not_ready &= ~target_id;
  8743. if (scsiq->d3.done_stat != QD_NO_ERROR) {
  8744. asc_dvc->start_motor &=
  8745. ~target_id;
  8746. }
  8747. }
  8748. }
  8749. return (1);
  8750. } else {
  8751. AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
  8752. FATAL_ERR_QDONE:
  8753. if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
  8754. asc_isr_callback(asc_dvc, scsiq);
  8755. }
  8756. return (0x80);
  8757. }
  8758. }
  8759. return (0);
  8760. }
  8761. static int AscISR(ASC_DVC_VAR *asc_dvc)
  8762. {
  8763. ASC_CS_TYPE chipstat;
  8764. PortAddr iop_base;
  8765. ushort saved_ram_addr;
  8766. uchar ctrl_reg;
  8767. uchar saved_ctrl_reg;
  8768. int int_pending;
  8769. int status;
  8770. uchar host_flag;
  8771. iop_base = asc_dvc->iop_base;
  8772. int_pending = FALSE;
  8773. if (AscIsIntPending(iop_base) == 0)
  8774. return int_pending;
  8775. if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
  8776. return ERR;
  8777. }
  8778. if (asc_dvc->in_critical_cnt != 0) {
  8779. AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
  8780. return ERR;
  8781. }
  8782. if (asc_dvc->is_in_int) {
  8783. AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
  8784. return ERR;
  8785. }
  8786. asc_dvc->is_in_int = TRUE;
  8787. ctrl_reg = AscGetChipControl(iop_base);
  8788. saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
  8789. CC_SINGLE_STEP | CC_DIAG | CC_TEST));
  8790. chipstat = AscGetChipStatus(iop_base);
  8791. if (chipstat & CSW_SCSI_RESET_LATCH) {
  8792. if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
  8793. int i = 10;
  8794. int_pending = TRUE;
  8795. asc_dvc->sdtr_done = 0;
  8796. saved_ctrl_reg &= (uchar)(~CC_HALT);
  8797. while ((AscGetChipStatus(iop_base) &
  8798. CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
  8799. mdelay(100);
  8800. }
  8801. AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
  8802. AscSetChipControl(iop_base, CC_HALT);
  8803. AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
  8804. AscSetChipStatus(iop_base, 0);
  8805. chipstat = AscGetChipStatus(iop_base);
  8806. }
  8807. }
  8808. saved_ram_addr = AscGetChipLramAddr(iop_base);
  8809. host_flag = AscReadLramByte(iop_base,
  8810. ASCV_HOST_FLAG_B) &
  8811. (uchar)(~ASC_HOST_FLAG_IN_ISR);
  8812. AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
  8813. (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
  8814. if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
  8815. AscAckInterrupt(iop_base);
  8816. int_pending = TRUE;
  8817. if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
  8818. if (AscIsrChipHalted(asc_dvc) == ERR) {
  8819. goto ISR_REPORT_QDONE_FATAL_ERROR;
  8820. } else {
  8821. saved_ctrl_reg &= (uchar)(~CC_HALT);
  8822. }
  8823. } else {
  8824. ISR_REPORT_QDONE_FATAL_ERROR:
  8825. if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
  8826. while (((status =
  8827. AscIsrQDone(asc_dvc)) & 0x01) != 0) {
  8828. }
  8829. } else {
  8830. do {
  8831. if ((status =
  8832. AscIsrQDone(asc_dvc)) == 1) {
  8833. break;
  8834. }
  8835. } while (status == 0x11);
  8836. }
  8837. if ((status & 0x80) != 0)
  8838. int_pending = ERR;
  8839. }
  8840. }
  8841. AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
  8842. AscSetChipLramAddr(iop_base, saved_ram_addr);
  8843. AscSetChipControl(iop_base, saved_ctrl_reg);
  8844. asc_dvc->is_in_int = FALSE;
  8845. return int_pending;
  8846. }
  8847. /*
  8848. * advansys_reset()
  8849. *
  8850. * Reset the bus associated with the command 'scp'.
  8851. *
  8852. * This function runs its own thread. Interrupts must be blocked but
  8853. * sleeping is allowed and no locking other than for host structures is
  8854. * required. Returns SUCCESS or FAILED.
  8855. */
  8856. static int advansys_reset(struct scsi_cmnd *scp)
  8857. {
  8858. struct Scsi_Host *shost = scp->device->host;
  8859. struct asc_board *boardp = shost_priv(shost);
  8860. unsigned long flags;
  8861. int status;
  8862. int ret = SUCCESS;
  8863. ASC_DBG1(1, "advansys_reset: 0x%p\n", scp);
  8864. ASC_STATS(shost, reset);
  8865. scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
  8866. if (ASC_NARROW_BOARD(boardp)) {
  8867. ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
  8868. /* Reset the chip and SCSI bus. */
  8869. ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
  8870. status = AscInitAsc1000Driver(asc_dvc);
  8871. /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
  8872. if (asc_dvc->err_code) {
  8873. scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
  8874. "0x%x\n", asc_dvc->err_code);
  8875. ret = FAILED;
  8876. } else if (status) {
  8877. scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
  8878. "0x%x\n", status);
  8879. } else {
  8880. scmd_printk(KERN_INFO, scp, "SCSI bus reset "
  8881. "successful\n");
  8882. }
  8883. ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
  8884. spin_lock_irqsave(&boardp->lock, flags);
  8885. } else {
  8886. /*
  8887. * If the suggest reset bus flags are set, then reset the bus.
  8888. * Otherwise only reset the device.
  8889. */
  8890. ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
  8891. /*
  8892. * Reset the target's SCSI bus.
  8893. */
  8894. ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
  8895. switch (AdvResetChipAndSB(adv_dvc)) {
  8896. case ASC_TRUE:
  8897. scmd_printk(KERN_INFO, scp, "SCSI bus reset "
  8898. "successful\n");
  8899. break;
  8900. case ASC_FALSE:
  8901. default:
  8902. scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
  8903. ret = FAILED;
  8904. break;
  8905. }
  8906. spin_lock_irqsave(&boardp->lock, flags);
  8907. AdvISR(adv_dvc);
  8908. }
  8909. /* Save the time of the most recently completed reset. */
  8910. boardp->last_reset = jiffies;
  8911. spin_unlock_irqrestore(&boardp->lock, flags);
  8912. ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
  8913. return ret;
  8914. }
  8915. /*
  8916. * advansys_biosparam()
  8917. *
  8918. * Translate disk drive geometry if the "BIOS greater than 1 GB"
  8919. * support is enabled for a drive.
  8920. *
  8921. * ip (information pointer) is an int array with the following definition:
  8922. * ip[0]: heads
  8923. * ip[1]: sectors
  8924. * ip[2]: cylinders
  8925. */
  8926. static int
  8927. advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
  8928. sector_t capacity, int ip[])
  8929. {
  8930. struct asc_board *boardp = shost_priv(sdev->host);
  8931. ASC_DBG(1, "advansys_biosparam: begin\n");
  8932. ASC_STATS(sdev->host, biosparam);
  8933. if (ASC_NARROW_BOARD(boardp)) {
  8934. if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
  8935. ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
  8936. ip[0] = 255;
  8937. ip[1] = 63;
  8938. } else {
  8939. ip[0] = 64;
  8940. ip[1] = 32;
  8941. }
  8942. } else {
  8943. if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
  8944. BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
  8945. ip[0] = 255;
  8946. ip[1] = 63;
  8947. } else {
  8948. ip[0] = 64;
  8949. ip[1] = 32;
  8950. }
  8951. }
  8952. ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
  8953. ASC_DBG(1, "advansys_biosparam: end\n");
  8954. return 0;
  8955. }
  8956. /*
  8957. * First-level interrupt handler.
  8958. *
  8959. * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
  8960. */
  8961. static irqreturn_t advansys_interrupt(int irq, void *dev_id)
  8962. {
  8963. unsigned long flags;
  8964. struct Scsi_Host *shost = dev_id;
  8965. struct asc_board *boardp = shost_priv(shost);
  8966. irqreturn_t result = IRQ_NONE;
  8967. ASC_DBG1(2, "advansys_interrupt: boardp 0x%p\n", boardp);
  8968. spin_lock_irqsave(&boardp->lock, flags);
  8969. if (ASC_NARROW_BOARD(boardp)) {
  8970. if (AscIsIntPending(shost->io_port)) {
  8971. result = IRQ_HANDLED;
  8972. ASC_STATS(shost, interrupt);
  8973. ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
  8974. AscISR(&boardp->dvc_var.asc_dvc_var);
  8975. }
  8976. } else {
  8977. ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
  8978. if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
  8979. result = IRQ_HANDLED;
  8980. ASC_STATS(shost, interrupt);
  8981. }
  8982. }
  8983. spin_unlock_irqrestore(&boardp->lock, flags);
  8984. ASC_DBG(1, "advansys_interrupt: end\n");
  8985. return result;
  8986. }
  8987. static int AscHostReqRiscHalt(PortAddr iop_base)
  8988. {
  8989. int count = 0;
  8990. int sta = 0;
  8991. uchar saved_stop_code;
  8992. if (AscIsChipHalted(iop_base))
  8993. return (1);
  8994. saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
  8995. AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
  8996. ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
  8997. do {
  8998. if (AscIsChipHalted(iop_base)) {
  8999. sta = 1;
  9000. break;
  9001. }
  9002. mdelay(100);
  9003. } while (count++ < 20);
  9004. AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
  9005. return (sta);
  9006. }
  9007. static int
  9008. AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
  9009. {
  9010. int sta = FALSE;
  9011. if (AscHostReqRiscHalt(iop_base)) {
  9012. sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
  9013. AscStartChip(iop_base);
  9014. }
  9015. return sta;
  9016. }
  9017. static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
  9018. {
  9019. char type = sdev->type;
  9020. ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
  9021. if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
  9022. return;
  9023. if (asc_dvc->init_sdtr & tid_bits)
  9024. return;
  9025. if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
  9026. asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
  9027. asc_dvc->pci_fix_asyn_xfer |= tid_bits;
  9028. if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
  9029. (type == TYPE_ROM) || (type == TYPE_TAPE))
  9030. asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
  9031. if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
  9032. AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
  9033. ASYN_SDTR_DATA_FIX_PCI_REV_AB);
  9034. }
  9035. static void
  9036. advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
  9037. {
  9038. ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
  9039. ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
  9040. if (sdev->lun == 0) {
  9041. ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
  9042. if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
  9043. asc_dvc->init_sdtr |= tid_bit;
  9044. } else {
  9045. asc_dvc->init_sdtr &= ~tid_bit;
  9046. }
  9047. if (orig_init_sdtr != asc_dvc->init_sdtr)
  9048. AscAsyncFix(asc_dvc, sdev);
  9049. }
  9050. if (sdev->tagged_supported) {
  9051. if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
  9052. if (sdev->lun == 0) {
  9053. asc_dvc->cfg->can_tagged_qng |= tid_bit;
  9054. asc_dvc->use_tagged_qng |= tid_bit;
  9055. }
  9056. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
  9057. asc_dvc->max_dvc_qng[sdev->id]);
  9058. }
  9059. } else {
  9060. if (sdev->lun == 0) {
  9061. asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
  9062. asc_dvc->use_tagged_qng &= ~tid_bit;
  9063. }
  9064. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  9065. }
  9066. if ((sdev->lun == 0) &&
  9067. (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
  9068. AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
  9069. asc_dvc->cfg->disc_enable);
  9070. AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
  9071. asc_dvc->use_tagged_qng);
  9072. AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
  9073. asc_dvc->cfg->can_tagged_qng);
  9074. asc_dvc->max_dvc_qng[sdev->id] =
  9075. asc_dvc->cfg->max_tag_qng[sdev->id];
  9076. AscWriteLramByte(asc_dvc->iop_base,
  9077. (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
  9078. asc_dvc->max_dvc_qng[sdev->id]);
  9079. }
  9080. }
  9081. /*
  9082. * Wide Transfers
  9083. *
  9084. * If the EEPROM enabled WDTR for the device and the device supports wide
  9085. * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
  9086. * write the new value to the microcode.
  9087. */
  9088. static void
  9089. advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
  9090. {
  9091. unsigned short cfg_word;
  9092. AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
  9093. if ((cfg_word & tidmask) != 0)
  9094. return;
  9095. cfg_word |= tidmask;
  9096. AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
  9097. /*
  9098. * Clear the microcode SDTR and WDTR negotiation done indicators for
  9099. * the target to cause it to negotiate with the new setting set above.
  9100. * WDTR when accepted causes the target to enter asynchronous mode, so
  9101. * SDTR must be negotiated.
  9102. */
  9103. AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
  9104. cfg_word &= ~tidmask;
  9105. AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
  9106. AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
  9107. cfg_word &= ~tidmask;
  9108. AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
  9109. }
  9110. /*
  9111. * Synchronous Transfers
  9112. *
  9113. * If the EEPROM enabled SDTR for the device and the device
  9114. * supports synchronous transfers, then turn on the device's
  9115. * 'sdtr_able' bit. Write the new value to the microcode.
  9116. */
  9117. static void
  9118. advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
  9119. {
  9120. unsigned short cfg_word;
  9121. AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
  9122. if ((cfg_word & tidmask) != 0)
  9123. return;
  9124. cfg_word |= tidmask;
  9125. AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
  9126. /*
  9127. * Clear the microcode "SDTR negotiation" done indicator for the
  9128. * target to cause it to negotiate with the new setting set above.
  9129. */
  9130. AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
  9131. cfg_word &= ~tidmask;
  9132. AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
  9133. }
  9134. /*
  9135. * PPR (Parallel Protocol Request) Capable
  9136. *
  9137. * If the device supports DT mode, then it must be PPR capable.
  9138. * The PPR message will be used in place of the SDTR and WDTR
  9139. * messages to negotiate synchronous speed and offset, transfer
  9140. * width, and protocol options.
  9141. */
  9142. static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
  9143. AdvPortAddr iop_base, unsigned short tidmask)
  9144. {
  9145. AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
  9146. adv_dvc->ppr_able |= tidmask;
  9147. AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
  9148. }
  9149. static void
  9150. advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
  9151. {
  9152. AdvPortAddr iop_base = adv_dvc->iop_base;
  9153. unsigned short tidmask = 1 << sdev->id;
  9154. if (sdev->lun == 0) {
  9155. /*
  9156. * Handle WDTR, SDTR, and Tag Queuing. If the feature
  9157. * is enabled in the EEPROM and the device supports the
  9158. * feature, then enable it in the microcode.
  9159. */
  9160. if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
  9161. advansys_wide_enable_wdtr(iop_base, tidmask);
  9162. if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
  9163. advansys_wide_enable_sdtr(iop_base, tidmask);
  9164. if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
  9165. advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
  9166. /*
  9167. * Tag Queuing is disabled for the BIOS which runs in polled
  9168. * mode and would see no benefit from Tag Queuing. Also by
  9169. * disabling Tag Queuing in the BIOS devices with Tag Queuing
  9170. * bugs will at least work with the BIOS.
  9171. */
  9172. if ((adv_dvc->tagqng_able & tidmask) &&
  9173. sdev->tagged_supported) {
  9174. unsigned short cfg_word;
  9175. AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
  9176. cfg_word |= tidmask;
  9177. AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
  9178. cfg_word);
  9179. AdvWriteByteLram(iop_base,
  9180. ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
  9181. adv_dvc->max_dvc_qng);
  9182. }
  9183. }
  9184. if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
  9185. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
  9186. adv_dvc->max_dvc_qng);
  9187. } else {
  9188. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  9189. }
  9190. }
  9191. /*
  9192. * Set the number of commands to queue per device for the
  9193. * specified host adapter.
  9194. */
  9195. static int advansys_slave_configure(struct scsi_device *sdev)
  9196. {
  9197. struct asc_board *boardp = shost_priv(sdev->host);
  9198. if (ASC_NARROW_BOARD(boardp))
  9199. advansys_narrow_slave_configure(sdev,
  9200. &boardp->dvc_var.asc_dvc_var);
  9201. else
  9202. advansys_wide_slave_configure(sdev,
  9203. &boardp->dvc_var.adv_dvc_var);
  9204. return 0;
  9205. }
  9206. static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
  9207. struct asc_scsi_q *asc_scsi_q)
  9208. {
  9209. memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
  9210. /*
  9211. * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
  9212. */
  9213. asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp);
  9214. /*
  9215. * Build the ASC_SCSI_Q request.
  9216. */
  9217. asc_scsi_q->cdbptr = &scp->cmnd[0];
  9218. asc_scsi_q->q2.cdb_len = scp->cmd_len;
  9219. asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
  9220. asc_scsi_q->q1.target_lun = scp->device->lun;
  9221. asc_scsi_q->q2.target_ix =
  9222. ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
  9223. asc_scsi_q->q1.sense_addr =
  9224. cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
  9225. asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
  9226. /*
  9227. * If there are any outstanding requests for the current target,
  9228. * then every 255th request send an ORDERED request. This heuristic
  9229. * tries to retain the benefit of request sorting while preventing
  9230. * request starvation. 255 is the max number of tags or pending commands
  9231. * a device may have outstanding.
  9232. *
  9233. * The request count is incremented below for every successfully
  9234. * started request.
  9235. *
  9236. */
  9237. if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
  9238. (boardp->reqcnt[scp->device->id] % 255) == 0) {
  9239. asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
  9240. } else {
  9241. asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
  9242. }
  9243. /*
  9244. * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
  9245. * buffer command.
  9246. */
  9247. if (scp->use_sg == 0) {
  9248. /*
  9249. * CDB request of single contiguous buffer.
  9250. */
  9251. ASC_STATS(scp->device->host, cont_cnt);
  9252. scp->SCp.dma_handle = scp->request_bufflen ?
  9253. dma_map_single(boardp->dev, scp->request_buffer,
  9254. scp->request_bufflen,
  9255. scp->sc_data_direction) : 0;
  9256. asc_scsi_q->q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
  9257. asc_scsi_q->q1.data_cnt = cpu_to_le32(scp->request_bufflen);
  9258. ASC_STATS_ADD(scp->device->host, cont_xfer,
  9259. ASC_CEILING(scp->request_bufflen, 512));
  9260. asc_scsi_q->q1.sg_queue_cnt = 0;
  9261. asc_scsi_q->sg_head = NULL;
  9262. } else {
  9263. /*
  9264. * CDB scatter-gather request list.
  9265. */
  9266. int sgcnt;
  9267. int use_sg;
  9268. struct scatterlist *slp;
  9269. struct asc_sg_head *asc_sg_head;
  9270. slp = (struct scatterlist *)scp->request_buffer;
  9271. use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
  9272. scp->sc_data_direction);
  9273. if (use_sg > scp->device->host->sg_tablesize) {
  9274. ASC_PRINT3("asc_build_req: board %d: use_sg %d > "
  9275. "sg_tablesize %d\n", boardp->id, use_sg,
  9276. scp->device->host->sg_tablesize);
  9277. dma_unmap_sg(boardp->dev, slp, scp->use_sg,
  9278. scp->sc_data_direction);
  9279. scp->result = HOST_BYTE(DID_ERROR);
  9280. return ASC_ERROR;
  9281. }
  9282. ASC_STATS(scp->device->host, sg_cnt);
  9283. asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
  9284. use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
  9285. if (!asc_sg_head) {
  9286. dma_unmap_sg(boardp->dev, slp, scp->use_sg,
  9287. scp->sc_data_direction);
  9288. scp->result = HOST_BYTE(DID_SOFT_ERROR);
  9289. return ASC_ERROR;
  9290. }
  9291. asc_scsi_q->q1.cntl |= QC_SG_HEAD;
  9292. asc_scsi_q->sg_head = asc_sg_head;
  9293. asc_scsi_q->q1.data_cnt = 0;
  9294. asc_scsi_q->q1.data_addr = 0;
  9295. /* This is a byte value, otherwise it would need to be swapped. */
  9296. asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
  9297. ASC_STATS_ADD(scp->device->host, sg_elem,
  9298. asc_sg_head->entry_cnt);
  9299. /*
  9300. * Convert scatter-gather list into ASC_SG_HEAD list.
  9301. */
  9302. for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
  9303. asc_sg_head->sg_list[sgcnt].addr =
  9304. cpu_to_le32(sg_dma_address(slp));
  9305. asc_sg_head->sg_list[sgcnt].bytes =
  9306. cpu_to_le32(sg_dma_len(slp));
  9307. ASC_STATS_ADD(scp->device->host, sg_xfer,
  9308. ASC_CEILING(sg_dma_len(slp), 512));
  9309. }
  9310. }
  9311. ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
  9312. ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
  9313. return ASC_NOERROR;
  9314. }
  9315. /*
  9316. * Build scatter-gather list for Adv Library (Wide Board).
  9317. *
  9318. * Additional ADV_SG_BLOCK structures will need to be allocated
  9319. * if the total number of scatter-gather elements exceeds
  9320. * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
  9321. * assumed to be physically contiguous.
  9322. *
  9323. * Return:
  9324. * ADV_SUCCESS(1) - SG List successfully created
  9325. * ADV_ERROR(-1) - SG List creation failed
  9326. */
  9327. static int
  9328. adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
  9329. int use_sg)
  9330. {
  9331. adv_sgblk_t *sgblkp;
  9332. ADV_SCSI_REQ_Q *scsiqp;
  9333. struct scatterlist *slp;
  9334. int sg_elem_cnt;
  9335. ADV_SG_BLOCK *sg_block, *prev_sg_block;
  9336. ADV_PADDR sg_block_paddr;
  9337. int i;
  9338. scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
  9339. slp = (struct scatterlist *)scp->request_buffer;
  9340. sg_elem_cnt = use_sg;
  9341. prev_sg_block = NULL;
  9342. reqp->sgblkp = NULL;
  9343. for (;;) {
  9344. /*
  9345. * Allocate a 'adv_sgblk_t' structure from the board free
  9346. * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
  9347. * (15) scatter-gather elements.
  9348. */
  9349. if ((sgblkp = boardp->adv_sgblkp) == NULL) {
  9350. ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
  9351. ASC_STATS(scp->device->host, adv_build_nosg);
  9352. /*
  9353. * Allocation failed. Free 'adv_sgblk_t' structures
  9354. * already allocated for the request.
  9355. */
  9356. while ((sgblkp = reqp->sgblkp) != NULL) {
  9357. /* Remove 'sgblkp' from the request list. */
  9358. reqp->sgblkp = sgblkp->next_sgblkp;
  9359. /* Add 'sgblkp' to the board free list. */
  9360. sgblkp->next_sgblkp = boardp->adv_sgblkp;
  9361. boardp->adv_sgblkp = sgblkp;
  9362. }
  9363. return ASC_BUSY;
  9364. }
  9365. /* Complete 'adv_sgblk_t' board allocation. */
  9366. boardp->adv_sgblkp = sgblkp->next_sgblkp;
  9367. sgblkp->next_sgblkp = NULL;
  9368. /*
  9369. * Get 8 byte aligned virtual and physical addresses
  9370. * for the allocated ADV_SG_BLOCK structure.
  9371. */
  9372. sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
  9373. sg_block_paddr = virt_to_bus(sg_block);
  9374. /*
  9375. * Check if this is the first 'adv_sgblk_t' for the
  9376. * request.
  9377. */
  9378. if (reqp->sgblkp == NULL) {
  9379. /* Request's first scatter-gather block. */
  9380. reqp->sgblkp = sgblkp;
  9381. /*
  9382. * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
  9383. * address pointers.
  9384. */
  9385. scsiqp->sg_list_ptr = sg_block;
  9386. scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
  9387. } else {
  9388. /* Request's second or later scatter-gather block. */
  9389. sgblkp->next_sgblkp = reqp->sgblkp;
  9390. reqp->sgblkp = sgblkp;
  9391. /*
  9392. * Point the previous ADV_SG_BLOCK structure to
  9393. * the newly allocated ADV_SG_BLOCK structure.
  9394. */
  9395. prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
  9396. }
  9397. for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
  9398. sg_block->sg_list[i].sg_addr =
  9399. cpu_to_le32(sg_dma_address(slp));
  9400. sg_block->sg_list[i].sg_count =
  9401. cpu_to_le32(sg_dma_len(slp));
  9402. ASC_STATS_ADD(scp->device->host, sg_xfer,
  9403. ASC_CEILING(sg_dma_len(slp), 512));
  9404. if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
  9405. sg_block->sg_cnt = i + 1;
  9406. sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
  9407. return ADV_SUCCESS;
  9408. }
  9409. slp++;
  9410. }
  9411. sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
  9412. prev_sg_block = sg_block;
  9413. }
  9414. }
  9415. /*
  9416. * Build a request structure for the Adv Library (Wide Board).
  9417. *
  9418. * If an adv_req_t can not be allocated to issue the request,
  9419. * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
  9420. *
  9421. * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
  9422. * microcode for DMA addresses or math operations are byte swapped
  9423. * to little-endian order.
  9424. */
  9425. static int
  9426. adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
  9427. ADV_SCSI_REQ_Q **adv_scsiqpp)
  9428. {
  9429. adv_req_t *reqp;
  9430. ADV_SCSI_REQ_Q *scsiqp;
  9431. int i;
  9432. int ret;
  9433. /*
  9434. * Allocate an adv_req_t structure from the board to execute
  9435. * the command.
  9436. */
  9437. if (boardp->adv_reqp == NULL) {
  9438. ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
  9439. ASC_STATS(scp->device->host, adv_build_noreq);
  9440. return ASC_BUSY;
  9441. } else {
  9442. reqp = boardp->adv_reqp;
  9443. boardp->adv_reqp = reqp->next_reqp;
  9444. reqp->next_reqp = NULL;
  9445. }
  9446. /*
  9447. * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
  9448. */
  9449. scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
  9450. /*
  9451. * Initialize the structure.
  9452. */
  9453. scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
  9454. /*
  9455. * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
  9456. */
  9457. scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
  9458. /*
  9459. * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
  9460. */
  9461. reqp->cmndp = scp;
  9462. /*
  9463. * Build the ADV_SCSI_REQ_Q request.
  9464. */
  9465. /* Set CDB length and copy it to the request structure. */
  9466. scsiqp->cdb_len = scp->cmd_len;
  9467. /* Copy first 12 CDB bytes to cdb[]. */
  9468. for (i = 0; i < scp->cmd_len && i < 12; i++) {
  9469. scsiqp->cdb[i] = scp->cmnd[i];
  9470. }
  9471. /* Copy last 4 CDB bytes, if present, to cdb16[]. */
  9472. for (; i < scp->cmd_len; i++) {
  9473. scsiqp->cdb16[i - 12] = scp->cmnd[i];
  9474. }
  9475. scsiqp->target_id = scp->device->id;
  9476. scsiqp->target_lun = scp->device->lun;
  9477. scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
  9478. scsiqp->sense_len = sizeof(scp->sense_buffer);
  9479. /*
  9480. * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
  9481. * buffer command.
  9482. */
  9483. scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
  9484. scsiqp->vdata_addr = scp->request_buffer;
  9485. scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
  9486. if (scp->use_sg == 0) {
  9487. /*
  9488. * CDB request of single contiguous buffer.
  9489. */
  9490. reqp->sgblkp = NULL;
  9491. scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
  9492. if (scp->request_bufflen) {
  9493. scsiqp->vdata_addr = scp->request_buffer;
  9494. scp->SCp.dma_handle =
  9495. dma_map_single(boardp->dev, scp->request_buffer,
  9496. scp->request_bufflen,
  9497. scp->sc_data_direction);
  9498. } else {
  9499. scsiqp->vdata_addr = NULL;
  9500. scp->SCp.dma_handle = 0;
  9501. }
  9502. scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
  9503. scsiqp->sg_list_ptr = NULL;
  9504. scsiqp->sg_real_addr = 0;
  9505. ASC_STATS(scp->device->host, cont_cnt);
  9506. ASC_STATS_ADD(scp->device->host, cont_xfer,
  9507. ASC_CEILING(scp->request_bufflen, 512));
  9508. } else {
  9509. /*
  9510. * CDB scatter-gather request list.
  9511. */
  9512. struct scatterlist *slp;
  9513. int use_sg;
  9514. slp = (struct scatterlist *)scp->request_buffer;
  9515. use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
  9516. scp->sc_data_direction);
  9517. if (use_sg > ADV_MAX_SG_LIST) {
  9518. ASC_PRINT3("adv_build_req: board %d: use_sg %d > "
  9519. "ADV_MAX_SG_LIST %d\n", boardp->id, use_sg,
  9520. scp->device->host->sg_tablesize);
  9521. dma_unmap_sg(boardp->dev, slp, scp->use_sg,
  9522. scp->sc_data_direction);
  9523. scp->result = HOST_BYTE(DID_ERROR);
  9524. /*
  9525. * Free the 'adv_req_t' structure by adding it back
  9526. * to the board free list.
  9527. */
  9528. reqp->next_reqp = boardp->adv_reqp;
  9529. boardp->adv_reqp = reqp;
  9530. return ASC_ERROR;
  9531. }
  9532. ret = adv_get_sglist(boardp, reqp, scp, use_sg);
  9533. if (ret != ADV_SUCCESS) {
  9534. /*
  9535. * Free the adv_req_t structure by adding it back to
  9536. * the board free list.
  9537. */
  9538. reqp->next_reqp = boardp->adv_reqp;
  9539. boardp->adv_reqp = reqp;
  9540. return ret;
  9541. }
  9542. ASC_STATS(scp->device->host, sg_cnt);
  9543. ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
  9544. }
  9545. ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
  9546. ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
  9547. *adv_scsiqpp = scsiqp;
  9548. return ASC_NOERROR;
  9549. }
  9550. static int AscSgListToQueue(int sg_list)
  9551. {
  9552. int n_sg_list_qs;
  9553. n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
  9554. if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
  9555. n_sg_list_qs++;
  9556. return n_sg_list_qs + 1;
  9557. }
  9558. static uint
  9559. AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
  9560. {
  9561. uint cur_used_qs;
  9562. uint cur_free_qs;
  9563. ASC_SCSI_BIT_ID_TYPE target_id;
  9564. uchar tid_no;
  9565. target_id = ASC_TIX_TO_TARGET_ID(target_ix);
  9566. tid_no = ASC_TIX_TO_TID(target_ix);
  9567. if ((asc_dvc->unit_not_ready & target_id) ||
  9568. (asc_dvc->queue_full_or_busy & target_id)) {
  9569. return 0;
  9570. }
  9571. if (n_qs == 1) {
  9572. cur_used_qs = (uint) asc_dvc->cur_total_qng +
  9573. (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
  9574. } else {
  9575. cur_used_qs = (uint) asc_dvc->cur_total_qng +
  9576. (uint) ASC_MIN_FREE_Q;
  9577. }
  9578. if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
  9579. cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
  9580. if (asc_dvc->cur_dvc_qng[tid_no] >=
  9581. asc_dvc->max_dvc_qng[tid_no]) {
  9582. return 0;
  9583. }
  9584. return cur_free_qs;
  9585. }
  9586. if (n_qs > 1) {
  9587. if ((n_qs > asc_dvc->last_q_shortage)
  9588. && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
  9589. asc_dvc->last_q_shortage = n_qs;
  9590. }
  9591. }
  9592. return 0;
  9593. }
  9594. static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
  9595. {
  9596. ushort q_addr;
  9597. uchar next_qp;
  9598. uchar q_status;
  9599. q_addr = ASC_QNO_TO_QADDR(free_q_head);
  9600. q_status = (uchar)AscReadLramByte(iop_base,
  9601. (ushort)(q_addr +
  9602. ASC_SCSIQ_B_STATUS));
  9603. next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
  9604. if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
  9605. return next_qp;
  9606. return ASC_QLINK_END;
  9607. }
  9608. static uchar
  9609. AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
  9610. {
  9611. uchar i;
  9612. for (i = 0; i < n_free_q; i++) {
  9613. free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
  9614. if (free_q_head == ASC_QLINK_END)
  9615. break;
  9616. }
  9617. return free_q_head;
  9618. }
  9619. /*
  9620. * void
  9621. * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
  9622. *
  9623. * Calling/Exit State:
  9624. * none
  9625. *
  9626. * Description:
  9627. * Output an ASC_SCSI_Q structure to the chip
  9628. */
  9629. static void
  9630. DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
  9631. {
  9632. int i;
  9633. ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
  9634. AscSetChipLramAddr(iop_base, s_addr);
  9635. for (i = 0; i < 2 * words; i += 2) {
  9636. if (i == 4 || i == 20) {
  9637. continue;
  9638. }
  9639. outpw(iop_base + IOP_RAM_DATA,
  9640. ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
  9641. }
  9642. }
  9643. static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
  9644. {
  9645. ushort q_addr;
  9646. uchar tid_no;
  9647. uchar sdtr_data;
  9648. uchar syn_period_ix;
  9649. uchar syn_offset;
  9650. PortAddr iop_base;
  9651. iop_base = asc_dvc->iop_base;
  9652. if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
  9653. ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
  9654. tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
  9655. sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
  9656. syn_period_ix =
  9657. (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
  9658. syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
  9659. AscMsgOutSDTR(asc_dvc,
  9660. asc_dvc->sdtr_period_tbl[syn_period_ix],
  9661. syn_offset);
  9662. scsiq->q1.cntl |= QC_MSG_OUT;
  9663. }
  9664. q_addr = ASC_QNO_TO_QADDR(q_no);
  9665. if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
  9666. scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
  9667. }
  9668. scsiq->q1.status = QS_FREE;
  9669. AscMemWordCopyPtrToLram(iop_base,
  9670. q_addr + ASC_SCSIQ_CDB_BEG,
  9671. (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
  9672. DvcPutScsiQ(iop_base,
  9673. q_addr + ASC_SCSIQ_CPY_BEG,
  9674. (uchar *)&scsiq->q1.cntl,
  9675. ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
  9676. AscWriteLramWord(iop_base,
  9677. (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
  9678. (ushort)(((ushort)scsiq->q1.
  9679. q_no << 8) | (ushort)QS_READY));
  9680. return 1;
  9681. }
  9682. static int
  9683. AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
  9684. {
  9685. int sta;
  9686. int i;
  9687. ASC_SG_HEAD *sg_head;
  9688. ASC_SG_LIST_Q scsi_sg_q;
  9689. ASC_DCNT saved_data_addr;
  9690. ASC_DCNT saved_data_cnt;
  9691. PortAddr iop_base;
  9692. ushort sg_list_dwords;
  9693. ushort sg_index;
  9694. ushort sg_entry_cnt;
  9695. ushort q_addr;
  9696. uchar next_qp;
  9697. iop_base = asc_dvc->iop_base;
  9698. sg_head = scsiq->sg_head;
  9699. saved_data_addr = scsiq->q1.data_addr;
  9700. saved_data_cnt = scsiq->q1.data_cnt;
  9701. scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
  9702. scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
  9703. #if CC_VERY_LONG_SG_LIST
  9704. /*
  9705. * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
  9706. * then not all SG elements will fit in the allocated queues.
  9707. * The rest of the SG elements will be copied when the RISC
  9708. * completes the SG elements that fit and halts.
  9709. */
  9710. if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
  9711. /*
  9712. * Set sg_entry_cnt to be the number of SG elements that
  9713. * will fit in the allocated SG queues. It is minus 1, because
  9714. * the first SG element is handled above. ASC_MAX_SG_LIST is
  9715. * already inflated by 1 to account for this. For example it
  9716. * may be 50 which is 1 + 7 queues * 7 SG elements.
  9717. */
  9718. sg_entry_cnt = ASC_MAX_SG_LIST - 1;
  9719. /*
  9720. * Keep track of remaining number of SG elements that will
  9721. * need to be handled from a_isr.c.
  9722. */
  9723. scsiq->remain_sg_entry_cnt =
  9724. sg_head->entry_cnt - ASC_MAX_SG_LIST;
  9725. } else {
  9726. #endif /* CC_VERY_LONG_SG_LIST */
  9727. /*
  9728. * Set sg_entry_cnt to be the number of SG elements that
  9729. * will fit in the allocated SG queues. It is minus 1, because
  9730. * the first SG element is handled above.
  9731. */
  9732. sg_entry_cnt = sg_head->entry_cnt - 1;
  9733. #if CC_VERY_LONG_SG_LIST
  9734. }
  9735. #endif /* CC_VERY_LONG_SG_LIST */
  9736. if (sg_entry_cnt != 0) {
  9737. scsiq->q1.cntl |= QC_SG_HEAD;
  9738. q_addr = ASC_QNO_TO_QADDR(q_no);
  9739. sg_index = 1;
  9740. scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
  9741. scsi_sg_q.sg_head_qp = q_no;
  9742. scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
  9743. for (i = 0; i < sg_head->queue_cnt; i++) {
  9744. scsi_sg_q.seq_no = i + 1;
  9745. if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
  9746. sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
  9747. sg_entry_cnt -= ASC_SG_LIST_PER_Q;
  9748. if (i == 0) {
  9749. scsi_sg_q.sg_list_cnt =
  9750. ASC_SG_LIST_PER_Q;
  9751. scsi_sg_q.sg_cur_list_cnt =
  9752. ASC_SG_LIST_PER_Q;
  9753. } else {
  9754. scsi_sg_q.sg_list_cnt =
  9755. ASC_SG_LIST_PER_Q - 1;
  9756. scsi_sg_q.sg_cur_list_cnt =
  9757. ASC_SG_LIST_PER_Q - 1;
  9758. }
  9759. } else {
  9760. #if CC_VERY_LONG_SG_LIST
  9761. /*
  9762. * This is the last SG queue in the list of
  9763. * allocated SG queues. If there are more
  9764. * SG elements than will fit in the allocated
  9765. * queues, then set the QCSG_SG_XFER_MORE flag.
  9766. */
  9767. if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
  9768. scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
  9769. } else {
  9770. #endif /* CC_VERY_LONG_SG_LIST */
  9771. scsi_sg_q.cntl |= QCSG_SG_XFER_END;
  9772. #if CC_VERY_LONG_SG_LIST
  9773. }
  9774. #endif /* CC_VERY_LONG_SG_LIST */
  9775. sg_list_dwords = sg_entry_cnt << 1;
  9776. if (i == 0) {
  9777. scsi_sg_q.sg_list_cnt = sg_entry_cnt;
  9778. scsi_sg_q.sg_cur_list_cnt =
  9779. sg_entry_cnt;
  9780. } else {
  9781. scsi_sg_q.sg_list_cnt =
  9782. sg_entry_cnt - 1;
  9783. scsi_sg_q.sg_cur_list_cnt =
  9784. sg_entry_cnt - 1;
  9785. }
  9786. sg_entry_cnt = 0;
  9787. }
  9788. next_qp = AscReadLramByte(iop_base,
  9789. (ushort)(q_addr +
  9790. ASC_SCSIQ_B_FWD));
  9791. scsi_sg_q.q_no = next_qp;
  9792. q_addr = ASC_QNO_TO_QADDR(next_qp);
  9793. AscMemWordCopyPtrToLram(iop_base,
  9794. q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
  9795. (uchar *)&scsi_sg_q,
  9796. sizeof(ASC_SG_LIST_Q) >> 1);
  9797. AscMemDWordCopyPtrToLram(iop_base,
  9798. q_addr + ASC_SGQ_LIST_BEG,
  9799. (uchar *)&sg_head->
  9800. sg_list[sg_index],
  9801. sg_list_dwords);
  9802. sg_index += ASC_SG_LIST_PER_Q;
  9803. scsiq->next_sg_index = sg_index;
  9804. }
  9805. } else {
  9806. scsiq->q1.cntl &= ~QC_SG_HEAD;
  9807. }
  9808. sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
  9809. scsiq->q1.data_addr = saved_data_addr;
  9810. scsiq->q1.data_cnt = saved_data_cnt;
  9811. return (sta);
  9812. }
  9813. static int
  9814. AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
  9815. {
  9816. PortAddr iop_base;
  9817. uchar free_q_head;
  9818. uchar next_qp;
  9819. uchar tid_no;
  9820. uchar target_ix;
  9821. int sta;
  9822. iop_base = asc_dvc->iop_base;
  9823. target_ix = scsiq->q2.target_ix;
  9824. tid_no = ASC_TIX_TO_TID(target_ix);
  9825. sta = 0;
  9826. free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
  9827. if (n_q_required > 1) {
  9828. next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
  9829. (uchar)n_q_required);
  9830. if (next_qp != ASC_QLINK_END) {
  9831. asc_dvc->last_q_shortage = 0;
  9832. scsiq->sg_head->queue_cnt = n_q_required - 1;
  9833. scsiq->q1.q_no = free_q_head;
  9834. sta = AscPutReadySgListQueue(asc_dvc, scsiq,
  9835. free_q_head);
  9836. }
  9837. } else if (n_q_required == 1) {
  9838. next_qp = AscAllocFreeQueue(iop_base, free_q_head);
  9839. if (next_qp != ASC_QLINK_END) {
  9840. scsiq->q1.q_no = free_q_head;
  9841. sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
  9842. }
  9843. }
  9844. if (sta == 1) {
  9845. AscPutVarFreeQHead(iop_base, next_qp);
  9846. asc_dvc->cur_total_qng += n_q_required;
  9847. asc_dvc->cur_dvc_qng[tid_no]++;
  9848. }
  9849. return sta;
  9850. }
  9851. #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
  9852. static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
  9853. INQUIRY,
  9854. REQUEST_SENSE,
  9855. READ_CAPACITY,
  9856. READ_TOC,
  9857. MODE_SELECT,
  9858. MODE_SENSE,
  9859. MODE_SELECT_10,
  9860. MODE_SENSE_10,
  9861. 0xFF,
  9862. 0xFF,
  9863. 0xFF,
  9864. 0xFF,
  9865. 0xFF,
  9866. 0xFF,
  9867. 0xFF,
  9868. 0xFF
  9869. };
  9870. static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
  9871. {
  9872. PortAddr iop_base;
  9873. int sta;
  9874. int n_q_required;
  9875. int disable_syn_offset_one_fix;
  9876. int i;
  9877. ASC_PADDR addr;
  9878. ushort sg_entry_cnt = 0;
  9879. ushort sg_entry_cnt_minus_one = 0;
  9880. uchar target_ix;
  9881. uchar tid_no;
  9882. uchar sdtr_data;
  9883. uchar extra_bytes;
  9884. uchar scsi_cmd;
  9885. uchar disable_cmd;
  9886. ASC_SG_HEAD *sg_head;
  9887. ASC_DCNT data_cnt;
  9888. iop_base = asc_dvc->iop_base;
  9889. sg_head = scsiq->sg_head;
  9890. if (asc_dvc->err_code != 0)
  9891. return (ERR);
  9892. scsiq->q1.q_no = 0;
  9893. if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
  9894. scsiq->q1.extra_bytes = 0;
  9895. }
  9896. sta = 0;
  9897. target_ix = scsiq->q2.target_ix;
  9898. tid_no = ASC_TIX_TO_TID(target_ix);
  9899. n_q_required = 1;
  9900. if (scsiq->cdbptr[0] == REQUEST_SENSE) {
  9901. if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
  9902. asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
  9903. sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
  9904. AscMsgOutSDTR(asc_dvc,
  9905. asc_dvc->
  9906. sdtr_period_tbl[(sdtr_data >> 4) &
  9907. (uchar)(asc_dvc->
  9908. max_sdtr_index -
  9909. 1)],
  9910. (uchar)(sdtr_data & (uchar)
  9911. ASC_SYN_MAX_OFFSET));
  9912. scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
  9913. }
  9914. }
  9915. if (asc_dvc->in_critical_cnt != 0) {
  9916. AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
  9917. return (ERR);
  9918. }
  9919. asc_dvc->in_critical_cnt++;
  9920. if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
  9921. if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
  9922. asc_dvc->in_critical_cnt--;
  9923. return (ERR);
  9924. }
  9925. #if !CC_VERY_LONG_SG_LIST
  9926. if (sg_entry_cnt > ASC_MAX_SG_LIST) {
  9927. asc_dvc->in_critical_cnt--;
  9928. return (ERR);
  9929. }
  9930. #endif /* !CC_VERY_LONG_SG_LIST */
  9931. if (sg_entry_cnt == 1) {
  9932. scsiq->q1.data_addr =
  9933. (ADV_PADDR)sg_head->sg_list[0].addr;
  9934. scsiq->q1.data_cnt =
  9935. (ADV_DCNT)sg_head->sg_list[0].bytes;
  9936. scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
  9937. }
  9938. sg_entry_cnt_minus_one = sg_entry_cnt - 1;
  9939. }
  9940. scsi_cmd = scsiq->cdbptr[0];
  9941. disable_syn_offset_one_fix = FALSE;
  9942. if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
  9943. !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
  9944. if (scsiq->q1.cntl & QC_SG_HEAD) {
  9945. data_cnt = 0;
  9946. for (i = 0; i < sg_entry_cnt; i++) {
  9947. data_cnt +=
  9948. (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
  9949. bytes);
  9950. }
  9951. } else {
  9952. data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
  9953. }
  9954. if (data_cnt != 0UL) {
  9955. if (data_cnt < 512UL) {
  9956. disable_syn_offset_one_fix = TRUE;
  9957. } else {
  9958. for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
  9959. i++) {
  9960. disable_cmd =
  9961. _syn_offset_one_disable_cmd[i];
  9962. if (disable_cmd == 0xFF) {
  9963. break;
  9964. }
  9965. if (scsi_cmd == disable_cmd) {
  9966. disable_syn_offset_one_fix =
  9967. TRUE;
  9968. break;
  9969. }
  9970. }
  9971. }
  9972. }
  9973. }
  9974. if (disable_syn_offset_one_fix) {
  9975. scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
  9976. scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
  9977. ASC_TAG_FLAG_DISABLE_DISCONNECT);
  9978. } else {
  9979. scsiq->q2.tag_code &= 0x27;
  9980. }
  9981. if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
  9982. if (asc_dvc->bug_fix_cntl) {
  9983. if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
  9984. if ((scsi_cmd == READ_6) ||
  9985. (scsi_cmd == READ_10)) {
  9986. addr =
  9987. (ADV_PADDR)le32_to_cpu(sg_head->
  9988. sg_list
  9989. [sg_entry_cnt_minus_one].
  9990. addr) +
  9991. (ADV_DCNT)le32_to_cpu(sg_head->
  9992. sg_list
  9993. [sg_entry_cnt_minus_one].
  9994. bytes);
  9995. extra_bytes =
  9996. (uchar)((ushort)addr & 0x0003);
  9997. if ((extra_bytes != 0)
  9998. &&
  9999. ((scsiq->q2.
  10000. tag_code &
  10001. ASC_TAG_FLAG_EXTRA_BYTES)
  10002. == 0)) {
  10003. scsiq->q2.tag_code |=
  10004. ASC_TAG_FLAG_EXTRA_BYTES;
  10005. scsiq->q1.extra_bytes =
  10006. extra_bytes;
  10007. data_cnt =
  10008. le32_to_cpu(sg_head->
  10009. sg_list
  10010. [sg_entry_cnt_minus_one].
  10011. bytes);
  10012. data_cnt -=
  10013. (ASC_DCNT) extra_bytes;
  10014. sg_head->
  10015. sg_list
  10016. [sg_entry_cnt_minus_one].
  10017. bytes =
  10018. cpu_to_le32(data_cnt);
  10019. }
  10020. }
  10021. }
  10022. }
  10023. sg_head->entry_to_copy = sg_head->entry_cnt;
  10024. #if CC_VERY_LONG_SG_LIST
  10025. /*
  10026. * Set the sg_entry_cnt to the maximum possible. The rest of
  10027. * the SG elements will be copied when the RISC completes the
  10028. * SG elements that fit and halts.
  10029. */
  10030. if (sg_entry_cnt > ASC_MAX_SG_LIST) {
  10031. sg_entry_cnt = ASC_MAX_SG_LIST;
  10032. }
  10033. #endif /* CC_VERY_LONG_SG_LIST */
  10034. n_q_required = AscSgListToQueue(sg_entry_cnt);
  10035. if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
  10036. (uint) n_q_required)
  10037. || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
  10038. if ((sta =
  10039. AscSendScsiQueue(asc_dvc, scsiq,
  10040. n_q_required)) == 1) {
  10041. asc_dvc->in_critical_cnt--;
  10042. return (sta);
  10043. }
  10044. }
  10045. } else {
  10046. if (asc_dvc->bug_fix_cntl) {
  10047. if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
  10048. if ((scsi_cmd == READ_6) ||
  10049. (scsi_cmd == READ_10)) {
  10050. addr =
  10051. le32_to_cpu(scsiq->q1.data_addr) +
  10052. le32_to_cpu(scsiq->q1.data_cnt);
  10053. extra_bytes =
  10054. (uchar)((ushort)addr & 0x0003);
  10055. if ((extra_bytes != 0)
  10056. &&
  10057. ((scsiq->q2.
  10058. tag_code &
  10059. ASC_TAG_FLAG_EXTRA_BYTES)
  10060. == 0)) {
  10061. data_cnt =
  10062. le32_to_cpu(scsiq->q1.
  10063. data_cnt);
  10064. if (((ushort)data_cnt & 0x01FF)
  10065. == 0) {
  10066. scsiq->q2.tag_code |=
  10067. ASC_TAG_FLAG_EXTRA_BYTES;
  10068. data_cnt -= (ASC_DCNT)
  10069. extra_bytes;
  10070. scsiq->q1.data_cnt =
  10071. cpu_to_le32
  10072. (data_cnt);
  10073. scsiq->q1.extra_bytes =
  10074. extra_bytes;
  10075. }
  10076. }
  10077. }
  10078. }
  10079. }
  10080. n_q_required = 1;
  10081. if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
  10082. ((scsiq->q1.cntl & QC_URGENT) != 0)) {
  10083. if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
  10084. n_q_required)) == 1) {
  10085. asc_dvc->in_critical_cnt--;
  10086. return (sta);
  10087. }
  10088. }
  10089. }
  10090. asc_dvc->in_critical_cnt--;
  10091. return (sta);
  10092. }
  10093. /*
  10094. * AdvExeScsiQueue() - Send a request to the RISC microcode program.
  10095. *
  10096. * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
  10097. * add the carrier to the ICQ (Initiator Command Queue), and tickle the
  10098. * RISC to notify it a new command is ready to be executed.
  10099. *
  10100. * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
  10101. * set to SCSI_MAX_RETRY.
  10102. *
  10103. * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
  10104. * for DMA addresses or math operations are byte swapped to little-endian
  10105. * order.
  10106. *
  10107. * Return:
  10108. * ADV_SUCCESS(1) - The request was successfully queued.
  10109. * ADV_BUSY(0) - Resource unavailable; Retry again after pending
  10110. * request completes.
  10111. * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
  10112. * host IC error.
  10113. */
  10114. static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
  10115. {
  10116. AdvPortAddr iop_base;
  10117. ADV_DCNT req_size;
  10118. ADV_PADDR req_paddr;
  10119. ADV_CARR_T *new_carrp;
  10120. /*
  10121. * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
  10122. */
  10123. if (scsiq->target_id > ADV_MAX_TID) {
  10124. scsiq->host_status = QHSTA_M_INVALID_DEVICE;
  10125. scsiq->done_status = QD_WITH_ERROR;
  10126. return ADV_ERROR;
  10127. }
  10128. iop_base = asc_dvc->iop_base;
  10129. /*
  10130. * Allocate a carrier ensuring at least one carrier always
  10131. * remains on the freelist and initialize fields.
  10132. */
  10133. if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
  10134. return ADV_BUSY;
  10135. }
  10136. asc_dvc->carr_freelist = (ADV_CARR_T *)
  10137. ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
  10138. asc_dvc->carr_pending_cnt++;
  10139. /*
  10140. * Set the carrier to be a stopper by setting 'next_vpa'
  10141. * to the stopper value. The current stopper will be changed
  10142. * below to point to the new stopper.
  10143. */
  10144. new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
  10145. /*
  10146. * Clear the ADV_SCSI_REQ_Q done flag.
  10147. */
  10148. scsiq->a_flag &= ~ADV_SCSIQ_DONE;
  10149. req_size = sizeof(ADV_SCSI_REQ_Q);
  10150. req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
  10151. (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
  10152. BUG_ON(req_paddr & 31);
  10153. BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
  10154. /* Wait for assertion before making little-endian */
  10155. req_paddr = cpu_to_le32(req_paddr);
  10156. /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
  10157. scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
  10158. scsiq->scsiq_rptr = req_paddr;
  10159. scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
  10160. /*
  10161. * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
  10162. * order during initialization.
  10163. */
  10164. scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
  10165. /*
  10166. * Use the current stopper to send the ADV_SCSI_REQ_Q command to
  10167. * the microcode. The newly allocated stopper will become the new
  10168. * stopper.
  10169. */
  10170. asc_dvc->icq_sp->areq_vpa = req_paddr;
  10171. /*
  10172. * Set the 'next_vpa' pointer for the old stopper to be the
  10173. * physical address of the new stopper. The RISC can only
  10174. * follow physical addresses.
  10175. */
  10176. asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
  10177. /*
  10178. * Set the host adapter stopper pointer to point to the new carrier.
  10179. */
  10180. asc_dvc->icq_sp = new_carrp;
  10181. if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
  10182. asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
  10183. /*
  10184. * Tickle the RISC to tell it to read its Command Queue Head pointer.
  10185. */
  10186. AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
  10187. if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
  10188. /*
  10189. * Clear the tickle value. In the ASC-3550 the RISC flag
  10190. * command 'clr_tickle_a' does not work unless the host
  10191. * value is cleared.
  10192. */
  10193. AdvWriteByteRegister(iop_base, IOPB_TICKLE,
  10194. ADV_TICKLE_NOP);
  10195. }
  10196. } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
  10197. /*
  10198. * Notify the RISC a carrier is ready by writing the physical
  10199. * address of the new carrier stopper to the COMMA register.
  10200. */
  10201. AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
  10202. le32_to_cpu(new_carrp->carr_pa));
  10203. }
  10204. return ADV_SUCCESS;
  10205. }
  10206. /*
  10207. * Execute a single 'Scsi_Cmnd'.
  10208. *
  10209. * The function 'done' is called when the request has been completed.
  10210. *
  10211. * Scsi_Cmnd:
  10212. *
  10213. * host - board controlling device
  10214. * device - device to send command
  10215. * target - target of device
  10216. * lun - lun of device
  10217. * cmd_len - length of SCSI CDB
  10218. * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
  10219. * use_sg - if non-zero indicates scatter-gather request with use_sg elements
  10220. *
  10221. * if (use_sg == 0) {
  10222. * request_buffer - buffer address for request
  10223. * request_bufflen - length of request buffer
  10224. * } else {
  10225. * request_buffer - pointer to scatterlist structure
  10226. * }
  10227. *
  10228. * sense_buffer - sense command buffer
  10229. *
  10230. * result (4 bytes of an int):
  10231. * Byte Meaning
  10232. * 0 SCSI Status Byte Code
  10233. * 1 SCSI One Byte Message Code
  10234. * 2 Host Error Code
  10235. * 3 Mid-Level Error Code
  10236. *
  10237. * host driver fields:
  10238. * SCp - Scsi_Pointer used for command processing status
  10239. * scsi_done - used to save caller's done function
  10240. * host_scribble - used for pointer to another struct scsi_cmnd
  10241. *
  10242. * If this function returns ASC_NOERROR the request will be completed
  10243. * from the interrupt handler.
  10244. *
  10245. * If this function returns ASC_ERROR the host error code has been set,
  10246. * and the called must call asc_scsi_done.
  10247. *
  10248. * If ASC_BUSY is returned the request will be returned to the midlayer
  10249. * and re-tried later.
  10250. */
  10251. static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
  10252. {
  10253. int ret, err_code;
  10254. struct asc_board *boardp = shost_priv(scp->device->host);
  10255. ASC_DBG1(1, "asc_execute_scsi_cmnd: scp 0x%p\n", scp);
  10256. if (ASC_NARROW_BOARD(boardp)) {
  10257. ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
  10258. struct asc_scsi_q asc_scsi_q;
  10259. /* asc_build_req() can not return ASC_BUSY. */
  10260. ret = asc_build_req(boardp, scp, &asc_scsi_q);
  10261. if (ret == ASC_ERROR) {
  10262. ASC_STATS(scp->device->host, build_error);
  10263. return ASC_ERROR;
  10264. }
  10265. ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
  10266. kfree(asc_scsi_q.sg_head);
  10267. err_code = asc_dvc->err_code;
  10268. } else {
  10269. ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
  10270. ADV_SCSI_REQ_Q *adv_scsiqp;
  10271. switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
  10272. case ASC_NOERROR:
  10273. ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req "
  10274. "ASC_NOERROR\n");
  10275. break;
  10276. case ASC_BUSY:
  10277. ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
  10278. "ASC_BUSY\n");
  10279. /*
  10280. * The asc_stats fields 'adv_build_noreq' and
  10281. * 'adv_build_nosg' count wide board busy conditions.
  10282. * They are updated in adv_build_req and
  10283. * adv_get_sglist, respectively.
  10284. */
  10285. return ASC_BUSY;
  10286. case ASC_ERROR:
  10287. default:
  10288. ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
  10289. "ASC_ERROR\n");
  10290. ASC_STATS(scp->device->host, build_error);
  10291. return ASC_ERROR;
  10292. }
  10293. ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
  10294. err_code = adv_dvc->err_code;
  10295. }
  10296. switch (ret) {
  10297. case ASC_NOERROR:
  10298. ASC_STATS(scp->device->host, exe_noerror);
  10299. /*
  10300. * Increment monotonically increasing per device
  10301. * successful request counter. Wrapping doesn't matter.
  10302. */
  10303. boardp->reqcnt[scp->device->id]++;
  10304. ASC_DBG(1, "asc_execute_scsi_cmnd: ExeScsiQueue(), "
  10305. "ASC_NOERROR\n");
  10306. break;
  10307. case ASC_BUSY:
  10308. ASC_STATS(scp->device->host, exe_busy);
  10309. break;
  10310. case ASC_ERROR:
  10311. ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
  10312. "ASC_ERROR, err_code 0x%x\n", boardp->id, err_code);
  10313. ASC_STATS(scp->device->host, exe_error);
  10314. scp->result = HOST_BYTE(DID_ERROR);
  10315. break;
  10316. default:
  10317. ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
  10318. "unknown, err_code 0x%x\n", boardp->id, err_code);
  10319. ASC_STATS(scp->device->host, exe_unknown);
  10320. scp->result = HOST_BYTE(DID_ERROR);
  10321. break;
  10322. }
  10323. ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
  10324. return ret;
  10325. }
  10326. /*
  10327. * advansys_queuecommand() - interrupt-driven I/O entrypoint.
  10328. *
  10329. * This function always returns 0. Command return status is saved
  10330. * in the 'scp' result field.
  10331. */
  10332. static int
  10333. advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
  10334. {
  10335. struct Scsi_Host *shost = scp->device->host;
  10336. struct asc_board *boardp = shost_priv(shost);
  10337. unsigned long flags;
  10338. int asc_res, result = 0;
  10339. ASC_STATS(shost, queuecommand);
  10340. scp->scsi_done = done;
  10341. /*
  10342. * host_lock taken by mid-level prior to call, but need
  10343. * to protect against own ISR
  10344. */
  10345. spin_lock_irqsave(&boardp->lock, flags);
  10346. asc_res = asc_execute_scsi_cmnd(scp);
  10347. spin_unlock_irqrestore(&boardp->lock, flags);
  10348. switch (asc_res) {
  10349. case ASC_NOERROR:
  10350. break;
  10351. case ASC_BUSY:
  10352. result = SCSI_MLQUEUE_HOST_BUSY;
  10353. break;
  10354. case ASC_ERROR:
  10355. default:
  10356. asc_scsi_done(scp);
  10357. break;
  10358. }
  10359. return result;
  10360. }
  10361. static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
  10362. {
  10363. PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
  10364. (PortAddr) (ASC_EISA_CFG_IOP_MASK);
  10365. return inpw(eisa_cfg_iop);
  10366. }
  10367. /*
  10368. * Return the BIOS address of the adapter at the specified
  10369. * I/O port and with the specified bus type.
  10370. */
  10371. static unsigned short __devinit
  10372. AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
  10373. {
  10374. unsigned short cfg_lsw;
  10375. unsigned short bios_addr;
  10376. /*
  10377. * The PCI BIOS is re-located by the motherboard BIOS. Because
  10378. * of this the driver can not determine where a PCI BIOS is
  10379. * loaded and executes.
  10380. */
  10381. if (bus_type & ASC_IS_PCI)
  10382. return 0;
  10383. if ((bus_type & ASC_IS_EISA) != 0) {
  10384. cfg_lsw = AscGetEisaChipCfg(iop_base);
  10385. cfg_lsw &= 0x000F;
  10386. bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
  10387. return bios_addr;
  10388. }
  10389. cfg_lsw = AscGetChipCfgLsw(iop_base);
  10390. /*
  10391. * ISA PnP uses the top bit as the 32K BIOS flag
  10392. */
  10393. if (bus_type == ASC_IS_ISAPNP)
  10394. cfg_lsw &= 0x7FFF;
  10395. bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
  10396. return bios_addr;
  10397. }
  10398. static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
  10399. {
  10400. ushort cfg_lsw;
  10401. if (AscGetChipScsiID(iop_base) == new_host_id) {
  10402. return (new_host_id);
  10403. }
  10404. cfg_lsw = AscGetChipCfgLsw(iop_base);
  10405. cfg_lsw &= 0xF8FF;
  10406. cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
  10407. AscSetChipCfgLsw(iop_base, cfg_lsw);
  10408. return (AscGetChipScsiID(iop_base));
  10409. }
  10410. static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
  10411. {
  10412. unsigned char sc;
  10413. AscSetBank(iop_base, 1);
  10414. sc = inp(iop_base + IOP_REG_SC);
  10415. AscSetBank(iop_base, 0);
  10416. return sc;
  10417. }
  10418. static unsigned char __devinit
  10419. AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
  10420. {
  10421. if (bus_type & ASC_IS_EISA) {
  10422. PortAddr eisa_iop;
  10423. unsigned char revision;
  10424. eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
  10425. (PortAddr) ASC_EISA_REV_IOP_MASK;
  10426. revision = inp(eisa_iop);
  10427. return ASC_CHIP_MIN_VER_EISA - 1 + revision;
  10428. }
  10429. return AscGetChipVerNo(iop_base);
  10430. }
  10431. #ifdef CONFIG_ISA
  10432. static void __devinit AscEnableIsaDma(uchar dma_channel)
  10433. {
  10434. if (dma_channel < 4) {
  10435. outp(0x000B, (ushort)(0xC0 | dma_channel));
  10436. outp(0x000A, dma_channel);
  10437. } else if (dma_channel < 8) {
  10438. outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
  10439. outp(0x00D4, (ushort)(dma_channel - 4));
  10440. }
  10441. return;
  10442. }
  10443. #endif /* CONFIG_ISA */
  10444. static int AscStopQueueExe(PortAddr iop_base)
  10445. {
  10446. int count = 0;
  10447. if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
  10448. AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
  10449. ASC_STOP_REQ_RISC_STOP);
  10450. do {
  10451. if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
  10452. ASC_STOP_ACK_RISC_STOP) {
  10453. return (1);
  10454. }
  10455. mdelay(100);
  10456. } while (count++ < 20);
  10457. }
  10458. return (0);
  10459. }
  10460. static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
  10461. {
  10462. if (bus_type & ASC_IS_ISA)
  10463. return ASC_MAX_ISA_DMA_COUNT;
  10464. else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
  10465. return ASC_MAX_VL_DMA_COUNT;
  10466. return ASC_MAX_PCI_DMA_COUNT;
  10467. }
  10468. #ifdef CONFIG_ISA
  10469. static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
  10470. {
  10471. ushort channel;
  10472. channel = AscGetChipCfgLsw(iop_base) & 0x0003;
  10473. if (channel == 0x03)
  10474. return (0);
  10475. else if (channel == 0x00)
  10476. return (7);
  10477. return (channel + 4);
  10478. }
  10479. static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
  10480. {
  10481. ushort cfg_lsw;
  10482. uchar value;
  10483. if ((dma_channel >= 5) && (dma_channel <= 7)) {
  10484. if (dma_channel == 7)
  10485. value = 0x00;
  10486. else
  10487. value = dma_channel - 4;
  10488. cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
  10489. cfg_lsw |= value;
  10490. AscSetChipCfgLsw(iop_base, cfg_lsw);
  10491. return (AscGetIsaDmaChannel(iop_base));
  10492. }
  10493. return 0;
  10494. }
  10495. static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
  10496. {
  10497. uchar speed_value;
  10498. AscSetBank(iop_base, 1);
  10499. speed_value = AscReadChipDmaSpeed(iop_base);
  10500. speed_value &= 0x07;
  10501. AscSetBank(iop_base, 0);
  10502. return speed_value;
  10503. }
  10504. static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
  10505. {
  10506. speed_value &= 0x07;
  10507. AscSetBank(iop_base, 1);
  10508. AscWriteChipDmaSpeed(iop_base, speed_value);
  10509. AscSetBank(iop_base, 0);
  10510. return AscGetIsaDmaSpeed(iop_base);
  10511. }
  10512. #endif /* CONFIG_ISA */
  10513. static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
  10514. {
  10515. int i;
  10516. PortAddr iop_base;
  10517. ushort warn_code;
  10518. uchar chip_version;
  10519. iop_base = asc_dvc->iop_base;
  10520. warn_code = 0;
  10521. asc_dvc->err_code = 0;
  10522. if ((asc_dvc->bus_type &
  10523. (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
  10524. asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
  10525. }
  10526. AscSetChipControl(iop_base, CC_HALT);
  10527. AscSetChipStatus(iop_base, 0);
  10528. asc_dvc->bug_fix_cntl = 0;
  10529. asc_dvc->pci_fix_asyn_xfer = 0;
  10530. asc_dvc->pci_fix_asyn_xfer_always = 0;
  10531. /* asc_dvc->init_state initalized in AscInitGetConfig(). */
  10532. asc_dvc->sdtr_done = 0;
  10533. asc_dvc->cur_total_qng = 0;
  10534. asc_dvc->is_in_int = 0;
  10535. asc_dvc->in_critical_cnt = 0;
  10536. asc_dvc->last_q_shortage = 0;
  10537. asc_dvc->use_tagged_qng = 0;
  10538. asc_dvc->no_scam = 0;
  10539. asc_dvc->unit_not_ready = 0;
  10540. asc_dvc->queue_full_or_busy = 0;
  10541. asc_dvc->redo_scam = 0;
  10542. asc_dvc->res2 = 0;
  10543. asc_dvc->host_init_sdtr_index = 0;
  10544. asc_dvc->cfg->can_tagged_qng = 0;
  10545. asc_dvc->cfg->cmd_qng_enabled = 0;
  10546. asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
  10547. asc_dvc->init_sdtr = 0;
  10548. asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
  10549. asc_dvc->scsi_reset_wait = 3;
  10550. asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
  10551. asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
  10552. asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
  10553. asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
  10554. asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
  10555. chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
  10556. asc_dvc->cfg->chip_version = chip_version;
  10557. asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
  10558. asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
  10559. asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
  10560. asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
  10561. asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
  10562. asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
  10563. asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
  10564. asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
  10565. asc_dvc->max_sdtr_index = 7;
  10566. if ((asc_dvc->bus_type & ASC_IS_PCI) &&
  10567. (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
  10568. asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
  10569. asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
  10570. asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
  10571. asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
  10572. asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
  10573. asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
  10574. asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
  10575. asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
  10576. asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
  10577. asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
  10578. asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
  10579. asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
  10580. asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
  10581. asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
  10582. asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
  10583. asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
  10584. asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
  10585. asc_dvc->max_sdtr_index = 15;
  10586. if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
  10587. AscSetExtraControl(iop_base,
  10588. (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
  10589. } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
  10590. AscSetExtraControl(iop_base,
  10591. (SEC_ACTIVE_NEGATE |
  10592. SEC_ENABLE_FILTER));
  10593. }
  10594. }
  10595. if (asc_dvc->bus_type == ASC_IS_PCI) {
  10596. AscSetExtraControl(iop_base,
  10597. (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
  10598. }
  10599. asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
  10600. #ifdef CONFIG_ISA
  10601. if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
  10602. if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
  10603. AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
  10604. asc_dvc->bus_type = ASC_IS_ISAPNP;
  10605. }
  10606. asc_dvc->cfg->isa_dma_channel =
  10607. (uchar)AscGetIsaDmaChannel(iop_base);
  10608. }
  10609. #endif /* CONFIG_ISA */
  10610. for (i = 0; i <= ASC_MAX_TID; i++) {
  10611. asc_dvc->cur_dvc_qng[i] = 0;
  10612. asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
  10613. asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
  10614. asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
  10615. asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
  10616. }
  10617. return warn_code;
  10618. }
  10619. static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
  10620. {
  10621. int retry;
  10622. for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
  10623. unsigned char read_back;
  10624. AscSetChipEEPCmd(iop_base, cmd_reg);
  10625. mdelay(1);
  10626. read_back = AscGetChipEEPCmd(iop_base);
  10627. if (read_back == cmd_reg)
  10628. return 1;
  10629. }
  10630. return 0;
  10631. }
  10632. static void __devinit AscWaitEEPRead(void)
  10633. {
  10634. mdelay(1);
  10635. }
  10636. static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
  10637. {
  10638. ushort read_wval;
  10639. uchar cmd_reg;
  10640. AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
  10641. AscWaitEEPRead();
  10642. cmd_reg = addr | ASC_EEP_CMD_READ;
  10643. AscWriteEEPCmdReg(iop_base, cmd_reg);
  10644. AscWaitEEPRead();
  10645. read_wval = AscGetChipEEPData(iop_base);
  10646. AscWaitEEPRead();
  10647. return read_wval;
  10648. }
  10649. static ushort __devinit
  10650. AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
  10651. {
  10652. ushort wval;
  10653. ushort sum;
  10654. ushort *wbuf;
  10655. int cfg_beg;
  10656. int cfg_end;
  10657. int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
  10658. int s_addr;
  10659. wbuf = (ushort *)cfg_buf;
  10660. sum = 0;
  10661. /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
  10662. for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
  10663. *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
  10664. sum += *wbuf;
  10665. }
  10666. if (bus_type & ASC_IS_VL) {
  10667. cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
  10668. cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
  10669. } else {
  10670. cfg_beg = ASC_EEP_DVC_CFG_BEG;
  10671. cfg_end = ASC_EEP_MAX_DVC_ADDR;
  10672. }
  10673. for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
  10674. wval = AscReadEEPWord(iop_base, (uchar)s_addr);
  10675. if (s_addr <= uchar_end_in_config) {
  10676. /*
  10677. * Swap all char fields - must unswap bytes already swapped
  10678. * by AscReadEEPWord().
  10679. */
  10680. *wbuf = le16_to_cpu(wval);
  10681. } else {
  10682. /* Don't swap word field at the end - cntl field. */
  10683. *wbuf = wval;
  10684. }
  10685. sum += wval; /* Checksum treats all EEPROM data as words. */
  10686. }
  10687. /*
  10688. * Read the checksum word which will be compared against 'sum'
  10689. * by the caller. Word field already swapped.
  10690. */
  10691. *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
  10692. return sum;
  10693. }
  10694. static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
  10695. {
  10696. PortAddr iop_base;
  10697. ushort q_addr;
  10698. ushort saved_word;
  10699. int sta;
  10700. iop_base = asc_dvc->iop_base;
  10701. sta = 0;
  10702. q_addr = ASC_QNO_TO_QADDR(241);
  10703. saved_word = AscReadLramWord(iop_base, q_addr);
  10704. AscSetChipLramAddr(iop_base, q_addr);
  10705. AscSetChipLramData(iop_base, 0x55AA);
  10706. mdelay(10);
  10707. AscSetChipLramAddr(iop_base, q_addr);
  10708. if (AscGetChipLramData(iop_base) == 0x55AA) {
  10709. sta = 1;
  10710. AscWriteLramWord(iop_base, q_addr, saved_word);
  10711. }
  10712. return (sta);
  10713. }
  10714. static void __devinit AscWaitEEPWrite(void)
  10715. {
  10716. mdelay(20);
  10717. return;
  10718. }
  10719. static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
  10720. {
  10721. ushort read_back;
  10722. int retry;
  10723. retry = 0;
  10724. while (TRUE) {
  10725. AscSetChipEEPData(iop_base, data_reg);
  10726. mdelay(1);
  10727. read_back = AscGetChipEEPData(iop_base);
  10728. if (read_back == data_reg) {
  10729. return (1);
  10730. }
  10731. if (retry++ > ASC_EEP_MAX_RETRY) {
  10732. return (0);
  10733. }
  10734. }
  10735. }
  10736. static ushort __devinit
  10737. AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
  10738. {
  10739. ushort read_wval;
  10740. read_wval = AscReadEEPWord(iop_base, addr);
  10741. if (read_wval != word_val) {
  10742. AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
  10743. AscWaitEEPRead();
  10744. AscWriteEEPDataReg(iop_base, word_val);
  10745. AscWaitEEPRead();
  10746. AscWriteEEPCmdReg(iop_base,
  10747. (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
  10748. AscWaitEEPWrite();
  10749. AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
  10750. AscWaitEEPRead();
  10751. return (AscReadEEPWord(iop_base, addr));
  10752. }
  10753. return (read_wval);
  10754. }
  10755. static int __devinit
  10756. AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
  10757. {
  10758. int n_error;
  10759. ushort *wbuf;
  10760. ushort word;
  10761. ushort sum;
  10762. int s_addr;
  10763. int cfg_beg;
  10764. int cfg_end;
  10765. int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
  10766. wbuf = (ushort *)cfg_buf;
  10767. n_error = 0;
  10768. sum = 0;
  10769. /* Write two config words; AscWriteEEPWord() will swap bytes. */
  10770. for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
  10771. sum += *wbuf;
  10772. if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
  10773. n_error++;
  10774. }
  10775. }
  10776. if (bus_type & ASC_IS_VL) {
  10777. cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
  10778. cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
  10779. } else {
  10780. cfg_beg = ASC_EEP_DVC_CFG_BEG;
  10781. cfg_end = ASC_EEP_MAX_DVC_ADDR;
  10782. }
  10783. for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
  10784. if (s_addr <= uchar_end_in_config) {
  10785. /*
  10786. * This is a char field. Swap char fields before they are
  10787. * swapped again by AscWriteEEPWord().
  10788. */
  10789. word = cpu_to_le16(*wbuf);
  10790. if (word !=
  10791. AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
  10792. n_error++;
  10793. }
  10794. } else {
  10795. /* Don't swap word field at the end - cntl field. */
  10796. if (*wbuf !=
  10797. AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
  10798. n_error++;
  10799. }
  10800. }
  10801. sum += *wbuf; /* Checksum calculated from word values. */
  10802. }
  10803. /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
  10804. *wbuf = sum;
  10805. if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
  10806. n_error++;
  10807. }
  10808. /* Read EEPROM back again. */
  10809. wbuf = (ushort *)cfg_buf;
  10810. /*
  10811. * Read two config words; Byte-swapping done by AscReadEEPWord().
  10812. */
  10813. for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
  10814. if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
  10815. n_error++;
  10816. }
  10817. }
  10818. if (bus_type & ASC_IS_VL) {
  10819. cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
  10820. cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
  10821. } else {
  10822. cfg_beg = ASC_EEP_DVC_CFG_BEG;
  10823. cfg_end = ASC_EEP_MAX_DVC_ADDR;
  10824. }
  10825. for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
  10826. if (s_addr <= uchar_end_in_config) {
  10827. /*
  10828. * Swap all char fields. Must unswap bytes already swapped
  10829. * by AscReadEEPWord().
  10830. */
  10831. word =
  10832. le16_to_cpu(AscReadEEPWord
  10833. (iop_base, (uchar)s_addr));
  10834. } else {
  10835. /* Don't swap word field at the end - cntl field. */
  10836. word = AscReadEEPWord(iop_base, (uchar)s_addr);
  10837. }
  10838. if (*wbuf != word) {
  10839. n_error++;
  10840. }
  10841. }
  10842. /* Read checksum; Byte swapping not needed. */
  10843. if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
  10844. n_error++;
  10845. }
  10846. return n_error;
  10847. }
  10848. static int __devinit
  10849. AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
  10850. {
  10851. int retry;
  10852. int n_error;
  10853. retry = 0;
  10854. while (TRUE) {
  10855. if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
  10856. bus_type)) == 0) {
  10857. break;
  10858. }
  10859. if (++retry > ASC_EEP_MAX_RETRY) {
  10860. break;
  10861. }
  10862. }
  10863. return n_error;
  10864. }
  10865. static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
  10866. {
  10867. ASCEEP_CONFIG eep_config_buf;
  10868. ASCEEP_CONFIG *eep_config;
  10869. PortAddr iop_base;
  10870. ushort chksum;
  10871. ushort warn_code;
  10872. ushort cfg_msw, cfg_lsw;
  10873. int i;
  10874. int write_eep = 0;
  10875. iop_base = asc_dvc->iop_base;
  10876. warn_code = 0;
  10877. AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
  10878. AscStopQueueExe(iop_base);
  10879. if ((AscStopChip(iop_base) == FALSE) ||
  10880. (AscGetChipScsiCtrl(iop_base) != 0)) {
  10881. asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
  10882. AscResetChipAndScsiBus(asc_dvc);
  10883. mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
  10884. }
  10885. if (AscIsChipHalted(iop_base) == FALSE) {
  10886. asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
  10887. return (warn_code);
  10888. }
  10889. AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
  10890. if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
  10891. asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
  10892. return (warn_code);
  10893. }
  10894. eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
  10895. cfg_msw = AscGetChipCfgMsw(iop_base);
  10896. cfg_lsw = AscGetChipCfgLsw(iop_base);
  10897. if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
  10898. cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
  10899. warn_code |= ASC_WARN_CFG_MSW_RECOVER;
  10900. AscSetChipCfgMsw(iop_base, cfg_msw);
  10901. }
  10902. chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
  10903. ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
  10904. if (chksum == 0) {
  10905. chksum = 0xaa55;
  10906. }
  10907. if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
  10908. warn_code |= ASC_WARN_AUTO_CONFIG;
  10909. if (asc_dvc->cfg->chip_version == 3) {
  10910. if (eep_config->cfg_lsw != cfg_lsw) {
  10911. warn_code |= ASC_WARN_EEPROM_RECOVER;
  10912. eep_config->cfg_lsw =
  10913. AscGetChipCfgLsw(iop_base);
  10914. }
  10915. if (eep_config->cfg_msw != cfg_msw) {
  10916. warn_code |= ASC_WARN_EEPROM_RECOVER;
  10917. eep_config->cfg_msw =
  10918. AscGetChipCfgMsw(iop_base);
  10919. }
  10920. }
  10921. }
  10922. eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
  10923. eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
  10924. ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
  10925. eep_config->chksum);
  10926. if (chksum != eep_config->chksum) {
  10927. if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
  10928. ASC_CHIP_VER_PCI_ULTRA_3050) {
  10929. ASC_DBG(1,
  10930. "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
  10931. eep_config->init_sdtr = 0xFF;
  10932. eep_config->disc_enable = 0xFF;
  10933. eep_config->start_motor = 0xFF;
  10934. eep_config->use_cmd_qng = 0;
  10935. eep_config->max_total_qng = 0xF0;
  10936. eep_config->max_tag_qng = 0x20;
  10937. eep_config->cntl = 0xBFFF;
  10938. ASC_EEP_SET_CHIP_ID(eep_config, 7);
  10939. eep_config->no_scam = 0;
  10940. eep_config->adapter_info[0] = 0;
  10941. eep_config->adapter_info[1] = 0;
  10942. eep_config->adapter_info[2] = 0;
  10943. eep_config->adapter_info[3] = 0;
  10944. eep_config->adapter_info[4] = 0;
  10945. /* Indicate EEPROM-less board. */
  10946. eep_config->adapter_info[5] = 0xBB;
  10947. } else {
  10948. ASC_PRINT
  10949. ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
  10950. write_eep = 1;
  10951. warn_code |= ASC_WARN_EEPROM_CHKSUM;
  10952. }
  10953. }
  10954. asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
  10955. asc_dvc->cfg->disc_enable = eep_config->disc_enable;
  10956. asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
  10957. asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
  10958. asc_dvc->start_motor = eep_config->start_motor;
  10959. asc_dvc->dvc_cntl = eep_config->cntl;
  10960. asc_dvc->no_scam = eep_config->no_scam;
  10961. asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
  10962. asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
  10963. asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
  10964. asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
  10965. asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
  10966. asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
  10967. if (!AscTestExternalLram(asc_dvc)) {
  10968. if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
  10969. ASC_IS_PCI_ULTRA)) {
  10970. eep_config->max_total_qng =
  10971. ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
  10972. eep_config->max_tag_qng =
  10973. ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
  10974. } else {
  10975. eep_config->cfg_msw |= 0x0800;
  10976. cfg_msw |= 0x0800;
  10977. AscSetChipCfgMsw(iop_base, cfg_msw);
  10978. eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
  10979. eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
  10980. }
  10981. } else {
  10982. }
  10983. if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
  10984. eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
  10985. }
  10986. if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
  10987. eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
  10988. }
  10989. if (eep_config->max_tag_qng > eep_config->max_total_qng) {
  10990. eep_config->max_tag_qng = eep_config->max_total_qng;
  10991. }
  10992. if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
  10993. eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
  10994. }
  10995. asc_dvc->max_total_qng = eep_config->max_total_qng;
  10996. if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
  10997. eep_config->use_cmd_qng) {
  10998. eep_config->disc_enable = eep_config->use_cmd_qng;
  10999. warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
  11000. }
  11001. ASC_EEP_SET_CHIP_ID(eep_config,
  11002. ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
  11003. asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
  11004. if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
  11005. !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
  11006. asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
  11007. }
  11008. for (i = 0; i <= ASC_MAX_TID; i++) {
  11009. asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
  11010. asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
  11011. asc_dvc->cfg->sdtr_period_offset[i] =
  11012. (uchar)(ASC_DEF_SDTR_OFFSET |
  11013. (asc_dvc->host_init_sdtr_index << 4));
  11014. }
  11015. eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
  11016. if (write_eep) {
  11017. if ((i = AscSetEEPConfig(iop_base, eep_config,
  11018. asc_dvc->bus_type)) != 0) {
  11019. ASC_PRINT1
  11020. ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
  11021. i);
  11022. } else {
  11023. ASC_PRINT
  11024. ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
  11025. }
  11026. }
  11027. return (warn_code);
  11028. }
  11029. static int __devinit AscInitGetConfig(struct asc_board *boardp)
  11030. {
  11031. ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
  11032. unsigned short warn_code = 0;
  11033. asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
  11034. if (asc_dvc->err_code != 0)
  11035. return asc_dvc->err_code;
  11036. if (AscFindSignature(asc_dvc->iop_base)) {
  11037. warn_code |= AscInitAscDvcVar(asc_dvc);
  11038. warn_code |= AscInitFromEEP(asc_dvc);
  11039. asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
  11040. if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
  11041. asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
  11042. } else {
  11043. asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
  11044. }
  11045. switch (warn_code) {
  11046. case 0: /* No error */
  11047. break;
  11048. case ASC_WARN_IO_PORT_ROTATE:
  11049. ASC_PRINT1("AscInitGetConfig: board %d: I/O port address "
  11050. "modified\n", boardp->id);
  11051. break;
  11052. case ASC_WARN_AUTO_CONFIG:
  11053. ASC_PRINT1("AscInitGetConfig: board %d: I/O port increment "
  11054. "switch enabled\n", boardp->id);
  11055. break;
  11056. case ASC_WARN_EEPROM_CHKSUM:
  11057. ASC_PRINT1("AscInitGetConfig: board %d: EEPROM checksum "
  11058. "error\n", boardp->id);
  11059. break;
  11060. case ASC_WARN_IRQ_MODIFIED:
  11061. ASC_PRINT1("AscInitGetConfig: board %d: IRQ modified\n",
  11062. boardp->id);
  11063. break;
  11064. case ASC_WARN_CMD_QNG_CONFLICT:
  11065. ASC_PRINT1("AscInitGetConfig: board %d: tag queuing enabled "
  11066. "w/o disconnects\n", boardp->id);
  11067. break;
  11068. default:
  11069. ASC_PRINT2("AscInitGetConfig: board %d: unknown warning: "
  11070. "0x%x\n", boardp->id, warn_code);
  11071. break;
  11072. }
  11073. if (asc_dvc->err_code != 0) {
  11074. ASC_PRINT3("AscInitGetConfig: board %d error: init_state 0x%x, "
  11075. "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
  11076. asc_dvc->err_code);
  11077. }
  11078. return asc_dvc->err_code;
  11079. }
  11080. static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct asc_board *boardp)
  11081. {
  11082. ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
  11083. PortAddr iop_base = asc_dvc->iop_base;
  11084. unsigned short cfg_msw;
  11085. unsigned short warn_code = 0;
  11086. asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
  11087. if (asc_dvc->err_code != 0)
  11088. return asc_dvc->err_code;
  11089. if (!AscFindSignature(asc_dvc->iop_base)) {
  11090. asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
  11091. return asc_dvc->err_code;
  11092. }
  11093. cfg_msw = AscGetChipCfgMsw(iop_base);
  11094. if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
  11095. cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
  11096. warn_code |= ASC_WARN_CFG_MSW_RECOVER;
  11097. AscSetChipCfgMsw(iop_base, cfg_msw);
  11098. }
  11099. if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
  11100. asc_dvc->cfg->cmd_qng_enabled) {
  11101. asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
  11102. warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
  11103. }
  11104. if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
  11105. warn_code |= ASC_WARN_AUTO_CONFIG;
  11106. }
  11107. #ifdef CONFIG_PCI
  11108. if (asc_dvc->bus_type & ASC_IS_PCI) {
  11109. cfg_msw &= 0xFFC0;
  11110. AscSetChipCfgMsw(iop_base, cfg_msw);
  11111. if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
  11112. } else {
  11113. if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
  11114. (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
  11115. asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
  11116. asc_dvc->bug_fix_cntl |=
  11117. ASC_BUG_FIX_ASYN_USE_SYN;
  11118. }
  11119. }
  11120. } else
  11121. #endif /* CONFIG_PCI */
  11122. if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
  11123. if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
  11124. == ASC_CHIP_VER_ASYN_BUG) {
  11125. asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
  11126. }
  11127. }
  11128. if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
  11129. asc_dvc->cfg->chip_scsi_id) {
  11130. asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
  11131. }
  11132. #ifdef CONFIG_ISA
  11133. if (asc_dvc->bus_type & ASC_IS_ISA) {
  11134. AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
  11135. AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
  11136. }
  11137. #endif /* CONFIG_ISA */
  11138. asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
  11139. switch (warn_code) {
  11140. case 0: /* No error. */
  11141. break;
  11142. case ASC_WARN_IO_PORT_ROTATE:
  11143. ASC_PRINT1("AscInitSetConfig: board %d: I/O port address "
  11144. "modified\n", boardp->id);
  11145. break;
  11146. case ASC_WARN_AUTO_CONFIG:
  11147. ASC_PRINT1("AscInitSetConfig: board %d: I/O port increment "
  11148. "switch enabled\n", boardp->id);
  11149. break;
  11150. case ASC_WARN_EEPROM_CHKSUM:
  11151. ASC_PRINT1("AscInitSetConfig: board %d: EEPROM checksum "
  11152. "error\n", boardp->id);
  11153. break;
  11154. case ASC_WARN_IRQ_MODIFIED:
  11155. ASC_PRINT1("AscInitSetConfig: board %d: IRQ modified\n",
  11156. boardp->id);
  11157. break;
  11158. case ASC_WARN_CMD_QNG_CONFLICT:
  11159. ASC_PRINT1("AscInitSetConfig: board %d: tag queuing w/o "
  11160. "disconnects\n",
  11161. boardp->id);
  11162. break;
  11163. default:
  11164. ASC_PRINT2("AscInitSetConfig: board %d: unknown warning: "
  11165. "0x%x\n", boardp->id, warn_code);
  11166. break;
  11167. }
  11168. if (asc_dvc->err_code != 0) {
  11169. ASC_PRINT3("AscInitSetConfig: board %d error: init_state 0x%x, "
  11170. "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
  11171. asc_dvc->err_code);
  11172. }
  11173. return asc_dvc->err_code;
  11174. }
  11175. /*
  11176. * EEPROM Configuration.
  11177. *
  11178. * All drivers should use this structure to set the default EEPROM
  11179. * configuration. The BIOS now uses this structure when it is built.
  11180. * Additional structure information can be found in a_condor.h where
  11181. * the structure is defined.
  11182. *
  11183. * The *_Field_IsChar structs are needed to correct for endianness.
  11184. * These values are read from the board 16 bits at a time directly
  11185. * into the structs. Because some fields are char, the values will be
  11186. * in the wrong order. The *_Field_IsChar tells when to flip the
  11187. * bytes. Data read and written to PCI memory is automatically swapped
  11188. * on big-endian platforms so char fields read as words are actually being
  11189. * unswapped on big-endian platforms.
  11190. */
  11191. static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
  11192. ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
  11193. 0x0000, /* cfg_msw */
  11194. 0xFFFF, /* disc_enable */
  11195. 0xFFFF, /* wdtr_able */
  11196. 0xFFFF, /* sdtr_able */
  11197. 0xFFFF, /* start_motor */
  11198. 0xFFFF, /* tagqng_able */
  11199. 0xFFFF, /* bios_scan */
  11200. 0, /* scam_tolerant */
  11201. 7, /* adapter_scsi_id */
  11202. 0, /* bios_boot_delay */
  11203. 3, /* scsi_reset_delay */
  11204. 0, /* bios_id_lun */
  11205. 0, /* termination */
  11206. 0, /* reserved1 */
  11207. 0xFFE7, /* bios_ctrl */
  11208. 0xFFFF, /* ultra_able */
  11209. 0, /* reserved2 */
  11210. ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
  11211. ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
  11212. 0, /* dvc_cntl */
  11213. 0, /* bug_fix */
  11214. 0, /* serial_number_word1 */
  11215. 0, /* serial_number_word2 */
  11216. 0, /* serial_number_word3 */
  11217. 0, /* check_sum */
  11218. {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  11219. , /* oem_name[16] */
  11220. 0, /* dvc_err_code */
  11221. 0, /* adv_err_code */
  11222. 0, /* adv_err_addr */
  11223. 0, /* saved_dvc_err_code */
  11224. 0, /* saved_adv_err_code */
  11225. 0, /* saved_adv_err_addr */
  11226. 0 /* num_of_err */
  11227. };
  11228. static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
  11229. 0, /* cfg_lsw */
  11230. 0, /* cfg_msw */
  11231. 0, /* -disc_enable */
  11232. 0, /* wdtr_able */
  11233. 0, /* sdtr_able */
  11234. 0, /* start_motor */
  11235. 0, /* tagqng_able */
  11236. 0, /* bios_scan */
  11237. 0, /* scam_tolerant */
  11238. 1, /* adapter_scsi_id */
  11239. 1, /* bios_boot_delay */
  11240. 1, /* scsi_reset_delay */
  11241. 1, /* bios_id_lun */
  11242. 1, /* termination */
  11243. 1, /* reserved1 */
  11244. 0, /* bios_ctrl */
  11245. 0, /* ultra_able */
  11246. 0, /* reserved2 */
  11247. 1, /* max_host_qng */
  11248. 1, /* max_dvc_qng */
  11249. 0, /* dvc_cntl */
  11250. 0, /* bug_fix */
  11251. 0, /* serial_number_word1 */
  11252. 0, /* serial_number_word2 */
  11253. 0, /* serial_number_word3 */
  11254. 0, /* check_sum */
  11255. {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
  11256. , /* oem_name[16] */
  11257. 0, /* dvc_err_code */
  11258. 0, /* adv_err_code */
  11259. 0, /* adv_err_addr */
  11260. 0, /* saved_dvc_err_code */
  11261. 0, /* saved_adv_err_code */
  11262. 0, /* saved_adv_err_addr */
  11263. 0 /* num_of_err */
  11264. };
  11265. static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
  11266. ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
  11267. 0x0000, /* 01 cfg_msw */
  11268. 0xFFFF, /* 02 disc_enable */
  11269. 0xFFFF, /* 03 wdtr_able */
  11270. 0x4444, /* 04 sdtr_speed1 */
  11271. 0xFFFF, /* 05 start_motor */
  11272. 0xFFFF, /* 06 tagqng_able */
  11273. 0xFFFF, /* 07 bios_scan */
  11274. 0, /* 08 scam_tolerant */
  11275. 7, /* 09 adapter_scsi_id */
  11276. 0, /* bios_boot_delay */
  11277. 3, /* 10 scsi_reset_delay */
  11278. 0, /* bios_id_lun */
  11279. 0, /* 11 termination_se */
  11280. 0, /* termination_lvd */
  11281. 0xFFE7, /* 12 bios_ctrl */
  11282. 0x4444, /* 13 sdtr_speed2 */
  11283. 0x4444, /* 14 sdtr_speed3 */
  11284. ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
  11285. ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
  11286. 0, /* 16 dvc_cntl */
  11287. 0x4444, /* 17 sdtr_speed4 */
  11288. 0, /* 18 serial_number_word1 */
  11289. 0, /* 19 serial_number_word2 */
  11290. 0, /* 20 serial_number_word3 */
  11291. 0, /* 21 check_sum */
  11292. {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  11293. , /* 22-29 oem_name[16] */
  11294. 0, /* 30 dvc_err_code */
  11295. 0, /* 31 adv_err_code */
  11296. 0, /* 32 adv_err_addr */
  11297. 0, /* 33 saved_dvc_err_code */
  11298. 0, /* 34 saved_adv_err_code */
  11299. 0, /* 35 saved_adv_err_addr */
  11300. 0, /* 36 reserved */
  11301. 0, /* 37 reserved */
  11302. 0, /* 38 reserved */
  11303. 0, /* 39 reserved */
  11304. 0, /* 40 reserved */
  11305. 0, /* 41 reserved */
  11306. 0, /* 42 reserved */
  11307. 0, /* 43 reserved */
  11308. 0, /* 44 reserved */
  11309. 0, /* 45 reserved */
  11310. 0, /* 46 reserved */
  11311. 0, /* 47 reserved */
  11312. 0, /* 48 reserved */
  11313. 0, /* 49 reserved */
  11314. 0, /* 50 reserved */
  11315. 0, /* 51 reserved */
  11316. 0, /* 52 reserved */
  11317. 0, /* 53 reserved */
  11318. 0, /* 54 reserved */
  11319. 0, /* 55 reserved */
  11320. 0, /* 56 cisptr_lsw */
  11321. 0, /* 57 cisprt_msw */
  11322. PCI_VENDOR_ID_ASP, /* 58 subsysvid */
  11323. PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
  11324. 0, /* 60 reserved */
  11325. 0, /* 61 reserved */
  11326. 0, /* 62 reserved */
  11327. 0 /* 63 reserved */
  11328. };
  11329. static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
  11330. 0, /* 00 cfg_lsw */
  11331. 0, /* 01 cfg_msw */
  11332. 0, /* 02 disc_enable */
  11333. 0, /* 03 wdtr_able */
  11334. 0, /* 04 sdtr_speed1 */
  11335. 0, /* 05 start_motor */
  11336. 0, /* 06 tagqng_able */
  11337. 0, /* 07 bios_scan */
  11338. 0, /* 08 scam_tolerant */
  11339. 1, /* 09 adapter_scsi_id */
  11340. 1, /* bios_boot_delay */
  11341. 1, /* 10 scsi_reset_delay */
  11342. 1, /* bios_id_lun */
  11343. 1, /* 11 termination_se */
  11344. 1, /* termination_lvd */
  11345. 0, /* 12 bios_ctrl */
  11346. 0, /* 13 sdtr_speed2 */
  11347. 0, /* 14 sdtr_speed3 */
  11348. 1, /* 15 max_host_qng */
  11349. 1, /* max_dvc_qng */
  11350. 0, /* 16 dvc_cntl */
  11351. 0, /* 17 sdtr_speed4 */
  11352. 0, /* 18 serial_number_word1 */
  11353. 0, /* 19 serial_number_word2 */
  11354. 0, /* 20 serial_number_word3 */
  11355. 0, /* 21 check_sum */
  11356. {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
  11357. , /* 22-29 oem_name[16] */
  11358. 0, /* 30 dvc_err_code */
  11359. 0, /* 31 adv_err_code */
  11360. 0, /* 32 adv_err_addr */
  11361. 0, /* 33 saved_dvc_err_code */
  11362. 0, /* 34 saved_adv_err_code */
  11363. 0, /* 35 saved_adv_err_addr */
  11364. 0, /* 36 reserved */
  11365. 0, /* 37 reserved */
  11366. 0, /* 38 reserved */
  11367. 0, /* 39 reserved */
  11368. 0, /* 40 reserved */
  11369. 0, /* 41 reserved */
  11370. 0, /* 42 reserved */
  11371. 0, /* 43 reserved */
  11372. 0, /* 44 reserved */
  11373. 0, /* 45 reserved */
  11374. 0, /* 46 reserved */
  11375. 0, /* 47 reserved */
  11376. 0, /* 48 reserved */
  11377. 0, /* 49 reserved */
  11378. 0, /* 50 reserved */
  11379. 0, /* 51 reserved */
  11380. 0, /* 52 reserved */
  11381. 0, /* 53 reserved */
  11382. 0, /* 54 reserved */
  11383. 0, /* 55 reserved */
  11384. 0, /* 56 cisptr_lsw */
  11385. 0, /* 57 cisprt_msw */
  11386. 0, /* 58 subsysvid */
  11387. 0, /* 59 subsysid */
  11388. 0, /* 60 reserved */
  11389. 0, /* 61 reserved */
  11390. 0, /* 62 reserved */
  11391. 0 /* 63 reserved */
  11392. };
  11393. static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
  11394. ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
  11395. 0x0000, /* 01 cfg_msw */
  11396. 0xFFFF, /* 02 disc_enable */
  11397. 0xFFFF, /* 03 wdtr_able */
  11398. 0x5555, /* 04 sdtr_speed1 */
  11399. 0xFFFF, /* 05 start_motor */
  11400. 0xFFFF, /* 06 tagqng_able */
  11401. 0xFFFF, /* 07 bios_scan */
  11402. 0, /* 08 scam_tolerant */
  11403. 7, /* 09 adapter_scsi_id */
  11404. 0, /* bios_boot_delay */
  11405. 3, /* 10 scsi_reset_delay */
  11406. 0, /* bios_id_lun */
  11407. 0, /* 11 termination_se */
  11408. 0, /* termination_lvd */
  11409. 0xFFE7, /* 12 bios_ctrl */
  11410. 0x5555, /* 13 sdtr_speed2 */
  11411. 0x5555, /* 14 sdtr_speed3 */
  11412. ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
  11413. ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
  11414. 0, /* 16 dvc_cntl */
  11415. 0x5555, /* 17 sdtr_speed4 */
  11416. 0, /* 18 serial_number_word1 */
  11417. 0, /* 19 serial_number_word2 */
  11418. 0, /* 20 serial_number_word3 */
  11419. 0, /* 21 check_sum */
  11420. {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  11421. , /* 22-29 oem_name[16] */
  11422. 0, /* 30 dvc_err_code */
  11423. 0, /* 31 adv_err_code */
  11424. 0, /* 32 adv_err_addr */
  11425. 0, /* 33 saved_dvc_err_code */
  11426. 0, /* 34 saved_adv_err_code */
  11427. 0, /* 35 saved_adv_err_addr */
  11428. 0, /* 36 reserved */
  11429. 0, /* 37 reserved */
  11430. 0, /* 38 reserved */
  11431. 0, /* 39 reserved */
  11432. 0, /* 40 reserved */
  11433. 0, /* 41 reserved */
  11434. 0, /* 42 reserved */
  11435. 0, /* 43 reserved */
  11436. 0, /* 44 reserved */
  11437. 0, /* 45 reserved */
  11438. 0, /* 46 reserved */
  11439. 0, /* 47 reserved */
  11440. 0, /* 48 reserved */
  11441. 0, /* 49 reserved */
  11442. 0, /* 50 reserved */
  11443. 0, /* 51 reserved */
  11444. 0, /* 52 reserved */
  11445. 0, /* 53 reserved */
  11446. 0, /* 54 reserved */
  11447. 0, /* 55 reserved */
  11448. 0, /* 56 cisptr_lsw */
  11449. 0, /* 57 cisprt_msw */
  11450. PCI_VENDOR_ID_ASP, /* 58 subsysvid */
  11451. PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
  11452. 0, /* 60 reserved */
  11453. 0, /* 61 reserved */
  11454. 0, /* 62 reserved */
  11455. 0 /* 63 reserved */
  11456. };
  11457. static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
  11458. 0, /* 00 cfg_lsw */
  11459. 0, /* 01 cfg_msw */
  11460. 0, /* 02 disc_enable */
  11461. 0, /* 03 wdtr_able */
  11462. 0, /* 04 sdtr_speed1 */
  11463. 0, /* 05 start_motor */
  11464. 0, /* 06 tagqng_able */
  11465. 0, /* 07 bios_scan */
  11466. 0, /* 08 scam_tolerant */
  11467. 1, /* 09 adapter_scsi_id */
  11468. 1, /* bios_boot_delay */
  11469. 1, /* 10 scsi_reset_delay */
  11470. 1, /* bios_id_lun */
  11471. 1, /* 11 termination_se */
  11472. 1, /* termination_lvd */
  11473. 0, /* 12 bios_ctrl */
  11474. 0, /* 13 sdtr_speed2 */
  11475. 0, /* 14 sdtr_speed3 */
  11476. 1, /* 15 max_host_qng */
  11477. 1, /* max_dvc_qng */
  11478. 0, /* 16 dvc_cntl */
  11479. 0, /* 17 sdtr_speed4 */
  11480. 0, /* 18 serial_number_word1 */
  11481. 0, /* 19 serial_number_word2 */
  11482. 0, /* 20 serial_number_word3 */
  11483. 0, /* 21 check_sum */
  11484. {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
  11485. , /* 22-29 oem_name[16] */
  11486. 0, /* 30 dvc_err_code */
  11487. 0, /* 31 adv_err_code */
  11488. 0, /* 32 adv_err_addr */
  11489. 0, /* 33 saved_dvc_err_code */
  11490. 0, /* 34 saved_adv_err_code */
  11491. 0, /* 35 saved_adv_err_addr */
  11492. 0, /* 36 reserved */
  11493. 0, /* 37 reserved */
  11494. 0, /* 38 reserved */
  11495. 0, /* 39 reserved */
  11496. 0, /* 40 reserved */
  11497. 0, /* 41 reserved */
  11498. 0, /* 42 reserved */
  11499. 0, /* 43 reserved */
  11500. 0, /* 44 reserved */
  11501. 0, /* 45 reserved */
  11502. 0, /* 46 reserved */
  11503. 0, /* 47 reserved */
  11504. 0, /* 48 reserved */
  11505. 0, /* 49 reserved */
  11506. 0, /* 50 reserved */
  11507. 0, /* 51 reserved */
  11508. 0, /* 52 reserved */
  11509. 0, /* 53 reserved */
  11510. 0, /* 54 reserved */
  11511. 0, /* 55 reserved */
  11512. 0, /* 56 cisptr_lsw */
  11513. 0, /* 57 cisprt_msw */
  11514. 0, /* 58 subsysvid */
  11515. 0, /* 59 subsysid */
  11516. 0, /* 60 reserved */
  11517. 0, /* 61 reserved */
  11518. 0, /* 62 reserved */
  11519. 0 /* 63 reserved */
  11520. };
  11521. #ifdef CONFIG_PCI
  11522. /*
  11523. * Wait for EEPROM command to complete
  11524. */
  11525. static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
  11526. {
  11527. int eep_delay_ms;
  11528. for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
  11529. if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
  11530. ASC_EEP_CMD_DONE) {
  11531. break;
  11532. }
  11533. mdelay(1);
  11534. }
  11535. if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
  11536. 0)
  11537. BUG();
  11538. }
  11539. /*
  11540. * Read the EEPROM from specified location
  11541. */
  11542. static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
  11543. {
  11544. AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
  11545. ASC_EEP_CMD_READ | eep_word_addr);
  11546. AdvWaitEEPCmd(iop_base);
  11547. return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
  11548. }
  11549. /*
  11550. * Write the EEPROM from 'cfg_buf'.
  11551. */
  11552. void __devinit
  11553. AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
  11554. {
  11555. ushort *wbuf;
  11556. ushort addr, chksum;
  11557. ushort *charfields;
  11558. wbuf = (ushort *)cfg_buf;
  11559. charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
  11560. chksum = 0;
  11561. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
  11562. AdvWaitEEPCmd(iop_base);
  11563. /*
  11564. * Write EEPROM from word 0 to word 20.
  11565. */
  11566. for (addr = ADV_EEP_DVC_CFG_BEGIN;
  11567. addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
  11568. ushort word;
  11569. if (*charfields++) {
  11570. word = cpu_to_le16(*wbuf);
  11571. } else {
  11572. word = *wbuf;
  11573. }
  11574. chksum += *wbuf; /* Checksum is calculated from word values. */
  11575. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
  11576. AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
  11577. ASC_EEP_CMD_WRITE | addr);
  11578. AdvWaitEEPCmd(iop_base);
  11579. mdelay(ADV_EEP_DELAY_MS);
  11580. }
  11581. /*
  11582. * Write EEPROM checksum at word 21.
  11583. */
  11584. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
  11585. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
  11586. AdvWaitEEPCmd(iop_base);
  11587. wbuf++;
  11588. charfields++;
  11589. /*
  11590. * Write EEPROM OEM name at words 22 to 29.
  11591. */
  11592. for (addr = ADV_EEP_DVC_CTL_BEGIN;
  11593. addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
  11594. ushort word;
  11595. if (*charfields++) {
  11596. word = cpu_to_le16(*wbuf);
  11597. } else {
  11598. word = *wbuf;
  11599. }
  11600. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
  11601. AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
  11602. ASC_EEP_CMD_WRITE | addr);
  11603. AdvWaitEEPCmd(iop_base);
  11604. }
  11605. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
  11606. AdvWaitEEPCmd(iop_base);
  11607. }
  11608. /*
  11609. * Write the EEPROM from 'cfg_buf'.
  11610. */
  11611. void __devinit
  11612. AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
  11613. {
  11614. ushort *wbuf;
  11615. ushort *charfields;
  11616. ushort addr, chksum;
  11617. wbuf = (ushort *)cfg_buf;
  11618. charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
  11619. chksum = 0;
  11620. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
  11621. AdvWaitEEPCmd(iop_base);
  11622. /*
  11623. * Write EEPROM from word 0 to word 20.
  11624. */
  11625. for (addr = ADV_EEP_DVC_CFG_BEGIN;
  11626. addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
  11627. ushort word;
  11628. if (*charfields++) {
  11629. word = cpu_to_le16(*wbuf);
  11630. } else {
  11631. word = *wbuf;
  11632. }
  11633. chksum += *wbuf; /* Checksum is calculated from word values. */
  11634. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
  11635. AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
  11636. ASC_EEP_CMD_WRITE | addr);
  11637. AdvWaitEEPCmd(iop_base);
  11638. mdelay(ADV_EEP_DELAY_MS);
  11639. }
  11640. /*
  11641. * Write EEPROM checksum at word 21.
  11642. */
  11643. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
  11644. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
  11645. AdvWaitEEPCmd(iop_base);
  11646. wbuf++;
  11647. charfields++;
  11648. /*
  11649. * Write EEPROM OEM name at words 22 to 29.
  11650. */
  11651. for (addr = ADV_EEP_DVC_CTL_BEGIN;
  11652. addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
  11653. ushort word;
  11654. if (*charfields++) {
  11655. word = cpu_to_le16(*wbuf);
  11656. } else {
  11657. word = *wbuf;
  11658. }
  11659. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
  11660. AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
  11661. ASC_EEP_CMD_WRITE | addr);
  11662. AdvWaitEEPCmd(iop_base);
  11663. }
  11664. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
  11665. AdvWaitEEPCmd(iop_base);
  11666. }
  11667. /*
  11668. * Write the EEPROM from 'cfg_buf'.
  11669. */
  11670. void __devinit
  11671. AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
  11672. {
  11673. ushort *wbuf;
  11674. ushort *charfields;
  11675. ushort addr, chksum;
  11676. wbuf = (ushort *)cfg_buf;
  11677. charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
  11678. chksum = 0;
  11679. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
  11680. AdvWaitEEPCmd(iop_base);
  11681. /*
  11682. * Write EEPROM from word 0 to word 20.
  11683. */
  11684. for (addr = ADV_EEP_DVC_CFG_BEGIN;
  11685. addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
  11686. ushort word;
  11687. if (*charfields++) {
  11688. word = cpu_to_le16(*wbuf);
  11689. } else {
  11690. word = *wbuf;
  11691. }
  11692. chksum += *wbuf; /* Checksum is calculated from word values. */
  11693. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
  11694. AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
  11695. ASC_EEP_CMD_WRITE | addr);
  11696. AdvWaitEEPCmd(iop_base);
  11697. mdelay(ADV_EEP_DELAY_MS);
  11698. }
  11699. /*
  11700. * Write EEPROM checksum at word 21.
  11701. */
  11702. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
  11703. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
  11704. AdvWaitEEPCmd(iop_base);
  11705. wbuf++;
  11706. charfields++;
  11707. /*
  11708. * Write EEPROM OEM name at words 22 to 29.
  11709. */
  11710. for (addr = ADV_EEP_DVC_CTL_BEGIN;
  11711. addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
  11712. ushort word;
  11713. if (*charfields++) {
  11714. word = cpu_to_le16(*wbuf);
  11715. } else {
  11716. word = *wbuf;
  11717. }
  11718. AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
  11719. AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
  11720. ASC_EEP_CMD_WRITE | addr);
  11721. AdvWaitEEPCmd(iop_base);
  11722. }
  11723. AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
  11724. AdvWaitEEPCmd(iop_base);
  11725. }
  11726. /*
  11727. * Read EEPROM configuration into the specified buffer.
  11728. *
  11729. * Return a checksum based on the EEPROM configuration read.
  11730. */
  11731. static ushort __devinit
  11732. AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
  11733. {
  11734. ushort wval, chksum;
  11735. ushort *wbuf;
  11736. int eep_addr;
  11737. ushort *charfields;
  11738. charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
  11739. wbuf = (ushort *)cfg_buf;
  11740. chksum = 0;
  11741. for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
  11742. eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
  11743. wval = AdvReadEEPWord(iop_base, eep_addr);
  11744. chksum += wval; /* Checksum is calculated from word values. */
  11745. if (*charfields++) {
  11746. *wbuf = le16_to_cpu(wval);
  11747. } else {
  11748. *wbuf = wval;
  11749. }
  11750. }
  11751. /* Read checksum word. */
  11752. *wbuf = AdvReadEEPWord(iop_base, eep_addr);
  11753. wbuf++;
  11754. charfields++;
  11755. /* Read rest of EEPROM not covered by the checksum. */
  11756. for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
  11757. eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
  11758. *wbuf = AdvReadEEPWord(iop_base, eep_addr);
  11759. if (*charfields++) {
  11760. *wbuf = le16_to_cpu(*wbuf);
  11761. }
  11762. }
  11763. return chksum;
  11764. }
  11765. /*
  11766. * Read EEPROM configuration into the specified buffer.
  11767. *
  11768. * Return a checksum based on the EEPROM configuration read.
  11769. */
  11770. static ushort __devinit
  11771. AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
  11772. {
  11773. ushort wval, chksum;
  11774. ushort *wbuf;
  11775. int eep_addr;
  11776. ushort *charfields;
  11777. charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
  11778. wbuf = (ushort *)cfg_buf;
  11779. chksum = 0;
  11780. for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
  11781. eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
  11782. wval = AdvReadEEPWord(iop_base, eep_addr);
  11783. chksum += wval; /* Checksum is calculated from word values. */
  11784. if (*charfields++) {
  11785. *wbuf = le16_to_cpu(wval);
  11786. } else {
  11787. *wbuf = wval;
  11788. }
  11789. }
  11790. /* Read checksum word. */
  11791. *wbuf = AdvReadEEPWord(iop_base, eep_addr);
  11792. wbuf++;
  11793. charfields++;
  11794. /* Read rest of EEPROM not covered by the checksum. */
  11795. for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
  11796. eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
  11797. *wbuf = AdvReadEEPWord(iop_base, eep_addr);
  11798. if (*charfields++) {
  11799. *wbuf = le16_to_cpu(*wbuf);
  11800. }
  11801. }
  11802. return chksum;
  11803. }
  11804. /*
  11805. * Read EEPROM configuration into the specified buffer.
  11806. *
  11807. * Return a checksum based on the EEPROM configuration read.
  11808. */
  11809. static ushort __devinit
  11810. AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
  11811. {
  11812. ushort wval, chksum;
  11813. ushort *wbuf;
  11814. int eep_addr;
  11815. ushort *charfields;
  11816. charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
  11817. wbuf = (ushort *)cfg_buf;
  11818. chksum = 0;
  11819. for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
  11820. eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
  11821. wval = AdvReadEEPWord(iop_base, eep_addr);
  11822. chksum += wval; /* Checksum is calculated from word values. */
  11823. if (*charfields++) {
  11824. *wbuf = le16_to_cpu(wval);
  11825. } else {
  11826. *wbuf = wval;
  11827. }
  11828. }
  11829. /* Read checksum word. */
  11830. *wbuf = AdvReadEEPWord(iop_base, eep_addr);
  11831. wbuf++;
  11832. charfields++;
  11833. /* Read rest of EEPROM not covered by the checksum. */
  11834. for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
  11835. eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
  11836. *wbuf = AdvReadEEPWord(iop_base, eep_addr);
  11837. if (*charfields++) {
  11838. *wbuf = le16_to_cpu(*wbuf);
  11839. }
  11840. }
  11841. return chksum;
  11842. }
  11843. /*
  11844. * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
  11845. * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
  11846. * all of this is done.
  11847. *
  11848. * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
  11849. *
  11850. * For a non-fatal error return a warning code. If there are no warnings
  11851. * then 0 is returned.
  11852. *
  11853. * Note: Chip is stopped on entry.
  11854. */
  11855. static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
  11856. {
  11857. AdvPortAddr iop_base;
  11858. ushort warn_code;
  11859. ADVEEP_3550_CONFIG eep_config;
  11860. iop_base = asc_dvc->iop_base;
  11861. warn_code = 0;
  11862. /*
  11863. * Read the board's EEPROM configuration.
  11864. *
  11865. * Set default values if a bad checksum is found.
  11866. */
  11867. if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
  11868. warn_code |= ASC_WARN_EEPROM_CHKSUM;
  11869. /*
  11870. * Set EEPROM default values.
  11871. */
  11872. memcpy(&eep_config, &Default_3550_EEPROM_Config,
  11873. sizeof(ADVEEP_3550_CONFIG));
  11874. /*
  11875. * Assume the 6 byte board serial number that was read from
  11876. * EEPROM is correct even if the EEPROM checksum failed.
  11877. */
  11878. eep_config.serial_number_word3 =
  11879. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
  11880. eep_config.serial_number_word2 =
  11881. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
  11882. eep_config.serial_number_word1 =
  11883. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
  11884. AdvSet3550EEPConfig(iop_base, &eep_config);
  11885. }
  11886. /*
  11887. * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
  11888. * EEPROM configuration that was read.
  11889. *
  11890. * This is the mapping of EEPROM fields to Adv Library fields.
  11891. */
  11892. asc_dvc->wdtr_able = eep_config.wdtr_able;
  11893. asc_dvc->sdtr_able = eep_config.sdtr_able;
  11894. asc_dvc->ultra_able = eep_config.ultra_able;
  11895. asc_dvc->tagqng_able = eep_config.tagqng_able;
  11896. asc_dvc->cfg->disc_enable = eep_config.disc_enable;
  11897. asc_dvc->max_host_qng = eep_config.max_host_qng;
  11898. asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
  11899. asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
  11900. asc_dvc->start_motor = eep_config.start_motor;
  11901. asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
  11902. asc_dvc->bios_ctrl = eep_config.bios_ctrl;
  11903. asc_dvc->no_scam = eep_config.scam_tolerant;
  11904. asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
  11905. asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
  11906. asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
  11907. /*
  11908. * Set the host maximum queuing (max. 253, min. 16) and the per device
  11909. * maximum queuing (max. 63, min. 4).
  11910. */
  11911. if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
  11912. eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
  11913. } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
  11914. /* If the value is zero, assume it is uninitialized. */
  11915. if (eep_config.max_host_qng == 0) {
  11916. eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
  11917. } else {
  11918. eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
  11919. }
  11920. }
  11921. if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
  11922. eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
  11923. } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
  11924. /* If the value is zero, assume it is uninitialized. */
  11925. if (eep_config.max_dvc_qng == 0) {
  11926. eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
  11927. } else {
  11928. eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
  11929. }
  11930. }
  11931. /*
  11932. * If 'max_dvc_qng' is greater than 'max_host_qng', then
  11933. * set 'max_dvc_qng' to 'max_host_qng'.
  11934. */
  11935. if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
  11936. eep_config.max_dvc_qng = eep_config.max_host_qng;
  11937. }
  11938. /*
  11939. * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
  11940. * values based on possibly adjusted EEPROM values.
  11941. */
  11942. asc_dvc->max_host_qng = eep_config.max_host_qng;
  11943. asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
  11944. /*
  11945. * If the EEPROM 'termination' field is set to automatic (0), then set
  11946. * the ADV_DVC_CFG 'termination' field to automatic also.
  11947. *
  11948. * If the termination is specified with a non-zero 'termination'
  11949. * value check that a legal value is set and set the ADV_DVC_CFG
  11950. * 'termination' field appropriately.
  11951. */
  11952. if (eep_config.termination == 0) {
  11953. asc_dvc->cfg->termination = 0; /* auto termination */
  11954. } else {
  11955. /* Enable manual control with low off / high off. */
  11956. if (eep_config.termination == 1) {
  11957. asc_dvc->cfg->termination = TERM_CTL_SEL;
  11958. /* Enable manual control with low off / high on. */
  11959. } else if (eep_config.termination == 2) {
  11960. asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
  11961. /* Enable manual control with low on / high on. */
  11962. } else if (eep_config.termination == 3) {
  11963. asc_dvc->cfg->termination =
  11964. TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
  11965. } else {
  11966. /*
  11967. * The EEPROM 'termination' field contains a bad value. Use
  11968. * automatic termination instead.
  11969. */
  11970. asc_dvc->cfg->termination = 0;
  11971. warn_code |= ASC_WARN_EEPROM_TERMINATION;
  11972. }
  11973. }
  11974. return warn_code;
  11975. }
  11976. /*
  11977. * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
  11978. * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
  11979. * all of this is done.
  11980. *
  11981. * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
  11982. *
  11983. * For a non-fatal error return a warning code. If there are no warnings
  11984. * then 0 is returned.
  11985. *
  11986. * Note: Chip is stopped on entry.
  11987. */
  11988. static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
  11989. {
  11990. AdvPortAddr iop_base;
  11991. ushort warn_code;
  11992. ADVEEP_38C0800_CONFIG eep_config;
  11993. uchar tid, termination;
  11994. ushort sdtr_speed = 0;
  11995. iop_base = asc_dvc->iop_base;
  11996. warn_code = 0;
  11997. /*
  11998. * Read the board's EEPROM configuration.
  11999. *
  12000. * Set default values if a bad checksum is found.
  12001. */
  12002. if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
  12003. eep_config.check_sum) {
  12004. warn_code |= ASC_WARN_EEPROM_CHKSUM;
  12005. /*
  12006. * Set EEPROM default values.
  12007. */
  12008. memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
  12009. sizeof(ADVEEP_38C0800_CONFIG));
  12010. /*
  12011. * Assume the 6 byte board serial number that was read from
  12012. * EEPROM is correct even if the EEPROM checksum failed.
  12013. */
  12014. eep_config.serial_number_word3 =
  12015. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
  12016. eep_config.serial_number_word2 =
  12017. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
  12018. eep_config.serial_number_word1 =
  12019. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
  12020. AdvSet38C0800EEPConfig(iop_base, &eep_config);
  12021. }
  12022. /*
  12023. * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
  12024. * EEPROM configuration that was read.
  12025. *
  12026. * This is the mapping of EEPROM fields to Adv Library fields.
  12027. */
  12028. asc_dvc->wdtr_able = eep_config.wdtr_able;
  12029. asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
  12030. asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
  12031. asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
  12032. asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
  12033. asc_dvc->tagqng_able = eep_config.tagqng_able;
  12034. asc_dvc->cfg->disc_enable = eep_config.disc_enable;
  12035. asc_dvc->max_host_qng = eep_config.max_host_qng;
  12036. asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
  12037. asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
  12038. asc_dvc->start_motor = eep_config.start_motor;
  12039. asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
  12040. asc_dvc->bios_ctrl = eep_config.bios_ctrl;
  12041. asc_dvc->no_scam = eep_config.scam_tolerant;
  12042. asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
  12043. asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
  12044. asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
  12045. /*
  12046. * For every Target ID if any of its 'sdtr_speed[1234]' bits
  12047. * are set, then set an 'sdtr_able' bit for it.
  12048. */
  12049. asc_dvc->sdtr_able = 0;
  12050. for (tid = 0; tid <= ADV_MAX_TID; tid++) {
  12051. if (tid == 0) {
  12052. sdtr_speed = asc_dvc->sdtr_speed1;
  12053. } else if (tid == 4) {
  12054. sdtr_speed = asc_dvc->sdtr_speed2;
  12055. } else if (tid == 8) {
  12056. sdtr_speed = asc_dvc->sdtr_speed3;
  12057. } else if (tid == 12) {
  12058. sdtr_speed = asc_dvc->sdtr_speed4;
  12059. }
  12060. if (sdtr_speed & ADV_MAX_TID) {
  12061. asc_dvc->sdtr_able |= (1 << tid);
  12062. }
  12063. sdtr_speed >>= 4;
  12064. }
  12065. /*
  12066. * Set the host maximum queuing (max. 253, min. 16) and the per device
  12067. * maximum queuing (max. 63, min. 4).
  12068. */
  12069. if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
  12070. eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
  12071. } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
  12072. /* If the value is zero, assume it is uninitialized. */
  12073. if (eep_config.max_host_qng == 0) {
  12074. eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
  12075. } else {
  12076. eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
  12077. }
  12078. }
  12079. if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
  12080. eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
  12081. } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
  12082. /* If the value is zero, assume it is uninitialized. */
  12083. if (eep_config.max_dvc_qng == 0) {
  12084. eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
  12085. } else {
  12086. eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
  12087. }
  12088. }
  12089. /*
  12090. * If 'max_dvc_qng' is greater than 'max_host_qng', then
  12091. * set 'max_dvc_qng' to 'max_host_qng'.
  12092. */
  12093. if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
  12094. eep_config.max_dvc_qng = eep_config.max_host_qng;
  12095. }
  12096. /*
  12097. * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
  12098. * values based on possibly adjusted EEPROM values.
  12099. */
  12100. asc_dvc->max_host_qng = eep_config.max_host_qng;
  12101. asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
  12102. /*
  12103. * If the EEPROM 'termination' field is set to automatic (0), then set
  12104. * the ADV_DVC_CFG 'termination' field to automatic also.
  12105. *
  12106. * If the termination is specified with a non-zero 'termination'
  12107. * value check that a legal value is set and set the ADV_DVC_CFG
  12108. * 'termination' field appropriately.
  12109. */
  12110. if (eep_config.termination_se == 0) {
  12111. termination = 0; /* auto termination for SE */
  12112. } else {
  12113. /* Enable manual control with low off / high off. */
  12114. if (eep_config.termination_se == 1) {
  12115. termination = 0;
  12116. /* Enable manual control with low off / high on. */
  12117. } else if (eep_config.termination_se == 2) {
  12118. termination = TERM_SE_HI;
  12119. /* Enable manual control with low on / high on. */
  12120. } else if (eep_config.termination_se == 3) {
  12121. termination = TERM_SE;
  12122. } else {
  12123. /*
  12124. * The EEPROM 'termination_se' field contains a bad value.
  12125. * Use automatic termination instead.
  12126. */
  12127. termination = 0;
  12128. warn_code |= ASC_WARN_EEPROM_TERMINATION;
  12129. }
  12130. }
  12131. if (eep_config.termination_lvd == 0) {
  12132. asc_dvc->cfg->termination = termination; /* auto termination for LVD */
  12133. } else {
  12134. /* Enable manual control with low off / high off. */
  12135. if (eep_config.termination_lvd == 1) {
  12136. asc_dvc->cfg->termination = termination;
  12137. /* Enable manual control with low off / high on. */
  12138. } else if (eep_config.termination_lvd == 2) {
  12139. asc_dvc->cfg->termination = termination | TERM_LVD_HI;
  12140. /* Enable manual control with low on / high on. */
  12141. } else if (eep_config.termination_lvd == 3) {
  12142. asc_dvc->cfg->termination = termination | TERM_LVD;
  12143. } else {
  12144. /*
  12145. * The EEPROM 'termination_lvd' field contains a bad value.
  12146. * Use automatic termination instead.
  12147. */
  12148. asc_dvc->cfg->termination = termination;
  12149. warn_code |= ASC_WARN_EEPROM_TERMINATION;
  12150. }
  12151. }
  12152. return warn_code;
  12153. }
  12154. /*
  12155. * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
  12156. * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
  12157. * all of this is done.
  12158. *
  12159. * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
  12160. *
  12161. * For a non-fatal error return a warning code. If there are no warnings
  12162. * then 0 is returned.
  12163. *
  12164. * Note: Chip is stopped on entry.
  12165. */
  12166. static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
  12167. {
  12168. AdvPortAddr iop_base;
  12169. ushort warn_code;
  12170. ADVEEP_38C1600_CONFIG eep_config;
  12171. uchar tid, termination;
  12172. ushort sdtr_speed = 0;
  12173. iop_base = asc_dvc->iop_base;
  12174. warn_code = 0;
  12175. /*
  12176. * Read the board's EEPROM configuration.
  12177. *
  12178. * Set default values if a bad checksum is found.
  12179. */
  12180. if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
  12181. eep_config.check_sum) {
  12182. struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
  12183. warn_code |= ASC_WARN_EEPROM_CHKSUM;
  12184. /*
  12185. * Set EEPROM default values.
  12186. */
  12187. memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
  12188. sizeof(ADVEEP_38C1600_CONFIG));
  12189. if (PCI_FUNC(pdev->devfn) != 0) {
  12190. u8 ints;
  12191. /*
  12192. * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
  12193. * and old Mac system booting problem. The Expansion
  12194. * ROM must be disabled in Function 1 for these systems
  12195. */
  12196. eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
  12197. /*
  12198. * Clear the INTAB (bit 11) if the GPIO 0 input
  12199. * indicates the Function 1 interrupt line is wired
  12200. * to INTB.
  12201. *
  12202. * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
  12203. * 1 - Function 1 interrupt line wired to INT A.
  12204. * 0 - Function 1 interrupt line wired to INT B.
  12205. *
  12206. * Note: Function 0 is always wired to INTA.
  12207. * Put all 5 GPIO bits in input mode and then read
  12208. * their input values.
  12209. */
  12210. AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
  12211. ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
  12212. if ((ints & 0x01) == 0)
  12213. eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
  12214. }
  12215. /*
  12216. * Assume the 6 byte board serial number that was read from
  12217. * EEPROM is correct even if the EEPROM checksum failed.
  12218. */
  12219. eep_config.serial_number_word3 =
  12220. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
  12221. eep_config.serial_number_word2 =
  12222. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
  12223. eep_config.serial_number_word1 =
  12224. AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
  12225. AdvSet38C1600EEPConfig(iop_base, &eep_config);
  12226. }
  12227. /*
  12228. * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
  12229. * EEPROM configuration that was read.
  12230. *
  12231. * This is the mapping of EEPROM fields to Adv Library fields.
  12232. */
  12233. asc_dvc->wdtr_able = eep_config.wdtr_able;
  12234. asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
  12235. asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
  12236. asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
  12237. asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
  12238. asc_dvc->ppr_able = 0;
  12239. asc_dvc->tagqng_able = eep_config.tagqng_able;
  12240. asc_dvc->cfg->disc_enable = eep_config.disc_enable;
  12241. asc_dvc->max_host_qng = eep_config.max_host_qng;
  12242. asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
  12243. asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
  12244. asc_dvc->start_motor = eep_config.start_motor;
  12245. asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
  12246. asc_dvc->bios_ctrl = eep_config.bios_ctrl;
  12247. asc_dvc->no_scam = eep_config.scam_tolerant;
  12248. /*
  12249. * For every Target ID if any of its 'sdtr_speed[1234]' bits
  12250. * are set, then set an 'sdtr_able' bit for it.
  12251. */
  12252. asc_dvc->sdtr_able = 0;
  12253. for (tid = 0; tid <= ASC_MAX_TID; tid++) {
  12254. if (tid == 0) {
  12255. sdtr_speed = asc_dvc->sdtr_speed1;
  12256. } else if (tid == 4) {
  12257. sdtr_speed = asc_dvc->sdtr_speed2;
  12258. } else if (tid == 8) {
  12259. sdtr_speed = asc_dvc->sdtr_speed3;
  12260. } else if (tid == 12) {
  12261. sdtr_speed = asc_dvc->sdtr_speed4;
  12262. }
  12263. if (sdtr_speed & ASC_MAX_TID) {
  12264. asc_dvc->sdtr_able |= (1 << tid);
  12265. }
  12266. sdtr_speed >>= 4;
  12267. }
  12268. /*
  12269. * Set the host maximum queuing (max. 253, min. 16) and the per device
  12270. * maximum queuing (max. 63, min. 4).
  12271. */
  12272. if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
  12273. eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
  12274. } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
  12275. /* If the value is zero, assume it is uninitialized. */
  12276. if (eep_config.max_host_qng == 0) {
  12277. eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
  12278. } else {
  12279. eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
  12280. }
  12281. }
  12282. if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
  12283. eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
  12284. } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
  12285. /* If the value is zero, assume it is uninitialized. */
  12286. if (eep_config.max_dvc_qng == 0) {
  12287. eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
  12288. } else {
  12289. eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
  12290. }
  12291. }
  12292. /*
  12293. * If 'max_dvc_qng' is greater than 'max_host_qng', then
  12294. * set 'max_dvc_qng' to 'max_host_qng'.
  12295. */
  12296. if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
  12297. eep_config.max_dvc_qng = eep_config.max_host_qng;
  12298. }
  12299. /*
  12300. * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
  12301. * values based on possibly adjusted EEPROM values.
  12302. */
  12303. asc_dvc->max_host_qng = eep_config.max_host_qng;
  12304. asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
  12305. /*
  12306. * If the EEPROM 'termination' field is set to automatic (0), then set
  12307. * the ASC_DVC_CFG 'termination' field to automatic also.
  12308. *
  12309. * If the termination is specified with a non-zero 'termination'
  12310. * value check that a legal value is set and set the ASC_DVC_CFG
  12311. * 'termination' field appropriately.
  12312. */
  12313. if (eep_config.termination_se == 0) {
  12314. termination = 0; /* auto termination for SE */
  12315. } else {
  12316. /* Enable manual control with low off / high off. */
  12317. if (eep_config.termination_se == 1) {
  12318. termination = 0;
  12319. /* Enable manual control with low off / high on. */
  12320. } else if (eep_config.termination_se == 2) {
  12321. termination = TERM_SE_HI;
  12322. /* Enable manual control with low on / high on. */
  12323. } else if (eep_config.termination_se == 3) {
  12324. termination = TERM_SE;
  12325. } else {
  12326. /*
  12327. * The EEPROM 'termination_se' field contains a bad value.
  12328. * Use automatic termination instead.
  12329. */
  12330. termination = 0;
  12331. warn_code |= ASC_WARN_EEPROM_TERMINATION;
  12332. }
  12333. }
  12334. if (eep_config.termination_lvd == 0) {
  12335. asc_dvc->cfg->termination = termination; /* auto termination for LVD */
  12336. } else {
  12337. /* Enable manual control with low off / high off. */
  12338. if (eep_config.termination_lvd == 1) {
  12339. asc_dvc->cfg->termination = termination;
  12340. /* Enable manual control with low off / high on. */
  12341. } else if (eep_config.termination_lvd == 2) {
  12342. asc_dvc->cfg->termination = termination | TERM_LVD_HI;
  12343. /* Enable manual control with low on / high on. */
  12344. } else if (eep_config.termination_lvd == 3) {
  12345. asc_dvc->cfg->termination = termination | TERM_LVD;
  12346. } else {
  12347. /*
  12348. * The EEPROM 'termination_lvd' field contains a bad value.
  12349. * Use automatic termination instead.
  12350. */
  12351. asc_dvc->cfg->termination = termination;
  12352. warn_code |= ASC_WARN_EEPROM_TERMINATION;
  12353. }
  12354. }
  12355. return warn_code;
  12356. }
  12357. /*
  12358. * Initialize the ADV_DVC_VAR structure.
  12359. *
  12360. * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
  12361. *
  12362. * For a non-fatal error return a warning code. If there are no warnings
  12363. * then 0 is returned.
  12364. */
  12365. static int __devinit
  12366. AdvInitGetConfig(struct pci_dev *pdev, struct asc_board *boardp)
  12367. {
  12368. ADV_DVC_VAR *asc_dvc = &boardp->dvc_var.adv_dvc_var;
  12369. unsigned short warn_code = 0;
  12370. AdvPortAddr iop_base = asc_dvc->iop_base;
  12371. u16 cmd;
  12372. int status;
  12373. asc_dvc->err_code = 0;
  12374. /*
  12375. * Save the state of the PCI Configuration Command Register
  12376. * "Parity Error Response Control" Bit. If the bit is clear (0),
  12377. * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
  12378. * DMA parity errors.
  12379. */
  12380. asc_dvc->cfg->control_flag = 0;
  12381. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  12382. if ((cmd & PCI_COMMAND_PARITY) == 0)
  12383. asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
  12384. asc_dvc->cfg->chip_version =
  12385. AdvGetChipVersion(iop_base, asc_dvc->bus_type);
  12386. ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
  12387. (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
  12388. (ushort)ADV_CHIP_ID_BYTE);
  12389. ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
  12390. (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
  12391. (ushort)ADV_CHIP_ID_WORD);
  12392. /*
  12393. * Reset the chip to start and allow register writes.
  12394. */
  12395. if (AdvFindSignature(iop_base) == 0) {
  12396. asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
  12397. return ADV_ERROR;
  12398. } else {
  12399. /*
  12400. * The caller must set 'chip_type' to a valid setting.
  12401. */
  12402. if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
  12403. asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
  12404. asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
  12405. asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
  12406. return ADV_ERROR;
  12407. }
  12408. /*
  12409. * Reset Chip.
  12410. */
  12411. AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
  12412. ADV_CTRL_REG_CMD_RESET);
  12413. mdelay(100);
  12414. AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
  12415. ADV_CTRL_REG_CMD_WR_IO_REG);
  12416. if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
  12417. status = AdvInitFrom38C1600EEP(asc_dvc);
  12418. } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
  12419. status = AdvInitFrom38C0800EEP(asc_dvc);
  12420. } else {
  12421. status = AdvInitFrom3550EEP(asc_dvc);
  12422. }
  12423. warn_code |= status;
  12424. }
  12425. if (warn_code != 0) {
  12426. ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
  12427. boardp->id, warn_code);
  12428. }
  12429. if (asc_dvc->err_code) {
  12430. ASC_PRINT2("AdvInitGetConfig: board %d error: err_code 0x%x\n",
  12431. boardp->id, asc_dvc->err_code);
  12432. }
  12433. return asc_dvc->err_code;
  12434. }
  12435. #endif
  12436. static struct scsi_host_template advansys_template = {
  12437. .proc_name = DRV_NAME,
  12438. #ifdef CONFIG_PROC_FS
  12439. .proc_info = advansys_proc_info,
  12440. #endif
  12441. .name = DRV_NAME,
  12442. .info = advansys_info,
  12443. .queuecommand = advansys_queuecommand,
  12444. .eh_bus_reset_handler = advansys_reset,
  12445. .bios_param = advansys_biosparam,
  12446. .slave_configure = advansys_slave_configure,
  12447. /*
  12448. * Because the driver may control an ISA adapter 'unchecked_isa_dma'
  12449. * must be set. The flag will be cleared in advansys_board_found
  12450. * for non-ISA adapters.
  12451. */
  12452. .unchecked_isa_dma = 1,
  12453. /*
  12454. * All adapters controlled by this driver are capable of large
  12455. * scatter-gather lists. According to the mid-level SCSI documentation
  12456. * this obviates any performance gain provided by setting
  12457. * 'use_clustering'. But empirically while CPU utilization is increased
  12458. * by enabling clustering, I/O throughput increases as well.
  12459. */
  12460. .use_clustering = ENABLE_CLUSTERING,
  12461. };
  12462. static int __devinit
  12463. advansys_wide_init_chip(struct asc_board *boardp, ADV_DVC_VAR *adv_dvc_varp)
  12464. {
  12465. int req_cnt = 0;
  12466. adv_req_t *reqp = NULL;
  12467. int sg_cnt = 0;
  12468. adv_sgblk_t *sgp;
  12469. int warn_code, err_code;
  12470. /*
  12471. * Allocate buffer carrier structures. The total size
  12472. * is about 4 KB, so allocate all at once.
  12473. */
  12474. boardp->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
  12475. ASC_DBG1(1, "advansys_wide_init_chip: carrp 0x%p\n", boardp->carrp);
  12476. if (!boardp->carrp)
  12477. goto kmalloc_failed;
  12478. /*
  12479. * Allocate up to 'max_host_qng' request structures for the Wide
  12480. * board. The total size is about 16 KB, so allocate all at once.
  12481. * If the allocation fails decrement and try again.
  12482. */
  12483. for (req_cnt = adv_dvc_varp->max_host_qng; req_cnt > 0; req_cnt--) {
  12484. reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
  12485. ASC_DBG3(1, "advansys_wide_init_chip: reqp 0x%p, req_cnt %d, "
  12486. "bytes %lu\n", reqp, req_cnt,
  12487. (ulong)sizeof(adv_req_t) * req_cnt);
  12488. if (reqp)
  12489. break;
  12490. }
  12491. if (!reqp)
  12492. goto kmalloc_failed;
  12493. boardp->orig_reqp = reqp;
  12494. /*
  12495. * Allocate up to ADV_TOT_SG_BLOCK request structures for
  12496. * the Wide board. Each structure is about 136 bytes.
  12497. */
  12498. boardp->adv_sgblkp = NULL;
  12499. for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
  12500. sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
  12501. if (!sgp)
  12502. break;
  12503. sgp->next_sgblkp = boardp->adv_sgblkp;
  12504. boardp->adv_sgblkp = sgp;
  12505. }
  12506. ASC_DBG3(1, "advansys_wide_init_chip: sg_cnt %d * %u = %u bytes\n",
  12507. sg_cnt, sizeof(adv_sgblk_t),
  12508. (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
  12509. if (!boardp->adv_sgblkp)
  12510. goto kmalloc_failed;
  12511. adv_dvc_varp->carrier_buf = boardp->carrp;
  12512. /*
  12513. * Point 'adv_reqp' to the request structures and
  12514. * link them together.
  12515. */
  12516. req_cnt--;
  12517. reqp[req_cnt].next_reqp = NULL;
  12518. for (; req_cnt > 0; req_cnt--) {
  12519. reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
  12520. }
  12521. boardp->adv_reqp = &reqp[0];
  12522. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  12523. ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc3550Driver()\n");
  12524. warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
  12525. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  12526. ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C0800Driver()"
  12527. "\n");
  12528. warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
  12529. } else {
  12530. ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C1600Driver()"
  12531. "\n");
  12532. warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
  12533. }
  12534. err_code = adv_dvc_varp->err_code;
  12535. if (warn_code || err_code) {
  12536. ASC_PRINT3("advansys_wide_init_chip: board %d error: warn 0x%x,"
  12537. " error 0x%x\n", boardp->id, warn_code, err_code);
  12538. }
  12539. goto exit;
  12540. kmalloc_failed:
  12541. ASC_PRINT1("advansys_wide_init_chip: board %d error: kmalloc() "
  12542. "failed\n", boardp->id);
  12543. err_code = ADV_ERROR;
  12544. exit:
  12545. return err_code;
  12546. }
  12547. static void advansys_wide_free_mem(struct asc_board *boardp)
  12548. {
  12549. kfree(boardp->carrp);
  12550. boardp->carrp = NULL;
  12551. kfree(boardp->orig_reqp);
  12552. boardp->orig_reqp = boardp->adv_reqp = NULL;
  12553. while (boardp->adv_sgblkp) {
  12554. adv_sgblk_t *sgp = boardp->adv_sgblkp;
  12555. boardp->adv_sgblkp = sgp->next_sgblkp;
  12556. kfree(sgp);
  12557. }
  12558. }
  12559. static int __devinit advansys_board_found(struct Scsi_Host *shost,
  12560. unsigned int iop, int bus_type)
  12561. {
  12562. struct pci_dev *pdev;
  12563. struct asc_board *boardp = shost_priv(shost);
  12564. ASC_DVC_VAR *asc_dvc_varp = NULL;
  12565. ADV_DVC_VAR *adv_dvc_varp = NULL;
  12566. int share_irq, warn_code, ret;
  12567. boardp->id = asc_board_count++;
  12568. spin_lock_init(&boardp->lock);
  12569. pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
  12570. if (ASC_NARROW_BOARD(boardp)) {
  12571. ASC_DBG(1, "advansys_board_found: narrow board\n");
  12572. asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
  12573. asc_dvc_varp->bus_type = bus_type;
  12574. asc_dvc_varp->drv_ptr = boardp;
  12575. asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
  12576. asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
  12577. asc_dvc_varp->iop_base = iop;
  12578. } else {
  12579. #ifdef CONFIG_PCI
  12580. ASC_DBG(1, "advansys_board_found: wide board\n");
  12581. adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
  12582. adv_dvc_varp->drv_ptr = boardp;
  12583. adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
  12584. if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
  12585. ASC_DBG(1, "advansys_board_found: ASC-3550\n");
  12586. adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
  12587. } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
  12588. ASC_DBG(1, "advansys_board_found: ASC-38C0800\n");
  12589. adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
  12590. } else {
  12591. ASC_DBG(1, "advansys_board_found: ASC-38C1600\n");
  12592. adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
  12593. }
  12594. boardp->asc_n_io_port = pci_resource_len(pdev, 1);
  12595. boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
  12596. boardp->asc_n_io_port);
  12597. if (!boardp->ioremap_addr) {
  12598. ASC_PRINT3
  12599. ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n",
  12600. boardp->id, pci_resource_start(pdev, 1),
  12601. boardp->asc_n_io_port);
  12602. ret = -ENODEV;
  12603. goto err_shost;
  12604. }
  12605. adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr
  12606. ASC_DBG1(1, "advansys_board_found: iop_base: 0x%lx\n",
  12607. adv_dvc_varp->iop_base);
  12608. /*
  12609. * Even though it isn't used to access wide boards, other
  12610. * than for the debug line below, save I/O Port address so
  12611. * that it can be reported.
  12612. */
  12613. boardp->ioport = iop;
  12614. ASC_DBG2(1, "advansys_board_found: iopb_chip_id_1 0x%x, "
  12615. "iopw_chip_id_0 0x%x\n", (ushort)inp(iop + 1),
  12616. (ushort)inpw(iop));
  12617. #endif /* CONFIG_PCI */
  12618. }
  12619. #ifdef CONFIG_PROC_FS
  12620. /*
  12621. * Allocate buffer for printing information from
  12622. * /proc/scsi/advansys/[0...].
  12623. */
  12624. boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
  12625. if (!boardp->prtbuf) {
  12626. ASC_PRINT2("advansys_board_found: board %d: kmalloc(%d) "
  12627. "returned NULL\n", boardp->id, ASC_PRTBUF_SIZE);
  12628. ret = -ENOMEM;
  12629. goto err_unmap;
  12630. }
  12631. #endif /* CONFIG_PROC_FS */
  12632. if (ASC_NARROW_BOARD(boardp)) {
  12633. /*
  12634. * Set the board bus type and PCI IRQ before
  12635. * calling AscInitGetConfig().
  12636. */
  12637. switch (asc_dvc_varp->bus_type) {
  12638. #ifdef CONFIG_ISA
  12639. case ASC_IS_ISA:
  12640. shost->unchecked_isa_dma = TRUE;
  12641. share_irq = 0;
  12642. break;
  12643. case ASC_IS_VL:
  12644. shost->unchecked_isa_dma = FALSE;
  12645. share_irq = 0;
  12646. break;
  12647. case ASC_IS_EISA:
  12648. shost->unchecked_isa_dma = FALSE;
  12649. share_irq = IRQF_SHARED;
  12650. break;
  12651. #endif /* CONFIG_ISA */
  12652. #ifdef CONFIG_PCI
  12653. case ASC_IS_PCI:
  12654. shost->unchecked_isa_dma = FALSE;
  12655. share_irq = IRQF_SHARED;
  12656. break;
  12657. #endif /* CONFIG_PCI */
  12658. default:
  12659. ASC_PRINT2
  12660. ("advansys_board_found: board %d: unknown adapter type: %d\n",
  12661. boardp->id, asc_dvc_varp->bus_type);
  12662. shost->unchecked_isa_dma = TRUE;
  12663. share_irq = 0;
  12664. break;
  12665. }
  12666. /*
  12667. * NOTE: AscInitGetConfig() may change the board's
  12668. * bus_type value. The bus_type value should no
  12669. * longer be used. If the bus_type field must be
  12670. * referenced only use the bit-wise AND operator "&".
  12671. */
  12672. ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n");
  12673. ret = AscInitGetConfig(boardp) ? -ENODEV : 0;
  12674. } else {
  12675. #ifdef CONFIG_PCI
  12676. /*
  12677. * For Wide boards set PCI information before calling
  12678. * AdvInitGetConfig().
  12679. */
  12680. shost->unchecked_isa_dma = FALSE;
  12681. share_irq = IRQF_SHARED;
  12682. ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n");
  12683. ret = AdvInitGetConfig(pdev, boardp) ? -ENODEV : 0;
  12684. #endif /* CONFIG_PCI */
  12685. }
  12686. if (ret)
  12687. goto err_free_proc;
  12688. /*
  12689. * Save the EEPROM configuration so that it can be displayed
  12690. * from /proc/scsi/advansys/[0...].
  12691. */
  12692. if (ASC_NARROW_BOARD(boardp)) {
  12693. ASCEEP_CONFIG *ep;
  12694. /*
  12695. * Set the adapter's target id bit in the 'init_tidmask' field.
  12696. */
  12697. boardp->init_tidmask |=
  12698. ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
  12699. /*
  12700. * Save EEPROM settings for the board.
  12701. */
  12702. ep = &boardp->eep_config.asc_eep;
  12703. ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
  12704. ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
  12705. ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
  12706. ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
  12707. ep->start_motor = asc_dvc_varp->start_motor;
  12708. ep->cntl = asc_dvc_varp->dvc_cntl;
  12709. ep->no_scam = asc_dvc_varp->no_scam;
  12710. ep->max_total_qng = asc_dvc_varp->max_total_qng;
  12711. ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
  12712. /* 'max_tag_qng' is set to the same value for every device. */
  12713. ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
  12714. ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
  12715. ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
  12716. ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
  12717. ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
  12718. ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
  12719. ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
  12720. /*
  12721. * Modify board configuration.
  12722. */
  12723. ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n");
  12724. ret = AscInitSetConfig(pdev, boardp) ? -ENODEV : 0;
  12725. if (ret)
  12726. goto err_free_proc;
  12727. } else {
  12728. ADVEEP_3550_CONFIG *ep_3550;
  12729. ADVEEP_38C0800_CONFIG *ep_38C0800;
  12730. ADVEEP_38C1600_CONFIG *ep_38C1600;
  12731. /*
  12732. * Save Wide EEP Configuration Information.
  12733. */
  12734. if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
  12735. ep_3550 = &boardp->eep_config.adv_3550_eep;
  12736. ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
  12737. ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
  12738. ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
  12739. ep_3550->termination = adv_dvc_varp->cfg->termination;
  12740. ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
  12741. ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
  12742. ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
  12743. ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
  12744. ep_3550->ultra_able = adv_dvc_varp->ultra_able;
  12745. ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
  12746. ep_3550->start_motor = adv_dvc_varp->start_motor;
  12747. ep_3550->scsi_reset_delay =
  12748. adv_dvc_varp->scsi_reset_wait;
  12749. ep_3550->serial_number_word1 =
  12750. adv_dvc_varp->cfg->serial1;
  12751. ep_3550->serial_number_word2 =
  12752. adv_dvc_varp->cfg->serial2;
  12753. ep_3550->serial_number_word3 =
  12754. adv_dvc_varp->cfg->serial3;
  12755. } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
  12756. ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
  12757. ep_38C0800->adapter_scsi_id =
  12758. adv_dvc_varp->chip_scsi_id;
  12759. ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
  12760. ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
  12761. ep_38C0800->termination_lvd =
  12762. adv_dvc_varp->cfg->termination;
  12763. ep_38C0800->disc_enable =
  12764. adv_dvc_varp->cfg->disc_enable;
  12765. ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
  12766. ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
  12767. ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
  12768. ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
  12769. ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
  12770. ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
  12771. ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
  12772. ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
  12773. ep_38C0800->start_motor = adv_dvc_varp->start_motor;
  12774. ep_38C0800->scsi_reset_delay =
  12775. adv_dvc_varp->scsi_reset_wait;
  12776. ep_38C0800->serial_number_word1 =
  12777. adv_dvc_varp->cfg->serial1;
  12778. ep_38C0800->serial_number_word2 =
  12779. adv_dvc_varp->cfg->serial2;
  12780. ep_38C0800->serial_number_word3 =
  12781. adv_dvc_varp->cfg->serial3;
  12782. } else {
  12783. ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
  12784. ep_38C1600->adapter_scsi_id =
  12785. adv_dvc_varp->chip_scsi_id;
  12786. ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
  12787. ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
  12788. ep_38C1600->termination_lvd =
  12789. adv_dvc_varp->cfg->termination;
  12790. ep_38C1600->disc_enable =
  12791. adv_dvc_varp->cfg->disc_enable;
  12792. ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
  12793. ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
  12794. ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
  12795. ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
  12796. ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
  12797. ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
  12798. ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
  12799. ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
  12800. ep_38C1600->start_motor = adv_dvc_varp->start_motor;
  12801. ep_38C1600->scsi_reset_delay =
  12802. adv_dvc_varp->scsi_reset_wait;
  12803. ep_38C1600->serial_number_word1 =
  12804. adv_dvc_varp->cfg->serial1;
  12805. ep_38C1600->serial_number_word2 =
  12806. adv_dvc_varp->cfg->serial2;
  12807. ep_38C1600->serial_number_word3 =
  12808. adv_dvc_varp->cfg->serial3;
  12809. }
  12810. /*
  12811. * Set the adapter's target id bit in the 'init_tidmask' field.
  12812. */
  12813. boardp->init_tidmask |=
  12814. ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
  12815. }
  12816. /*
  12817. * Channels are numbered beginning with 0. For AdvanSys one host
  12818. * structure supports one channel. Multi-channel boards have a
  12819. * separate host structure for each channel.
  12820. */
  12821. shost->max_channel = 0;
  12822. if (ASC_NARROW_BOARD(boardp)) {
  12823. shost->max_id = ASC_MAX_TID + 1;
  12824. shost->max_lun = ASC_MAX_LUN + 1;
  12825. shost->max_cmd_len = ASC_MAX_CDB_LEN;
  12826. shost->io_port = asc_dvc_varp->iop_base;
  12827. boardp->asc_n_io_port = ASC_IOADR_GAP;
  12828. shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
  12829. /* Set maximum number of queues the adapter can handle. */
  12830. shost->can_queue = asc_dvc_varp->max_total_qng;
  12831. } else {
  12832. shost->max_id = ADV_MAX_TID + 1;
  12833. shost->max_lun = ADV_MAX_LUN + 1;
  12834. shost->max_cmd_len = ADV_MAX_CDB_LEN;
  12835. /*
  12836. * Save the I/O Port address and length even though
  12837. * I/O ports are not used to access Wide boards.
  12838. * Instead the Wide boards are accessed with
  12839. * PCI Memory Mapped I/O.
  12840. */
  12841. shost->io_port = iop;
  12842. shost->this_id = adv_dvc_varp->chip_scsi_id;
  12843. /* Set maximum number of queues the adapter can handle. */
  12844. shost->can_queue = adv_dvc_varp->max_host_qng;
  12845. }
  12846. /*
  12847. * Following v1.3.89, 'cmd_per_lun' is no longer needed
  12848. * and should be set to zero.
  12849. *
  12850. * But because of a bug introduced in v1.3.89 if the driver is
  12851. * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
  12852. * SCSI function 'allocate_device' will panic. To allow the driver
  12853. * to work as a module in these kernels set 'cmd_per_lun' to 1.
  12854. *
  12855. * Note: This is wrong. cmd_per_lun should be set to the depth
  12856. * you want on untagged devices always.
  12857. #ifdef MODULE
  12858. */
  12859. shost->cmd_per_lun = 1;
  12860. /* #else
  12861. shost->cmd_per_lun = 0;
  12862. #endif */
  12863. /*
  12864. * Set the maximum number of scatter-gather elements the
  12865. * adapter can handle.
  12866. */
  12867. if (ASC_NARROW_BOARD(boardp)) {
  12868. /*
  12869. * Allow two commands with 'sg_tablesize' scatter-gather
  12870. * elements to be executed simultaneously. This value is
  12871. * the theoretical hardware limit. It may be decreased
  12872. * below.
  12873. */
  12874. shost->sg_tablesize =
  12875. (((asc_dvc_varp->max_total_qng - 2) / 2) *
  12876. ASC_SG_LIST_PER_Q) + 1;
  12877. } else {
  12878. shost->sg_tablesize = ADV_MAX_SG_LIST;
  12879. }
  12880. /*
  12881. * The value of 'sg_tablesize' can not exceed the SCSI
  12882. * mid-level driver definition of SG_ALL. SG_ALL also
  12883. * must not be exceeded, because it is used to define the
  12884. * size of the scatter-gather table in 'struct asc_sg_head'.
  12885. */
  12886. if (shost->sg_tablesize > SG_ALL) {
  12887. shost->sg_tablesize = SG_ALL;
  12888. }
  12889. ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize);
  12890. /* BIOS start address. */
  12891. if (ASC_NARROW_BOARD(boardp)) {
  12892. shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
  12893. asc_dvc_varp->bus_type);
  12894. } else {
  12895. /*
  12896. * Fill-in BIOS board variables. The Wide BIOS saves
  12897. * information in LRAM that is used by the driver.
  12898. */
  12899. AdvReadWordLram(adv_dvc_varp->iop_base,
  12900. BIOS_SIGNATURE, boardp->bios_signature);
  12901. AdvReadWordLram(adv_dvc_varp->iop_base,
  12902. BIOS_VERSION, boardp->bios_version);
  12903. AdvReadWordLram(adv_dvc_varp->iop_base,
  12904. BIOS_CODESEG, boardp->bios_codeseg);
  12905. AdvReadWordLram(adv_dvc_varp->iop_base,
  12906. BIOS_CODELEN, boardp->bios_codelen);
  12907. ASC_DBG2(1,
  12908. "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n",
  12909. boardp->bios_signature, boardp->bios_version);
  12910. ASC_DBG2(1,
  12911. "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n",
  12912. boardp->bios_codeseg, boardp->bios_codelen);
  12913. /*
  12914. * If the BIOS saved a valid signature, then fill in
  12915. * the BIOS code segment base address.
  12916. */
  12917. if (boardp->bios_signature == 0x55AA) {
  12918. /*
  12919. * Convert x86 realmode code segment to a linear
  12920. * address by shifting left 4.
  12921. */
  12922. shost->base = ((ulong)boardp->bios_codeseg << 4);
  12923. } else {
  12924. shost->base = 0;
  12925. }
  12926. }
  12927. /*
  12928. * Register Board Resources - I/O Port, DMA, IRQ
  12929. */
  12930. /* Register DMA Channel for Narrow boards. */
  12931. shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
  12932. #ifdef CONFIG_ISA
  12933. if (ASC_NARROW_BOARD(boardp)) {
  12934. /* Register DMA channel for ISA bus. */
  12935. if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
  12936. shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
  12937. ret = request_dma(shost->dma_channel, DRV_NAME);
  12938. if (ret) {
  12939. ASC_PRINT3
  12940. ("advansys_board_found: board %d: request_dma() %d failed %d\n",
  12941. boardp->id, shost->dma_channel, ret);
  12942. goto err_free_proc;
  12943. }
  12944. AscEnableIsaDma(shost->dma_channel);
  12945. }
  12946. }
  12947. #endif /* CONFIG_ISA */
  12948. /* Register IRQ Number. */
  12949. ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", boardp->irq);
  12950. ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
  12951. DRV_NAME, shost);
  12952. if (ret) {
  12953. if (ret == -EBUSY) {
  12954. ASC_PRINT2
  12955. ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n",
  12956. boardp->id, boardp->irq);
  12957. } else if (ret == -EINVAL) {
  12958. ASC_PRINT2
  12959. ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n",
  12960. boardp->id, boardp->irq);
  12961. } else {
  12962. ASC_PRINT3
  12963. ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n",
  12964. boardp->id, boardp->irq, ret);
  12965. }
  12966. goto err_free_dma;
  12967. }
  12968. /*
  12969. * Initialize board RISC chip and enable interrupts.
  12970. */
  12971. if (ASC_NARROW_BOARD(boardp)) {
  12972. ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n");
  12973. warn_code = AscInitAsc1000Driver(asc_dvc_varp);
  12974. if (warn_code || asc_dvc_varp->err_code) {
  12975. ASC_PRINT4("advansys_board_found: board %d error: "
  12976. "init_state 0x%x, warn 0x%x, error 0x%x\n",
  12977. boardp->id, asc_dvc_varp->init_state,
  12978. warn_code, asc_dvc_varp->err_code);
  12979. if (asc_dvc_varp->err_code)
  12980. ret = -ENODEV;
  12981. }
  12982. } else {
  12983. if (advansys_wide_init_chip(boardp, adv_dvc_varp))
  12984. ret = -ENODEV;
  12985. }
  12986. if (ret)
  12987. goto err_free_wide_mem;
  12988. ASC_DBG_PRT_SCSI_HOST(2, shost);
  12989. ret = scsi_add_host(shost, boardp->dev);
  12990. if (ret)
  12991. goto err_free_wide_mem;
  12992. scsi_scan_host(shost);
  12993. return 0;
  12994. err_free_wide_mem:
  12995. advansys_wide_free_mem(boardp);
  12996. free_irq(boardp->irq, shost);
  12997. err_free_dma:
  12998. if (shost->dma_channel != NO_ISA_DMA)
  12999. free_dma(shost->dma_channel);
  13000. err_free_proc:
  13001. kfree(boardp->prtbuf);
  13002. err_unmap:
  13003. if (boardp->ioremap_addr)
  13004. iounmap(boardp->ioremap_addr);
  13005. err_shost:
  13006. return ret;
  13007. }
  13008. /*
  13009. * advansys_release()
  13010. *
  13011. * Release resources allocated for a single AdvanSys adapter.
  13012. */
  13013. static int advansys_release(struct Scsi_Host *shost)
  13014. {
  13015. struct asc_board *boardp = shost_priv(shost);
  13016. ASC_DBG(1, "advansys_release: begin\n");
  13017. scsi_remove_host(shost);
  13018. free_irq(boardp->irq, shost);
  13019. if (shost->dma_channel != NO_ISA_DMA) {
  13020. ASC_DBG(1, "advansys_release: free_dma()\n");
  13021. free_dma(shost->dma_channel);
  13022. }
  13023. if (!ASC_NARROW_BOARD(boardp)) {
  13024. iounmap(boardp->ioremap_addr);
  13025. advansys_wide_free_mem(boardp);
  13026. }
  13027. kfree(boardp->prtbuf);
  13028. scsi_host_put(shost);
  13029. ASC_DBG(1, "advansys_release: end\n");
  13030. return 0;
  13031. }
  13032. #define ASC_IOADR_TABLE_MAX_IX 11
  13033. static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
  13034. 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
  13035. 0x0210, 0x0230, 0x0250, 0x0330
  13036. };
  13037. /*
  13038. * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
  13039. * 00: 10
  13040. * 01: 11
  13041. * 10: 12
  13042. * 11: 15
  13043. */
  13044. static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base)
  13045. {
  13046. unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
  13047. unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
  13048. if (chip_irq == 13)
  13049. chip_irq = 15;
  13050. return chip_irq;
  13051. }
  13052. static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
  13053. {
  13054. int err = -ENODEV;
  13055. PortAddr iop_base = _asc_def_iop_base[id];
  13056. struct Scsi_Host *shost;
  13057. struct asc_board *board;
  13058. if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
  13059. ASC_DBG1(1, "advansys_isa_match: I/O port 0x%x busy\n",
  13060. iop_base);
  13061. return -ENODEV;
  13062. }
  13063. ASC_DBG1(1, "advansys_isa_match: probing I/O port 0x%x\n", iop_base);
  13064. if (!AscFindSignature(iop_base))
  13065. goto release_region;
  13066. if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
  13067. goto release_region;
  13068. err = -ENOMEM;
  13069. shost = scsi_host_alloc(&advansys_template, sizeof(*board));
  13070. if (!shost)
  13071. goto release_region;
  13072. board = shost_priv(shost);
  13073. board->irq = advansys_isa_irq_no(iop_base);
  13074. board->dev = dev;
  13075. err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
  13076. if (err)
  13077. goto free_host;
  13078. dev_set_drvdata(dev, shost);
  13079. return 0;
  13080. free_host:
  13081. scsi_host_put(shost);
  13082. release_region:
  13083. release_region(iop_base, ASC_IOADR_GAP);
  13084. return err;
  13085. }
  13086. static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
  13087. {
  13088. int ioport = _asc_def_iop_base[id];
  13089. advansys_release(dev_get_drvdata(dev));
  13090. release_region(ioport, ASC_IOADR_GAP);
  13091. return 0;
  13092. }
  13093. static struct isa_driver advansys_isa_driver = {
  13094. .probe = advansys_isa_probe,
  13095. .remove = __devexit_p(advansys_isa_remove),
  13096. .driver = {
  13097. .owner = THIS_MODULE,
  13098. .name = DRV_NAME,
  13099. },
  13100. };
  13101. /*
  13102. * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
  13103. * 000: invalid
  13104. * 001: 10
  13105. * 010: 11
  13106. * 011: 12
  13107. * 100: invalid
  13108. * 101: 14
  13109. * 110: 15
  13110. * 111: invalid
  13111. */
  13112. static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base)
  13113. {
  13114. unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
  13115. unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
  13116. if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
  13117. return 0;
  13118. return chip_irq;
  13119. }
  13120. static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
  13121. {
  13122. int err = -ENODEV;
  13123. PortAddr iop_base = _asc_def_iop_base[id];
  13124. struct Scsi_Host *shost;
  13125. struct asc_board *board;
  13126. if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
  13127. ASC_DBG1(1, "advansys_vlb_match: I/O port 0x%x busy\n",
  13128. iop_base);
  13129. return -ENODEV;
  13130. }
  13131. ASC_DBG1(1, "advansys_vlb_match: probing I/O port 0x%x\n", iop_base);
  13132. if (!AscFindSignature(iop_base))
  13133. goto release_region;
  13134. /*
  13135. * I don't think this condition can actually happen, but the old
  13136. * driver did it, and the chances of finding a VLB setup in 2007
  13137. * to do testing with is slight to none.
  13138. */
  13139. if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
  13140. goto release_region;
  13141. err = -ENOMEM;
  13142. shost = scsi_host_alloc(&advansys_template, sizeof(*board));
  13143. if (!shost)
  13144. goto release_region;
  13145. board = shost_priv(shost);
  13146. board->irq = advansys_vlb_irq_no(iop_base);
  13147. board->dev = dev;
  13148. err = advansys_board_found(shost, iop_base, ASC_IS_VL);
  13149. if (err)
  13150. goto free_host;
  13151. dev_set_drvdata(dev, shost);
  13152. return 0;
  13153. free_host:
  13154. scsi_host_put(shost);
  13155. release_region:
  13156. release_region(iop_base, ASC_IOADR_GAP);
  13157. return -ENODEV;
  13158. }
  13159. static struct isa_driver advansys_vlb_driver = {
  13160. .probe = advansys_vlb_probe,
  13161. .remove = __devexit_p(advansys_isa_remove),
  13162. .driver = {
  13163. .owner = THIS_MODULE,
  13164. .name = "advansys_vlb",
  13165. },
  13166. };
  13167. static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
  13168. { "ABP7401" },
  13169. { "ABP7501" },
  13170. { "" }
  13171. };
  13172. MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
  13173. /*
  13174. * EISA is a little more tricky than PCI; each EISA device may have two
  13175. * channels, and this driver is written to make each channel its own Scsi_Host
  13176. */
  13177. struct eisa_scsi_data {
  13178. struct Scsi_Host *host[2];
  13179. };
  13180. /*
  13181. * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
  13182. * 000: 10
  13183. * 001: 11
  13184. * 010: 12
  13185. * 011: invalid
  13186. * 100: 14
  13187. * 101: 15
  13188. * 110: invalid
  13189. * 111: invalid
  13190. */
  13191. static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev)
  13192. {
  13193. unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
  13194. unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
  13195. if ((chip_irq == 13) || (chip_irq > 15))
  13196. return 0;
  13197. return chip_irq;
  13198. }
  13199. static int __devinit advansys_eisa_probe(struct device *dev)
  13200. {
  13201. int i, ioport, irq = 0;
  13202. int err;
  13203. struct eisa_device *edev = to_eisa_device(dev);
  13204. struct eisa_scsi_data *data;
  13205. err = -ENOMEM;
  13206. data = kzalloc(sizeof(*data), GFP_KERNEL);
  13207. if (!data)
  13208. goto fail;
  13209. ioport = edev->base_addr + 0xc30;
  13210. err = -ENODEV;
  13211. for (i = 0; i < 2; i++, ioport += 0x20) {
  13212. struct asc_board *board;
  13213. struct Scsi_Host *shost;
  13214. if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
  13215. printk(KERN_WARNING "Region %x-%x busy\n", ioport,
  13216. ioport + ASC_IOADR_GAP - 1);
  13217. continue;
  13218. }
  13219. if (!AscFindSignature(ioport)) {
  13220. release_region(ioport, ASC_IOADR_GAP);
  13221. continue;
  13222. }
  13223. /*
  13224. * I don't know why we need to do this for EISA chips, but
  13225. * not for any others. It looks to be equivalent to
  13226. * AscGetChipCfgMsw, but I may have overlooked something,
  13227. * so I'm not converting it until I get an EISA board to
  13228. * test with.
  13229. */
  13230. inw(ioport + 4);
  13231. if (!irq)
  13232. irq = advansys_eisa_irq_no(edev);
  13233. err = -ENOMEM;
  13234. shost = scsi_host_alloc(&advansys_template, sizeof(*board));
  13235. if (!shost)
  13236. goto release_region;
  13237. board = shost_priv(shost);
  13238. board->irq = irq;
  13239. board->dev = dev;
  13240. err = advansys_board_found(shost, ioport, ASC_IS_EISA);
  13241. if (!err) {
  13242. data->host[i] = shost;
  13243. continue;
  13244. }
  13245. scsi_host_put(shost);
  13246. release_region:
  13247. release_region(ioport, ASC_IOADR_GAP);
  13248. break;
  13249. }
  13250. if (err)
  13251. goto free_data;
  13252. dev_set_drvdata(dev, data);
  13253. return 0;
  13254. free_data:
  13255. kfree(data->host[0]);
  13256. kfree(data->host[1]);
  13257. kfree(data);
  13258. fail:
  13259. return err;
  13260. }
  13261. static __devexit int advansys_eisa_remove(struct device *dev)
  13262. {
  13263. int i;
  13264. struct eisa_scsi_data *data = dev_get_drvdata(dev);
  13265. for (i = 0; i < 2; i++) {
  13266. int ioport;
  13267. struct Scsi_Host *shost = data->host[i];
  13268. if (!shost)
  13269. continue;
  13270. ioport = shost->io_port;
  13271. advansys_release(shost);
  13272. release_region(ioport, ASC_IOADR_GAP);
  13273. }
  13274. kfree(data);
  13275. return 0;
  13276. }
  13277. static struct eisa_driver advansys_eisa_driver = {
  13278. .id_table = advansys_eisa_table,
  13279. .driver = {
  13280. .name = DRV_NAME,
  13281. .probe = advansys_eisa_probe,
  13282. .remove = __devexit_p(advansys_eisa_remove),
  13283. }
  13284. };
  13285. /* PCI Devices supported by this driver */
  13286. static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
  13287. {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
  13288. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  13289. {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
  13290. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  13291. {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
  13292. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  13293. {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
  13294. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  13295. {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
  13296. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  13297. {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
  13298. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  13299. {}
  13300. };
  13301. MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
  13302. static void __devinit advansys_set_latency(struct pci_dev *pdev)
  13303. {
  13304. if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
  13305. (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
  13306. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
  13307. } else {
  13308. u8 latency;
  13309. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
  13310. if (latency < 0x20)
  13311. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
  13312. }
  13313. }
  13314. static int __devinit
  13315. advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  13316. {
  13317. int err, ioport;
  13318. struct Scsi_Host *shost;
  13319. struct asc_board *board;
  13320. err = pci_enable_device(pdev);
  13321. if (err)
  13322. goto fail;
  13323. err = pci_request_regions(pdev, DRV_NAME);
  13324. if (err)
  13325. goto disable_device;
  13326. pci_set_master(pdev);
  13327. advansys_set_latency(pdev);
  13328. err = -ENODEV;
  13329. if (pci_resource_len(pdev, 0) == 0)
  13330. goto release_region;
  13331. ioport = pci_resource_start(pdev, 0);
  13332. err = -ENOMEM;
  13333. shost = scsi_host_alloc(&advansys_template, sizeof(*board));
  13334. if (!shost)
  13335. goto release_region;
  13336. board = shost_priv(shost);
  13337. board->irq = pdev->irq;
  13338. board->dev = &pdev->dev;
  13339. if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
  13340. pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
  13341. pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
  13342. board->flags |= ASC_IS_WIDE_BOARD;
  13343. }
  13344. err = advansys_board_found(shost, ioport, ASC_IS_PCI);
  13345. if (err)
  13346. goto free_host;
  13347. pci_set_drvdata(pdev, shost);
  13348. return 0;
  13349. free_host:
  13350. scsi_host_put(shost);
  13351. release_region:
  13352. pci_release_regions(pdev);
  13353. disable_device:
  13354. pci_disable_device(pdev);
  13355. fail:
  13356. return err;
  13357. }
  13358. static void __devexit advansys_pci_remove(struct pci_dev *pdev)
  13359. {
  13360. advansys_release(pci_get_drvdata(pdev));
  13361. pci_release_regions(pdev);
  13362. pci_disable_device(pdev);
  13363. }
  13364. static struct pci_driver advansys_pci_driver = {
  13365. .name = DRV_NAME,
  13366. .id_table = advansys_pci_tbl,
  13367. .probe = advansys_pci_probe,
  13368. .remove = __devexit_p(advansys_pci_remove),
  13369. };
  13370. static int __init advansys_init(void)
  13371. {
  13372. int error;
  13373. error = isa_register_driver(&advansys_isa_driver,
  13374. ASC_IOADR_TABLE_MAX_IX);
  13375. if (error)
  13376. goto fail;
  13377. error = isa_register_driver(&advansys_vlb_driver,
  13378. ASC_IOADR_TABLE_MAX_IX);
  13379. if (error)
  13380. goto unregister_isa;
  13381. error = eisa_driver_register(&advansys_eisa_driver);
  13382. if (error)
  13383. goto unregister_vlb;
  13384. error = pci_register_driver(&advansys_pci_driver);
  13385. if (error)
  13386. goto unregister_eisa;
  13387. return 0;
  13388. unregister_eisa:
  13389. eisa_driver_unregister(&advansys_eisa_driver);
  13390. unregister_vlb:
  13391. isa_unregister_driver(&advansys_vlb_driver);
  13392. unregister_isa:
  13393. isa_unregister_driver(&advansys_isa_driver);
  13394. fail:
  13395. return error;
  13396. }
  13397. static void __exit advansys_exit(void)
  13398. {
  13399. pci_unregister_driver(&advansys_pci_driver);
  13400. eisa_driver_unregister(&advansys_eisa_driver);
  13401. isa_unregister_driver(&advansys_vlb_driver);
  13402. isa_unregister_driver(&advansys_isa_driver);
  13403. }
  13404. module_init(advansys_init);
  13405. module_exit(advansys_exit);
  13406. MODULE_LICENSE("GPL");