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linux-vybrid_pu...
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arch
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unicore32
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include
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mach
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regs-pci.h

regs-pci.h 4.2 KB
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  1. /*
    2. 

  2.  * PKUnity AHB-PCI Bridge Registers
    3. 

  3.  */
    4. 

  4. 

  5. /*
    6. 

  6.  * AHB/PCI fixed physical address for pci addess configuration
    7. 

  7.  */
    8. 

  8. /*
    9. 

  9.  * PCICFG Bridge Base Reg.
    10. 

  10.  */
    11. 

  11. #define PCICFG_BRIBASE          __REG(PKUNITY_PCICFG_BASE + 0x0000)
    12. 

  12. /*
    13. 

  13.  * PCICFG Address Reg.
    14. 

  14.  */
    15. 

  15. #define PCICFG_ADDR             __REG(PKUNITY_PCICFG_BASE + 0x0004)
    16. 

  16. /*
    17. 

  17.  * PCICFG Address Reg.
    18. 

  18.  */
    19. 

  19. #define PCICFG_DATA             __REG(PKUNITY_PCICFG_BASE + 0x0008)
    20. 

  20. 

  21. /*
    22. 

  22.  * PCI Bridge configuration space
    23. 

  23.  */
    24. 

  24. #define PCIBRI_ID		__REG(PKUNITY_PCIBRI_BASE + 0x0000)
    25. 

  25. #define PCIBRI_CMD		__REG(PKUNITY_PCIBRI_BASE + 0x0004)
    26. 

  26. #define PCIBRI_CLASS		__REG(PKUNITY_PCIBRI_BASE + 0x0008)
    27. 

  27. #define PCIBRI_LTR		__REG(PKUNITY_PCIBRI_BASE + 0x000C)
    28. 

  28. #define PCIBRI_BAR0		__REG(PKUNITY_PCIBRI_BASE + 0x0010)
    29. 

  29. #define PCIBRI_BAR1		__REG(PKUNITY_PCIBRI_BASE + 0x0014)
    30. 

  30. #define PCIBRI_BAR2		__REG(PKUNITY_PCIBRI_BASE + 0x0018)
    31. 

  31. #define PCIBRI_BAR3		__REG(PKUNITY_PCIBRI_BASE + 0x001C)
    32. 

  32. #define PCIBRI_BAR4		__REG(PKUNITY_PCIBRI_BASE + 0x0020)
    33. 

  33. #define PCIBRI_BAR5		__REG(PKUNITY_PCIBRI_BASE + 0x0024)
    34. 

  34. 

  35. #define PCIBRI_PCICTL0		__REG(PKUNITY_PCIBRI_BASE + 0x0100)
    36. 

  36. #define PCIBRI_PCIBAR0		__REG(PKUNITY_PCIBRI_BASE + 0x0104)
    37. 

  37. #define PCIBRI_PCIAMR0		__REG(PKUNITY_PCIBRI_BASE + 0x0108)
    38. 

  38. #define PCIBRI_PCITAR0		__REG(PKUNITY_PCIBRI_BASE + 0x010C)
    39. 

  39. #define PCIBRI_PCICTL1		__REG(PKUNITY_PCIBRI_BASE + 0x0110)
    40. 

  40. #define PCIBRI_PCIBAR1		__REG(PKUNITY_PCIBRI_BASE + 0x0114)
    41. 

  41. #define PCIBRI_PCIAMR1		__REG(PKUNITY_PCIBRI_BASE + 0x0118)
    42. 

  42. #define PCIBRI_PCITAR1		__REG(PKUNITY_PCIBRI_BASE + 0x011C)
    43. 

  43. #define PCIBRI_PCICTL2		__REG(PKUNITY_PCIBRI_BASE + 0x0120)
    44. 

  44. #define PCIBRI_PCIBAR2		__REG(PKUNITY_PCIBRI_BASE + 0x0124)
    45. 

  45. #define PCIBRI_PCIAMR2		__REG(PKUNITY_PCIBRI_BASE + 0x0128)
    46. 

  46. #define PCIBRI_PCITAR2		__REG(PKUNITY_PCIBRI_BASE + 0x012C)
    47. 

  47. #define PCIBRI_PCICTL3		__REG(PKUNITY_PCIBRI_BASE + 0x0130)
    48. 

  48. #define PCIBRI_PCIBAR3		__REG(PKUNITY_PCIBRI_BASE + 0x0134)
    49. 

  49. #define PCIBRI_PCIAMR3		__REG(PKUNITY_PCIBRI_BASE + 0x0138)
    50. 

  50. #define PCIBRI_PCITAR3		__REG(PKUNITY_PCIBRI_BASE + 0x013C)
    51. 

  51. #define PCIBRI_PCICTL4		__REG(PKUNITY_PCIBRI_BASE + 0x0140)
    52. 

  52. #define PCIBRI_PCIBAR4		__REG(PKUNITY_PCIBRI_BASE + 0x0144)
    53. 

  53. #define PCIBRI_PCIAMR4		__REG(PKUNITY_PCIBRI_BASE + 0x0148)
    54. 

  54. #define PCIBRI_PCITAR4		__REG(PKUNITY_PCIBRI_BASE + 0x014C)
    55. 

  55. #define PCIBRI_PCICTL5		__REG(PKUNITY_PCIBRI_BASE + 0x0150)
    56. 

  56. #define PCIBRI_PCIBAR5		__REG(PKUNITY_PCIBRI_BASE + 0x0154)
    57. 

  57. #define PCIBRI_PCIAMR5		__REG(PKUNITY_PCIBRI_BASE + 0x0158)
    58. 

  58. #define PCIBRI_PCITAR5		__REG(PKUNITY_PCIBRI_BASE + 0x015C)
    59. 

  59. 

  60. #define PCIBRI_AHBCTL0		__REG(PKUNITY_PCIBRI_BASE + 0x0180)
    61. 

  61. #define PCIBRI_AHBBAR0		__REG(PKUNITY_PCIBRI_BASE + 0x0184)
    62. 

  62. #define PCIBRI_AHBAMR0		__REG(PKUNITY_PCIBRI_BASE + 0x0188)
    63. 

  63. #define PCIBRI_AHBTAR0		__REG(PKUNITY_PCIBRI_BASE + 0x018C)
    64. 

  64. #define PCIBRI_AHBCTL1		__REG(PKUNITY_PCIBRI_BASE + 0x0190)
    65. 

  65. #define PCIBRI_AHBBAR1		__REG(PKUNITY_PCIBRI_BASE + 0x0194)
    66. 

  66. #define PCIBRI_AHBAMR1		__REG(PKUNITY_PCIBRI_BASE + 0x0198)
    67. 

  67. #define PCIBRI_AHBTAR1		__REG(PKUNITY_PCIBRI_BASE + 0x019C)
    68. 

  68. #define PCIBRI_AHBCTL2		__REG(PKUNITY_PCIBRI_BASE + 0x01A0)
    69. 

  69. #define PCIBRI_AHBBAR2		__REG(PKUNITY_PCIBRI_BASE + 0x01A4)
    70. 

  70. #define PCIBRI_AHBAMR2		__REG(PKUNITY_PCIBRI_BASE + 0x01A8)
    71. 

  71. #define PCIBRI_AHBTAR2		__REG(PKUNITY_PCIBRI_BASE + 0x01AC)
    72. 

  72. #define PCIBRI_AHBCTL3		__REG(PKUNITY_PCIBRI_BASE + 0x01B0)
    73. 

  73. #define PCIBRI_AHBBAR3		__REG(PKUNITY_PCIBRI_BASE + 0x01B4)
    74. 

  74. #define PCIBRI_AHBAMR3		__REG(PKUNITY_PCIBRI_BASE + 0x01B8)
    75. 

  75. #define PCIBRI_AHBTAR3		__REG(PKUNITY_PCIBRI_BASE + 0x01BC)
    76. 

  76. #define PCIBRI_AHBCTL4		__REG(PKUNITY_PCIBRI_BASE + 0x01C0)
    77. 

  77. #define PCIBRI_AHBBAR4		__REG(PKUNITY_PCIBRI_BASE + 0x01C4)
    78. 

  78. #define PCIBRI_AHBAMR4		__REG(PKUNITY_PCIBRI_BASE + 0x01C8)
    79. 

  79. #define PCIBRI_AHBTAR4		__REG(PKUNITY_PCIBRI_BASE + 0x01CC)
    80. 

  80. #define PCIBRI_AHBCTL5		__REG(PKUNITY_PCIBRI_BASE + 0x01D0)
    81. 

  81. #define PCIBRI_AHBBAR5		__REG(PKUNITY_PCIBRI_BASE + 0x01D4)
    82. 

  82. #define PCIBRI_AHBAMR5		__REG(PKUNITY_PCIBRI_BASE + 0x01D8)
    83. 

  83. #define PCIBRI_AHBTAR5		__REG(PKUNITY_PCIBRI_BASE + 0x01DC)
    84. 

  84. 

  85. #define PCIBRI_CTLx_AT          FIELD(1, 1, 2)
    86. 

  86. #define PCIBRI_CTLx_PREF        FIELD(1, 1, 1)
    87. 

  87. #define PCIBRI_CTLx_MRL         FIELD(1, 1, 0)
    88. 

  88. 

  89. #define PCIBRI_BARx_ADDR        FIELD(0xFFFFFFFC, 30, 2)
    90. 

  90. #define PCIBRI_BARx_IO          FIELD(1, 1, 0)
    91. 

  91. #define PCIBRI_BARx_MEM         FIELD(0, 1, 0)
    92. 

  92. 

  93. #define PCIBRI_CMD_IO           FIELD(1, 1, 0)
    94. 

  94. #define PCIBRI_CMD_MEM          FIELD(1, 1, 1)
    95.