board-3430sdp.c 20 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/board-3430sdp.c
  3. *
  4. * Copyright (C) 2007 Texas Instruments
  5. *
  6. * Modified from mach-omap2/board-generic.c
  7. *
  8. * Initial code: Syed Mohammed Khasim
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. #include <linux/input.h>
  19. #include <linux/input/matrix_keypad.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/i2c/twl.h>
  22. #include <linux/regulator/machine.h>
  23. #include <linux/io.h>
  24. #include <linux/gpio.h>
  25. #include <linux/mmc/host.h>
  26. #include <mach/hardware.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include <plat/mcspi.h>
  31. #include <plat/board.h>
  32. #include <plat/usb.h>
  33. #include <plat/common.h>
  34. #include <plat/dma.h>
  35. #include <plat/gpmc.h>
  36. #include <plat/display.h>
  37. #include <plat/panel-generic-dpi.h>
  38. #include <plat/gpmc-smc91x.h>
  39. #include "board-flash.h"
  40. #include "mux.h"
  41. #include "sdram-qimonda-hyb18m512160af-6.h"
  42. #include "hsmmc.h"
  43. #include "pm.h"
  44. #include "control.h"
  45. #include "common-board-devices.h"
  46. #define CONFIG_DISABLE_HFCLK 1
  47. #define SDP3430_TS_GPIO_IRQ_SDPV1 3
  48. #define SDP3430_TS_GPIO_IRQ_SDPV2 2
  49. #define ENABLE_VAUX3_DEDICATED 0x03
  50. #define ENABLE_VAUX3_DEV_GRP 0x20
  51. #define TWL4030_MSECURE_GPIO 22
  52. /* FIXME: These values need to be updated based on more profiling on 3430sdp*/
  53. static struct cpuidle_params omap3_cpuidle_params_table[] = {
  54. /* C1 */
  55. {1, 2, 2, 5},
  56. /* C2 */
  57. {1, 10, 10, 30},
  58. /* C3 */
  59. {1, 50, 50, 300},
  60. /* C4 */
  61. {1, 1500, 1800, 4000},
  62. /* C5 */
  63. {1, 2500, 7500, 12000},
  64. /* C6 */
  65. {1, 3000, 8500, 15000},
  66. /* C7 */
  67. {1, 10000, 30000, 300000},
  68. };
  69. static uint32_t board_keymap[] = {
  70. KEY(0, 0, KEY_LEFT),
  71. KEY(0, 1, KEY_RIGHT),
  72. KEY(0, 2, KEY_A),
  73. KEY(0, 3, KEY_B),
  74. KEY(0, 4, KEY_C),
  75. KEY(1, 0, KEY_DOWN),
  76. KEY(1, 1, KEY_UP),
  77. KEY(1, 2, KEY_E),
  78. KEY(1, 3, KEY_F),
  79. KEY(1, 4, KEY_G),
  80. KEY(2, 0, KEY_ENTER),
  81. KEY(2, 1, KEY_I),
  82. KEY(2, 2, KEY_J),
  83. KEY(2, 3, KEY_K),
  84. KEY(2, 4, KEY_3),
  85. KEY(3, 0, KEY_M),
  86. KEY(3, 1, KEY_N),
  87. KEY(3, 2, KEY_O),
  88. KEY(3, 3, KEY_P),
  89. KEY(3, 4, KEY_Q),
  90. KEY(4, 0, KEY_R),
  91. KEY(4, 1, KEY_4),
  92. KEY(4, 2, KEY_T),
  93. KEY(4, 3, KEY_U),
  94. KEY(4, 4, KEY_D),
  95. KEY(5, 0, KEY_V),
  96. KEY(5, 1, KEY_W),
  97. KEY(5, 2, KEY_L),
  98. KEY(5, 3, KEY_S),
  99. KEY(5, 4, KEY_H),
  100. 0
  101. };
  102. static struct matrix_keymap_data board_map_data = {
  103. .keymap = board_keymap,
  104. .keymap_size = ARRAY_SIZE(board_keymap),
  105. };
  106. static struct twl4030_keypad_data sdp3430_kp_data = {
  107. .keymap_data = &board_map_data,
  108. .rows = 5,
  109. .cols = 6,
  110. .rep = 1,
  111. };
  112. #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
  113. #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
  114. static struct gpio sdp3430_dss_gpios[] __initdata = {
  115. {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
  116. {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
  117. };
  118. static int lcd_enabled;
  119. static int dvi_enabled;
  120. static void __init sdp3430_display_init(void)
  121. {
  122. int r;
  123. r = gpio_request_array(sdp3430_dss_gpios,
  124. ARRAY_SIZE(sdp3430_dss_gpios));
  125. if (r)
  126. printk(KERN_ERR "failed to get LCD control GPIOs\n");
  127. }
  128. static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
  129. {
  130. if (dvi_enabled) {
  131. printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
  132. return -EINVAL;
  133. }
  134. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
  135. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
  136. lcd_enabled = 1;
  137. return 0;
  138. }
  139. static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
  140. {
  141. lcd_enabled = 0;
  142. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
  143. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
  144. }
  145. static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
  146. {
  147. if (lcd_enabled) {
  148. printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
  149. return -EINVAL;
  150. }
  151. dvi_enabled = 1;
  152. return 0;
  153. }
  154. static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
  155. {
  156. dvi_enabled = 0;
  157. }
  158. static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
  159. {
  160. return 0;
  161. }
  162. static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
  163. {
  164. }
  165. static struct omap_dss_device sdp3430_lcd_device = {
  166. .name = "lcd",
  167. .driver_name = "sharp_ls_panel",
  168. .type = OMAP_DISPLAY_TYPE_DPI,
  169. .phy.dpi.data_lines = 16,
  170. .platform_enable = sdp3430_panel_enable_lcd,
  171. .platform_disable = sdp3430_panel_disable_lcd,
  172. };
  173. static struct panel_generic_dpi_data dvi_panel = {
  174. .name = "generic",
  175. .platform_enable = sdp3430_panel_enable_dvi,
  176. .platform_disable = sdp3430_panel_disable_dvi,
  177. };
  178. static struct omap_dss_device sdp3430_dvi_device = {
  179. .name = "dvi",
  180. .type = OMAP_DISPLAY_TYPE_DPI,
  181. .driver_name = "generic_dpi_panel",
  182. .data = &dvi_panel,
  183. .phy.dpi.data_lines = 24,
  184. };
  185. static struct omap_dss_device sdp3430_tv_device = {
  186. .name = "tv",
  187. .driver_name = "venc",
  188. .type = OMAP_DISPLAY_TYPE_VENC,
  189. .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
  190. .platform_enable = sdp3430_panel_enable_tv,
  191. .platform_disable = sdp3430_panel_disable_tv,
  192. };
  193. static struct omap_dss_device *sdp3430_dss_devices[] = {
  194. &sdp3430_lcd_device,
  195. &sdp3430_dvi_device,
  196. &sdp3430_tv_device,
  197. };
  198. static struct omap_dss_board_info sdp3430_dss_data = {
  199. .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
  200. .devices = sdp3430_dss_devices,
  201. .default_device = &sdp3430_lcd_device,
  202. };
  203. static struct omap_board_config_kernel sdp3430_config[] __initdata = {
  204. };
  205. static void __init omap_3430sdp_init_early(void)
  206. {
  207. omap2_init_common_infrastructure();
  208. omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
  209. }
  210. static int sdp3430_batt_table[] = {
  211. /* 0 C*/
  212. 30800, 29500, 28300, 27100,
  213. 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
  214. 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
  215. 11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
  216. 8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
  217. 5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
  218. 4040, 3910, 3790, 3670, 3550
  219. };
  220. static struct twl4030_bci_platform_data sdp3430_bci_data = {
  221. .battery_tmp_tbl = sdp3430_batt_table,
  222. .tblsize = ARRAY_SIZE(sdp3430_batt_table),
  223. };
  224. static struct omap2_hsmmc_info mmc[] = {
  225. {
  226. .mmc = 1,
  227. /* 8 bits (default) requires S6.3 == ON,
  228. * so the SIM card isn't used; else 4 bits.
  229. */
  230. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  231. .gpio_wp = 4,
  232. },
  233. {
  234. .mmc = 2,
  235. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  236. .gpio_wp = 7,
  237. },
  238. {} /* Terminator */
  239. };
  240. static int sdp3430_twl_gpio_setup(struct device *dev,
  241. unsigned gpio, unsigned ngpio)
  242. {
  243. /* gpio + 0 is "mmc0_cd" (input/IRQ),
  244. * gpio + 1 is "mmc1_cd" (input/IRQ)
  245. */
  246. mmc[0].gpio_cd = gpio + 0;
  247. mmc[1].gpio_cd = gpio + 1;
  248. omap2_hsmmc_init(mmc);
  249. /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
  250. gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
  251. /* gpio + 15 is "sub_lcd_nRST" (output) */
  252. gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
  253. return 0;
  254. }
  255. static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
  256. .gpio_base = OMAP_MAX_GPIO_LINES,
  257. .irq_base = TWL4030_GPIO_IRQ_BASE,
  258. .irq_end = TWL4030_GPIO_IRQ_END,
  259. .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
  260. | BIT(16) | BIT(17),
  261. .setup = sdp3430_twl_gpio_setup,
  262. };
  263. static struct twl4030_usb_data sdp3430_usb_data = {
  264. .usb_mode = T2_USB_MODE_ULPI,
  265. };
  266. static struct twl4030_madc_platform_data sdp3430_madc_data = {
  267. .irq_line = 1,
  268. };
  269. /* regulator consumer mappings */
  270. /* ads7846 on SPI */
  271. static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
  272. REGULATOR_SUPPLY("vcc", "spi1.0"),
  273. };
  274. static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
  275. REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
  276. };
  277. /* VPLL2 for digital video outputs */
  278. static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
  279. REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
  280. REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
  281. };
  282. static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
  283. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
  284. };
  285. static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
  286. REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
  287. };
  288. static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
  289. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
  290. };
  291. /*
  292. * Apply all the fixed voltages since most versions of U-Boot
  293. * don't bother with that initialization.
  294. */
  295. /* VAUX1 for mainboard (irda and sub-lcd) */
  296. static struct regulator_init_data sdp3430_vaux1 = {
  297. .constraints = {
  298. .min_uV = 2800000,
  299. .max_uV = 2800000,
  300. .apply_uV = true,
  301. .valid_modes_mask = REGULATOR_MODE_NORMAL
  302. | REGULATOR_MODE_STANDBY,
  303. .valid_ops_mask = REGULATOR_CHANGE_MODE
  304. | REGULATOR_CHANGE_STATUS,
  305. },
  306. };
  307. /* VAUX2 for camera module */
  308. static struct regulator_init_data sdp3430_vaux2 = {
  309. .constraints = {
  310. .min_uV = 2800000,
  311. .max_uV = 2800000,
  312. .apply_uV = true,
  313. .valid_modes_mask = REGULATOR_MODE_NORMAL
  314. | REGULATOR_MODE_STANDBY,
  315. .valid_ops_mask = REGULATOR_CHANGE_MODE
  316. | REGULATOR_CHANGE_STATUS,
  317. },
  318. };
  319. /* VAUX3 for LCD board */
  320. static struct regulator_init_data sdp3430_vaux3 = {
  321. .constraints = {
  322. .min_uV = 2800000,
  323. .max_uV = 2800000,
  324. .apply_uV = true,
  325. .valid_modes_mask = REGULATOR_MODE_NORMAL
  326. | REGULATOR_MODE_STANDBY,
  327. .valid_ops_mask = REGULATOR_CHANGE_MODE
  328. | REGULATOR_CHANGE_STATUS,
  329. },
  330. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
  331. .consumer_supplies = sdp3430_vaux3_supplies,
  332. };
  333. /* VAUX4 for OMAP VDD_CSI2 (camera) */
  334. static struct regulator_init_data sdp3430_vaux4 = {
  335. .constraints = {
  336. .min_uV = 1800000,
  337. .max_uV = 1800000,
  338. .apply_uV = true,
  339. .valid_modes_mask = REGULATOR_MODE_NORMAL
  340. | REGULATOR_MODE_STANDBY,
  341. .valid_ops_mask = REGULATOR_CHANGE_MODE
  342. | REGULATOR_CHANGE_STATUS,
  343. },
  344. };
  345. /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
  346. static struct regulator_init_data sdp3430_vmmc1 = {
  347. .constraints = {
  348. .min_uV = 1850000,
  349. .max_uV = 3150000,
  350. .valid_modes_mask = REGULATOR_MODE_NORMAL
  351. | REGULATOR_MODE_STANDBY,
  352. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  353. | REGULATOR_CHANGE_MODE
  354. | REGULATOR_CHANGE_STATUS,
  355. },
  356. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
  357. .consumer_supplies = sdp3430_vmmc1_supplies,
  358. };
  359. /* VMMC2 for MMC2 card */
  360. static struct regulator_init_data sdp3430_vmmc2 = {
  361. .constraints = {
  362. .min_uV = 1850000,
  363. .max_uV = 1850000,
  364. .apply_uV = true,
  365. .valid_modes_mask = REGULATOR_MODE_NORMAL
  366. | REGULATOR_MODE_STANDBY,
  367. .valid_ops_mask = REGULATOR_CHANGE_MODE
  368. | REGULATOR_CHANGE_STATUS,
  369. },
  370. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
  371. .consumer_supplies = sdp3430_vmmc2_supplies,
  372. };
  373. /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
  374. static struct regulator_init_data sdp3430_vsim = {
  375. .constraints = {
  376. .min_uV = 1800000,
  377. .max_uV = 3000000,
  378. .valid_modes_mask = REGULATOR_MODE_NORMAL
  379. | REGULATOR_MODE_STANDBY,
  380. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  381. | REGULATOR_CHANGE_MODE
  382. | REGULATOR_CHANGE_STATUS,
  383. },
  384. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
  385. .consumer_supplies = sdp3430_vsim_supplies,
  386. };
  387. /* VDAC for DSS driving S-Video */
  388. static struct regulator_init_data sdp3430_vdac = {
  389. .constraints = {
  390. .min_uV = 1800000,
  391. .max_uV = 1800000,
  392. .apply_uV = true,
  393. .valid_modes_mask = REGULATOR_MODE_NORMAL
  394. | REGULATOR_MODE_STANDBY,
  395. .valid_ops_mask = REGULATOR_CHANGE_MODE
  396. | REGULATOR_CHANGE_STATUS,
  397. },
  398. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
  399. .consumer_supplies = sdp3430_vdda_dac_supplies,
  400. };
  401. static struct regulator_init_data sdp3430_vpll2 = {
  402. .constraints = {
  403. .name = "VDVI",
  404. .min_uV = 1800000,
  405. .max_uV = 1800000,
  406. .apply_uV = true,
  407. .valid_modes_mask = REGULATOR_MODE_NORMAL
  408. | REGULATOR_MODE_STANDBY,
  409. .valid_ops_mask = REGULATOR_CHANGE_MODE
  410. | REGULATOR_CHANGE_STATUS,
  411. },
  412. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
  413. .consumer_supplies = sdp3430_vpll2_supplies,
  414. };
  415. static struct twl4030_codec_audio_data sdp3430_audio;
  416. static struct twl4030_codec_data sdp3430_codec = {
  417. .audio_mclk = 26000000,
  418. .audio = &sdp3430_audio,
  419. };
  420. static struct twl4030_platform_data sdp3430_twldata = {
  421. .irq_base = TWL4030_IRQ_BASE,
  422. .irq_end = TWL4030_IRQ_END,
  423. /* platform_data for children goes here */
  424. .bci = &sdp3430_bci_data,
  425. .gpio = &sdp3430_gpio_data,
  426. .madc = &sdp3430_madc_data,
  427. .keypad = &sdp3430_kp_data,
  428. .usb = &sdp3430_usb_data,
  429. .codec = &sdp3430_codec,
  430. .vaux1 = &sdp3430_vaux1,
  431. .vaux2 = &sdp3430_vaux2,
  432. .vaux3 = &sdp3430_vaux3,
  433. .vaux4 = &sdp3430_vaux4,
  434. .vmmc1 = &sdp3430_vmmc1,
  435. .vmmc2 = &sdp3430_vmmc2,
  436. .vsim = &sdp3430_vsim,
  437. .vdac = &sdp3430_vdac,
  438. .vpll2 = &sdp3430_vpll2,
  439. };
  440. static int __init omap3430_i2c_init(void)
  441. {
  442. /* i2c1 for PMIC only */
  443. omap3_pmic_init("twl4030", &sdp3430_twldata);
  444. /* i2c2 on camera connector (for sensor control) and optional isp1301 */
  445. omap_register_i2c_bus(2, 400, NULL, 0);
  446. /* i2c3 on display connector (for DVI, tfp410) */
  447. omap_register_i2c_bus(3, 400, NULL, 0);
  448. return 0;
  449. }
  450. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  451. static struct omap_smc91x_platform_data board_smc91x_data = {
  452. .cs = 3,
  453. .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
  454. IORESOURCE_IRQ_LOWLEVEL,
  455. };
  456. static void __init board_smc91x_init(void)
  457. {
  458. if (omap_rev() > OMAP3430_REV_ES1_0)
  459. board_smc91x_data.gpio_irq = 6;
  460. else
  461. board_smc91x_data.gpio_irq = 29;
  462. gpmc_smc91x_init(&board_smc91x_data);
  463. }
  464. #else
  465. static inline void board_smc91x_init(void)
  466. {
  467. }
  468. #endif
  469. static void enable_board_wakeup_source(void)
  470. {
  471. /* T2 interrupt line (keypad) */
  472. omap_mux_init_signal("sys_nirq",
  473. OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
  474. }
  475. static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
  476. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  477. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  478. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  479. .phy_reset = true,
  480. .reset_gpio_port[0] = 57,
  481. .reset_gpio_port[1] = 61,
  482. .reset_gpio_port[2] = -EINVAL
  483. };
  484. #ifdef CONFIG_OMAP_MUX
  485. static struct omap_board_mux board_mux[] __initdata = {
  486. { .reg_offset = OMAP_MUX_TERMINATOR },
  487. };
  488. static struct omap_device_pad serial1_pads[] __initdata = {
  489. /*
  490. * Note that off output enable is an active low
  491. * signal. So setting this means pin is a
  492. * input enabled in off mode
  493. */
  494. OMAP_MUX_STATIC("uart1_cts.uart1_cts",
  495. OMAP_PIN_INPUT |
  496. OMAP_PIN_OFF_INPUT_PULLDOWN |
  497. OMAP_OFFOUT_EN |
  498. OMAP_MUX_MODE0),
  499. OMAP_MUX_STATIC("uart1_rts.uart1_rts",
  500. OMAP_PIN_OUTPUT |
  501. OMAP_OFF_EN |
  502. OMAP_MUX_MODE0),
  503. OMAP_MUX_STATIC("uart1_rx.uart1_rx",
  504. OMAP_PIN_INPUT |
  505. OMAP_PIN_OFF_INPUT_PULLDOWN |
  506. OMAP_OFFOUT_EN |
  507. OMAP_MUX_MODE0),
  508. OMAP_MUX_STATIC("uart1_tx.uart1_tx",
  509. OMAP_PIN_OUTPUT |
  510. OMAP_OFF_EN |
  511. OMAP_MUX_MODE0),
  512. };
  513. static struct omap_device_pad serial2_pads[] __initdata = {
  514. OMAP_MUX_STATIC("uart2_cts.uart2_cts",
  515. OMAP_PIN_INPUT_PULLUP |
  516. OMAP_PIN_OFF_INPUT_PULLDOWN |
  517. OMAP_OFFOUT_EN |
  518. OMAP_MUX_MODE0),
  519. OMAP_MUX_STATIC("uart2_rts.uart2_rts",
  520. OMAP_PIN_OUTPUT |
  521. OMAP_OFF_EN |
  522. OMAP_MUX_MODE0),
  523. OMAP_MUX_STATIC("uart2_rx.uart2_rx",
  524. OMAP_PIN_INPUT |
  525. OMAP_PIN_OFF_INPUT_PULLDOWN |
  526. OMAP_OFFOUT_EN |
  527. OMAP_MUX_MODE0),
  528. OMAP_MUX_STATIC("uart2_tx.uart2_tx",
  529. OMAP_PIN_OUTPUT |
  530. OMAP_OFF_EN |
  531. OMAP_MUX_MODE0),
  532. };
  533. static struct omap_device_pad serial3_pads[] __initdata = {
  534. OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
  535. OMAP_PIN_INPUT_PULLDOWN |
  536. OMAP_PIN_OFF_INPUT_PULLDOWN |
  537. OMAP_OFFOUT_EN |
  538. OMAP_MUX_MODE0),
  539. OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
  540. OMAP_PIN_OUTPUT |
  541. OMAP_OFF_EN |
  542. OMAP_MUX_MODE0),
  543. OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
  544. OMAP_PIN_INPUT |
  545. OMAP_PIN_OFF_INPUT_PULLDOWN |
  546. OMAP_OFFOUT_EN |
  547. OMAP_MUX_MODE0),
  548. OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
  549. OMAP_PIN_OUTPUT |
  550. OMAP_OFF_EN |
  551. OMAP_MUX_MODE0),
  552. };
  553. static struct omap_board_data serial1_data = {
  554. .id = 0,
  555. .pads = serial1_pads,
  556. .pads_cnt = ARRAY_SIZE(serial1_pads),
  557. };
  558. static struct omap_board_data serial2_data = {
  559. .id = 1,
  560. .pads = serial2_pads,
  561. .pads_cnt = ARRAY_SIZE(serial2_pads),
  562. };
  563. static struct omap_board_data serial3_data = {
  564. .id = 2,
  565. .pads = serial3_pads,
  566. .pads_cnt = ARRAY_SIZE(serial3_pads),
  567. };
  568. static inline void board_serial_init(void)
  569. {
  570. omap_serial_init_port(&serial1_data);
  571. omap_serial_init_port(&serial2_data);
  572. omap_serial_init_port(&serial3_data);
  573. }
  574. #else
  575. #define board_mux NULL
  576. static inline void board_serial_init(void)
  577. {
  578. omap_serial_init();
  579. }
  580. #endif
  581. /*
  582. * SDP3430 V2 Board CS organization
  583. * Different from SDP3430 V1. Now 4 switches used to specify CS
  584. *
  585. * See also the Switch S8 settings in the comments.
  586. */
  587. static char chip_sel_3430[][GPMC_CS_NUM] = {
  588. {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
  589. {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
  590. {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
  591. };
  592. static struct mtd_partition sdp_nor_partitions[] = {
  593. /* bootloader (U-Boot, etc) in first sector */
  594. {
  595. .name = "Bootloader-NOR",
  596. .offset = 0,
  597. .size = SZ_256K,
  598. .mask_flags = MTD_WRITEABLE, /* force read-only */
  599. },
  600. /* bootloader params in the next sector */
  601. {
  602. .name = "Params-NOR",
  603. .offset = MTDPART_OFS_APPEND,
  604. .size = SZ_256K,
  605. .mask_flags = 0,
  606. },
  607. /* kernel */
  608. {
  609. .name = "Kernel-NOR",
  610. .offset = MTDPART_OFS_APPEND,
  611. .size = SZ_2M,
  612. .mask_flags = 0
  613. },
  614. /* file system */
  615. {
  616. .name = "Filesystem-NOR",
  617. .offset = MTDPART_OFS_APPEND,
  618. .size = MTDPART_SIZ_FULL,
  619. .mask_flags = 0
  620. }
  621. };
  622. static struct mtd_partition sdp_onenand_partitions[] = {
  623. {
  624. .name = "X-Loader-OneNAND",
  625. .offset = 0,
  626. .size = 4 * (64 * 2048),
  627. .mask_flags = MTD_WRITEABLE /* force read-only */
  628. },
  629. {
  630. .name = "U-Boot-OneNAND",
  631. .offset = MTDPART_OFS_APPEND,
  632. .size = 2 * (64 * 2048),
  633. .mask_flags = MTD_WRITEABLE /* force read-only */
  634. },
  635. {
  636. .name = "U-Boot Environment-OneNAND",
  637. .offset = MTDPART_OFS_APPEND,
  638. .size = 1 * (64 * 2048),
  639. },
  640. {
  641. .name = "Kernel-OneNAND",
  642. .offset = MTDPART_OFS_APPEND,
  643. .size = 16 * (64 * 2048),
  644. },
  645. {
  646. .name = "File System-OneNAND",
  647. .offset = MTDPART_OFS_APPEND,
  648. .size = MTDPART_SIZ_FULL,
  649. },
  650. };
  651. static struct mtd_partition sdp_nand_partitions[] = {
  652. /* All the partition sizes are listed in terms of NAND block size */
  653. {
  654. .name = "X-Loader-NAND",
  655. .offset = 0,
  656. .size = 4 * (64 * 2048),
  657. .mask_flags = MTD_WRITEABLE, /* force read-only */
  658. },
  659. {
  660. .name = "U-Boot-NAND",
  661. .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
  662. .size = 10 * (64 * 2048),
  663. .mask_flags = MTD_WRITEABLE, /* force read-only */
  664. },
  665. {
  666. .name = "Boot Env-NAND",
  667. .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
  668. .size = 6 * (64 * 2048),
  669. },
  670. {
  671. .name = "Kernel-NAND",
  672. .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
  673. .size = 40 * (64 * 2048),
  674. },
  675. {
  676. .name = "File System - NAND",
  677. .size = MTDPART_SIZ_FULL,
  678. .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
  679. },
  680. };
  681. static struct flash_partitions sdp_flash_partitions[] = {
  682. {
  683. .parts = sdp_nor_partitions,
  684. .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
  685. },
  686. {
  687. .parts = sdp_onenand_partitions,
  688. .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
  689. },
  690. {
  691. .parts = sdp_nand_partitions,
  692. .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
  693. },
  694. };
  695. static void __init omap_3430sdp_init(void)
  696. {
  697. int gpio_pendown;
  698. omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
  699. omap_board_config = sdp3430_config;
  700. omap_board_config_size = ARRAY_SIZE(sdp3430_config);
  701. omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
  702. omap3430_i2c_init();
  703. omap_display_init(&sdp3430_dss_data);
  704. if (omap_rev() > OMAP3430_REV_ES1_0)
  705. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
  706. else
  707. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
  708. omap_ads7846_init(1, gpio_pendown, 310, NULL);
  709. board_serial_init();
  710. usb_musb_init(NULL);
  711. board_smc91x_init();
  712. board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
  713. sdp3430_display_init();
  714. enable_board_wakeup_source();
  715. usbhs_init(&usbhs_bdata);
  716. }
  717. MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
  718. /* Maintainer: Syed Khasim - Texas Instruments Inc */
  719. .boot_params = 0x80000100,
  720. .reserve = omap_reserve,
  721. .map_io = omap3_map_io,
  722. .init_early = omap_3430sdp_init_early,
  723. .init_irq = omap_init_irq,
  724. .init_machine = omap_3430sdp_init,
  725. .timer = &omap_timer,
  726. MACHINE_END