cpqphp_pci.c 39 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563
  1. /*
  2. * Compaq Hot Plug Controller Driver
  3. *
  4. * Copyright (C) 1995,2001 Compaq Computer Corporation
  5. * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
  6. * Copyright (C) 2001 IBM Corp.
  7. *
  8. * All rights reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or (at
  13. * your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  18. * NON INFRINGEMENT. See the GNU General Public License for more
  19. * details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. * Send feedback to <greg@kroah.com>
  26. *
  27. */
  28. #include <linux/module.h>
  29. #include <linux/kernel.h>
  30. #include <linux/types.h>
  31. #include <linux/slab.h>
  32. #include <linux/workqueue.h>
  33. #include <linux/proc_fs.h>
  34. #include <linux/pci.h>
  35. #include <linux/pci_hotplug.h>
  36. #include "../pci.h"
  37. #include "cpqphp.h"
  38. #include "cpqphp_nvram.h"
  39. u8 cpqhp_nic_irq;
  40. u8 cpqhp_disk_irq;
  41. static u16 unused_IRQ;
  42. /*
  43. * detect_HRT_floating_pointer
  44. *
  45. * find the Hot Plug Resource Table in the specified region of memory.
  46. *
  47. */
  48. static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end)
  49. {
  50. void __iomem *fp;
  51. void __iomem *endp;
  52. u8 temp1, temp2, temp3, temp4;
  53. int status = 0;
  54. endp = (end - sizeof(struct hrt) + 1);
  55. for (fp = begin; fp <= endp; fp += 16) {
  56. temp1 = readb(fp + SIG0);
  57. temp2 = readb(fp + SIG1);
  58. temp3 = readb(fp + SIG2);
  59. temp4 = readb(fp + SIG3);
  60. if (temp1 == '$' &&
  61. temp2 == 'H' &&
  62. temp3 == 'R' &&
  63. temp4 == 'T') {
  64. status = 1;
  65. break;
  66. }
  67. }
  68. if (!status)
  69. fp = NULL;
  70. dbg("Discovered Hotplug Resource Table at %p\n", fp);
  71. return fp;
  72. }
  73. int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
  74. {
  75. unsigned char bus;
  76. struct pci_bus *child;
  77. int num;
  78. if (func->pci_dev == NULL)
  79. func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
  80. /* No pci device, we need to create it then */
  81. if (func->pci_dev == NULL) {
  82. dbg("INFO: pci_dev still null\n");
  83. num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function));
  84. if (num)
  85. pci_bus_add_devices(ctrl->pci_dev->bus);
  86. func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
  87. if (func->pci_dev == NULL) {
  88. dbg("ERROR: pci_dev still null\n");
  89. return 0;
  90. }
  91. }
  92. if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  93. pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
  94. child = (struct pci_bus*) pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
  95. pci_do_scan_bus(child);
  96. }
  97. return 0;
  98. }
  99. int cpqhp_unconfigure_device(struct pci_func* func)
  100. {
  101. int j;
  102. dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
  103. for (j=0; j<8 ; j++) {
  104. struct pci_dev* temp = pci_find_slot(func->bus, PCI_DEVFN(func->device, j));
  105. if (temp)
  106. pci_remove_bus_device(temp);
  107. }
  108. return 0;
  109. }
  110. static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
  111. {
  112. u32 vendID = 0;
  113. if (pci_bus_read_config_dword (bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
  114. return -1;
  115. if (vendID == 0xffffffff)
  116. return -1;
  117. return pci_bus_read_config_dword (bus, devfn, offset, value);
  118. }
  119. /*
  120. * cpqhp_set_irq
  121. *
  122. * @bus_num: bus number of PCI device
  123. * @dev_num: device number of PCI device
  124. * @slot: pointer to u8 where slot number will be returned
  125. */
  126. int cpqhp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
  127. {
  128. int rc = 0;
  129. if (cpqhp_legacy_mode) {
  130. struct pci_dev *fakedev;
  131. struct pci_bus *fakebus;
  132. u16 temp_word;
  133. fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL);
  134. fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL);
  135. if (!fakedev || !fakebus) {
  136. kfree(fakedev);
  137. kfree(fakebus);
  138. return -ENOMEM;
  139. }
  140. fakedev->devfn = dev_num << 3;
  141. fakedev->bus = fakebus;
  142. fakebus->number = bus_num;
  143. dbg("%s: dev %d, bus %d, pin %d, num %d\n",
  144. __func__, dev_num, bus_num, int_pin, irq_num);
  145. rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num);
  146. kfree(fakedev);
  147. kfree(fakebus);
  148. dbg("%s: rc %d\n", __func__, rc);
  149. if (!rc)
  150. return !rc;
  151. /* set the Edge Level Control Register (ELCR) */
  152. temp_word = inb(0x4d0);
  153. temp_word |= inb(0x4d1) << 8;
  154. temp_word |= 0x01 << irq_num;
  155. /* This should only be for x86 as it sets the Edge Level
  156. * Control Register
  157. */
  158. outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word &
  159. 0xFF00) >> 8), 0x4d1); rc = 0; }
  160. return rc;
  161. }
  162. /*
  163. * WTF??? This function isn't in the code, yet a function calls it, but the
  164. * compiler optimizes it away? strange. Here as a placeholder to keep the
  165. * compiler happy.
  166. */
  167. static int PCI_ScanBusNonBridge (u8 bus, u8 device)
  168. {
  169. return 0;
  170. }
  171. static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 * dev_num)
  172. {
  173. u16 tdevice;
  174. u32 work;
  175. u8 tbus;
  176. ctrl->pci_bus->number = bus_num;
  177. for (tdevice = 0; tdevice < 0xFF; tdevice++) {
  178. /* Scan for access first */
  179. if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
  180. continue;
  181. dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
  182. /* Yep we got one. Not a bridge ? */
  183. if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) {
  184. *dev_num = tdevice;
  185. dbg("found it !\n");
  186. return 0;
  187. }
  188. }
  189. for (tdevice = 0; tdevice < 0xFF; tdevice++) {
  190. /* Scan for access first */
  191. if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
  192. continue;
  193. dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
  194. /* Yep we got one. bridge ? */
  195. if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
  196. pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
  197. dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
  198. if (PCI_ScanBusNonBridge(tbus, tdevice) == 0)
  199. return 0;
  200. }
  201. }
  202. return -1;
  203. }
  204. static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge)
  205. {
  206. int loop, len;
  207. u32 work;
  208. u8 tbus, tdevice, tslot;
  209. len = cpqhp_routing_table_length();
  210. for (loop = 0; loop < len; ++loop) {
  211. tbus = cpqhp_routing_table->slots[loop].bus;
  212. tdevice = cpqhp_routing_table->slots[loop].devfn;
  213. tslot = cpqhp_routing_table->slots[loop].slot;
  214. if (tslot == slot) {
  215. *bus_num = tbus;
  216. *dev_num = tdevice;
  217. ctrl->pci_bus->number = tbus;
  218. pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
  219. if (!nobridge || (work == 0xffffffff))
  220. return 0;
  221. dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
  222. pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
  223. dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
  224. if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
  225. pci_bus_read_config_byte (ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
  226. dbg("Scan bus for Non Bridge: bus %d\n", tbus);
  227. if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
  228. *bus_num = tbus;
  229. return 0;
  230. }
  231. } else
  232. return 0;
  233. }
  234. }
  235. return -1;
  236. }
  237. int cpqhp_get_bus_dev (struct controller *ctrl, u8 * bus_num, u8 * dev_num, u8 slot)
  238. {
  239. /* plain (bridges allowed) */
  240. return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
  241. }
  242. /* More PCI configuration routines; this time centered around hotplug
  243. * controller
  244. */
  245. /*
  246. * cpqhp_save_config
  247. *
  248. * Reads configuration for all slots in a PCI bus and saves info.
  249. *
  250. * Note: For non-hot plug busses, the slot # saved is the device #
  251. *
  252. * returns 0 if success
  253. */
  254. int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
  255. {
  256. long rc;
  257. u8 class_code;
  258. u8 header_type;
  259. u32 ID;
  260. u8 secondary_bus;
  261. struct pci_func *new_slot;
  262. int sub_bus;
  263. int FirstSupported;
  264. int LastSupported;
  265. int max_functions;
  266. int function;
  267. u8 DevError;
  268. int device = 0;
  269. int cloop = 0;
  270. int stop_it;
  271. int index;
  272. /* Decide which slots are supported */
  273. if (is_hot_plug) {
  274. /*
  275. * is_hot_plug is the slot mask
  276. */
  277. FirstSupported = is_hot_plug >> 4;
  278. LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1;
  279. } else {
  280. FirstSupported = 0;
  281. LastSupported = 0x1F;
  282. }
  283. /* Save PCI configuration space for all devices in supported slots */
  284. ctrl->pci_bus->number = busnumber;
  285. for (device = FirstSupported; device <= LastSupported; device++) {
  286. ID = 0xFFFFFFFF;
  287. rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
  288. if (ID == 0xFFFFFFFF) {
  289. if (is_hot_plug) {
  290. /* Setup slot structure with entry for empty
  291. * slot
  292. */
  293. new_slot = cpqhp_slot_create(busnumber);
  294. if (new_slot == NULL)
  295. return 1;
  296. new_slot->bus = (u8) busnumber;
  297. new_slot->device = (u8) device;
  298. new_slot->function = 0;
  299. new_slot->is_a_board = 0;
  300. new_slot->presence_save = 0;
  301. new_slot->switch_save = 0;
  302. }
  303. continue;
  304. }
  305. rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
  306. if (rc)
  307. return rc;
  308. rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
  309. if (rc)
  310. return rc;
  311. /* If multi-function device, set max_functions to 8 */
  312. if (header_type & 0x80)
  313. max_functions = 8;
  314. else
  315. max_functions = 1;
  316. function = 0;
  317. do {
  318. DevError = 0;
  319. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
  320. /* Recurse the subordinate bus
  321. * get the subordinate bus number
  322. */
  323. rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus);
  324. if (rc) {
  325. return rc;
  326. } else {
  327. sub_bus = (int) secondary_bus;
  328. /* Save secondary bus cfg spc
  329. * with this recursive call.
  330. */
  331. rc = cpqhp_save_config(ctrl, sub_bus, 0);
  332. if (rc)
  333. return rc;
  334. ctrl->pci_bus->number = busnumber;
  335. }
  336. }
  337. index = 0;
  338. new_slot = cpqhp_slot_find(busnumber, device, index++);
  339. while (new_slot &&
  340. (new_slot->function != (u8) function))
  341. new_slot = cpqhp_slot_find(busnumber, device, index++);
  342. if (!new_slot) {
  343. /* Setup slot structure. */
  344. new_slot = cpqhp_slot_create(busnumber);
  345. if (new_slot == NULL)
  346. return 1;
  347. }
  348. new_slot->bus = (u8) busnumber;
  349. new_slot->device = (u8) device;
  350. new_slot->function = (u8) function;
  351. new_slot->is_a_board = 1;
  352. new_slot->switch_save = 0x10;
  353. /* In case of unsupported board */
  354. new_slot->status = DevError;
  355. new_slot->pci_dev = pci_find_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
  356. for (cloop = 0; cloop < 0x20; cloop++) {
  357. rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
  358. if (rc)
  359. return rc;
  360. }
  361. function++;
  362. stop_it = 0;
  363. /* this loop skips to the next present function
  364. * reading in Class Code and Header type.
  365. */
  366. while ((function < max_functions) && (!stop_it)) {
  367. rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
  368. if (ID == 0xFFFFFFFF) {
  369. function++;
  370. continue;
  371. }
  372. rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code);
  373. if (rc)
  374. return rc;
  375. rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type);
  376. if (rc)
  377. return rc;
  378. stop_it++;
  379. }
  380. } while (function < max_functions);
  381. } /* End of FOR loop */
  382. return 0;
  383. }
  384. /*
  385. * cpqhp_save_slot_config
  386. *
  387. * Saves configuration info for all PCI devices in a given slot
  388. * including subordinate busses.
  389. *
  390. * returns 0 if success
  391. */
  392. int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot)
  393. {
  394. long rc;
  395. u8 class_code;
  396. u8 header_type;
  397. u32 ID;
  398. u8 secondary_bus;
  399. int sub_bus;
  400. int max_functions;
  401. int function = 0;
  402. int cloop = 0;
  403. int stop_it;
  404. ID = 0xFFFFFFFF;
  405. ctrl->pci_bus->number = new_slot->bus;
  406. pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
  407. if (ID == 0xFFFFFFFF)
  408. return 2;
  409. pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
  410. pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
  411. if (header_type & 0x80) /* Multi-function device */
  412. max_functions = 8;
  413. else
  414. max_functions = 1;
  415. while (function < max_functions) {
  416. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
  417. /* Recurse the subordinate bus */
  418. pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
  419. sub_bus = (int) secondary_bus;
  420. /* Save the config headers for the secondary
  421. * bus.
  422. */
  423. rc = cpqhp_save_config(ctrl, sub_bus, 0);
  424. if (rc)
  425. return(rc);
  426. ctrl->pci_bus->number = new_slot->bus;
  427. }
  428. new_slot->status = 0;
  429. for (cloop = 0; cloop < 0x20; cloop++)
  430. pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
  431. function++;
  432. stop_it = 0;
  433. /* this loop skips to the next present function
  434. * reading in the Class Code and the Header type.
  435. */
  436. while ((function < max_functions) && (!stop_it)) {
  437. pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
  438. if (ID == 0xFFFFFFFF)
  439. function++;
  440. else {
  441. pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
  442. pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type);
  443. stop_it++;
  444. }
  445. }
  446. }
  447. return 0;
  448. }
  449. /*
  450. * cpqhp_save_base_addr_length
  451. *
  452. * Saves the length of all base address registers for the
  453. * specified slot. this is for hot plug REPLACE
  454. *
  455. * returns 0 if success
  456. */
  457. int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func * func)
  458. {
  459. u8 cloop;
  460. u8 header_type;
  461. u8 secondary_bus;
  462. u8 type;
  463. int sub_bus;
  464. u32 temp_register;
  465. u32 base;
  466. u32 rc;
  467. struct pci_func *next;
  468. int index = 0;
  469. struct pci_bus *pci_bus = ctrl->pci_bus;
  470. unsigned int devfn;
  471. func = cpqhp_slot_find(func->bus, func->device, index++);
  472. while (func != NULL) {
  473. pci_bus->number = func->bus;
  474. devfn = PCI_DEVFN(func->device, func->function);
  475. /* Check for Bridge */
  476. pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
  477. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
  478. pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
  479. sub_bus = (int) secondary_bus;
  480. next = cpqhp_slot_list[sub_bus];
  481. while (next != NULL) {
  482. rc = cpqhp_save_base_addr_length(ctrl, next);
  483. if (rc)
  484. return rc;
  485. next = next->next;
  486. }
  487. pci_bus->number = func->bus;
  488. /* FIXME: this loop is duplicated in the non-bridge
  489. * case. The two could be rolled together Figure out
  490. * IO and memory base lengths
  491. */
  492. for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
  493. temp_register = 0xFFFFFFFF;
  494. pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
  495. pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
  496. /* If this register is implemented */
  497. if (base) {
  498. if (base & 0x01L) {
  499. /* IO base
  500. * set base = amount of IO space
  501. * requested
  502. */
  503. base = base & 0xFFFFFFFE;
  504. base = (~base) + 1;
  505. type = 1;
  506. } else {
  507. /* memory base */
  508. base = base & 0xFFFFFFF0;
  509. base = (~base) + 1;
  510. type = 0;
  511. }
  512. } else {
  513. base = 0x0L;
  514. type = 0;
  515. }
  516. /* Save information in slot structure */
  517. func->base_length[(cloop - 0x10) >> 2] =
  518. base;
  519. func->base_type[(cloop - 0x10) >> 2] = type;
  520. } /* End of base register loop */
  521. } else if ((header_type & 0x7F) == 0x00) {
  522. /* Figure out IO and memory base lengths */
  523. for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
  524. temp_register = 0xFFFFFFFF;
  525. pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
  526. pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
  527. /* If this register is implemented */
  528. if (base) {
  529. if (base & 0x01L) {
  530. /* IO base
  531. * base = amount of IO space
  532. * requested
  533. */
  534. base = base & 0xFFFFFFFE;
  535. base = (~base) + 1;
  536. type = 1;
  537. } else {
  538. /* memory base
  539. * base = amount of memory
  540. * space requested
  541. */
  542. base = base & 0xFFFFFFF0;
  543. base = (~base) + 1;
  544. type = 0;
  545. }
  546. } else {
  547. base = 0x0L;
  548. type = 0;
  549. }
  550. /* Save information in slot structure */
  551. func->base_length[(cloop - 0x10) >> 2] = base;
  552. func->base_type[(cloop - 0x10) >> 2] = type;
  553. } /* End of base register loop */
  554. } else { /* Some other unknown header type */
  555. }
  556. /* find the next device in this slot */
  557. func = cpqhp_slot_find(func->bus, func->device, index++);
  558. }
  559. return(0);
  560. }
  561. /*
  562. * cpqhp_save_used_resources
  563. *
  564. * Stores used resource information for existing boards. this is
  565. * for boards that were in the system when this driver was loaded.
  566. * this function is for hot plug ADD
  567. *
  568. * returns 0 if success
  569. */
  570. int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func)
  571. {
  572. u8 cloop;
  573. u8 header_type;
  574. u8 secondary_bus;
  575. u8 temp_byte;
  576. u8 b_base;
  577. u8 b_length;
  578. u16 command;
  579. u16 save_command;
  580. u16 w_base;
  581. u16 w_length;
  582. u32 temp_register;
  583. u32 save_base;
  584. u32 base;
  585. int index = 0;
  586. struct pci_resource *mem_node;
  587. struct pci_resource *p_mem_node;
  588. struct pci_resource *io_node;
  589. struct pci_resource *bus_node;
  590. struct pci_bus *pci_bus = ctrl->pci_bus;
  591. unsigned int devfn;
  592. func = cpqhp_slot_find(func->bus, func->device, index++);
  593. while ((func != NULL) && func->is_a_board) {
  594. pci_bus->number = func->bus;
  595. devfn = PCI_DEVFN(func->device, func->function);
  596. /* Save the command register */
  597. pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
  598. /* disable card */
  599. command = 0x00;
  600. pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
  601. /* Check for Bridge */
  602. pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
  603. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
  604. /* Clear Bridge Control Register */
  605. command = 0x00;
  606. pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
  607. pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
  608. pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
  609. bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
  610. if (!bus_node)
  611. return -ENOMEM;
  612. bus_node->base = secondary_bus;
  613. bus_node->length = temp_byte - secondary_bus + 1;
  614. bus_node->next = func->bus_head;
  615. func->bus_head = bus_node;
  616. /* Save IO base and Limit registers */
  617. pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base);
  618. pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length);
  619. if ((b_base <= b_length) && (save_command & 0x01)) {
  620. io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
  621. if (!io_node)
  622. return -ENOMEM;
  623. io_node->base = (b_base & 0xF0) << 8;
  624. io_node->length = (b_length - b_base + 0x10) << 8;
  625. io_node->next = func->io_head;
  626. func->io_head = io_node;
  627. }
  628. /* Save memory base and Limit registers */
  629. pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
  630. pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
  631. if ((w_base <= w_length) && (save_command & 0x02)) {
  632. mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
  633. if (!mem_node)
  634. return -ENOMEM;
  635. mem_node->base = w_base << 16;
  636. mem_node->length = (w_length - w_base + 0x10) << 16;
  637. mem_node->next = func->mem_head;
  638. func->mem_head = mem_node;
  639. }
  640. /* Save prefetchable memory base and Limit registers */
  641. pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
  642. pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
  643. if ((w_base <= w_length) && (save_command & 0x02)) {
  644. p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
  645. if (!p_mem_node)
  646. return -ENOMEM;
  647. p_mem_node->base = w_base << 16;
  648. p_mem_node->length = (w_length - w_base + 0x10) << 16;
  649. p_mem_node->next = func->p_mem_head;
  650. func->p_mem_head = p_mem_node;
  651. }
  652. /* Figure out IO and memory base lengths */
  653. for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
  654. pci_bus_read_config_dword (pci_bus, devfn, cloop, &save_base);
  655. temp_register = 0xFFFFFFFF;
  656. pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
  657. pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
  658. temp_register = base;
  659. /* If this register is implemented */
  660. if (base) {
  661. if (((base & 0x03L) == 0x01)
  662. && (save_command & 0x01)) {
  663. /* IO base
  664. * set temp_register = amount
  665. * of IO space requested
  666. */
  667. temp_register = base & 0xFFFFFFFE;
  668. temp_register = (~temp_register) + 1;
  669. io_node = kmalloc(sizeof(*io_node),
  670. GFP_KERNEL);
  671. if (!io_node)
  672. return -ENOMEM;
  673. io_node->base =
  674. save_base & (~0x03L);
  675. io_node->length = temp_register;
  676. io_node->next = func->io_head;
  677. func->io_head = io_node;
  678. } else
  679. if (((base & 0x0BL) == 0x08)
  680. && (save_command & 0x02)) {
  681. /* prefetchable memory base */
  682. temp_register = base & 0xFFFFFFF0;
  683. temp_register = (~temp_register) + 1;
  684. p_mem_node = kmalloc(sizeof(*p_mem_node),
  685. GFP_KERNEL);
  686. if (!p_mem_node)
  687. return -ENOMEM;
  688. p_mem_node->base = save_base & (~0x0FL);
  689. p_mem_node->length = temp_register;
  690. p_mem_node->next = func->p_mem_head;
  691. func->p_mem_head = p_mem_node;
  692. } else
  693. if (((base & 0x0BL) == 0x00)
  694. && (save_command & 0x02)) {
  695. /* prefetchable memory base */
  696. temp_register = base & 0xFFFFFFF0;
  697. temp_register = (~temp_register) + 1;
  698. mem_node = kmalloc(sizeof(*mem_node),
  699. GFP_KERNEL);
  700. if (!mem_node)
  701. return -ENOMEM;
  702. mem_node->base = save_base & (~0x0FL);
  703. mem_node->length = temp_register;
  704. mem_node->next = func->mem_head;
  705. func->mem_head = mem_node;
  706. } else
  707. return(1);
  708. }
  709. } /* End of base register loop */
  710. /* Standard header */
  711. } else if ((header_type & 0x7F) == 0x00) {
  712. /* Figure out IO and memory base lengths */
  713. for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
  714. pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
  715. temp_register = 0xFFFFFFFF;
  716. pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
  717. pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
  718. temp_register = base;
  719. /* If this register is implemented */
  720. if (base) {
  721. if (((base & 0x03L) == 0x01)
  722. && (save_command & 0x01)) {
  723. /* IO base
  724. * set temp_register = amount
  725. * of IO space requested
  726. */
  727. temp_register = base & 0xFFFFFFFE;
  728. temp_register = (~temp_register) + 1;
  729. io_node = kmalloc(sizeof(*io_node),
  730. GFP_KERNEL);
  731. if (!io_node)
  732. return -ENOMEM;
  733. io_node->base = save_base & (~0x01L);
  734. io_node->length = temp_register;
  735. io_node->next = func->io_head;
  736. func->io_head = io_node;
  737. } else
  738. if (((base & 0x0BL) == 0x08)
  739. && (save_command & 0x02)) {
  740. /* prefetchable memory base */
  741. temp_register = base & 0xFFFFFFF0;
  742. temp_register = (~temp_register) + 1;
  743. p_mem_node = kmalloc(sizeof(*p_mem_node),
  744. GFP_KERNEL);
  745. if (!p_mem_node)
  746. return -ENOMEM;
  747. p_mem_node->base = save_base & (~0x0FL);
  748. p_mem_node->length = temp_register;
  749. p_mem_node->next = func->p_mem_head;
  750. func->p_mem_head = p_mem_node;
  751. } else
  752. if (((base & 0x0BL) == 0x00)
  753. && (save_command & 0x02)) {
  754. /* prefetchable memory base */
  755. temp_register = base & 0xFFFFFFF0;
  756. temp_register = (~temp_register) + 1;
  757. mem_node = kmalloc(sizeof(*mem_node),
  758. GFP_KERNEL);
  759. if (!mem_node)
  760. return -ENOMEM;
  761. mem_node->base = save_base & (~0x0FL);
  762. mem_node->length = temp_register;
  763. mem_node->next = func->mem_head;
  764. func->mem_head = mem_node;
  765. } else
  766. return(1);
  767. }
  768. } /* End of base register loop */
  769. }
  770. /* find the next device in this slot */
  771. func = cpqhp_slot_find(func->bus, func->device, index++);
  772. }
  773. return 0;
  774. }
  775. /*
  776. * cpqhp_configure_board
  777. *
  778. * Copies saved configuration information to one slot.
  779. * this is called recursively for bridge devices.
  780. * this is for hot plug REPLACE!
  781. *
  782. * returns 0 if success
  783. */
  784. int cpqhp_configure_board(struct controller *ctrl, struct pci_func * func)
  785. {
  786. int cloop;
  787. u8 header_type;
  788. u8 secondary_bus;
  789. int sub_bus;
  790. struct pci_func *next;
  791. u32 temp;
  792. u32 rc;
  793. int index = 0;
  794. struct pci_bus *pci_bus = ctrl->pci_bus;
  795. unsigned int devfn;
  796. func = cpqhp_slot_find(func->bus, func->device, index++);
  797. while (func != NULL) {
  798. pci_bus->number = func->bus;
  799. devfn = PCI_DEVFN(func->device, func->function);
  800. /* Start at the top of config space so that the control
  801. * registers are programmed last
  802. */
  803. for (cloop = 0x3C; cloop > 0; cloop -= 4)
  804. pci_bus_write_config_dword (pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
  805. pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
  806. /* If this is a bridge device, restore subordinate devices */
  807. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
  808. pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
  809. sub_bus = (int) secondary_bus;
  810. next = cpqhp_slot_list[sub_bus];
  811. while (next != NULL) {
  812. rc = cpqhp_configure_board(ctrl, next);
  813. if (rc)
  814. return rc;
  815. next = next->next;
  816. }
  817. } else {
  818. /* Check all the base Address Registers to make sure
  819. * they are the same. If not, the board is different.
  820. */
  821. for (cloop = 16; cloop < 40; cloop += 4) {
  822. pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp);
  823. if (temp != func->config_space[cloop >> 2]) {
  824. dbg("Config space compare failure!!! offset = %x\n", cloop);
  825. dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function);
  826. dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]);
  827. return 1;
  828. }
  829. }
  830. }
  831. func->configured = 1;
  832. func = cpqhp_slot_find(func->bus, func->device, index++);
  833. }
  834. return 0;
  835. }
  836. /*
  837. * cpqhp_valid_replace
  838. *
  839. * this function checks to see if a board is the same as the
  840. * one it is replacing. this check will detect if the device's
  841. * vendor or device id's are the same
  842. *
  843. * returns 0 if the board is the same nonzero otherwise
  844. */
  845. int cpqhp_valid_replace(struct controller *ctrl, struct pci_func * func)
  846. {
  847. u8 cloop;
  848. u8 header_type;
  849. u8 secondary_bus;
  850. u8 type;
  851. u32 temp_register = 0;
  852. u32 base;
  853. u32 rc;
  854. struct pci_func *next;
  855. int index = 0;
  856. struct pci_bus *pci_bus = ctrl->pci_bus;
  857. unsigned int devfn;
  858. if (!func->is_a_board)
  859. return(ADD_NOT_SUPPORTED);
  860. func = cpqhp_slot_find(func->bus, func->device, index++);
  861. while (func != NULL) {
  862. pci_bus->number = func->bus;
  863. devfn = PCI_DEVFN(func->device, func->function);
  864. pci_bus_read_config_dword (pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
  865. /* No adapter present */
  866. if (temp_register == 0xFFFFFFFF)
  867. return(NO_ADAPTER_PRESENT);
  868. if (temp_register != func->config_space[0])
  869. return(ADAPTER_NOT_SAME);
  870. /* Check for same revision number and class code */
  871. pci_bus_read_config_dword (pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
  872. /* Adapter not the same */
  873. if (temp_register != func->config_space[0x08 >> 2])
  874. return(ADAPTER_NOT_SAME);
  875. /* Check for Bridge */
  876. pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
  877. if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
  878. /* In order to continue checking, we must program the
  879. * bus registers in the bridge to respond to accesses
  880. * for its subordinate bus(es)
  881. */
  882. temp_register = func->config_space[0x18 >> 2];
  883. pci_bus_write_config_dword (pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
  884. secondary_bus = (temp_register >> 8) & 0xFF;
  885. next = cpqhp_slot_list[secondary_bus];
  886. while (next != NULL) {
  887. rc = cpqhp_valid_replace(ctrl, next);
  888. if (rc)
  889. return rc;
  890. next = next->next;
  891. }
  892. }
  893. /* Check to see if it is a standard config header */
  894. else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
  895. /* Check subsystem vendor and ID */
  896. pci_bus_read_config_dword (pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
  897. if (temp_register != func->config_space[0x2C >> 2]) {
  898. /* If it's a SMART-2 and the register isn't
  899. * filled in, ignore the difference because
  900. * they just have an old rev of the firmware
  901. */
  902. if (!((func->config_space[0] == 0xAE100E11)
  903. && (temp_register == 0x00L)))
  904. return(ADAPTER_NOT_SAME);
  905. }
  906. /* Figure out IO and memory base lengths */
  907. for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
  908. temp_register = 0xFFFFFFFF;
  909. pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
  910. pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
  911. /* If this register is implemented */
  912. if (base) {
  913. if (base & 0x01L) {
  914. /* IO base
  915. * set base = amount of IO
  916. * space requested
  917. */
  918. base = base & 0xFFFFFFFE;
  919. base = (~base) + 1;
  920. type = 1;
  921. } else {
  922. /* memory base */
  923. base = base & 0xFFFFFFF0;
  924. base = (~base) + 1;
  925. type = 0;
  926. }
  927. } else {
  928. base = 0x0L;
  929. type = 0;
  930. }
  931. /* Check information in slot structure */
  932. if (func->base_length[(cloop - 0x10) >> 2] != base)
  933. return(ADAPTER_NOT_SAME);
  934. if (func->base_type[(cloop - 0x10) >> 2] != type)
  935. return(ADAPTER_NOT_SAME);
  936. } /* End of base register loop */
  937. } /* End of (type 0 config space) else */
  938. else {
  939. /* this is not a type 0 or 1 config space header so
  940. * we don't know how to do it
  941. */
  942. return(DEVICE_TYPE_NOT_SUPPORTED);
  943. }
  944. /* Get the next function */
  945. func = cpqhp_slot_find(func->bus, func->device, index++);
  946. }
  947. return 0;
  948. }
  949. /*
  950. * cpqhp_find_available_resources
  951. *
  952. * Finds available memory, IO, and IRQ resources for programming
  953. * devices which may be added to the system
  954. * this function is for hot plug ADD!
  955. *
  956. * returns 0 if success
  957. */
  958. int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start)
  959. {
  960. u8 temp;
  961. u8 populated_slot;
  962. u8 bridged_slot;
  963. void __iomem *one_slot;
  964. void __iomem *rom_resource_table;
  965. struct pci_func *func = NULL;
  966. int i = 10, index;
  967. u32 temp_dword, rc;
  968. struct pci_resource *mem_node;
  969. struct pci_resource *p_mem_node;
  970. struct pci_resource *io_node;
  971. struct pci_resource *bus_node;
  972. rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff);
  973. dbg("rom_resource_table = %p\n", rom_resource_table);
  974. if (rom_resource_table == NULL)
  975. return -ENODEV;
  976. /* Sum all resources and setup resource maps */
  977. unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
  978. dbg("unused_IRQ = %x\n", unused_IRQ);
  979. temp = 0;
  980. while (unused_IRQ) {
  981. if (unused_IRQ & 1) {
  982. cpqhp_disk_irq = temp;
  983. break;
  984. }
  985. unused_IRQ = unused_IRQ >> 1;
  986. temp++;
  987. }
  988. dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq);
  989. unused_IRQ = unused_IRQ >> 1;
  990. temp++;
  991. while (unused_IRQ) {
  992. if (unused_IRQ & 1) {
  993. cpqhp_nic_irq = temp;
  994. break;
  995. }
  996. unused_IRQ = unused_IRQ >> 1;
  997. temp++;
  998. }
  999. dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq);
  1000. unused_IRQ = readl(rom_resource_table + PCIIRQ);
  1001. temp = 0;
  1002. if (!cpqhp_nic_irq)
  1003. cpqhp_nic_irq = ctrl->cfgspc_irq;
  1004. if (!cpqhp_disk_irq)
  1005. cpqhp_disk_irq = ctrl->cfgspc_irq;
  1006. dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq);
  1007. rc = compaq_nvram_load(rom_start, ctrl);
  1008. if (rc)
  1009. return rc;
  1010. one_slot = rom_resource_table + sizeof (struct hrt);
  1011. i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
  1012. dbg("number_of_entries = %d\n", i);
  1013. if (!readb(one_slot + SECONDARY_BUS))
  1014. return 1;
  1015. dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
  1016. while (i && readb(one_slot + SECONDARY_BUS)) {
  1017. u8 dev_func = readb(one_slot + DEV_FUNC);
  1018. u8 primary_bus = readb(one_slot + PRIMARY_BUS);
  1019. u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
  1020. u8 max_bus = readb(one_slot + MAX_BUS);
  1021. u16 io_base = readw(one_slot + IO_BASE);
  1022. u16 io_length = readw(one_slot + IO_LENGTH);
  1023. u16 mem_base = readw(one_slot + MEM_BASE);
  1024. u16 mem_length = readw(one_slot + MEM_LENGTH);
  1025. u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
  1026. u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
  1027. dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
  1028. dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
  1029. primary_bus, secondary_bus, max_bus);
  1030. /* If this entry isn't for our controller's bus, ignore it */
  1031. if (primary_bus != ctrl->bus) {
  1032. i--;
  1033. one_slot += sizeof (struct slot_rt);
  1034. continue;
  1035. }
  1036. /* find out if this entry is for an occupied slot */
  1037. ctrl->pci_bus->number = primary_bus;
  1038. pci_bus_read_config_dword (ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
  1039. dbg("temp_D_word = %x\n", temp_dword);
  1040. if (temp_dword != 0xFFFFFFFF) {
  1041. index = 0;
  1042. func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0);
  1043. while (func && (func->function != (dev_func & 0x07))) {
  1044. dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index);
  1045. func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++);
  1046. }
  1047. /* If we can't find a match, skip this table entry */
  1048. if (!func) {
  1049. i--;
  1050. one_slot += sizeof (struct slot_rt);
  1051. continue;
  1052. }
  1053. /* this may not work and shouldn't be used */
  1054. if (secondary_bus != primary_bus)
  1055. bridged_slot = 1;
  1056. else
  1057. bridged_slot = 0;
  1058. populated_slot = 1;
  1059. } else {
  1060. populated_slot = 0;
  1061. bridged_slot = 0;
  1062. }
  1063. /* If we've got a valid IO base, use it */
  1064. temp_dword = io_base + io_length;
  1065. if ((io_base) && (temp_dword < 0x10000)) {
  1066. io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
  1067. if (!io_node)
  1068. return -ENOMEM;
  1069. io_node->base = io_base;
  1070. io_node->length = io_length;
  1071. dbg("found io_node(base, length) = %x, %x\n",
  1072. io_node->base, io_node->length);
  1073. dbg("populated slot =%d \n", populated_slot);
  1074. if (!populated_slot) {
  1075. io_node->next = ctrl->io_head;
  1076. ctrl->io_head = io_node;
  1077. } else {
  1078. io_node->next = func->io_head;
  1079. func->io_head = io_node;
  1080. }
  1081. }
  1082. /* If we've got a valid memory base, use it */
  1083. temp_dword = mem_base + mem_length;
  1084. if ((mem_base) && (temp_dword < 0x10000)) {
  1085. mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
  1086. if (!mem_node)
  1087. return -ENOMEM;
  1088. mem_node->base = mem_base << 16;
  1089. mem_node->length = mem_length << 16;
  1090. dbg("found mem_node(base, length) = %x, %x\n",
  1091. mem_node->base, mem_node->length);
  1092. dbg("populated slot =%d \n", populated_slot);
  1093. if (!populated_slot) {
  1094. mem_node->next = ctrl->mem_head;
  1095. ctrl->mem_head = mem_node;
  1096. } else {
  1097. mem_node->next = func->mem_head;
  1098. func->mem_head = mem_node;
  1099. }
  1100. }
  1101. /* If we've got a valid prefetchable memory base, and
  1102. * the base + length isn't greater than 0xFFFF
  1103. */
  1104. temp_dword = pre_mem_base + pre_mem_length;
  1105. if ((pre_mem_base) && (temp_dword < 0x10000)) {
  1106. p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
  1107. if (!p_mem_node)
  1108. return -ENOMEM;
  1109. p_mem_node->base = pre_mem_base << 16;
  1110. p_mem_node->length = pre_mem_length << 16;
  1111. dbg("found p_mem_node(base, length) = %x, %x\n",
  1112. p_mem_node->base, p_mem_node->length);
  1113. dbg("populated slot =%d \n", populated_slot);
  1114. if (!populated_slot) {
  1115. p_mem_node->next = ctrl->p_mem_head;
  1116. ctrl->p_mem_head = p_mem_node;
  1117. } else {
  1118. p_mem_node->next = func->p_mem_head;
  1119. func->p_mem_head = p_mem_node;
  1120. }
  1121. }
  1122. /* If we've got a valid bus number, use it
  1123. * The second condition is to ignore bus numbers on
  1124. * populated slots that don't have PCI-PCI bridges
  1125. */
  1126. if (secondary_bus && (secondary_bus != primary_bus)) {
  1127. bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
  1128. if (!bus_node)
  1129. return -ENOMEM;
  1130. bus_node->base = secondary_bus;
  1131. bus_node->length = max_bus - secondary_bus + 1;
  1132. dbg("found bus_node(base, length) = %x, %x\n",
  1133. bus_node->base, bus_node->length);
  1134. dbg("populated slot =%d \n", populated_slot);
  1135. if (!populated_slot) {
  1136. bus_node->next = ctrl->bus_head;
  1137. ctrl->bus_head = bus_node;
  1138. } else {
  1139. bus_node->next = func->bus_head;
  1140. func->bus_head = bus_node;
  1141. }
  1142. }
  1143. i--;
  1144. one_slot += sizeof (struct slot_rt);
  1145. }
  1146. /* If all of the following fail, we don't have any resources for
  1147. * hot plug add
  1148. */
  1149. rc = 1;
  1150. rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head));
  1151. rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head));
  1152. rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head));
  1153. rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head));
  1154. return rc;
  1155. }
  1156. /*
  1157. * cpqhp_return_board_resources
  1158. *
  1159. * this routine returns all resources allocated to a board to
  1160. * the available pool.
  1161. *
  1162. * returns 0 if success
  1163. */
  1164. int cpqhp_return_board_resources(struct pci_func * func, struct resource_lists * resources)
  1165. {
  1166. int rc = 0;
  1167. struct pci_resource *node;
  1168. struct pci_resource *t_node;
  1169. dbg("%s\n", __func__);
  1170. if (!func)
  1171. return 1;
  1172. node = func->io_head;
  1173. func->io_head = NULL;
  1174. while (node) {
  1175. t_node = node->next;
  1176. return_resource(&(resources->io_head), node);
  1177. node = t_node;
  1178. }
  1179. node = func->mem_head;
  1180. func->mem_head = NULL;
  1181. while (node) {
  1182. t_node = node->next;
  1183. return_resource(&(resources->mem_head), node);
  1184. node = t_node;
  1185. }
  1186. node = func->p_mem_head;
  1187. func->p_mem_head = NULL;
  1188. while (node) {
  1189. t_node = node->next;
  1190. return_resource(&(resources->p_mem_head), node);
  1191. node = t_node;
  1192. }
  1193. node = func->bus_head;
  1194. func->bus_head = NULL;
  1195. while (node) {
  1196. t_node = node->next;
  1197. return_resource(&(resources->bus_head), node);
  1198. node = t_node;
  1199. }
  1200. rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head));
  1201. rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head));
  1202. rc |= cpqhp_resource_sort_and_combine(&(resources->io_head));
  1203. rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head));
  1204. return rc;
  1205. }
  1206. /*
  1207. * cpqhp_destroy_resource_list
  1208. *
  1209. * Puts node back in the resource list pointed to by head
  1210. */
  1211. void cpqhp_destroy_resource_list (struct resource_lists * resources)
  1212. {
  1213. struct pci_resource *res, *tres;
  1214. res = resources->io_head;
  1215. resources->io_head = NULL;
  1216. while (res) {
  1217. tres = res;
  1218. res = res->next;
  1219. kfree(tres);
  1220. }
  1221. res = resources->mem_head;
  1222. resources->mem_head = NULL;
  1223. while (res) {
  1224. tres = res;
  1225. res = res->next;
  1226. kfree(tres);
  1227. }
  1228. res = resources->p_mem_head;
  1229. resources->p_mem_head = NULL;
  1230. while (res) {
  1231. tres = res;
  1232. res = res->next;
  1233. kfree(tres);
  1234. }
  1235. res = resources->bus_head;
  1236. resources->bus_head = NULL;
  1237. while (res) {
  1238. tres = res;
  1239. res = res->next;
  1240. kfree(tres);
  1241. }
  1242. }
  1243. /*
  1244. * cpqhp_destroy_board_resources
  1245. *
  1246. * Puts node back in the resource list pointed to by head
  1247. */
  1248. void cpqhp_destroy_board_resources (struct pci_func * func)
  1249. {
  1250. struct pci_resource *res, *tres;
  1251. res = func->io_head;
  1252. func->io_head = NULL;
  1253. while (res) {
  1254. tres = res;
  1255. res = res->next;
  1256. kfree(tres);
  1257. }
  1258. res = func->mem_head;
  1259. func->mem_head = NULL;
  1260. while (res) {
  1261. tres = res;
  1262. res = res->next;
  1263. kfree(tres);
  1264. }
  1265. res = func->p_mem_head;
  1266. func->p_mem_head = NULL;
  1267. while (res) {
  1268. tres = res;
  1269. res = res->next;
  1270. kfree(tres);
  1271. }
  1272. res = func->bus_head;
  1273. func->bus_head = NULL;
  1274. while (res) {
  1275. tres = res;
  1276. res = res->next;
  1277. kfree(tres);
  1278. }
  1279. }