omap_hwmod_2420_data.c 57 KB

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  1. /*
  2. * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
  3. *
  4. * Copyright (C) 2009-2010 Nokia Corporation
  5. * Paul Walmsley
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * XXX handle crossbar/shared link difference for L3?
  12. * XXX these should be marked initdata for multi-OMAP kernels
  13. */
  14. #include <plat/omap_hwmod.h>
  15. #include <mach/irqs.h>
  16. #include <plat/cpu.h>
  17. #include <plat/dma.h>
  18. #include <plat/serial.h>
  19. #include <plat/i2c.h>
  20. #include <plat/gpio.h>
  21. #include <plat/mcspi.h>
  22. #include <plat/dmtimer.h>
  23. #include <plat/l3_2xxx.h>
  24. #include <plat/l4_2xxx.h>
  25. #include "omap_hwmod_common_data.h"
  26. #include "cm-regbits-24xx.h"
  27. #include "prm-regbits-24xx.h"
  28. #include "wd_timer.h"
  29. /*
  30. * OMAP2420 hardware module integration data
  31. *
  32. * ALl of the data in this section should be autogeneratable from the
  33. * TI hardware database or other technical documentation. Data that
  34. * is driver-specific or driver-kernel integration-specific belongs
  35. * elsewhere.
  36. */
  37. static struct omap_hwmod omap2420_mpu_hwmod;
  38. static struct omap_hwmod omap2420_iva_hwmod;
  39. static struct omap_hwmod omap2420_l3_main_hwmod;
  40. static struct omap_hwmod omap2420_l4_core_hwmod;
  41. static struct omap_hwmod omap2420_dss_core_hwmod;
  42. static struct omap_hwmod omap2420_dss_dispc_hwmod;
  43. static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  44. static struct omap_hwmod omap2420_dss_venc_hwmod;
  45. static struct omap_hwmod omap2420_wd_timer2_hwmod;
  46. static struct omap_hwmod omap2420_gpio1_hwmod;
  47. static struct omap_hwmod omap2420_gpio2_hwmod;
  48. static struct omap_hwmod omap2420_gpio3_hwmod;
  49. static struct omap_hwmod omap2420_gpio4_hwmod;
  50. static struct omap_hwmod omap2420_dma_system_hwmod;
  51. static struct omap_hwmod omap2420_mcspi1_hwmod;
  52. static struct omap_hwmod omap2420_mcspi2_hwmod;
  53. /* L3 -> L4_CORE interface */
  54. static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  55. .master = &omap2420_l3_main_hwmod,
  56. .slave = &omap2420_l4_core_hwmod,
  57. .user = OCP_USER_MPU | OCP_USER_SDMA,
  58. };
  59. /* MPU -> L3 interface */
  60. static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  61. .master = &omap2420_mpu_hwmod,
  62. .slave = &omap2420_l3_main_hwmod,
  63. .user = OCP_USER_MPU,
  64. };
  65. /* Slave interfaces on the L3 interconnect */
  66. static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  67. &omap2420_mpu__l3_main,
  68. };
  69. /* DSS -> l3 */
  70. static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  71. .master = &omap2420_dss_core_hwmod,
  72. .slave = &omap2420_l3_main_hwmod,
  73. .fw = {
  74. .omap2 = {
  75. .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
  76. .flags = OMAP_FIREWALL_L3,
  77. }
  78. },
  79. .user = OCP_USER_MPU | OCP_USER_SDMA,
  80. };
  81. /* Master interfaces on the L3 interconnect */
  82. static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  83. &omap2420_l3_main__l4_core,
  84. };
  85. /* L3 */
  86. static struct omap_hwmod omap2420_l3_main_hwmod = {
  87. .name = "l3_main",
  88. .class = &l3_hwmod_class,
  89. .masters = omap2420_l3_main_masters,
  90. .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
  91. .slaves = omap2420_l3_main_slaves,
  92. .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
  93. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  94. .flags = HWMOD_NO_IDLEST,
  95. };
  96. static struct omap_hwmod omap2420_l4_wkup_hwmod;
  97. static struct omap_hwmod omap2420_uart1_hwmod;
  98. static struct omap_hwmod omap2420_uart2_hwmod;
  99. static struct omap_hwmod omap2420_uart3_hwmod;
  100. static struct omap_hwmod omap2420_i2c1_hwmod;
  101. static struct omap_hwmod omap2420_i2c2_hwmod;
  102. static struct omap_hwmod omap2420_mcbsp1_hwmod;
  103. static struct omap_hwmod omap2420_mcbsp2_hwmod;
  104. /* l4 core -> mcspi1 interface */
  105. static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
  106. {
  107. .pa_start = 0x48098000,
  108. .pa_end = 0x480980ff,
  109. .flags = ADDR_TYPE_RT,
  110. },
  111. };
  112. static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
  113. .master = &omap2420_l4_core_hwmod,
  114. .slave = &omap2420_mcspi1_hwmod,
  115. .clk = "mcspi1_ick",
  116. .addr = omap2420_mcspi1_addr_space,
  117. .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
  118. .user = OCP_USER_MPU | OCP_USER_SDMA,
  119. };
  120. /* l4 core -> mcspi2 interface */
  121. static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
  122. {
  123. .pa_start = 0x4809a000,
  124. .pa_end = 0x4809a0ff,
  125. .flags = ADDR_TYPE_RT,
  126. },
  127. };
  128. static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
  129. .master = &omap2420_l4_core_hwmod,
  130. .slave = &omap2420_mcspi2_hwmod,
  131. .clk = "mcspi2_ick",
  132. .addr = omap2420_mcspi2_addr_space,
  133. .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
  134. .user = OCP_USER_MPU | OCP_USER_SDMA,
  135. };
  136. /* L4_CORE -> L4_WKUP interface */
  137. static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
  138. .master = &omap2420_l4_core_hwmod,
  139. .slave = &omap2420_l4_wkup_hwmod,
  140. .user = OCP_USER_MPU | OCP_USER_SDMA,
  141. };
  142. /* L4 CORE -> UART1 interface */
  143. static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
  144. {
  145. .pa_start = OMAP2_UART1_BASE,
  146. .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
  147. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  148. },
  149. };
  150. static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
  151. .master = &omap2420_l4_core_hwmod,
  152. .slave = &omap2420_uart1_hwmod,
  153. .clk = "uart1_ick",
  154. .addr = omap2420_uart1_addr_space,
  155. .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
  156. .user = OCP_USER_MPU | OCP_USER_SDMA,
  157. };
  158. /* L4 CORE -> UART2 interface */
  159. static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
  160. {
  161. .pa_start = OMAP2_UART2_BASE,
  162. .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
  163. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  164. },
  165. };
  166. static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
  167. .master = &omap2420_l4_core_hwmod,
  168. .slave = &omap2420_uart2_hwmod,
  169. .clk = "uart2_ick",
  170. .addr = omap2420_uart2_addr_space,
  171. .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
  172. .user = OCP_USER_MPU | OCP_USER_SDMA,
  173. };
  174. /* L4 PER -> UART3 interface */
  175. static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
  176. {
  177. .pa_start = OMAP2_UART3_BASE,
  178. .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
  179. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  180. },
  181. };
  182. static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
  183. .master = &omap2420_l4_core_hwmod,
  184. .slave = &omap2420_uart3_hwmod,
  185. .clk = "uart3_ick",
  186. .addr = omap2420_uart3_addr_space,
  187. .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
  188. .user = OCP_USER_MPU | OCP_USER_SDMA,
  189. };
  190. /* I2C IP block address space length (in bytes) */
  191. #define OMAP2_I2C_AS_LEN 128
  192. /* L4 CORE -> I2C1 interface */
  193. static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
  194. {
  195. .pa_start = 0x48070000,
  196. .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
  197. .flags = ADDR_TYPE_RT,
  198. },
  199. };
  200. static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
  201. .master = &omap2420_l4_core_hwmod,
  202. .slave = &omap2420_i2c1_hwmod,
  203. .clk = "i2c1_ick",
  204. .addr = omap2420_i2c1_addr_space,
  205. .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
  206. .user = OCP_USER_MPU | OCP_USER_SDMA,
  207. };
  208. /* L4 CORE -> I2C2 interface */
  209. static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
  210. {
  211. .pa_start = 0x48072000,
  212. .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
  213. .flags = ADDR_TYPE_RT,
  214. },
  215. };
  216. static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
  217. .master = &omap2420_l4_core_hwmod,
  218. .slave = &omap2420_i2c2_hwmod,
  219. .clk = "i2c2_ick",
  220. .addr = omap2420_i2c2_addr_space,
  221. .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
  222. .user = OCP_USER_MPU | OCP_USER_SDMA,
  223. };
  224. /* Slave interfaces on the L4_CORE interconnect */
  225. static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
  226. &omap2420_l3_main__l4_core,
  227. };
  228. /* Master interfaces on the L4_CORE interconnect */
  229. static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
  230. &omap2420_l4_core__l4_wkup,
  231. &omap2_l4_core__uart1,
  232. &omap2_l4_core__uart2,
  233. &omap2_l4_core__uart3,
  234. &omap2420_l4_core__i2c1,
  235. &omap2420_l4_core__i2c2
  236. };
  237. /* L4 CORE */
  238. static struct omap_hwmod omap2420_l4_core_hwmod = {
  239. .name = "l4_core",
  240. .class = &l4_hwmod_class,
  241. .masters = omap2420_l4_core_masters,
  242. .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
  243. .slaves = omap2420_l4_core_slaves,
  244. .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
  245. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  246. .flags = HWMOD_NO_IDLEST,
  247. };
  248. /* Slave interfaces on the L4_WKUP interconnect */
  249. static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
  250. &omap2420_l4_core__l4_wkup,
  251. };
  252. /* Master interfaces on the L4_WKUP interconnect */
  253. static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
  254. };
  255. /* L4 WKUP */
  256. static struct omap_hwmod omap2420_l4_wkup_hwmod = {
  257. .name = "l4_wkup",
  258. .class = &l4_hwmod_class,
  259. .masters = omap2420_l4_wkup_masters,
  260. .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
  261. .slaves = omap2420_l4_wkup_slaves,
  262. .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
  263. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  264. .flags = HWMOD_NO_IDLEST,
  265. };
  266. /* Master interfaces on the MPU device */
  267. static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
  268. &omap2420_mpu__l3_main,
  269. };
  270. /* MPU */
  271. static struct omap_hwmod omap2420_mpu_hwmod = {
  272. .name = "mpu",
  273. .class = &mpu_hwmod_class,
  274. .main_clk = "mpu_ck",
  275. .masters = omap2420_mpu_masters,
  276. .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
  277. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  278. };
  279. /*
  280. * IVA1 interface data
  281. */
  282. /* IVA <- L3 interface */
  283. static struct omap_hwmod_ocp_if omap2420_l3__iva = {
  284. .master = &omap2420_l3_main_hwmod,
  285. .slave = &omap2420_iva_hwmod,
  286. .clk = "iva1_ifck",
  287. .user = OCP_USER_MPU | OCP_USER_SDMA,
  288. };
  289. static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
  290. &omap2420_l3__iva,
  291. };
  292. /*
  293. * IVA2 (IVA2)
  294. */
  295. static struct omap_hwmod omap2420_iva_hwmod = {
  296. .name = "iva",
  297. .class = &iva_hwmod_class,
  298. .masters = omap2420_iva_masters,
  299. .masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
  300. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  301. };
  302. /* Timer Common */
  303. static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
  304. .rev_offs = 0x0000,
  305. .sysc_offs = 0x0010,
  306. .syss_offs = 0x0014,
  307. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  308. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  309. SYSC_HAS_AUTOIDLE),
  310. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  311. .sysc_fields = &omap_hwmod_sysc_type1,
  312. };
  313. static struct omap_hwmod_class omap2420_timer_hwmod_class = {
  314. .name = "timer",
  315. .sysc = &omap2420_timer_sysc,
  316. .rev = OMAP_TIMER_IP_VERSION_1,
  317. };
  318. /* timer1 */
  319. static struct omap_hwmod omap2420_timer1_hwmod;
  320. static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
  321. { .irq = 37, },
  322. };
  323. static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
  324. {
  325. .pa_start = 0x48028000,
  326. .pa_end = 0x48028000 + SZ_1K - 1,
  327. .flags = ADDR_TYPE_RT
  328. },
  329. };
  330. /* l4_wkup -> timer1 */
  331. static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
  332. .master = &omap2420_l4_wkup_hwmod,
  333. .slave = &omap2420_timer1_hwmod,
  334. .clk = "gpt1_ick",
  335. .addr = omap2420_timer1_addrs,
  336. .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
  337. .user = OCP_USER_MPU | OCP_USER_SDMA,
  338. };
  339. /* timer1 slave port */
  340. static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
  341. &omap2420_l4_wkup__timer1,
  342. };
  343. /* timer1 hwmod */
  344. static struct omap_hwmod omap2420_timer1_hwmod = {
  345. .name = "timer1",
  346. .mpu_irqs = omap2420_timer1_mpu_irqs,
  347. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
  348. .main_clk = "gpt1_fck",
  349. .prcm = {
  350. .omap2 = {
  351. .prcm_reg_id = 1,
  352. .module_bit = OMAP24XX_EN_GPT1_SHIFT,
  353. .module_offs = WKUP_MOD,
  354. .idlest_reg_id = 1,
  355. .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
  356. },
  357. },
  358. .slaves = omap2420_timer1_slaves,
  359. .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
  360. .class = &omap2420_timer_hwmod_class,
  361. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  362. };
  363. /* timer2 */
  364. static struct omap_hwmod omap2420_timer2_hwmod;
  365. static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
  366. { .irq = 38, },
  367. };
  368. static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
  369. {
  370. .pa_start = 0x4802a000,
  371. .pa_end = 0x4802a000 + SZ_1K - 1,
  372. .flags = ADDR_TYPE_RT
  373. },
  374. };
  375. /* l4_core -> timer2 */
  376. static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
  377. .master = &omap2420_l4_core_hwmod,
  378. .slave = &omap2420_timer2_hwmod,
  379. .clk = "gpt2_ick",
  380. .addr = omap2420_timer2_addrs,
  381. .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
  382. .user = OCP_USER_MPU | OCP_USER_SDMA,
  383. };
  384. /* timer2 slave port */
  385. static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
  386. &omap2420_l4_core__timer2,
  387. };
  388. /* timer2 hwmod */
  389. static struct omap_hwmod omap2420_timer2_hwmod = {
  390. .name = "timer2",
  391. .mpu_irqs = omap2420_timer2_mpu_irqs,
  392. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
  393. .main_clk = "gpt2_fck",
  394. .prcm = {
  395. .omap2 = {
  396. .prcm_reg_id = 1,
  397. .module_bit = OMAP24XX_EN_GPT2_SHIFT,
  398. .module_offs = CORE_MOD,
  399. .idlest_reg_id = 1,
  400. .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
  401. },
  402. },
  403. .slaves = omap2420_timer2_slaves,
  404. .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
  405. .class = &omap2420_timer_hwmod_class,
  406. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  407. };
  408. /* timer3 */
  409. static struct omap_hwmod omap2420_timer3_hwmod;
  410. static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
  411. { .irq = 39, },
  412. };
  413. static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
  414. {
  415. .pa_start = 0x48078000,
  416. .pa_end = 0x48078000 + SZ_1K - 1,
  417. .flags = ADDR_TYPE_RT
  418. },
  419. };
  420. /* l4_core -> timer3 */
  421. static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
  422. .master = &omap2420_l4_core_hwmod,
  423. .slave = &omap2420_timer3_hwmod,
  424. .clk = "gpt3_ick",
  425. .addr = omap2420_timer3_addrs,
  426. .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
  427. .user = OCP_USER_MPU | OCP_USER_SDMA,
  428. };
  429. /* timer3 slave port */
  430. static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
  431. &omap2420_l4_core__timer3,
  432. };
  433. /* timer3 hwmod */
  434. static struct omap_hwmod omap2420_timer3_hwmod = {
  435. .name = "timer3",
  436. .mpu_irqs = omap2420_timer3_mpu_irqs,
  437. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
  438. .main_clk = "gpt3_fck",
  439. .prcm = {
  440. .omap2 = {
  441. .prcm_reg_id = 1,
  442. .module_bit = OMAP24XX_EN_GPT3_SHIFT,
  443. .module_offs = CORE_MOD,
  444. .idlest_reg_id = 1,
  445. .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
  446. },
  447. },
  448. .slaves = omap2420_timer3_slaves,
  449. .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
  450. .class = &omap2420_timer_hwmod_class,
  451. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  452. };
  453. /* timer4 */
  454. static struct omap_hwmod omap2420_timer4_hwmod;
  455. static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
  456. { .irq = 40, },
  457. };
  458. static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
  459. {
  460. .pa_start = 0x4807a000,
  461. .pa_end = 0x4807a000 + SZ_1K - 1,
  462. .flags = ADDR_TYPE_RT
  463. },
  464. };
  465. /* l4_core -> timer4 */
  466. static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
  467. .master = &omap2420_l4_core_hwmod,
  468. .slave = &omap2420_timer4_hwmod,
  469. .clk = "gpt4_ick",
  470. .addr = omap2420_timer4_addrs,
  471. .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
  472. .user = OCP_USER_MPU | OCP_USER_SDMA,
  473. };
  474. /* timer4 slave port */
  475. static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
  476. &omap2420_l4_core__timer4,
  477. };
  478. /* timer4 hwmod */
  479. static struct omap_hwmod omap2420_timer4_hwmod = {
  480. .name = "timer4",
  481. .mpu_irqs = omap2420_timer4_mpu_irqs,
  482. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
  483. .main_clk = "gpt4_fck",
  484. .prcm = {
  485. .omap2 = {
  486. .prcm_reg_id = 1,
  487. .module_bit = OMAP24XX_EN_GPT4_SHIFT,
  488. .module_offs = CORE_MOD,
  489. .idlest_reg_id = 1,
  490. .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
  491. },
  492. },
  493. .slaves = omap2420_timer4_slaves,
  494. .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
  495. .class = &omap2420_timer_hwmod_class,
  496. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  497. };
  498. /* timer5 */
  499. static struct omap_hwmod omap2420_timer5_hwmod;
  500. static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
  501. { .irq = 41, },
  502. };
  503. static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
  504. {
  505. .pa_start = 0x4807c000,
  506. .pa_end = 0x4807c000 + SZ_1K - 1,
  507. .flags = ADDR_TYPE_RT
  508. },
  509. };
  510. /* l4_core -> timer5 */
  511. static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
  512. .master = &omap2420_l4_core_hwmod,
  513. .slave = &omap2420_timer5_hwmod,
  514. .clk = "gpt5_ick",
  515. .addr = omap2420_timer5_addrs,
  516. .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
  517. .user = OCP_USER_MPU | OCP_USER_SDMA,
  518. };
  519. /* timer5 slave port */
  520. static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
  521. &omap2420_l4_core__timer5,
  522. };
  523. /* timer5 hwmod */
  524. static struct omap_hwmod omap2420_timer5_hwmod = {
  525. .name = "timer5",
  526. .mpu_irqs = omap2420_timer5_mpu_irqs,
  527. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
  528. .main_clk = "gpt5_fck",
  529. .prcm = {
  530. .omap2 = {
  531. .prcm_reg_id = 1,
  532. .module_bit = OMAP24XX_EN_GPT5_SHIFT,
  533. .module_offs = CORE_MOD,
  534. .idlest_reg_id = 1,
  535. .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
  536. },
  537. },
  538. .slaves = omap2420_timer5_slaves,
  539. .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
  540. .class = &omap2420_timer_hwmod_class,
  541. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  542. };
  543. /* timer6 */
  544. static struct omap_hwmod omap2420_timer6_hwmod;
  545. static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
  546. { .irq = 42, },
  547. };
  548. static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
  549. {
  550. .pa_start = 0x4807e000,
  551. .pa_end = 0x4807e000 + SZ_1K - 1,
  552. .flags = ADDR_TYPE_RT
  553. },
  554. };
  555. /* l4_core -> timer6 */
  556. static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
  557. .master = &omap2420_l4_core_hwmod,
  558. .slave = &omap2420_timer6_hwmod,
  559. .clk = "gpt6_ick",
  560. .addr = omap2420_timer6_addrs,
  561. .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
  562. .user = OCP_USER_MPU | OCP_USER_SDMA,
  563. };
  564. /* timer6 slave port */
  565. static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
  566. &omap2420_l4_core__timer6,
  567. };
  568. /* timer6 hwmod */
  569. static struct omap_hwmod omap2420_timer6_hwmod = {
  570. .name = "timer6",
  571. .mpu_irqs = omap2420_timer6_mpu_irqs,
  572. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
  573. .main_clk = "gpt6_fck",
  574. .prcm = {
  575. .omap2 = {
  576. .prcm_reg_id = 1,
  577. .module_bit = OMAP24XX_EN_GPT6_SHIFT,
  578. .module_offs = CORE_MOD,
  579. .idlest_reg_id = 1,
  580. .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
  581. },
  582. },
  583. .slaves = omap2420_timer6_slaves,
  584. .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
  585. .class = &omap2420_timer_hwmod_class,
  586. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  587. };
  588. /* timer7 */
  589. static struct omap_hwmod omap2420_timer7_hwmod;
  590. static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
  591. { .irq = 43, },
  592. };
  593. static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
  594. {
  595. .pa_start = 0x48080000,
  596. .pa_end = 0x48080000 + SZ_1K - 1,
  597. .flags = ADDR_TYPE_RT
  598. },
  599. };
  600. /* l4_core -> timer7 */
  601. static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
  602. .master = &omap2420_l4_core_hwmod,
  603. .slave = &omap2420_timer7_hwmod,
  604. .clk = "gpt7_ick",
  605. .addr = omap2420_timer7_addrs,
  606. .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
  607. .user = OCP_USER_MPU | OCP_USER_SDMA,
  608. };
  609. /* timer7 slave port */
  610. static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
  611. &omap2420_l4_core__timer7,
  612. };
  613. /* timer7 hwmod */
  614. static struct omap_hwmod omap2420_timer7_hwmod = {
  615. .name = "timer7",
  616. .mpu_irqs = omap2420_timer7_mpu_irqs,
  617. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
  618. .main_clk = "gpt7_fck",
  619. .prcm = {
  620. .omap2 = {
  621. .prcm_reg_id = 1,
  622. .module_bit = OMAP24XX_EN_GPT7_SHIFT,
  623. .module_offs = CORE_MOD,
  624. .idlest_reg_id = 1,
  625. .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
  626. },
  627. },
  628. .slaves = omap2420_timer7_slaves,
  629. .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
  630. .class = &omap2420_timer_hwmod_class,
  631. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  632. };
  633. /* timer8 */
  634. static struct omap_hwmod omap2420_timer8_hwmod;
  635. static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
  636. { .irq = 44, },
  637. };
  638. static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
  639. {
  640. .pa_start = 0x48082000,
  641. .pa_end = 0x48082000 + SZ_1K - 1,
  642. .flags = ADDR_TYPE_RT
  643. },
  644. };
  645. /* l4_core -> timer8 */
  646. static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
  647. .master = &omap2420_l4_core_hwmod,
  648. .slave = &omap2420_timer8_hwmod,
  649. .clk = "gpt8_ick",
  650. .addr = omap2420_timer8_addrs,
  651. .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
  652. .user = OCP_USER_MPU | OCP_USER_SDMA,
  653. };
  654. /* timer8 slave port */
  655. static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
  656. &omap2420_l4_core__timer8,
  657. };
  658. /* timer8 hwmod */
  659. static struct omap_hwmod omap2420_timer8_hwmod = {
  660. .name = "timer8",
  661. .mpu_irqs = omap2420_timer8_mpu_irqs,
  662. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
  663. .main_clk = "gpt8_fck",
  664. .prcm = {
  665. .omap2 = {
  666. .prcm_reg_id = 1,
  667. .module_bit = OMAP24XX_EN_GPT8_SHIFT,
  668. .module_offs = CORE_MOD,
  669. .idlest_reg_id = 1,
  670. .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
  671. },
  672. },
  673. .slaves = omap2420_timer8_slaves,
  674. .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
  675. .class = &omap2420_timer_hwmod_class,
  676. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  677. };
  678. /* timer9 */
  679. static struct omap_hwmod omap2420_timer9_hwmod;
  680. static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
  681. { .irq = 45, },
  682. };
  683. static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
  684. {
  685. .pa_start = 0x48084000,
  686. .pa_end = 0x48084000 + SZ_1K - 1,
  687. .flags = ADDR_TYPE_RT
  688. },
  689. };
  690. /* l4_core -> timer9 */
  691. static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
  692. .master = &omap2420_l4_core_hwmod,
  693. .slave = &omap2420_timer9_hwmod,
  694. .clk = "gpt9_ick",
  695. .addr = omap2420_timer9_addrs,
  696. .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
  697. .user = OCP_USER_MPU | OCP_USER_SDMA,
  698. };
  699. /* timer9 slave port */
  700. static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
  701. &omap2420_l4_core__timer9,
  702. };
  703. /* timer9 hwmod */
  704. static struct omap_hwmod omap2420_timer9_hwmod = {
  705. .name = "timer9",
  706. .mpu_irqs = omap2420_timer9_mpu_irqs,
  707. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
  708. .main_clk = "gpt9_fck",
  709. .prcm = {
  710. .omap2 = {
  711. .prcm_reg_id = 1,
  712. .module_bit = OMAP24XX_EN_GPT9_SHIFT,
  713. .module_offs = CORE_MOD,
  714. .idlest_reg_id = 1,
  715. .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
  716. },
  717. },
  718. .slaves = omap2420_timer9_slaves,
  719. .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
  720. .class = &omap2420_timer_hwmod_class,
  721. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  722. };
  723. /* timer10 */
  724. static struct omap_hwmod omap2420_timer10_hwmod;
  725. static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
  726. { .irq = 46, },
  727. };
  728. static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
  729. {
  730. .pa_start = 0x48086000,
  731. .pa_end = 0x48086000 + SZ_1K - 1,
  732. .flags = ADDR_TYPE_RT
  733. },
  734. };
  735. /* l4_core -> timer10 */
  736. static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
  737. .master = &omap2420_l4_core_hwmod,
  738. .slave = &omap2420_timer10_hwmod,
  739. .clk = "gpt10_ick",
  740. .addr = omap2420_timer10_addrs,
  741. .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
  742. .user = OCP_USER_MPU | OCP_USER_SDMA,
  743. };
  744. /* timer10 slave port */
  745. static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
  746. &omap2420_l4_core__timer10,
  747. };
  748. /* timer10 hwmod */
  749. static struct omap_hwmod omap2420_timer10_hwmod = {
  750. .name = "timer10",
  751. .mpu_irqs = omap2420_timer10_mpu_irqs,
  752. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
  753. .main_clk = "gpt10_fck",
  754. .prcm = {
  755. .omap2 = {
  756. .prcm_reg_id = 1,
  757. .module_bit = OMAP24XX_EN_GPT10_SHIFT,
  758. .module_offs = CORE_MOD,
  759. .idlest_reg_id = 1,
  760. .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
  761. },
  762. },
  763. .slaves = omap2420_timer10_slaves,
  764. .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
  765. .class = &omap2420_timer_hwmod_class,
  766. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  767. };
  768. /* timer11 */
  769. static struct omap_hwmod omap2420_timer11_hwmod;
  770. static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
  771. { .irq = 47, },
  772. };
  773. static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
  774. {
  775. .pa_start = 0x48088000,
  776. .pa_end = 0x48088000 + SZ_1K - 1,
  777. .flags = ADDR_TYPE_RT
  778. },
  779. };
  780. /* l4_core -> timer11 */
  781. static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
  782. .master = &omap2420_l4_core_hwmod,
  783. .slave = &omap2420_timer11_hwmod,
  784. .clk = "gpt11_ick",
  785. .addr = omap2420_timer11_addrs,
  786. .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
  787. .user = OCP_USER_MPU | OCP_USER_SDMA,
  788. };
  789. /* timer11 slave port */
  790. static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
  791. &omap2420_l4_core__timer11,
  792. };
  793. /* timer11 hwmod */
  794. static struct omap_hwmod omap2420_timer11_hwmod = {
  795. .name = "timer11",
  796. .mpu_irqs = omap2420_timer11_mpu_irqs,
  797. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
  798. .main_clk = "gpt11_fck",
  799. .prcm = {
  800. .omap2 = {
  801. .prcm_reg_id = 1,
  802. .module_bit = OMAP24XX_EN_GPT11_SHIFT,
  803. .module_offs = CORE_MOD,
  804. .idlest_reg_id = 1,
  805. .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
  806. },
  807. },
  808. .slaves = omap2420_timer11_slaves,
  809. .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
  810. .class = &omap2420_timer_hwmod_class,
  811. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  812. };
  813. /* timer12 */
  814. static struct omap_hwmod omap2420_timer12_hwmod;
  815. static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
  816. { .irq = 48, },
  817. };
  818. static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
  819. {
  820. .pa_start = 0x4808a000,
  821. .pa_end = 0x4808a000 + SZ_1K - 1,
  822. .flags = ADDR_TYPE_RT
  823. },
  824. };
  825. /* l4_core -> timer12 */
  826. static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
  827. .master = &omap2420_l4_core_hwmod,
  828. .slave = &omap2420_timer12_hwmod,
  829. .clk = "gpt12_ick",
  830. .addr = omap2420_timer12_addrs,
  831. .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
  832. .user = OCP_USER_MPU | OCP_USER_SDMA,
  833. };
  834. /* timer12 slave port */
  835. static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
  836. &omap2420_l4_core__timer12,
  837. };
  838. /* timer12 hwmod */
  839. static struct omap_hwmod omap2420_timer12_hwmod = {
  840. .name = "timer12",
  841. .mpu_irqs = omap2420_timer12_mpu_irqs,
  842. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
  843. .main_clk = "gpt12_fck",
  844. .prcm = {
  845. .omap2 = {
  846. .prcm_reg_id = 1,
  847. .module_bit = OMAP24XX_EN_GPT12_SHIFT,
  848. .module_offs = CORE_MOD,
  849. .idlest_reg_id = 1,
  850. .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
  851. },
  852. },
  853. .slaves = omap2420_timer12_slaves,
  854. .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
  855. .class = &omap2420_timer_hwmod_class,
  856. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
  857. };
  858. /* l4_wkup -> wd_timer2 */
  859. static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
  860. {
  861. .pa_start = 0x48022000,
  862. .pa_end = 0x4802207f,
  863. .flags = ADDR_TYPE_RT
  864. },
  865. };
  866. static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
  867. .master = &omap2420_l4_wkup_hwmod,
  868. .slave = &omap2420_wd_timer2_hwmod,
  869. .clk = "mpu_wdt_ick",
  870. .addr = omap2420_wd_timer2_addrs,
  871. .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
  872. .user = OCP_USER_MPU | OCP_USER_SDMA,
  873. };
  874. /*
  875. * 'wd_timer' class
  876. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  877. * overflow condition
  878. */
  879. static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
  880. .rev_offs = 0x0000,
  881. .sysc_offs = 0x0010,
  882. .syss_offs = 0x0014,
  883. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  884. SYSC_HAS_AUTOIDLE),
  885. .sysc_fields = &omap_hwmod_sysc_type1,
  886. };
  887. static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
  888. .name = "wd_timer",
  889. .sysc = &omap2420_wd_timer_sysc,
  890. .pre_shutdown = &omap2_wd_timer_disable
  891. };
  892. /* wd_timer2 */
  893. static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
  894. &omap2420_l4_wkup__wd_timer2,
  895. };
  896. static struct omap_hwmod omap2420_wd_timer2_hwmod = {
  897. .name = "wd_timer2",
  898. .class = &omap2420_wd_timer_hwmod_class,
  899. .main_clk = "mpu_wdt_fck",
  900. .prcm = {
  901. .omap2 = {
  902. .prcm_reg_id = 1,
  903. .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
  904. .module_offs = WKUP_MOD,
  905. .idlest_reg_id = 1,
  906. .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
  907. },
  908. },
  909. .slaves = omap2420_wd_timer2_slaves,
  910. .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
  911. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  912. };
  913. /* UART */
  914. static struct omap_hwmod_class_sysconfig uart_sysc = {
  915. .rev_offs = 0x50,
  916. .sysc_offs = 0x54,
  917. .syss_offs = 0x58,
  918. .sysc_flags = (SYSC_HAS_SIDLEMODE |
  919. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  920. SYSC_HAS_AUTOIDLE),
  921. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  922. .sysc_fields = &omap_hwmod_sysc_type1,
  923. };
  924. static struct omap_hwmod_class uart_class = {
  925. .name = "uart",
  926. .sysc = &uart_sysc,
  927. };
  928. /* UART1 */
  929. static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
  930. { .irq = INT_24XX_UART1_IRQ, },
  931. };
  932. static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
  933. { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
  934. { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
  935. };
  936. static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
  937. &omap2_l4_core__uart1,
  938. };
  939. static struct omap_hwmod omap2420_uart1_hwmod = {
  940. .name = "uart1",
  941. .mpu_irqs = uart1_mpu_irqs,
  942. .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
  943. .sdma_reqs = uart1_sdma_reqs,
  944. .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
  945. .main_clk = "uart1_fck",
  946. .prcm = {
  947. .omap2 = {
  948. .module_offs = CORE_MOD,
  949. .prcm_reg_id = 1,
  950. .module_bit = OMAP24XX_EN_UART1_SHIFT,
  951. .idlest_reg_id = 1,
  952. .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
  953. },
  954. },
  955. .slaves = omap2420_uart1_slaves,
  956. .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
  957. .class = &uart_class,
  958. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  959. };
  960. /* UART2 */
  961. static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
  962. { .irq = INT_24XX_UART2_IRQ, },
  963. };
  964. static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
  965. { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
  966. { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
  967. };
  968. static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
  969. &omap2_l4_core__uart2,
  970. };
  971. static struct omap_hwmod omap2420_uart2_hwmod = {
  972. .name = "uart2",
  973. .mpu_irqs = uart2_mpu_irqs,
  974. .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
  975. .sdma_reqs = uart2_sdma_reqs,
  976. .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
  977. .main_clk = "uart2_fck",
  978. .prcm = {
  979. .omap2 = {
  980. .module_offs = CORE_MOD,
  981. .prcm_reg_id = 1,
  982. .module_bit = OMAP24XX_EN_UART2_SHIFT,
  983. .idlest_reg_id = 1,
  984. .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
  985. },
  986. },
  987. .slaves = omap2420_uart2_slaves,
  988. .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
  989. .class = &uart_class,
  990. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  991. };
  992. /* UART3 */
  993. static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
  994. { .irq = INT_24XX_UART3_IRQ, },
  995. };
  996. static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
  997. { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
  998. { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
  999. };
  1000. static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
  1001. &omap2_l4_core__uart3,
  1002. };
  1003. static struct omap_hwmod omap2420_uart3_hwmod = {
  1004. .name = "uart3",
  1005. .mpu_irqs = uart3_mpu_irqs,
  1006. .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
  1007. .sdma_reqs = uart3_sdma_reqs,
  1008. .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
  1009. .main_clk = "uart3_fck",
  1010. .prcm = {
  1011. .omap2 = {
  1012. .module_offs = CORE_MOD,
  1013. .prcm_reg_id = 2,
  1014. .module_bit = OMAP24XX_EN_UART3_SHIFT,
  1015. .idlest_reg_id = 2,
  1016. .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
  1017. },
  1018. },
  1019. .slaves = omap2420_uart3_slaves,
  1020. .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
  1021. .class = &uart_class,
  1022. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1023. };
  1024. /*
  1025. * 'dss' class
  1026. * display sub-system
  1027. */
  1028. static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
  1029. .rev_offs = 0x0000,
  1030. .sysc_offs = 0x0010,
  1031. .syss_offs = 0x0014,
  1032. .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1033. .sysc_fields = &omap_hwmod_sysc_type1,
  1034. };
  1035. static struct omap_hwmod_class omap2420_dss_hwmod_class = {
  1036. .name = "dss",
  1037. .sysc = &omap2420_dss_sysc,
  1038. };
  1039. static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
  1040. { .name = "dispc", .dma_req = 5 },
  1041. };
  1042. /* dss */
  1043. /* dss master ports */
  1044. static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
  1045. &omap2420_dss__l3,
  1046. };
  1047. static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
  1048. {
  1049. .pa_start = 0x48050000,
  1050. .pa_end = 0x480503FF,
  1051. .flags = ADDR_TYPE_RT
  1052. },
  1053. };
  1054. /* l4_core -> dss */
  1055. static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
  1056. .master = &omap2420_l4_core_hwmod,
  1057. .slave = &omap2420_dss_core_hwmod,
  1058. .clk = "dss_ick",
  1059. .addr = omap2420_dss_addrs,
  1060. .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
  1061. .fw = {
  1062. .omap2 = {
  1063. .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
  1064. .flags = OMAP_FIREWALL_L4,
  1065. }
  1066. },
  1067. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1068. };
  1069. /* dss slave ports */
  1070. static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
  1071. &omap2420_l4_core__dss,
  1072. };
  1073. static struct omap_hwmod_opt_clk dss_opt_clks[] = {
  1074. { .role = "tv_clk", .clk = "dss_54m_fck" },
  1075. { .role = "sys_clk", .clk = "dss2_fck" },
  1076. };
  1077. static struct omap_hwmod omap2420_dss_core_hwmod = {
  1078. .name = "dss_core",
  1079. .class = &omap2420_dss_hwmod_class,
  1080. .main_clk = "dss1_fck", /* instead of dss_fck */
  1081. .sdma_reqs = omap2420_dss_sdma_chs,
  1082. .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
  1083. .prcm = {
  1084. .omap2 = {
  1085. .prcm_reg_id = 1,
  1086. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  1087. .module_offs = CORE_MOD,
  1088. .idlest_reg_id = 1,
  1089. .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
  1090. },
  1091. },
  1092. .opt_clks = dss_opt_clks,
  1093. .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
  1094. .slaves = omap2420_dss_slaves,
  1095. .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
  1096. .masters = omap2420_dss_masters,
  1097. .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
  1098. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1099. .flags = HWMOD_NO_IDLEST,
  1100. };
  1101. /*
  1102. * 'dispc' class
  1103. * display controller
  1104. */
  1105. static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
  1106. .rev_offs = 0x0000,
  1107. .sysc_offs = 0x0010,
  1108. .syss_offs = 0x0014,
  1109. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  1110. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1111. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1112. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  1113. .sysc_fields = &omap_hwmod_sysc_type1,
  1114. };
  1115. static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
  1116. .name = "dispc",
  1117. .sysc = &omap2420_dispc_sysc,
  1118. };
  1119. static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
  1120. { .irq = 25 },
  1121. };
  1122. static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
  1123. {
  1124. .pa_start = 0x48050400,
  1125. .pa_end = 0x480507FF,
  1126. .flags = ADDR_TYPE_RT
  1127. },
  1128. };
  1129. /* l4_core -> dss_dispc */
  1130. static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
  1131. .master = &omap2420_l4_core_hwmod,
  1132. .slave = &omap2420_dss_dispc_hwmod,
  1133. .clk = "dss_ick",
  1134. .addr = omap2420_dss_dispc_addrs,
  1135. .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
  1136. .fw = {
  1137. .omap2 = {
  1138. .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
  1139. .flags = OMAP_FIREWALL_L4,
  1140. }
  1141. },
  1142. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1143. };
  1144. /* dss_dispc slave ports */
  1145. static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
  1146. &omap2420_l4_core__dss_dispc,
  1147. };
  1148. static struct omap_hwmod omap2420_dss_dispc_hwmod = {
  1149. .name = "dss_dispc",
  1150. .class = &omap2420_dispc_hwmod_class,
  1151. .mpu_irqs = omap2420_dispc_irqs,
  1152. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
  1153. .main_clk = "dss1_fck",
  1154. .prcm = {
  1155. .omap2 = {
  1156. .prcm_reg_id = 1,
  1157. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  1158. .module_offs = CORE_MOD,
  1159. .idlest_reg_id = 1,
  1160. .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
  1161. },
  1162. },
  1163. .slaves = omap2420_dss_dispc_slaves,
  1164. .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
  1165. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1166. .flags = HWMOD_NO_IDLEST,
  1167. };
  1168. /*
  1169. * 'rfbi' class
  1170. * remote frame buffer interface
  1171. */
  1172. static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
  1173. .rev_offs = 0x0000,
  1174. .sysc_offs = 0x0010,
  1175. .syss_offs = 0x0014,
  1176. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  1177. SYSC_HAS_AUTOIDLE),
  1178. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1179. .sysc_fields = &omap_hwmod_sysc_type1,
  1180. };
  1181. static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
  1182. .name = "rfbi",
  1183. .sysc = &omap2420_rfbi_sysc,
  1184. };
  1185. static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
  1186. {
  1187. .pa_start = 0x48050800,
  1188. .pa_end = 0x48050BFF,
  1189. .flags = ADDR_TYPE_RT
  1190. },
  1191. };
  1192. /* l4_core -> dss_rfbi */
  1193. static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
  1194. .master = &omap2420_l4_core_hwmod,
  1195. .slave = &omap2420_dss_rfbi_hwmod,
  1196. .clk = "dss_ick",
  1197. .addr = omap2420_dss_rfbi_addrs,
  1198. .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
  1199. .fw = {
  1200. .omap2 = {
  1201. .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
  1202. .flags = OMAP_FIREWALL_L4,
  1203. }
  1204. },
  1205. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1206. };
  1207. /* dss_rfbi slave ports */
  1208. static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
  1209. &omap2420_l4_core__dss_rfbi,
  1210. };
  1211. static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
  1212. .name = "dss_rfbi",
  1213. .class = &omap2420_rfbi_hwmod_class,
  1214. .main_clk = "dss1_fck",
  1215. .prcm = {
  1216. .omap2 = {
  1217. .prcm_reg_id = 1,
  1218. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  1219. .module_offs = CORE_MOD,
  1220. },
  1221. },
  1222. .slaves = omap2420_dss_rfbi_slaves,
  1223. .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
  1224. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1225. .flags = HWMOD_NO_IDLEST,
  1226. };
  1227. /*
  1228. * 'venc' class
  1229. * video encoder
  1230. */
  1231. static struct omap_hwmod_class omap2420_venc_hwmod_class = {
  1232. .name = "venc",
  1233. };
  1234. /* dss_venc */
  1235. static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
  1236. {
  1237. .pa_start = 0x48050C00,
  1238. .pa_end = 0x48050FFF,
  1239. .flags = ADDR_TYPE_RT
  1240. },
  1241. };
  1242. /* l4_core -> dss_venc */
  1243. static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
  1244. .master = &omap2420_l4_core_hwmod,
  1245. .slave = &omap2420_dss_venc_hwmod,
  1246. .clk = "dss_54m_fck",
  1247. .addr = omap2420_dss_venc_addrs,
  1248. .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
  1249. .fw = {
  1250. .omap2 = {
  1251. .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
  1252. .flags = OMAP_FIREWALL_L4,
  1253. }
  1254. },
  1255. .flags = OCPIF_SWSUP_IDLE,
  1256. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1257. };
  1258. /* dss_venc slave ports */
  1259. static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
  1260. &omap2420_l4_core__dss_venc,
  1261. };
  1262. static struct omap_hwmod omap2420_dss_venc_hwmod = {
  1263. .name = "dss_venc",
  1264. .class = &omap2420_venc_hwmod_class,
  1265. .main_clk = "dss1_fck",
  1266. .prcm = {
  1267. .omap2 = {
  1268. .prcm_reg_id = 1,
  1269. .module_bit = OMAP24XX_EN_DSS1_SHIFT,
  1270. .module_offs = CORE_MOD,
  1271. },
  1272. },
  1273. .slaves = omap2420_dss_venc_slaves,
  1274. .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
  1275. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1276. .flags = HWMOD_NO_IDLEST,
  1277. };
  1278. /* I2C common */
  1279. static struct omap_hwmod_class_sysconfig i2c_sysc = {
  1280. .rev_offs = 0x00,
  1281. .sysc_offs = 0x20,
  1282. .syss_offs = 0x10,
  1283. .sysc_flags = SYSC_HAS_SOFTRESET,
  1284. .sysc_fields = &omap_hwmod_sysc_type1,
  1285. };
  1286. static struct omap_hwmod_class i2c_class = {
  1287. .name = "i2c",
  1288. .sysc = &i2c_sysc,
  1289. };
  1290. static struct omap_i2c_dev_attr i2c_dev_attr;
  1291. /* I2C1 */
  1292. static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
  1293. { .irq = INT_24XX_I2C1_IRQ, },
  1294. };
  1295. static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
  1296. { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
  1297. { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
  1298. };
  1299. static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
  1300. &omap2420_l4_core__i2c1,
  1301. };
  1302. static struct omap_hwmod omap2420_i2c1_hwmod = {
  1303. .name = "i2c1",
  1304. .mpu_irqs = i2c1_mpu_irqs,
  1305. .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
  1306. .sdma_reqs = i2c1_sdma_reqs,
  1307. .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
  1308. .main_clk = "i2c1_fck",
  1309. .prcm = {
  1310. .omap2 = {
  1311. .module_offs = CORE_MOD,
  1312. .prcm_reg_id = 1,
  1313. .module_bit = OMAP2420_EN_I2C1_SHIFT,
  1314. .idlest_reg_id = 1,
  1315. .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
  1316. },
  1317. },
  1318. .slaves = omap2420_i2c1_slaves,
  1319. .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
  1320. .class = &i2c_class,
  1321. .dev_attr = &i2c_dev_attr,
  1322. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1323. .flags = HWMOD_16BIT_REG,
  1324. };
  1325. /* I2C2 */
  1326. static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
  1327. { .irq = INT_24XX_I2C2_IRQ, },
  1328. };
  1329. static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
  1330. { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
  1331. { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
  1332. };
  1333. static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
  1334. &omap2420_l4_core__i2c2,
  1335. };
  1336. static struct omap_hwmod omap2420_i2c2_hwmod = {
  1337. .name = "i2c2",
  1338. .mpu_irqs = i2c2_mpu_irqs,
  1339. .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
  1340. .sdma_reqs = i2c2_sdma_reqs,
  1341. .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
  1342. .main_clk = "i2c2_fck",
  1343. .prcm = {
  1344. .omap2 = {
  1345. .module_offs = CORE_MOD,
  1346. .prcm_reg_id = 1,
  1347. .module_bit = OMAP2420_EN_I2C2_SHIFT,
  1348. .idlest_reg_id = 1,
  1349. .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
  1350. },
  1351. },
  1352. .slaves = omap2420_i2c2_slaves,
  1353. .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
  1354. .class = &i2c_class,
  1355. .dev_attr = &i2c_dev_attr,
  1356. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1357. .flags = HWMOD_16BIT_REG,
  1358. };
  1359. /* l4_wkup -> gpio1 */
  1360. static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
  1361. {
  1362. .pa_start = 0x48018000,
  1363. .pa_end = 0x480181ff,
  1364. .flags = ADDR_TYPE_RT
  1365. },
  1366. };
  1367. static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
  1368. .master = &omap2420_l4_wkup_hwmod,
  1369. .slave = &omap2420_gpio1_hwmod,
  1370. .clk = "gpios_ick",
  1371. .addr = omap2420_gpio1_addr_space,
  1372. .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
  1373. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1374. };
  1375. /* l4_wkup -> gpio2 */
  1376. static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
  1377. {
  1378. .pa_start = 0x4801a000,
  1379. .pa_end = 0x4801a1ff,
  1380. .flags = ADDR_TYPE_RT
  1381. },
  1382. };
  1383. static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
  1384. .master = &omap2420_l4_wkup_hwmod,
  1385. .slave = &omap2420_gpio2_hwmod,
  1386. .clk = "gpios_ick",
  1387. .addr = omap2420_gpio2_addr_space,
  1388. .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
  1389. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1390. };
  1391. /* l4_wkup -> gpio3 */
  1392. static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
  1393. {
  1394. .pa_start = 0x4801c000,
  1395. .pa_end = 0x4801c1ff,
  1396. .flags = ADDR_TYPE_RT
  1397. },
  1398. };
  1399. static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
  1400. .master = &omap2420_l4_wkup_hwmod,
  1401. .slave = &omap2420_gpio3_hwmod,
  1402. .clk = "gpios_ick",
  1403. .addr = omap2420_gpio3_addr_space,
  1404. .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
  1405. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1406. };
  1407. /* l4_wkup -> gpio4 */
  1408. static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
  1409. {
  1410. .pa_start = 0x4801e000,
  1411. .pa_end = 0x4801e1ff,
  1412. .flags = ADDR_TYPE_RT
  1413. },
  1414. };
  1415. static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
  1416. .master = &omap2420_l4_wkup_hwmod,
  1417. .slave = &omap2420_gpio4_hwmod,
  1418. .clk = "gpios_ick",
  1419. .addr = omap2420_gpio4_addr_space,
  1420. .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
  1421. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1422. };
  1423. /* gpio dev_attr */
  1424. static struct omap_gpio_dev_attr gpio_dev_attr = {
  1425. .bank_width = 32,
  1426. .dbck_flag = false,
  1427. };
  1428. static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
  1429. .rev_offs = 0x0000,
  1430. .sysc_offs = 0x0010,
  1431. .syss_offs = 0x0014,
  1432. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  1433. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1434. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1435. .sysc_fields = &omap_hwmod_sysc_type1,
  1436. };
  1437. /*
  1438. * 'gpio' class
  1439. * general purpose io module
  1440. */
  1441. static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
  1442. .name = "gpio",
  1443. .sysc = &omap242x_gpio_sysc,
  1444. .rev = 0,
  1445. };
  1446. /* gpio1 */
  1447. static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
  1448. { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
  1449. };
  1450. static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
  1451. &omap2420_l4_wkup__gpio1,
  1452. };
  1453. static struct omap_hwmod omap2420_gpio1_hwmod = {
  1454. .name = "gpio1",
  1455. .mpu_irqs = omap242x_gpio1_irqs,
  1456. .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
  1457. .main_clk = "gpios_fck",
  1458. .prcm = {
  1459. .omap2 = {
  1460. .prcm_reg_id = 1,
  1461. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  1462. .module_offs = WKUP_MOD,
  1463. .idlest_reg_id = 1,
  1464. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  1465. },
  1466. },
  1467. .slaves = omap2420_gpio1_slaves,
  1468. .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
  1469. .class = &omap242x_gpio_hwmod_class,
  1470. .dev_attr = &gpio_dev_attr,
  1471. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1472. };
  1473. /* gpio2 */
  1474. static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
  1475. { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
  1476. };
  1477. static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
  1478. &omap2420_l4_wkup__gpio2,
  1479. };
  1480. static struct omap_hwmod omap2420_gpio2_hwmod = {
  1481. .name = "gpio2",
  1482. .mpu_irqs = omap242x_gpio2_irqs,
  1483. .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
  1484. .main_clk = "gpios_fck",
  1485. .prcm = {
  1486. .omap2 = {
  1487. .prcm_reg_id = 1,
  1488. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  1489. .module_offs = WKUP_MOD,
  1490. .idlest_reg_id = 1,
  1491. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  1492. },
  1493. },
  1494. .slaves = omap2420_gpio2_slaves,
  1495. .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
  1496. .class = &omap242x_gpio_hwmod_class,
  1497. .dev_attr = &gpio_dev_attr,
  1498. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1499. };
  1500. /* gpio3 */
  1501. static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
  1502. { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
  1503. };
  1504. static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
  1505. &omap2420_l4_wkup__gpio3,
  1506. };
  1507. static struct omap_hwmod omap2420_gpio3_hwmod = {
  1508. .name = "gpio3",
  1509. .mpu_irqs = omap242x_gpio3_irqs,
  1510. .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
  1511. .main_clk = "gpios_fck",
  1512. .prcm = {
  1513. .omap2 = {
  1514. .prcm_reg_id = 1,
  1515. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  1516. .module_offs = WKUP_MOD,
  1517. .idlest_reg_id = 1,
  1518. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  1519. },
  1520. },
  1521. .slaves = omap2420_gpio3_slaves,
  1522. .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
  1523. .class = &omap242x_gpio_hwmod_class,
  1524. .dev_attr = &gpio_dev_attr,
  1525. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1526. };
  1527. /* gpio4 */
  1528. static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
  1529. { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
  1530. };
  1531. static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
  1532. &omap2420_l4_wkup__gpio4,
  1533. };
  1534. static struct omap_hwmod omap2420_gpio4_hwmod = {
  1535. .name = "gpio4",
  1536. .mpu_irqs = omap242x_gpio4_irqs,
  1537. .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
  1538. .main_clk = "gpios_fck",
  1539. .prcm = {
  1540. .omap2 = {
  1541. .prcm_reg_id = 1,
  1542. .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
  1543. .module_offs = WKUP_MOD,
  1544. .idlest_reg_id = 1,
  1545. .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
  1546. },
  1547. },
  1548. .slaves = omap2420_gpio4_slaves,
  1549. .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
  1550. .class = &omap242x_gpio_hwmod_class,
  1551. .dev_attr = &gpio_dev_attr,
  1552. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1553. };
  1554. /* system dma */
  1555. static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
  1556. .rev_offs = 0x0000,
  1557. .sysc_offs = 0x002c,
  1558. .syss_offs = 0x0028,
  1559. .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
  1560. SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
  1561. SYSC_HAS_AUTOIDLE),
  1562. .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  1563. .sysc_fields = &omap_hwmod_sysc_type1,
  1564. };
  1565. static struct omap_hwmod_class omap2420_dma_hwmod_class = {
  1566. .name = "dma",
  1567. .sysc = &omap2420_dma_sysc,
  1568. };
  1569. /* dma attributes */
  1570. static struct omap_dma_dev_attr dma_dev_attr = {
  1571. .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
  1572. IS_CSSA_32 | IS_CDSA_32,
  1573. .lch_count = 32,
  1574. };
  1575. static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
  1576. { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
  1577. { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
  1578. { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
  1579. { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
  1580. };
  1581. static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
  1582. {
  1583. .pa_start = 0x48056000,
  1584. .pa_end = 0x4a0560ff,
  1585. .flags = ADDR_TYPE_RT
  1586. },
  1587. };
  1588. /* dma_system -> L3 */
  1589. static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
  1590. .master = &omap2420_dma_system_hwmod,
  1591. .slave = &omap2420_l3_main_hwmod,
  1592. .clk = "core_l3_ck",
  1593. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1594. };
  1595. /* dma_system master ports */
  1596. static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
  1597. &omap2420_dma_system__l3,
  1598. };
  1599. /* l4_core -> dma_system */
  1600. static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
  1601. .master = &omap2420_l4_core_hwmod,
  1602. .slave = &omap2420_dma_system_hwmod,
  1603. .clk = "sdma_ick",
  1604. .addr = omap2420_dma_system_addrs,
  1605. .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
  1606. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1607. };
  1608. /* dma_system slave ports */
  1609. static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
  1610. &omap2420_l4_core__dma_system,
  1611. };
  1612. static struct omap_hwmod omap2420_dma_system_hwmod = {
  1613. .name = "dma",
  1614. .class = &omap2420_dma_hwmod_class,
  1615. .mpu_irqs = omap2420_dma_system_irqs,
  1616. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
  1617. .main_clk = "core_l3_ck",
  1618. .slaves = omap2420_dma_system_slaves,
  1619. .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
  1620. .masters = omap2420_dma_system_masters,
  1621. .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
  1622. .dev_attr = &dma_dev_attr,
  1623. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1624. .flags = HWMOD_NO_IDLEST,
  1625. };
  1626. /*
  1627. * 'mailbox' class
  1628. * mailbox module allowing communication between the on-chip processors
  1629. * using a queued mailbox-interrupt mechanism.
  1630. */
  1631. static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
  1632. .rev_offs = 0x000,
  1633. .sysc_offs = 0x010,
  1634. .syss_offs = 0x014,
  1635. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1636. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1637. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1638. .sysc_fields = &omap_hwmod_sysc_type1,
  1639. };
  1640. static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
  1641. .name = "mailbox",
  1642. .sysc = &omap2420_mailbox_sysc,
  1643. };
  1644. /* mailbox */
  1645. static struct omap_hwmod omap2420_mailbox_hwmod;
  1646. static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
  1647. { .name = "dsp", .irq = 26 },
  1648. { .name = "iva", .irq = 34 },
  1649. };
  1650. static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
  1651. {
  1652. .pa_start = 0x48094000,
  1653. .pa_end = 0x480941ff,
  1654. .flags = ADDR_TYPE_RT,
  1655. },
  1656. };
  1657. /* l4_core -> mailbox */
  1658. static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
  1659. .master = &omap2420_l4_core_hwmod,
  1660. .slave = &omap2420_mailbox_hwmod,
  1661. .addr = omap2420_mailbox_addrs,
  1662. .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
  1663. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1664. };
  1665. /* mailbox slave ports */
  1666. static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
  1667. &omap2420_l4_core__mailbox,
  1668. };
  1669. static struct omap_hwmod omap2420_mailbox_hwmod = {
  1670. .name = "mailbox",
  1671. .class = &omap2420_mailbox_hwmod_class,
  1672. .mpu_irqs = omap2420_mailbox_irqs,
  1673. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
  1674. .main_clk = "mailboxes_ick",
  1675. .prcm = {
  1676. .omap2 = {
  1677. .prcm_reg_id = 1,
  1678. .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
  1679. .module_offs = CORE_MOD,
  1680. .idlest_reg_id = 1,
  1681. .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
  1682. },
  1683. },
  1684. .slaves = omap2420_mailbox_slaves,
  1685. .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
  1686. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1687. };
  1688. /*
  1689. * 'mcspi' class
  1690. * multichannel serial port interface (mcspi) / master/slave synchronous serial
  1691. * bus
  1692. */
  1693. static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
  1694. .rev_offs = 0x0000,
  1695. .sysc_offs = 0x0010,
  1696. .syss_offs = 0x0014,
  1697. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1698. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  1699. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  1700. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1701. .sysc_fields = &omap_hwmod_sysc_type1,
  1702. };
  1703. static struct omap_hwmod_class omap2420_mcspi_class = {
  1704. .name = "mcspi",
  1705. .sysc = &omap2420_mcspi_sysc,
  1706. .rev = OMAP2_MCSPI_REV,
  1707. };
  1708. /* mcspi1 */
  1709. static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
  1710. { .irq = 65 },
  1711. };
  1712. static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
  1713. { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
  1714. { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
  1715. { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
  1716. { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
  1717. { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
  1718. { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
  1719. { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
  1720. { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
  1721. };
  1722. static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
  1723. &omap2420_l4_core__mcspi1,
  1724. };
  1725. static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
  1726. .num_chipselect = 4,
  1727. };
  1728. static struct omap_hwmod omap2420_mcspi1_hwmod = {
  1729. .name = "mcspi1_hwmod",
  1730. .mpu_irqs = omap2420_mcspi1_mpu_irqs,
  1731. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
  1732. .sdma_reqs = omap2420_mcspi1_sdma_reqs,
  1733. .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
  1734. .main_clk = "mcspi1_fck",
  1735. .prcm = {
  1736. .omap2 = {
  1737. .module_offs = CORE_MOD,
  1738. .prcm_reg_id = 1,
  1739. .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
  1740. .idlest_reg_id = 1,
  1741. .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
  1742. },
  1743. },
  1744. .slaves = omap2420_mcspi1_slaves,
  1745. .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
  1746. .class = &omap2420_mcspi_class,
  1747. .dev_attr = &omap_mcspi1_dev_attr,
  1748. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1749. };
  1750. /* mcspi2 */
  1751. static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
  1752. { .irq = 66 },
  1753. };
  1754. static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
  1755. { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
  1756. { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
  1757. { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
  1758. { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
  1759. };
  1760. static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
  1761. &omap2420_l4_core__mcspi2,
  1762. };
  1763. static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
  1764. .num_chipselect = 2,
  1765. };
  1766. static struct omap_hwmod omap2420_mcspi2_hwmod = {
  1767. .name = "mcspi2_hwmod",
  1768. .mpu_irqs = omap2420_mcspi2_mpu_irqs,
  1769. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
  1770. .sdma_reqs = omap2420_mcspi2_sdma_reqs,
  1771. .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
  1772. .main_clk = "mcspi2_fck",
  1773. .prcm = {
  1774. .omap2 = {
  1775. .module_offs = CORE_MOD,
  1776. .prcm_reg_id = 1,
  1777. .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
  1778. .idlest_reg_id = 1,
  1779. .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
  1780. },
  1781. },
  1782. .slaves = omap2420_mcspi2_slaves,
  1783. .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
  1784. .class = &omap2420_mcspi_class,
  1785. .dev_attr = &omap_mcspi2_dev_attr,
  1786. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1787. };
  1788. /*
  1789. * 'mcbsp' class
  1790. * multi channel buffered serial port controller
  1791. */
  1792. static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
  1793. .name = "mcbsp",
  1794. };
  1795. /* mcbsp1 */
  1796. static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
  1797. { .name = "tx", .irq = 59 },
  1798. { .name = "rx", .irq = 60 },
  1799. };
  1800. static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
  1801. { .name = "rx", .dma_req = 32 },
  1802. { .name = "tx", .dma_req = 31 },
  1803. };
  1804. static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
  1805. {
  1806. .name = "mpu",
  1807. .pa_start = 0x48074000,
  1808. .pa_end = 0x480740ff,
  1809. .flags = ADDR_TYPE_RT
  1810. },
  1811. };
  1812. /* l4_core -> mcbsp1 */
  1813. static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
  1814. .master = &omap2420_l4_core_hwmod,
  1815. .slave = &omap2420_mcbsp1_hwmod,
  1816. .clk = "mcbsp1_ick",
  1817. .addr = omap2420_mcbsp1_addrs,
  1818. .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
  1819. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1820. };
  1821. /* mcbsp1 slave ports */
  1822. static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
  1823. &omap2420_l4_core__mcbsp1,
  1824. };
  1825. static struct omap_hwmod omap2420_mcbsp1_hwmod = {
  1826. .name = "mcbsp1",
  1827. .class = &omap2420_mcbsp_hwmod_class,
  1828. .mpu_irqs = omap2420_mcbsp1_irqs,
  1829. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs),
  1830. .sdma_reqs = omap2420_mcbsp1_sdma_chs,
  1831. .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
  1832. .main_clk = "mcbsp1_fck",
  1833. .prcm = {
  1834. .omap2 = {
  1835. .prcm_reg_id = 1,
  1836. .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
  1837. .module_offs = CORE_MOD,
  1838. .idlest_reg_id = 1,
  1839. .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
  1840. },
  1841. },
  1842. .slaves = omap2420_mcbsp1_slaves,
  1843. .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
  1844. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1845. };
  1846. /* mcbsp2 */
  1847. static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
  1848. { .name = "tx", .irq = 62 },
  1849. { .name = "rx", .irq = 63 },
  1850. };
  1851. static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
  1852. { .name = "rx", .dma_req = 34 },
  1853. { .name = "tx", .dma_req = 33 },
  1854. };
  1855. static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
  1856. {
  1857. .name = "mpu",
  1858. .pa_start = 0x48076000,
  1859. .pa_end = 0x480760ff,
  1860. .flags = ADDR_TYPE_RT
  1861. },
  1862. };
  1863. /* l4_core -> mcbsp2 */
  1864. static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
  1865. .master = &omap2420_l4_core_hwmod,
  1866. .slave = &omap2420_mcbsp2_hwmod,
  1867. .clk = "mcbsp2_ick",
  1868. .addr = omap2420_mcbsp2_addrs,
  1869. .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
  1870. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1871. };
  1872. /* mcbsp2 slave ports */
  1873. static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
  1874. &omap2420_l4_core__mcbsp2,
  1875. };
  1876. static struct omap_hwmod omap2420_mcbsp2_hwmod = {
  1877. .name = "mcbsp2",
  1878. .class = &omap2420_mcbsp_hwmod_class,
  1879. .mpu_irqs = omap2420_mcbsp2_irqs,
  1880. .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs),
  1881. .sdma_reqs = omap2420_mcbsp2_sdma_chs,
  1882. .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
  1883. .main_clk = "mcbsp2_fck",
  1884. .prcm = {
  1885. .omap2 = {
  1886. .prcm_reg_id = 1,
  1887. .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
  1888. .module_offs = CORE_MOD,
  1889. .idlest_reg_id = 1,
  1890. .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
  1891. },
  1892. },
  1893. .slaves = omap2420_mcbsp2_slaves,
  1894. .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
  1895. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  1896. };
  1897. static __initdata struct omap_hwmod *omap2420_hwmods[] = {
  1898. &omap2420_l3_main_hwmod,
  1899. &omap2420_l4_core_hwmod,
  1900. &omap2420_l4_wkup_hwmod,
  1901. &omap2420_mpu_hwmod,
  1902. &omap2420_iva_hwmod,
  1903. &omap2420_timer1_hwmod,
  1904. &omap2420_timer2_hwmod,
  1905. &omap2420_timer3_hwmod,
  1906. &omap2420_timer4_hwmod,
  1907. &omap2420_timer5_hwmod,
  1908. &omap2420_timer6_hwmod,
  1909. &omap2420_timer7_hwmod,
  1910. &omap2420_timer8_hwmod,
  1911. &omap2420_timer9_hwmod,
  1912. &omap2420_timer10_hwmod,
  1913. &omap2420_timer11_hwmod,
  1914. &omap2420_timer12_hwmod,
  1915. &omap2420_wd_timer2_hwmod,
  1916. &omap2420_uart1_hwmod,
  1917. &omap2420_uart2_hwmod,
  1918. &omap2420_uart3_hwmod,
  1919. /* dss class */
  1920. &omap2420_dss_core_hwmod,
  1921. &omap2420_dss_dispc_hwmod,
  1922. &omap2420_dss_rfbi_hwmod,
  1923. &omap2420_dss_venc_hwmod,
  1924. /* i2c class */
  1925. &omap2420_i2c1_hwmod,
  1926. &omap2420_i2c2_hwmod,
  1927. /* gpio class */
  1928. &omap2420_gpio1_hwmod,
  1929. &omap2420_gpio2_hwmod,
  1930. &omap2420_gpio3_hwmod,
  1931. &omap2420_gpio4_hwmod,
  1932. /* dma_system class*/
  1933. &omap2420_dma_system_hwmod,
  1934. /* mailbox class */
  1935. &omap2420_mailbox_hwmod,
  1936. /* mcbsp class */
  1937. &omap2420_mcbsp1_hwmod,
  1938. &omap2420_mcbsp2_hwmod,
  1939. /* mcspi class */
  1940. &omap2420_mcspi1_hwmod,
  1941. &omap2420_mcspi2_hwmod,
  1942. NULL,
  1943. };
  1944. int __init omap2420_hwmod_init(void)
  1945. {
  1946. return omap_hwmod_register(omap2420_hwmods);
  1947. }