ak4104.c 6.8 KB

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  1. /*
  2. * AK4104 ALSA SoC (ASoC) driver
  3. *
  4. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <sound/core.h>
  14. #include <sound/soc.h>
  15. #include <sound/initval.h>
  16. #include <linux/spi/spi.h>
  17. #include <sound/asoundef.h>
  18. /* AK4104 registers addresses */
  19. #define AK4104_REG_CONTROL1 0x00
  20. #define AK4104_REG_RESERVED 0x01
  21. #define AK4104_REG_CONTROL2 0x02
  22. #define AK4104_REG_TX 0x03
  23. #define AK4104_REG_CHN_STATUS(x) ((x) + 0x04)
  24. #define AK4104_NUM_REGS 10
  25. #define AK4104_REG_MASK 0x1f
  26. #define AK4104_READ 0xc0
  27. #define AK4104_WRITE 0xe0
  28. #define AK4104_RESERVED_VAL 0x5b
  29. /* Bit masks for AK4104 registers */
  30. #define AK4104_CONTROL1_RSTN (1 << 0)
  31. #define AK4104_CONTROL1_PW (1 << 1)
  32. #define AK4104_CONTROL1_DIF0 (1 << 2)
  33. #define AK4104_CONTROL1_DIF1 (1 << 3)
  34. #define AK4104_CONTROL2_SEL0 (1 << 0)
  35. #define AK4104_CONTROL2_SEL1 (1 << 1)
  36. #define AK4104_CONTROL2_MODE (1 << 2)
  37. #define AK4104_TX_TXE (1 << 0)
  38. #define AK4104_TX_V (1 << 1)
  39. #define DRV_NAME "ak4104-codec"
  40. struct ak4104_private {
  41. enum snd_soc_control_type control_type;
  42. void *control_data;
  43. };
  44. static int ak4104_fill_cache(struct snd_soc_codec *codec)
  45. {
  46. int i;
  47. u8 *reg_cache = codec->reg_cache;
  48. struct spi_device *spi = codec->control_data;
  49. for (i = 0; i < codec->driver->reg_cache_size; i++) {
  50. int ret = spi_w8r8(spi, i | AK4104_READ);
  51. if (ret < 0) {
  52. dev_err(&spi->dev, "SPI write failure\n");
  53. return ret;
  54. }
  55. reg_cache[i] = ret;
  56. }
  57. return 0;
  58. }
  59. static unsigned int ak4104_read_reg_cache(struct snd_soc_codec *codec,
  60. unsigned int reg)
  61. {
  62. u8 *reg_cache = codec->reg_cache;
  63. if (reg >= codec->driver->reg_cache_size)
  64. return -EINVAL;
  65. return reg_cache[reg];
  66. }
  67. static int ak4104_spi_write(struct snd_soc_codec *codec, unsigned int reg,
  68. unsigned int value)
  69. {
  70. u8 *cache = codec->reg_cache;
  71. struct spi_device *spi = codec->control_data;
  72. if (reg >= codec->driver->reg_cache_size)
  73. return -EINVAL;
  74. /* only write to the hardware if value has changed */
  75. if (cache[reg] != value) {
  76. u8 tmp[2] = { (reg & AK4104_REG_MASK) | AK4104_WRITE, value };
  77. if (spi_write(spi, tmp, sizeof(tmp))) {
  78. dev_err(&spi->dev, "SPI write failed\n");
  79. return -EIO;
  80. }
  81. cache[reg] = value;
  82. }
  83. return 0;
  84. }
  85. static int ak4104_set_dai_fmt(struct snd_soc_dai *codec_dai,
  86. unsigned int format)
  87. {
  88. struct snd_soc_codec *codec = codec_dai->codec;
  89. int val = 0;
  90. /* set DAI format */
  91. switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
  92. case SND_SOC_DAIFMT_RIGHT_J:
  93. break;
  94. case SND_SOC_DAIFMT_LEFT_J:
  95. val |= AK4104_CONTROL1_DIF0;
  96. break;
  97. case SND_SOC_DAIFMT_I2S:
  98. val |= AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1;
  99. break;
  100. default:
  101. dev_err(codec->dev, "invalid dai format\n");
  102. return -EINVAL;
  103. }
  104. /* This device can only be slave */
  105. if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  106. return -EINVAL;
  107. ret = snd_soc_update_bits(codec, AK4104_REG_CONTROL1,
  108. AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1,
  109. val);
  110. if (ret < 0)
  111. return ret;
  112. return 0;
  113. }
  114. static int ak4104_hw_params(struct snd_pcm_substream *substream,
  115. struct snd_pcm_hw_params *params,
  116. struct snd_soc_dai *dai)
  117. {
  118. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  119. struct snd_soc_codec *codec = rtd->codec;
  120. int val = 0;
  121. /* set the IEC958 bits: consumer mode, no copyright bit */
  122. val |= IEC958_AES0_CON_NOT_COPYRIGHT;
  123. ak4104_spi_write(codec, AK4104_REG_CHN_STATUS(0), val);
  124. val = 0;
  125. switch (params_rate(params)) {
  126. case 44100:
  127. val |= IEC958_AES3_CON_FS_44100;
  128. break;
  129. case 48000:
  130. val |= IEC958_AES3_CON_FS_48000;
  131. break;
  132. case 32000:
  133. val |= IEC958_AES3_CON_FS_32000;
  134. break;
  135. default:
  136. dev_err(codec->dev, "unsupported sampling rate\n");
  137. return -EINVAL;
  138. }
  139. return ak4104_spi_write(codec, AK4104_REG_CHN_STATUS(3), val);
  140. }
  141. static const struct snd_soc_dai_ops ak4101_dai_ops = {
  142. .hw_params = ak4104_hw_params,
  143. .set_fmt = ak4104_set_dai_fmt,
  144. };
  145. static struct snd_soc_dai_driver ak4104_dai = {
  146. .name = "ak4104-hifi",
  147. .playback = {
  148. .stream_name = "Playback",
  149. .channels_min = 2,
  150. .channels_max = 2,
  151. .rates = SNDRV_PCM_RATE_8000_192000,
  152. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  153. SNDRV_PCM_FMTBIT_S24_3LE |
  154. SNDRV_PCM_FMTBIT_S24_LE
  155. },
  156. .ops = &ak4101_dai_ops,
  157. };
  158. static int ak4104_probe(struct snd_soc_codec *codec)
  159. {
  160. struct ak4104_private *ak4104 = snd_soc_codec_get_drvdata(codec);
  161. int ret, val;
  162. codec->control_data = ak4104->control_data;
  163. /* read all regs and fill the cache */
  164. ret = ak4104_fill_cache(codec);
  165. if (ret < 0) {
  166. dev_err(codec->dev, "failed to fill register cache\n");
  167. return ret;
  168. }
  169. /* read the 'reserved' register - according to the datasheet, it
  170. * should contain 0x5b. Not a good way to verify the presence of
  171. * the device, but there is no hardware ID register. */
  172. if (ak4104_read_reg_cache(codec, AK4104_REG_RESERVED) !=
  173. AK4104_RESERVED_VAL)
  174. return -ENODEV;
  175. /* set power-up and non-reset bits */
  176. ret = snd_soc_update_bits(codec, AK4104_REG_CONTROL1,
  177. AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN,
  178. AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN);
  179. if (ret < 0)
  180. return ret;
  181. /* enable transmitter */
  182. ret = snd_soc_update_bits(codec, AK4104_REG_TX,
  183. AK4104_TX_TXE, AK4104_TX_TXE);
  184. if (ret < 0)
  185. return ret;
  186. return 0;
  187. }
  188. static int ak4104_remove(struct snd_soc_codec *codec)
  189. {
  190. snd_soc_update_bits(codec, AK4104_REG_CONTROL1,
  191. AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN, 0);
  192. return 0;
  193. }
  194. static struct snd_soc_codec_driver soc_codec_device_ak4104 = {
  195. .probe = ak4104_probe,
  196. .remove = ak4104_remove,
  197. .reg_cache_size = AK4104_NUM_REGS,
  198. .reg_word_size = sizeof(u8),
  199. };
  200. static int ak4104_spi_probe(struct spi_device *spi)
  201. {
  202. struct ak4104_private *ak4104;
  203. int ret;
  204. spi->bits_per_word = 8;
  205. spi->mode = SPI_MODE_0;
  206. ret = spi_setup(spi);
  207. if (ret < 0)
  208. return ret;
  209. ak4104 = devm_kzalloc(&spi->dev, sizeof(struct ak4104_private),
  210. GFP_KERNEL);
  211. if (ak4104 == NULL)
  212. return -ENOMEM;
  213. ak4104->control_data = spi;
  214. ak4104->control_type = SND_SOC_SPI;
  215. spi_set_drvdata(spi, ak4104);
  216. ret = snd_soc_register_codec(&spi->dev,
  217. &soc_codec_device_ak4104, &ak4104_dai, 1);
  218. return ret;
  219. }
  220. static int __devexit ak4104_spi_remove(struct spi_device *spi)
  221. {
  222. snd_soc_unregister_codec(&spi->dev);
  223. return 0;
  224. }
  225. static struct spi_driver ak4104_spi_driver = {
  226. .driver = {
  227. .name = DRV_NAME,
  228. .owner = THIS_MODULE,
  229. },
  230. .probe = ak4104_spi_probe,
  231. .remove = __devexit_p(ak4104_spi_remove),
  232. };
  233. module_spi_driver(ak4104_spi_driver);
  234. MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
  235. MODULE_DESCRIPTION("Asahi Kasei AK4104 ALSA SoC driver");
  236. MODULE_LICENSE("GPL");